1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 3; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \ 4; RUN: -check-prefix=P9BE -implicit-check-not frsp 5; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 6; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ 7; RUN: -check-prefix=P9LE -implicit-check-not frsp 8; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 9; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \ 10; RUN: -check-prefix=P8BE -implicit-check-not frsp 11; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 12; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ 13; RUN: -check-prefix=P8LE -implicit-check-not frsp 14 15; This test case comes from the following C test case (included as it may be 16; slightly more readable than the LLVM IR. 17 18;/* This test case provides various ways of building vectors to ensure we 19; produce optimal code for all cases. The cases are (for each type): 20; - All zeros 21; - All ones - split to build-vector-allones.ll 22; - Splat of a constant 23; - From different values already in registers 24; - From different constants 25; - From different values in memory 26; - Splat of a value in register 27; - Splat of a value in memory 28; - Inserting element into existing vector 29; - Inserting element from existing vector into existing vector 30; 31; With conversions (float <-> int) 32; - Splat of a constant 33; - From different values already in registers 34; - From different constants 35; - From different values in memory 36; - Splat of a value in register 37; - Splat of a value in memory 38; - Inserting element into existing vector 39; - Inserting element from existing vector into existing vector 40;*/ 41; 42;/*=================================== int ===================================*/ 43;// P8: xxlxor // 44;// P9: xxlxor // 45;vector int allZeroi() { // 46; return (vector int)0; // 47;} // 48;// P8: vspltisb -1 // 49;// P9: xxspltisb 255 // 50;vector int spltConst1i() { // 51; return (vector int)1; // 52;} // 53;// P8: vspltisw -15; vsrw // 54;// P9: vspltisw -15; vsrw // 55;vector int spltConst16ki() { // 56; return (vector int)((1<<15) - 1); // 57;} // 58;// P8: vspltisw -16; vsrw // 59;// P9: vspltisw -16; vsrw // 60;vector int spltConst32ki() { // 61; return (vector int)((1<<16) - 1); // 62;} // 63;// P8: 4 x mtvsrwz, 2 x xxmrgh, vmrgow // 64;// P9: 2 x mtvsrdd, vmrgow // 65;vector int fromRegsi(int a, int b, int c, int d) { // 66; return (vector int){ a, b, c, d }; // 67;} // 68;// P8: lxvd2x, xxswapd // 69;// P9: lxvx (or even lxv) // 70;vector int fromDiffConstsi() { // 71; return (vector int) { 242, -113, 889, 19 }; // 72;} // 73;// P8: lxvd2x, xxswapd // 74;// P9: lxvx // 75;vector int fromDiffMemConsAi(int *arr) { // 76; return (vector int) { arr[0], arr[1], arr[2], arr[3] }; // 77;} // 78;// P8: 2 x lxvd2x, 2 x xxswapd, vperm // 79;// P9: 2 x lxvx, vperm // 80;vector int fromDiffMemConsDi(int *arr) { // 81; return (vector int) { arr[3], arr[2], arr[1], arr[0] }; // 82;} // 83;// P8: sldi 2, lxvd2x, xxswapd // 84;// P9: sldi 2, lxvx // 85;vector int fromDiffMemVarAi(int *arr, int elem) { // 86; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 87;} // 88;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm // 89;// P9: sldi 2, 2 x lxvx, vperm // 90;vector int fromDiffMemVarDi(int *arr, int elem) { // 91; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 92;} // 93;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 94;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow // 95;vector int fromRandMemConsi(int *arr) { // 96; return (vector int) { arr[4], arr[18], arr[2], arr[88] }; // 97;} // 98;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 99;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow // 100;vector int fromRandMemVari(int *arr, int elem) { // 101; return (vector int) { arr[elem+4], arr[elem+1], arr[elem+2], arr[elem+8] };// 102;} // 103;// P8: mtvsrwz, xxspltw // 104;// P9: mtvsrws // 105;vector int spltRegVali(int val) { // 106; return (vector int) val; // 107;} // 108;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 109;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 110;vector int spltMemVali(int *ptr) { // 111; return (vector int)*ptr; // 112;} // 113;// P8: vspltisw // 114;// P9: vspltisw // 115;vector int spltCnstConvftoi() { // 116; return (vector int) 4.74f; // 117;} // 118;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 119;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 120;vector int fromRegsConvftoi(float a, float b, float c, float d) { // 121; return (vector int) { a, b, c, d }; // 122;} // 123;// P8: lxvd2x, xxswapd // 124;// P9: lxvx (even lxv) // 125;vector int fromDiffConstsConvftoi() { // 126; return (vector int) { 24.46f, 234.f, 988.19f, 422.39f }; // 127;} // 128;// P8: lxvd2x, xxswapd, xvcvspsxws // 129;// P9: lxvx, xvcvspsxws // 130;vector int fromDiffMemConsAConvftoi(float *ptr) { // 131; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 132;} // 133;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspsxws // 134;// P9: 2 x lxvx, vperm, xvcvspsxws // 135;vector int fromDiffMemConsDConvftoi(float *ptr) { // 136; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 137;} // 138;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 139;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 140;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 141;// sldi 2, load, xvcvspuxws // 142;vector int fromDiffMemVarAConvftoi(float *arr, int elem) { // 143; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 144;} // 145;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 146;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 147;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 148;// sldi 2, 2 x load, vperm, xvcvspuxws // 149;vector int fromDiffMemVarDConvftoi(float *arr, int elem) { // 150; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 151;} // 152;// P8: xscvdpsxws, xxspltw // 153;// P9: xscvdpsxws, xxspltw // 154;vector int spltRegValConvftoi(float val) { // 155; return (vector int) val; // 156;} // 157;// P8: lxsspx, xscvdpsxws, xxspltw // 158;// P9: lxvwsx, xvcvspsxws // 159;vector int spltMemValConvftoi(float *ptr) { // 160; return (vector int)*ptr; // 161;} // 162;// P8: vspltisw // 163;// P9: vspltisw // 164;vector int spltCnstConvdtoi() { // 165; return (vector int) 4.74; // 166;} // 167;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 168;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 169;vector int fromRegsConvdtoi(double a, double b, double c, double d) { // 170; return (vector int) { a, b, c, d }; // 171;} // 172;// P8: lxvd2x, xxswapd // 173;// P9: lxvx (even lxv) // 174;vector int fromDiffConstsConvdtoi() { // 175; return (vector int) { 24.46, 234., 988.19, 422.39 }; // 176;} // 177;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew // 178;// P9: 2 x lxvx, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew // 179;vector int fromDiffMemConsAConvdtoi(double *ptr) { // 180; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 181;} // 182;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 183;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 184;vector int fromDiffMemConsDConvdtoi(double *ptr) { // 185; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 186;} // 187;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 188;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 189;vector int fromDiffMemVarAConvdtoi(double *arr, int elem) { // 190; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 191;} // 192;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 193;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 194;vector int fromDiffMemVarDConvdtoi(double *arr, int elem) { // 195; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 196;} // 197;// P8: xscvdpsxws, xxspltw // 198;// P9: xscvdpsxws, xxspltw // 199;vector int spltRegValConvdtoi(double val) { // 200; return (vector int) val; // 201;} // 202;// P8: lxsdx, xscvdpsxws, xxspltw // 203;// P9: lxssp, xscvdpsxws, xxspltw // 204;vector int spltMemValConvdtoi(double *ptr) { // 205; return (vector int)*ptr; // 206;} // 207;/*=================================== int ===================================*/ 208;/*=============================== unsigned int ==============================*/ 209;// P8: xxlxor // 210;// P9: xxlxor // 211;vector unsigned int allZeroui() { // 212; return (vector unsigned int)0; // 213;} // 214;// P8: vspltisb -1 // 215;// P9: xxspltisb 255 // 216;vector unsigned int spltConst1ui() { // 217; return (vector unsigned int)1; // 218;} // 219;// P8: vspltisw -15; vsrw // 220;// P9: vspltisw -15; vsrw // 221;vector unsigned int spltConst16kui() { // 222; return (vector unsigned int)((1<<15) - 1); // 223;} // 224;// P8: vspltisw -16; vsrw // 225;// P9: vspltisw -16; vsrw // 226;vector unsigned int spltConst32kui() { // 227; return (vector unsigned int)((1<<16) - 1); // 228;} // 229;// P8: 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 230;// P9: 2 x mtvsrdd, vmrgow // 231;vector unsigned int fromRegsui(unsigned int a, unsigned int b, // 232; unsigned int c, unsigned int d) { // 233; return (vector unsigned int){ a, b, c, d }; // 234;} // 235;// P8: lxvd2x, xxswapd // 236;// P9: lxvx (or even lxv) // 237;vector unsigned int fromDiffConstsui() { // 238; return (vector unsigned int) { 242, -113, 889, 19 }; // 239;} // 240;// P8: lxvd2x, xxswapd // 241;// P9: lxvx // 242;vector unsigned int fromDiffMemConsAui(unsigned int *arr) { // 243; return (vector unsigned int) { arr[0], arr[1], arr[2], arr[3] }; // 244;} // 245;// P8: 2 x lxvd2x, 2 x xxswapd, vperm // 246;// P9: 2 x lxvx, vperm // 247;vector unsigned int fromDiffMemConsDui(unsigned int *arr) { // 248; return (vector unsigned int) { arr[3], arr[2], arr[1], arr[0] }; // 249;} // 250;// P8: sldi 2, lxvd2x, xxswapd // 251;// P9: sldi 2, lxvx // 252;vector unsigned int fromDiffMemVarAui(unsigned int *arr, int elem) { // 253; return (vector unsigned int) { arr[elem], arr[elem+1], // 254; arr[elem+2], arr[elem+3] }; // 255;} // 256;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm // 257;// P9: sldi 2, 2 x lxvx, vperm // 258;vector unsigned int fromDiffMemVarDui(unsigned int *arr, int elem) { // 259; return (vector unsigned int) { arr[elem], arr[elem-1], // 260; arr[elem-2], arr[elem-3] }; // 261;} // 262;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 263;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow // 264;vector unsigned int fromRandMemConsui(unsigned int *arr) { // 265; return (vector unsigned int) { arr[4], arr[18], arr[2], arr[88] }; // 266;} // 267;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 268;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow // 269;vector unsigned int fromRandMemVarui(unsigned int *arr, int elem) { // 270; return (vector unsigned int) { arr[elem+4], arr[elem+1], // 271; arr[elem+2], arr[elem+8] }; // 272;} // 273;// P8: mtvsrwz, xxspltw // 274;// P9: mtvsrws // 275;vector unsigned int spltRegValui(unsigned int val) { // 276; return (vector unsigned int) val; // 277;} // 278;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 279;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 280;vector unsigned int spltMemValui(unsigned int *ptr) { // 281; return (vector unsigned int)*ptr; // 282;} // 283;// P8: vspltisw // 284;// P9: vspltisw // 285;vector unsigned int spltCnstConvftoui() { // 286; return (vector unsigned int) 4.74f; // 287;} // 288;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 289;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 290;vector unsigned int fromRegsConvftoui(float a, float b, float c, float d) { // 291; return (vector unsigned int) { a, b, c, d }; // 292;} // 293;// P8: lxvd2x, xxswapd // 294;// P9: lxvx (even lxv) // 295;vector unsigned int fromDiffConstsConvftoui() { // 296; return (vector unsigned int) { 24.46f, 234.f, 988.19f, 422.39f }; // 297;} // 298;// P8: lxvd2x, xxswapd, xvcvspuxws // 299;// P9: lxvx, xvcvspuxws // 300;vector unsigned int fromDiffMemConsAConvftoui(float *ptr) { // 301; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 302;} // 303;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspuxws // 304;// P9: 2 x lxvx, vperm, xvcvspuxws // 305;vector unsigned int fromDiffMemConsDConvftoui(float *ptr) { // 306; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 307;} // 308;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 309;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 310;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 311;// sldi 2, load, xvcvspuxws // 312;vector unsigned int fromDiffMemVarAConvftoui(float *arr, int elem) { // 313; return (vector unsigned int) { arr[elem], arr[elem+1], // 314; arr[elem+2], arr[elem+3] }; // 315;} // 316;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 317;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 318;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 319;// sldi 2, 2 x load, vperm, xvcvspuxws // 320;vector unsigned int fromDiffMemVarDConvftoui(float *arr, int elem) { // 321; return (vector unsigned int) { arr[elem], arr[elem-1], // 322; arr[elem-2], arr[elem-3] }; // 323;} // 324;// P8: xscvdpuxws, xxspltw // 325;// P9: xscvdpuxws, xxspltw // 326;vector unsigned int spltRegValConvftoui(float val) { // 327; return (vector unsigned int) val; // 328;} // 329;// P8: lxsspx, xscvdpuxws, xxspltw // 330;// P9: lxvwsx, xvcvspuxws // 331;vector unsigned int spltMemValConvftoui(float *ptr) { // 332; return (vector unsigned int)*ptr; // 333;} // 334;// P8: vspltisw // 335;// P9: vspltisw // 336;vector unsigned int spltCnstConvdtoui() { // 337; return (vector unsigned int) 4.74; // 338;} // 339;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 340;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 341;vector unsigned int fromRegsConvdtoui(double a, double b, // 342; double c, double d) { // 343; return (vector unsigned int) { a, b, c, d }; // 344;} // 345;// P8: lxvd2x, xxswapd // 346;// P9: lxvx (even lxv) // 347;vector unsigned int fromDiffConstsConvdtoui() { // 348; return (vector unsigned int) { 24.46, 234., 988.19, 422.39 }; // 349;} // 350;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew // 351;// P9: 2 x lxvx, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew // 352;vector unsigned int fromDiffMemConsAConvdtoui(double *ptr) { // 353; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 354;} // 355;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 356;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 357;vector unsigned int fromDiffMemConsDConvdtoui(double *ptr) { // 358; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 359;} // 360;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 361;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 362;vector unsigned int fromDiffMemVarAConvdtoui(double *arr, int elem) { // 363; return (vector unsigned int) { arr[elem], arr[elem+1], // 364; arr[elem+2], arr[elem+3] }; // 365;} // 366;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 367;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 368;vector unsigned int fromDiffMemVarDConvdtoui(double *arr, int elem) { // 369; return (vector unsigned int) { arr[elem], arr[elem-1], // 370; arr[elem-2], arr[elem-3] }; // 371;} // 372;// P8: xscvdpuxws, xxspltw // 373;// P9: xscvdpuxws, xxspltw // 374;vector unsigned int spltRegValConvdtoui(double val) { // 375; return (vector unsigned int) val; // 376;} // 377;// P8: lxsspx, xscvdpuxws, xxspltw // 378;// P9: lfd, xscvdpuxws, xxspltw // 379;vector unsigned int spltMemValConvdtoui(double *ptr) { // 380; return (vector unsigned int)*ptr; // 381;} // 382;/*=============================== unsigned int ==============================*/ 383;/*=============================== long long =================================*/ 384;// P8: xxlxor // 385;// P9: xxlxor // 386;vector long long allZeroll() { // 387; return (vector long long)0; // 388;} // 389;// P8: vspltisb -1 // 390;// P9: xxspltisb 255 // 391;vector long long spltConst1ll() { // 392; return (vector long long)1; // 393;} // 394;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 395;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 396;vector long long spltConst16kll() { // 397; return (vector long long)((1<<15) - 1); // 398;} // 399;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 400;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 401;vector long long spltConst32kll() { // 402; return (vector long long)((1<<16) - 1); // 403;} // 404;// P8: 2 x mtvsrd, xxmrghd // 405;// P9: mtvsrdd // 406;vector long long fromRegsll(long long a, long long b) { // 407; return (vector long long){ a, b }; // 408;} // 409;// P8: lxvd2x, xxswapd // 410;// P9: lxvx (or even lxv) // 411;vector long long fromDiffConstsll() { // 412; return (vector long long) { 242, -113 }; // 413;} // 414;// P8: lxvd2x, xxswapd // 415;// P9: lxvx // 416;vector long long fromDiffMemConsAll(long long *arr) { // 417; return (vector long long) { arr[0], arr[1] }; // 418;} // 419;// P8: lxvd2x // 420;// P9: lxvx, xxswapd (maybe just use lxvd2x) // 421;vector long long fromDiffMemConsDll(long long *arr) { // 422; return (vector long long) { arr[3], arr[2] }; // 423;} // 424;// P8: sldi 3, lxvd2x, xxswapd // 425;// P9: sldi 3, lxvx // 426;vector long long fromDiffMemVarAll(long long *arr, int elem) { // 427; return (vector long long) { arr[elem], arr[elem+1] }; // 428;} // 429;// P8: sldi 3, lxvd2x // 430;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) // 431;vector long long fromDiffMemVarDll(long long *arr, int elem) { // 432; return (vector long long) { arr[elem], arr[elem-1] }; // 433;} // 434;// P8: 2 x ld, 2 x mtvsrd, xxmrghd // 435;// P9: 2 x ld, mtvsrdd // 436;vector long long fromRandMemConsll(long long *arr) { // 437; return (vector long long) { arr[4], arr[18] }; // 438;} // 439;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd // 440;// P9: sldi 3, add, 2 x ld, mtvsrdd // 441;vector long long fromRandMemVarll(long long *arr, int elem) { // 442; return (vector long long) { arr[elem+4], arr[elem+1] }; // 443;} // 444;// P8: mtvsrd, xxspltd // 445;// P9: mtvsrdd // 446;vector long long spltRegValll(long long val) { // 447; return (vector long long) val; // 448;} // 449;// P8: lxvdsx // 450;// P9: lxvdsx // 451;vector long long spltMemValll(long long *ptr) { // 452; return (vector long long)*ptr; // 453;} // 454;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 455;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 456;vector long long spltCnstConvftoll() { // 457; return (vector long long) 4.74f; // 458;} // 459;// P8: xxmrghd, xvcvdpsxds // 460;// P9: xxmrghd, xvcvdpsxds // 461;vector long long fromRegsConvftoll(float a, float b) { // 462; return (vector long long) { a, b }; // 463;} // 464;// P8: lxvd2x, xxswapd // 465;// P9: lxvx (even lxv) // 466;vector long long fromDiffConstsConvftoll() { // 467; return (vector long long) { 24.46f, 234.f }; // 468;} // 469;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds // 470;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds // 471;vector long long fromDiffMemConsAConvftoll(float *ptr) { // 472; return (vector long long) { ptr[0], ptr[1] }; // 473;} // 474;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds // 475;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds // 476;vector long long fromDiffMemConsDConvftoll(float *ptr) { // 477; return (vector long long) { ptr[3], ptr[2] }; // 478;} // 479;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds // 480;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds // 481;vector long long fromDiffMemVarAConvftoll(float *arr, int elem) { // 482; return (vector long long) { arr[elem], arr[elem+1] }; // 483;} // 484;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds // 485;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds // 486;vector long long fromDiffMemVarDConvftoll(float *arr, int elem) { // 487; return (vector long long) { arr[elem], arr[elem-1] }; // 488;} // 489;// P8: xscvdpsxds, xxspltd // 490;// P9: xscvdpsxds, xxspltd // 491;vector long long spltRegValConvftoll(float val) { // 492; return (vector long long) val; // 493;} // 494;// P8: lxsspx, xscvdpsxds, xxspltd // 495;// P9: lfs, xscvdpsxds, xxspltd // 496;vector long long spltMemValConvftoll(float *ptr) { // 497; return (vector long long)*ptr; // 498;} // 499;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 500;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 501;vector long long spltCnstConvdtoll() { // 502; return (vector long long) 4.74; // 503;} // 504;// P8: xxmrghd, xvcvdpsxds // 505;// P9: xxmrghd, xvcvdpsxds // 506;vector long long fromRegsConvdtoll(double a, double b) { // 507; return (vector long long) { a, b }; // 508;} // 509;// P8: lxvd2x, xxswapd // 510;// P9: lxvx (even lxv) // 511;vector long long fromDiffConstsConvdtoll() { // 512; return (vector long long) { 24.46, 234. }; // 513;} // 514;// P8: lxvd2x, xxswapd, xvcvdpsxds // 515;// P9: lxvx, xvcvdpsxds // 516;vector long long fromDiffMemConsAConvdtoll(double *ptr) { // 517; return (vector long long) { ptr[0], ptr[1] }; // 518;} // 519;// P8: lxvd2x, xvcvdpsxds // 520;// P9: lxvx, xxswapd, xvcvdpsxds // 521;vector long long fromDiffMemConsDConvdtoll(double *ptr) { // 522; return (vector long long) { ptr[3], ptr[2] }; // 523;} // 524;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpsxds // 525;// P9: sldi 3, lxvx, xvcvdpsxds // 526;vector long long fromDiffMemVarAConvdtoll(double *arr, int elem) { // 527; return (vector long long) { arr[elem], arr[elem+1] }; // 528;} // 529;// P8: sldi 3, lxvd2x, xvcvdpsxds // 530;// P9: sldi 3, lxvx, xxswapd, xvcvdpsxds // 531;vector long long fromDiffMemVarDConvdtoll(double *arr, int elem) { // 532; return (vector long long) { arr[elem], arr[elem-1] }; // 533;} // 534;// P8: xscvdpsxds, xxspltd // 535;// P9: xscvdpsxds, xxspltd // 536;vector long long spltRegValConvdtoll(double val) { // 537; return (vector long long) val; // 538;} // 539;// P8: lxvdsx, xvcvdpsxds // 540;// P9: lxvdsx, xvcvdpsxds // 541;vector long long spltMemValConvdtoll(double *ptr) { // 542; return (vector long long)*ptr; // 543;} // 544;/*=============================== long long =================================*/ 545;/*========================== unsigned long long =============================*/ 546;// P8: xxlxor // 547;// P9: xxlxor // 548;vector unsigned long long allZeroull() { // 549; return (vector unsigned long long)0; // 550;} // 551;// P8: vspltisb -1 // 552;// P9: xxspltisb 255 // 553;vector unsigned long long spltConst1ull() { // 554; return (vector unsigned long long)1; // 555;} // 556;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 557;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 558;vector unsigned long long spltConst16kull() { // 559; return (vector unsigned long long)((1<<15) - 1); // 560;} // 561;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 562;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 563;vector unsigned long long spltConst32kull() { // 564; return (vector unsigned long long)((1<<16) - 1); // 565;} // 566;// P8: 2 x mtvsrd, xxmrghd // 567;// P9: mtvsrdd // 568;vector unsigned long long fromRegsull(unsigned long long a, // 569; unsigned long long b) { // 570; return (vector unsigned long long){ a, b }; // 571;} // 572;// P8: lxvd2x, xxswapd // 573;// P9: lxvx (or even lxv) // 574;vector unsigned long long fromDiffConstsull() { // 575; return (vector unsigned long long) { 242, -113 }; // 576;} // 577;// P8: lxvd2x, xxswapd // 578;// P9: lxvx // 579;vector unsigned long long fromDiffMemConsAull(unsigned long long *arr) { // 580; return (vector unsigned long long) { arr[0], arr[1] }; // 581;} // 582;// P8: lxvd2x // 583;// P9: lxvx, xxswapd (maybe just use lxvd2x) // 584;vector unsigned long long fromDiffMemConsDull(unsigned long long *arr) { // 585; return (vector unsigned long long) { arr[3], arr[2] }; // 586;} // 587;// P8: sldi 3, lxvd2x, xxswapd // 588;// P9: sldi 3, lxvx // 589;vector unsigned long long fromDiffMemVarAull(unsigned long long *arr, // 590; int elem) { // 591; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 592;} // 593;// P8: sldi 3, lxvd2x // 594;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) // 595;vector unsigned long long fromDiffMemVarDull(unsigned long long *arr, // 596; int elem) { // 597; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 598;} // 599;// P8: 2 x ld, 2 x mtvsrd, xxmrghd // 600;// P9: 2 x ld, mtvsrdd // 601;vector unsigned long long fromRandMemConsull(unsigned long long *arr) { // 602; return (vector unsigned long long) { arr[4], arr[18] }; // 603;} // 604;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd // 605;// P9: sldi 3, add, 2 x ld, mtvsrdd // 606;vector unsigned long long fromRandMemVarull(unsigned long long *arr, // 607; int elem) { // 608; return (vector unsigned long long) { arr[elem+4], arr[elem+1] }; // 609;} // 610;// P8: mtvsrd, xxspltd // 611;// P9: mtvsrdd // 612;vector unsigned long long spltRegValull(unsigned long long val) { // 613; return (vector unsigned long long) val; // 614;} // 615;// P8: lxvdsx // 616;// P9: lxvdsx // 617;vector unsigned long long spltMemValull(unsigned long long *ptr) { // 618; return (vector unsigned long long)*ptr; // 619;} // 620;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 621;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 622;vector unsigned long long spltCnstConvftoull() { // 623; return (vector unsigned long long) 4.74f; // 624;} // 625;// P8: xxmrghd, xvcvdpuxds // 626;// P9: xxmrghd, xvcvdpuxds // 627;vector unsigned long long fromRegsConvftoull(float a, float b) { // 628; return (vector unsigned long long) { a, b }; // 629;} // 630;// P8: lxvd2x, xxswapd // 631;// P9: lxvx (even lxv) // 632;vector unsigned long long fromDiffConstsConvftoull() { // 633; return (vector unsigned long long) { 24.46f, 234.f }; // 634;} // 635;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds // 636;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds // 637;vector unsigned long long fromDiffMemConsAConvftoull(float *ptr) { // 638; return (vector unsigned long long) { ptr[0], ptr[1] }; // 639;} // 640;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds // 641;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds // 642;vector unsigned long long fromDiffMemConsDConvftoull(float *ptr) { // 643; return (vector unsigned long long) { ptr[3], ptr[2] }; // 644;} // 645;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds // 646;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds // 647;vector unsigned long long fromDiffMemVarAConvftoull(float *arr, int elem) { // 648; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 649;} // 650;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds // 651;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds // 652;vector unsigned long long fromDiffMemVarDConvftoull(float *arr, int elem) { // 653; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 654;} // 655;// P8: xscvdpuxds, xxspltd // 656;// P9: xscvdpuxds, xxspltd // 657;vector unsigned long long spltRegValConvftoull(float val) { // 658; return (vector unsigned long long) val; // 659;} // 660;// P8: lxsspx, xscvdpuxds, xxspltd // 661;// P9: lfs, xscvdpuxds, xxspltd // 662;vector unsigned long long spltMemValConvftoull(float *ptr) { // 663; return (vector unsigned long long)*ptr; // 664;} // 665;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 666;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 667;vector unsigned long long spltCnstConvdtoull() { // 668; return (vector unsigned long long) 4.74; // 669;} // 670;// P8: xxmrghd, xvcvdpuxds // 671;// P9: xxmrghd, xvcvdpuxds // 672;vector unsigned long long fromRegsConvdtoull(double a, double b) { // 673; return (vector unsigned long long) { a, b }; // 674;} // 675;// P8: lxvd2x, xxswapd // 676;// P9: lxvx (even lxv) // 677;vector unsigned long long fromDiffConstsConvdtoull() { // 678; return (vector unsigned long long) { 24.46, 234. }; // 679;} // 680;// P8: lxvd2x, xxswapd, xvcvdpuxds // 681;// P9: lxvx, xvcvdpuxds // 682;vector unsigned long long fromDiffMemConsAConvdtoull(double *ptr) { // 683; return (vector unsigned long long) { ptr[0], ptr[1] }; // 684;} // 685;// P8: lxvd2x, xvcvdpuxds // 686;// P9: lxvx, xxswapd, xvcvdpuxds // 687;vector unsigned long long fromDiffMemConsDConvdtoull(double *ptr) { // 688; return (vector unsigned long long) { ptr[3], ptr[2] }; // 689;} // 690;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpuxds // 691;// P9: sldi 3, lxvx, xvcvdpuxds // 692;vector unsigned long long fromDiffMemVarAConvdtoull(double *arr, int elem) { // 693; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 694;} // 695;// P8: sldi 3, lxvd2x, xvcvdpuxds // 696;// P9: sldi 3, lxvx, xxswapd, xvcvdpuxds // 697;vector unsigned long long fromDiffMemVarDConvdtoull(double *arr, int elem) { // 698; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 699;} // 700;// P8: xscvdpuxds, xxspltd // 701;// P9: xscvdpuxds, xxspltd // 702;vector unsigned long long spltRegValConvdtoull(double val) { // 703; return (vector unsigned long long) val; // 704;} // 705;// P8: lxvdsx, xvcvdpuxds // 706;// P9: lxvdsx, xvcvdpuxds // 707;vector unsigned long long spltMemValConvdtoull(double *ptr) { // 708; return (vector unsigned long long)*ptr; // 709;} // 710;/*========================== unsigned long long ==============================*/ 711 712define <4 x i32> @allZeroi() { 713; P9BE-LABEL: allZeroi: 714; P9BE: # %bb.0: # %entry 715; P9BE-NEXT: xxlxor v2, v2, v2 716; P9BE-NEXT: blr 717; 718; P9LE-LABEL: allZeroi: 719; P9LE: # %bb.0: # %entry 720; P9LE-NEXT: xxlxor v2, v2, v2 721; P9LE-NEXT: blr 722; 723; P8BE-LABEL: allZeroi: 724; P8BE: # %bb.0: # %entry 725; P8BE-NEXT: xxlxor v2, v2, v2 726; P8BE-NEXT: blr 727; 728; P8LE-LABEL: allZeroi: 729; P8LE: # %bb.0: # %entry 730; P8LE-NEXT: xxlxor v2, v2, v2 731; P8LE-NEXT: blr 732entry: 733 ret <4 x i32> zeroinitializer 734} 735 736define <4 x i32> @spltConst1i() { 737; P9BE-LABEL: spltConst1i: 738; P9BE: # %bb.0: # %entry 739; P9BE-NEXT: vspltisw v2, 1 740; P9BE-NEXT: blr 741; 742; P9LE-LABEL: spltConst1i: 743; P9LE: # %bb.0: # %entry 744; P9LE-NEXT: vspltisw v2, 1 745; P9LE-NEXT: blr 746; 747; P8BE-LABEL: spltConst1i: 748; P8BE: # %bb.0: # %entry 749; P8BE-NEXT: vspltisw v2, 1 750; P8BE-NEXT: blr 751; 752; P8LE-LABEL: spltConst1i: 753; P8LE: # %bb.0: # %entry 754; P8LE-NEXT: vspltisw v2, 1 755; P8LE-NEXT: blr 756entry: 757 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1> 758} 759 760define <4 x i32> @spltConst16ki() { 761; P9BE-LABEL: spltConst16ki: 762; P9BE: # %bb.0: # %entry 763; P9BE-NEXT: vspltisw v2, -15 764; P9BE-NEXT: vsrw v2, v2, v2 765; P9BE-NEXT: blr 766; 767; P9LE-LABEL: spltConst16ki: 768; P9LE: # %bb.0: # %entry 769; P9LE-NEXT: vspltisw v2, -15 770; P9LE-NEXT: vsrw v2, v2, v2 771; P9LE-NEXT: blr 772; 773; P8BE-LABEL: spltConst16ki: 774; P8BE: # %bb.0: # %entry 775; P8BE-NEXT: vspltisw v2, -15 776; P8BE-NEXT: vsrw v2, v2, v2 777; P8BE-NEXT: blr 778; 779; P8LE-LABEL: spltConst16ki: 780; P8LE: # %bb.0: # %entry 781; P8LE-NEXT: vspltisw v2, -15 782; P8LE-NEXT: vsrw v2, v2, v2 783; P8LE-NEXT: blr 784entry: 785 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 786} 787 788define <4 x i32> @spltConst32ki() { 789; P9BE-LABEL: spltConst32ki: 790; P9BE: # %bb.0: # %entry 791; P9BE-NEXT: vspltisw v2, -16 792; P9BE-NEXT: vsrw v2, v2, v2 793; P9BE-NEXT: blr 794; 795; P9LE-LABEL: spltConst32ki: 796; P9LE: # %bb.0: # %entry 797; P9LE-NEXT: vspltisw v2, -16 798; P9LE-NEXT: vsrw v2, v2, v2 799; P9LE-NEXT: blr 800; 801; P8BE-LABEL: spltConst32ki: 802; P8BE: # %bb.0: # %entry 803; P8BE-NEXT: vspltisw v2, -16 804; P8BE-NEXT: vsrw v2, v2, v2 805; P8BE-NEXT: blr 806; 807; P8LE-LABEL: spltConst32ki: 808; P8LE: # %bb.0: # %entry 809; P8LE-NEXT: vspltisw v2, -16 810; P8LE-NEXT: vsrw v2, v2, v2 811; P8LE-NEXT: blr 812entry: 813 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 814} 815 816define <4 x i32> @fromRegsi(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) { 817; P9BE-LABEL: fromRegsi: 818; P9BE: # %bb.0: # %entry 819; P9BE-NEXT: rldimi r6, r5, 32, 0 820; P9BE-NEXT: rldimi r4, r3, 32, 0 821; P9BE-NEXT: mtvsrdd v2, r4, r6 822; P9BE-NEXT: blr 823; 824; P9LE-LABEL: fromRegsi: 825; P9LE: # %bb.0: # %entry 826; P9LE-NEXT: rldimi r3, r4, 32, 0 827; P9LE-NEXT: rldimi r5, r6, 32, 0 828; P9LE-NEXT: mtvsrdd v2, r5, r3 829; P9LE-NEXT: blr 830; 831; P8BE-LABEL: fromRegsi: 832; P8BE: # %bb.0: # %entry 833; P8BE-NEXT: rldimi r6, r5, 32, 0 834; P8BE-NEXT: rldimi r4, r3, 32, 0 835; P8BE-NEXT: mtfprd f0, r6 836; P8BE-NEXT: mtfprd f1, r4 837; P8BE-NEXT: xxmrghd v2, vs1, vs0 838; P8BE-NEXT: blr 839; 840; P8LE-LABEL: fromRegsi: 841; P8LE: # %bb.0: # %entry 842; P8LE-NEXT: rldimi r3, r4, 32, 0 843; P8LE-NEXT: rldimi r5, r6, 32, 0 844; P8LE-NEXT: mtfprd f0, r3 845; P8LE-NEXT: mtfprd f1, r5 846; P8LE-NEXT: xxmrghd v2, vs1, vs0 847; P8LE-NEXT: blr 848entry: 849 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 850 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 851 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 852 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3 853 ret <4 x i32> %vecinit3 854} 855 856define <4 x i32> @fromDiffConstsi() { 857; P9BE-LABEL: fromDiffConstsi: 858; P9BE: # %bb.0: # %entry 859; P9BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha 860; P9BE-NEXT: addi r3, r3, .LCPI5_0@toc@l 861; P9BE-NEXT: lxv v2, 0(r3) 862; P9BE-NEXT: blr 863; 864; P9LE-LABEL: fromDiffConstsi: 865; P9LE: # %bb.0: # %entry 866; P9LE-NEXT: addis r3, r2, .LCPI5_0@toc@ha 867; P9LE-NEXT: addi r3, r3, .LCPI5_0@toc@l 868; P9LE-NEXT: lxv v2, 0(r3) 869; P9LE-NEXT: blr 870; 871; P8BE-LABEL: fromDiffConstsi: 872; P8BE: # %bb.0: # %entry 873; P8BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha 874; P8BE-NEXT: addi r3, r3, .LCPI5_0@toc@l 875; P8BE-NEXT: lxvw4x v2, 0, r3 876; P8BE-NEXT: blr 877; 878; P8LE-LABEL: fromDiffConstsi: 879; P8LE: # %bb.0: # %entry 880; P8LE-NEXT: addis r3, r2, .LCPI5_0@toc@ha 881; P8LE-NEXT: addi r3, r3, .LCPI5_0@toc@l 882; P8LE-NEXT: lvx v2, 0, r3 883; P8LE-NEXT: blr 884entry: 885 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19> 886} 887 888define <4 x i32> @fromDiffMemConsAi(i32* nocapture readonly %arr) { 889; P9BE-LABEL: fromDiffMemConsAi: 890; P9BE: # %bb.0: # %entry 891; P9BE-NEXT: lxv v2, 0(r3) 892; P9BE-NEXT: blr 893; 894; P9LE-LABEL: fromDiffMemConsAi: 895; P9LE: # %bb.0: # %entry 896; P9LE-NEXT: lxv v2, 0(r3) 897; P9LE-NEXT: blr 898; 899; P8BE-LABEL: fromDiffMemConsAi: 900; P8BE: # %bb.0: # %entry 901; P8BE-NEXT: lxvw4x v2, 0, r3 902; P8BE-NEXT: blr 903; 904; P8LE-LABEL: fromDiffMemConsAi: 905; P8LE: # %bb.0: # %entry 906; P8LE-NEXT: lxvd2x vs0, 0, r3 907; P8LE-NEXT: xxswapd v2, vs0 908; P8LE-NEXT: blr 909entry: 910 %0 = load i32, i32* %arr, align 4 911 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 912 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 1 913 %1 = load i32, i32* %arrayidx1, align 4 914 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 915 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 916 %2 = load i32, i32* %arrayidx3, align 4 917 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 918 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 3 919 %3 = load i32, i32* %arrayidx5, align 4 920 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 921 ret <4 x i32> %vecinit6 922} 923 924define <4 x i32> @fromDiffMemConsDi(i32* nocapture readonly %arr) { 925; P9BE-LABEL: fromDiffMemConsDi: 926; P9BE: # %bb.0: # %entry 927; P9BE-NEXT: lxv v2, 0(r3) 928; P9BE-NEXT: addis r3, r2, .LCPI7_0@toc@ha 929; P9BE-NEXT: addi r3, r3, .LCPI7_0@toc@l 930; P9BE-NEXT: lxv v3, 0(r3) 931; P9BE-NEXT: vperm v2, v2, v2, v3 932; P9BE-NEXT: blr 933; 934; P9LE-LABEL: fromDiffMemConsDi: 935; P9LE: # %bb.0: # %entry 936; P9LE-NEXT: lxvw4x v2, 0, r3 937; P9LE-NEXT: blr 938; 939; P8BE-LABEL: fromDiffMemConsDi: 940; P8BE: # %bb.0: # %entry 941; P8BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha 942; P8BE-NEXT: lxvw4x v2, 0, r3 943; P8BE-NEXT: addi r4, r4, .LCPI7_0@toc@l 944; P8BE-NEXT: lxvw4x v3, 0, r4 945; P8BE-NEXT: vperm v2, v2, v2, v3 946; P8BE-NEXT: blr 947; 948; P8LE-LABEL: fromDiffMemConsDi: 949; P8LE: # %bb.0: # %entry 950; P8LE-NEXT: lxvd2x vs0, 0, r3 951; P8LE-NEXT: addis r4, r2, .LCPI7_0@toc@ha 952; P8LE-NEXT: addi r3, r4, .LCPI7_0@toc@l 953; P8LE-NEXT: lvx v2, 0, r3 954; P8LE-NEXT: xxswapd v3, vs0 955; P8LE-NEXT: vperm v2, v3, v3, v2 956; P8LE-NEXT: blr 957entry: 958 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3 959 %0 = load i32, i32* %arrayidx, align 4 960 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 961 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 962 %1 = load i32, i32* %arrayidx1, align 4 963 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 964 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 1 965 %2 = load i32, i32* %arrayidx3, align 4 966 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 967 %3 = load i32, i32* %arr, align 4 968 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 969 ret <4 x i32> %vecinit6 970} 971 972define <4 x i32> @fromDiffMemVarAi(i32* nocapture readonly %arr, i32 signext %elem) { 973; P9BE-LABEL: fromDiffMemVarAi: 974; P9BE: # %bb.0: # %entry 975; P9BE-NEXT: sldi r4, r4, 2 976; P9BE-NEXT: lxvx v2, r3, r4 977; P9BE-NEXT: blr 978; 979; P9LE-LABEL: fromDiffMemVarAi: 980; P9LE: # %bb.0: # %entry 981; P9LE-NEXT: sldi r4, r4, 2 982; P9LE-NEXT: lxvx v2, r3, r4 983; P9LE-NEXT: blr 984; 985; P8BE-LABEL: fromDiffMemVarAi: 986; P8BE: # %bb.0: # %entry 987; P8BE-NEXT: sldi r4, r4, 2 988; P8BE-NEXT: lxvw4x v2, r3, r4 989; P8BE-NEXT: blr 990; 991; P8LE-LABEL: fromDiffMemVarAi: 992; P8LE: # %bb.0: # %entry 993; P8LE-NEXT: sldi r4, r4, 2 994; P8LE-NEXT: lxvd2x vs0, r3, r4 995; P8LE-NEXT: xxswapd v2, vs0 996; P8LE-NEXT: blr 997entry: 998 %idxprom = sext i32 %elem to i64 999 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 1000 %0 = load i32, i32* %arrayidx, align 4 1001 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1002 %add = add nsw i32 %elem, 1 1003 %idxprom1 = sext i32 %add to i64 1004 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 1005 %1 = load i32, i32* %arrayidx2, align 4 1006 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1007 %add4 = add nsw i32 %elem, 2 1008 %idxprom5 = sext i32 %add4 to i64 1009 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 1010 %2 = load i32, i32* %arrayidx6, align 4 1011 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 1012 %add8 = add nsw i32 %elem, 3 1013 %idxprom9 = sext i32 %add8 to i64 1014 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 1015 %3 = load i32, i32* %arrayidx10, align 4 1016 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 1017 ret <4 x i32> %vecinit11 1018} 1019 1020define <4 x i32> @fromDiffMemVarDi(i32* nocapture readonly %arr, i32 signext %elem) { 1021; P9BE-LABEL: fromDiffMemVarDi: 1022; P9BE: # %bb.0: # %entry 1023; P9BE-NEXT: sldi r4, r4, 2 1024; P9BE-NEXT: add r3, r3, r4 1025; P9BE-NEXT: li r4, -12 1026; P9BE-NEXT: lxvx v2, r3, r4 1027; P9BE-NEXT: addis r3, r2, .LCPI9_0@toc@ha 1028; P9BE-NEXT: addi r3, r3, .LCPI9_0@toc@l 1029; P9BE-NEXT: lxv v3, 0(r3) 1030; P9BE-NEXT: vperm v2, v2, v2, v3 1031; P9BE-NEXT: blr 1032; 1033; P9LE-LABEL: fromDiffMemVarDi: 1034; P9LE: # %bb.0: # %entry 1035; P9LE-NEXT: sldi r4, r4, 2 1036; P9LE-NEXT: add r3, r3, r4 1037; P9LE-NEXT: li r4, -12 1038; P9LE-NEXT: lxvx v2, r3, r4 1039; P9LE-NEXT: addis r3, r2, .LCPI9_0@toc@ha 1040; P9LE-NEXT: addi r3, r3, .LCPI9_0@toc@l 1041; P9LE-NEXT: lxv v3, 0(r3) 1042; P9LE-NEXT: vperm v2, v2, v2, v3 1043; P9LE-NEXT: blr 1044; 1045; P8BE-LABEL: fromDiffMemVarDi: 1046; P8BE: # %bb.0: # %entry 1047; P8BE-NEXT: sldi r4, r4, 2 1048; P8BE-NEXT: addis r5, r2, .LCPI9_0@toc@ha 1049; P8BE-NEXT: add r3, r3, r4 1050; P8BE-NEXT: addi r4, r5, .LCPI9_0@toc@l 1051; P8BE-NEXT: addi r3, r3, -12 1052; P8BE-NEXT: lxvw4x v3, 0, r4 1053; P8BE-NEXT: lxvw4x v2, 0, r3 1054; P8BE-NEXT: vperm v2, v2, v2, v3 1055; P8BE-NEXT: blr 1056; 1057; P8LE-LABEL: fromDiffMemVarDi: 1058; P8LE: # %bb.0: # %entry 1059; P8LE-NEXT: sldi r4, r4, 2 1060; P8LE-NEXT: addis r5, r2, .LCPI9_0@toc@ha 1061; P8LE-NEXT: add r3, r3, r4 1062; P8LE-NEXT: addi r3, r3, -12 1063; P8LE-NEXT: lxvd2x vs0, 0, r3 1064; P8LE-NEXT: addi r3, r5, .LCPI9_0@toc@l 1065; P8LE-NEXT: lvx v3, 0, r3 1066; P8LE-NEXT: xxswapd v2, vs0 1067; P8LE-NEXT: vperm v2, v2, v2, v3 1068; P8LE-NEXT: blr 1069entry: 1070 %idxprom = sext i32 %elem to i64 1071 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 1072 %0 = load i32, i32* %arrayidx, align 4 1073 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1074 %sub = add nsw i32 %elem, -1 1075 %idxprom1 = sext i32 %sub to i64 1076 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 1077 %1 = load i32, i32* %arrayidx2, align 4 1078 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1079 %sub4 = add nsw i32 %elem, -2 1080 %idxprom5 = sext i32 %sub4 to i64 1081 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 1082 %2 = load i32, i32* %arrayidx6, align 4 1083 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 1084 %sub8 = add nsw i32 %elem, -3 1085 %idxprom9 = sext i32 %sub8 to i64 1086 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 1087 %3 = load i32, i32* %arrayidx10, align 4 1088 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 1089 ret <4 x i32> %vecinit11 1090} 1091 1092define <4 x i32> @fromRandMemConsi(i32* nocapture readonly %arr) { 1093; P9BE-LABEL: fromRandMemConsi: 1094; P9BE: # %bb.0: # %entry 1095; P9BE-NEXT: lwz r4, 16(r3) 1096; P9BE-NEXT: lwz r5, 72(r3) 1097; P9BE-NEXT: lwz r6, 8(r3) 1098; P9BE-NEXT: lwz r3, 352(r3) 1099; P9BE-NEXT: rldimi r3, r6, 32, 0 1100; P9BE-NEXT: rldimi r5, r4, 32, 0 1101; P9BE-NEXT: mtvsrdd v2, r5, r3 1102; P9BE-NEXT: blr 1103; 1104; P9LE-LABEL: fromRandMemConsi: 1105; P9LE: # %bb.0: # %entry 1106; P9LE-NEXT: lwz r4, 16(r3) 1107; P9LE-NEXT: lwz r5, 72(r3) 1108; P9LE-NEXT: lwz r6, 8(r3) 1109; P9LE-NEXT: lwz r3, 352(r3) 1110; P9LE-NEXT: rldimi r4, r5, 32, 0 1111; P9LE-NEXT: rldimi r6, r3, 32, 0 1112; P9LE-NEXT: mtvsrdd v2, r6, r4 1113; P9LE-NEXT: blr 1114; 1115; P8BE-LABEL: fromRandMemConsi: 1116; P8BE: # %bb.0: # %entry 1117; P8BE-NEXT: lwz r4, 8(r3) 1118; P8BE-NEXT: lwz r5, 352(r3) 1119; P8BE-NEXT: lwz r6, 16(r3) 1120; P8BE-NEXT: lwz r3, 72(r3) 1121; P8BE-NEXT: rldimi r5, r4, 32, 0 1122; P8BE-NEXT: rldimi r3, r6, 32, 0 1123; P8BE-NEXT: mtfprd f0, r5 1124; P8BE-NEXT: mtfprd f1, r3 1125; P8BE-NEXT: xxmrghd v2, vs1, vs0 1126; P8BE-NEXT: blr 1127; 1128; P8LE-LABEL: fromRandMemConsi: 1129; P8LE: # %bb.0: # %entry 1130; P8LE-NEXT: lwz r4, 16(r3) 1131; P8LE-NEXT: lwz r5, 72(r3) 1132; P8LE-NEXT: lwz r6, 8(r3) 1133; P8LE-NEXT: lwz r3, 352(r3) 1134; P8LE-NEXT: rldimi r4, r5, 32, 0 1135; P8LE-NEXT: rldimi r6, r3, 32, 0 1136; P8LE-NEXT: mtfprd f0, r4 1137; P8LE-NEXT: mtfprd f1, r6 1138; P8LE-NEXT: xxmrghd v2, vs1, vs0 1139; P8LE-NEXT: blr 1140entry: 1141 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4 1142 %0 = load i32, i32* %arrayidx, align 4 1143 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1144 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18 1145 %1 = load i32, i32* %arrayidx1, align 4 1146 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1147 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 1148 %2 = load i32, i32* %arrayidx3, align 4 1149 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 1150 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 88 1151 %3 = load i32, i32* %arrayidx5, align 4 1152 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 1153 ret <4 x i32> %vecinit6 1154} 1155 1156define <4 x i32> @fromRandMemVari(i32* nocapture readonly %arr, i32 signext %elem) { 1157; P9BE-LABEL: fromRandMemVari: 1158; P9BE: # %bb.0: # %entry 1159; P9BE-NEXT: sldi r4, r4, 2 1160; P9BE-NEXT: add r3, r3, r4 1161; P9BE-NEXT: lwz r4, 16(r3) 1162; P9BE-NEXT: lwz r5, 4(r3) 1163; P9BE-NEXT: lwz r6, 8(r3) 1164; P9BE-NEXT: lwz r3, 32(r3) 1165; P9BE-NEXT: rldimi r3, r6, 32, 0 1166; P9BE-NEXT: rldimi r5, r4, 32, 0 1167; P9BE-NEXT: mtvsrdd v2, r5, r3 1168; P9BE-NEXT: blr 1169; 1170; P9LE-LABEL: fromRandMemVari: 1171; P9LE: # %bb.0: # %entry 1172; P9LE-NEXT: sldi r4, r4, 2 1173; P9LE-NEXT: add r3, r3, r4 1174; P9LE-NEXT: lwz r4, 16(r3) 1175; P9LE-NEXT: lwz r5, 4(r3) 1176; P9LE-NEXT: lwz r6, 8(r3) 1177; P9LE-NEXT: lwz r3, 32(r3) 1178; P9LE-NEXT: rldimi r4, r5, 32, 0 1179; P9LE-NEXT: rldimi r6, r3, 32, 0 1180; P9LE-NEXT: mtvsrdd v2, r6, r4 1181; P9LE-NEXT: blr 1182; 1183; P8BE-LABEL: fromRandMemVari: 1184; P8BE: # %bb.0: # %entry 1185; P8BE-NEXT: sldi r4, r4, 2 1186; P8BE-NEXT: add r3, r3, r4 1187; P8BE-NEXT: lwz r4, 8(r3) 1188; P8BE-NEXT: lwz r5, 32(r3) 1189; P8BE-NEXT: lwz r6, 16(r3) 1190; P8BE-NEXT: lwz r3, 4(r3) 1191; P8BE-NEXT: rldimi r5, r4, 32, 0 1192; P8BE-NEXT: rldimi r3, r6, 32, 0 1193; P8BE-NEXT: mtfprd f0, r5 1194; P8BE-NEXT: mtfprd f1, r3 1195; P8BE-NEXT: xxmrghd v2, vs1, vs0 1196; P8BE-NEXT: blr 1197; 1198; P8LE-LABEL: fromRandMemVari: 1199; P8LE: # %bb.0: # %entry 1200; P8LE-NEXT: sldi r4, r4, 2 1201; P8LE-NEXT: add r3, r3, r4 1202; P8LE-NEXT: lwz r4, 16(r3) 1203; P8LE-NEXT: lwz r5, 4(r3) 1204; P8LE-NEXT: lwz r6, 8(r3) 1205; P8LE-NEXT: lwz r3, 32(r3) 1206; P8LE-NEXT: rldimi r4, r5, 32, 0 1207; P8LE-NEXT: rldimi r6, r3, 32, 0 1208; P8LE-NEXT: mtfprd f0, r4 1209; P8LE-NEXT: mtfprd f1, r6 1210; P8LE-NEXT: xxmrghd v2, vs1, vs0 1211; P8LE-NEXT: blr 1212entry: 1213 %add = add nsw i32 %elem, 4 1214 %idxprom = sext i32 %add to i64 1215 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 1216 %0 = load i32, i32* %arrayidx, align 4 1217 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1218 %add1 = add nsw i32 %elem, 1 1219 %idxprom2 = sext i32 %add1 to i64 1220 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 %idxprom2 1221 %1 = load i32, i32* %arrayidx3, align 4 1222 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1223 %add5 = add nsw i32 %elem, 2 1224 %idxprom6 = sext i32 %add5 to i64 1225 %arrayidx7 = getelementptr inbounds i32, i32* %arr, i64 %idxprom6 1226 %2 = load i32, i32* %arrayidx7, align 4 1227 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2 1228 %add9 = add nsw i32 %elem, 8 1229 %idxprom10 = sext i32 %add9 to i64 1230 %arrayidx11 = getelementptr inbounds i32, i32* %arr, i64 %idxprom10 1231 %3 = load i32, i32* %arrayidx11, align 4 1232 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3 1233 ret <4 x i32> %vecinit12 1234} 1235 1236define <4 x i32> @spltRegVali(i32 signext %val) { 1237; P9BE-LABEL: spltRegVali: 1238; P9BE: # %bb.0: # %entry 1239; P9BE-NEXT: mtvsrws v2, r3 1240; P9BE-NEXT: blr 1241; 1242; P9LE-LABEL: spltRegVali: 1243; P9LE: # %bb.0: # %entry 1244; P9LE-NEXT: mtvsrws v2, r3 1245; P9LE-NEXT: blr 1246; 1247; P8BE-LABEL: spltRegVali: 1248; P8BE: # %bb.0: # %entry 1249; P8BE-NEXT: mtfprwz f0, r3 1250; P8BE-NEXT: xxspltw v2, vs0, 1 1251; P8BE-NEXT: blr 1252; 1253; P8LE-LABEL: spltRegVali: 1254; P8LE: # %bb.0: # %entry 1255; P8LE-NEXT: mtfprwz f0, r3 1256; P8LE-NEXT: xxspltw v2, vs0, 1 1257; P8LE-NEXT: blr 1258entry: 1259 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0 1260 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1261 ret <4 x i32> %splat.splat 1262} 1263 1264define <4 x i32> @spltMemVali(i32* nocapture readonly %ptr) { 1265; P9BE-LABEL: spltMemVali: 1266; P9BE: # %bb.0: # %entry 1267; P9BE-NEXT: lxvwsx v2, 0, r3 1268; P9BE-NEXT: blr 1269; 1270; P9LE-LABEL: spltMemVali: 1271; P9LE: # %bb.0: # %entry 1272; P9LE-NEXT: lxvwsx v2, 0, r3 1273; P9LE-NEXT: blr 1274; 1275; P8BE-LABEL: spltMemVali: 1276; P8BE: # %bb.0: # %entry 1277; P8BE-NEXT: lfiwzx f0, 0, r3 1278; P8BE-NEXT: xxspltw v2, vs0, 1 1279; P8BE-NEXT: blr 1280; 1281; P8LE-LABEL: spltMemVali: 1282; P8LE: # %bb.0: # %entry 1283; P8LE-NEXT: lfiwzx f0, 0, r3 1284; P8LE-NEXT: xxspltw v2, vs0, 1 1285; P8LE-NEXT: blr 1286entry: 1287 %0 = load i32, i32* %ptr, align 4 1288 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 1289 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1290 ret <4 x i32> %splat.splat 1291} 1292 1293define <4 x i32> @spltCnstConvftoi() { 1294; P9BE-LABEL: spltCnstConvftoi: 1295; P9BE: # %bb.0: # %entry 1296; P9BE-NEXT: vspltisw v2, 4 1297; P9BE-NEXT: blr 1298; 1299; P9LE-LABEL: spltCnstConvftoi: 1300; P9LE: # %bb.0: # %entry 1301; P9LE-NEXT: vspltisw v2, 4 1302; P9LE-NEXT: blr 1303; 1304; P8BE-LABEL: spltCnstConvftoi: 1305; P8BE: # %bb.0: # %entry 1306; P8BE-NEXT: vspltisw v2, 4 1307; P8BE-NEXT: blr 1308; 1309; P8LE-LABEL: spltCnstConvftoi: 1310; P8LE: # %bb.0: # %entry 1311; P8LE-NEXT: vspltisw v2, 4 1312; P8LE-NEXT: blr 1313entry: 1314 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 1315} 1316 1317define <4 x i32> @fromRegsConvftoi(float %a, float %b, float %c, float %d) { 1318; P9BE-LABEL: fromRegsConvftoi: 1319; P9BE: # %bb.0: # %entry 1320; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1321; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1322; P9BE-NEXT: xxmrghd vs0, vs2, vs4 1323; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1324; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1325; P9BE-NEXT: xvcvdpsxws v2, vs0 1326; P9BE-NEXT: xxmrghd vs0, vs1, vs3 1327; P9BE-NEXT: xvcvdpsxws v3, vs0 1328; P9BE-NEXT: vmrgew v2, v3, v2 1329; P9BE-NEXT: blr 1330; 1331; P9LE-LABEL: fromRegsConvftoi: 1332; P9LE: # %bb.0: # %entry 1333; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1334; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1335; P9LE-NEXT: xxmrghd vs0, vs3, vs1 1336; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1337; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1338; P9LE-NEXT: xvcvdpsxws v2, vs0 1339; P9LE-NEXT: xxmrghd vs0, vs4, vs2 1340; P9LE-NEXT: xvcvdpsxws v3, vs0 1341; P9LE-NEXT: vmrgew v2, v3, v2 1342; P9LE-NEXT: blr 1343; 1344; P8BE-LABEL: fromRegsConvftoi: 1345; P8BE: # %bb.0: # %entry 1346; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1347; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1348; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1349; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1350; P8BE-NEXT: xxmrghd vs0, vs2, vs4 1351; P8BE-NEXT: xxmrghd vs1, vs1, vs3 1352; P8BE-NEXT: xvcvdpsxws v2, vs0 1353; P8BE-NEXT: xvcvdpsxws v3, vs1 1354; P8BE-NEXT: vmrgew v2, v3, v2 1355; P8BE-NEXT: blr 1356; 1357; P8LE-LABEL: fromRegsConvftoi: 1358; P8LE: # %bb.0: # %entry 1359; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1360; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1361; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1362; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1363; P8LE-NEXT: xxmrghd vs0, vs3, vs1 1364; P8LE-NEXT: xxmrghd vs1, vs4, vs2 1365; P8LE-NEXT: xvcvdpsxws v2, vs0 1366; P8LE-NEXT: xvcvdpsxws v3, vs1 1367; P8LE-NEXT: vmrgew v2, v3, v2 1368; P8LE-NEXT: blr 1369entry: 1370 %conv = fptosi float %a to i32 1371 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1372 %conv1 = fptosi float %b to i32 1373 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 1374 %conv3 = fptosi float %c to i32 1375 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 1376 %conv5 = fptosi float %d to i32 1377 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 1378 ret <4 x i32> %vecinit6 1379} 1380 1381define <4 x i32> @fromDiffConstsConvftoi() { 1382; P9BE-LABEL: fromDiffConstsConvftoi: 1383; P9BE: # %bb.0: # %entry 1384; P9BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha 1385; P9BE-NEXT: addi r3, r3, .LCPI16_0@toc@l 1386; P9BE-NEXT: lxv v2, 0(r3) 1387; P9BE-NEXT: blr 1388; 1389; P9LE-LABEL: fromDiffConstsConvftoi: 1390; P9LE: # %bb.0: # %entry 1391; P9LE-NEXT: addis r3, r2, .LCPI16_0@toc@ha 1392; P9LE-NEXT: addi r3, r3, .LCPI16_0@toc@l 1393; P9LE-NEXT: lxv v2, 0(r3) 1394; P9LE-NEXT: blr 1395; 1396; P8BE-LABEL: fromDiffConstsConvftoi: 1397; P8BE: # %bb.0: # %entry 1398; P8BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha 1399; P8BE-NEXT: addi r3, r3, .LCPI16_0@toc@l 1400; P8BE-NEXT: lxvw4x v2, 0, r3 1401; P8BE-NEXT: blr 1402; 1403; P8LE-LABEL: fromDiffConstsConvftoi: 1404; P8LE: # %bb.0: # %entry 1405; P8LE-NEXT: addis r3, r2, .LCPI16_0@toc@ha 1406; P8LE-NEXT: addi r3, r3, .LCPI16_0@toc@l 1407; P8LE-NEXT: lvx v2, 0, r3 1408; P8LE-NEXT: blr 1409entry: 1410 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 1411} 1412 1413define <4 x i32> @fromDiffMemConsAConvftoi(float* nocapture readonly %ptr) { 1414; P9BE-LABEL: fromDiffMemConsAConvftoi: 1415; P9BE: # %bb.0: # %entry 1416; P9BE-NEXT: lxv vs0, 0(r3) 1417; P9BE-NEXT: xvcvspsxws v2, vs0 1418; P9BE-NEXT: blr 1419; 1420; P9LE-LABEL: fromDiffMemConsAConvftoi: 1421; P9LE: # %bb.0: # %entry 1422; P9LE-NEXT: lxv vs0, 0(r3) 1423; P9LE-NEXT: xvcvspsxws v2, vs0 1424; P9LE-NEXT: blr 1425; 1426; P8BE-LABEL: fromDiffMemConsAConvftoi: 1427; P8BE: # %bb.0: # %entry 1428; P8BE-NEXT: lxvw4x vs0, 0, r3 1429; P8BE-NEXT: xvcvspsxws v2, vs0 1430; P8BE-NEXT: blr 1431; 1432; P8LE-LABEL: fromDiffMemConsAConvftoi: 1433; P8LE: # %bb.0: # %entry 1434; P8LE-NEXT: lxvd2x vs0, 0, r3 1435; P8LE-NEXT: xxswapd v2, vs0 1436; P8LE-NEXT: xvcvspsxws v2, v2 1437; P8LE-NEXT: blr 1438entry: 1439 %0 = bitcast float* %ptr to <4 x float>* 1440 %1 = load <4 x float>, <4 x float>* %0, align 4 1441 %2 = fptosi <4 x float> %1 to <4 x i32> 1442 ret <4 x i32> %2 1443} 1444 1445define <4 x i32> @fromDiffMemConsDConvftoi(float* nocapture readonly %ptr) { 1446; P9BE-LABEL: fromDiffMemConsDConvftoi: 1447; P9BE: # %bb.0: # %entry 1448; P9BE-NEXT: lxv v2, 0(r3) 1449; P9BE-NEXT: addis r3, r2, .LCPI18_0@toc@ha 1450; P9BE-NEXT: addi r3, r3, .LCPI18_0@toc@l 1451; P9BE-NEXT: lxv v3, 0(r3) 1452; P9BE-NEXT: vperm v2, v2, v2, v3 1453; P9BE-NEXT: xvcvspsxws v2, v2 1454; P9BE-NEXT: blr 1455; 1456; P9LE-LABEL: fromDiffMemConsDConvftoi: 1457; P9LE: # %bb.0: # %entry 1458; P9LE-NEXT: lxv v2, 0(r3) 1459; P9LE-NEXT: addis r3, r2, .LCPI18_0@toc@ha 1460; P9LE-NEXT: addi r3, r3, .LCPI18_0@toc@l 1461; P9LE-NEXT: lxv v3, 0(r3) 1462; P9LE-NEXT: vperm v2, v2, v2, v3 1463; P9LE-NEXT: xvcvspsxws v2, v2 1464; P9LE-NEXT: blr 1465; 1466; P8BE-LABEL: fromDiffMemConsDConvftoi: 1467; P8BE: # %bb.0: # %entry 1468; P8BE-NEXT: addis r4, r2, .LCPI18_0@toc@ha 1469; P8BE-NEXT: lxvw4x v2, 0, r3 1470; P8BE-NEXT: addi r4, r4, .LCPI18_0@toc@l 1471; P8BE-NEXT: lxvw4x v3, 0, r4 1472; P8BE-NEXT: vperm v2, v2, v2, v3 1473; P8BE-NEXT: xvcvspsxws v2, v2 1474; P8BE-NEXT: blr 1475; 1476; P8LE-LABEL: fromDiffMemConsDConvftoi: 1477; P8LE: # %bb.0: # %entry 1478; P8LE-NEXT: lxvd2x vs0, 0, r3 1479; P8LE-NEXT: addis r4, r2, .LCPI18_0@toc@ha 1480; P8LE-NEXT: addi r3, r4, .LCPI18_0@toc@l 1481; P8LE-NEXT: lvx v2, 0, r3 1482; P8LE-NEXT: xxswapd v3, vs0 1483; P8LE-NEXT: vperm v2, v3, v3, v2 1484; P8LE-NEXT: xvcvspsxws v2, v2 1485; P8LE-NEXT: blr 1486entry: 1487 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 1488 %0 = load float, float* %arrayidx, align 4 1489 %conv = fptosi float %0 to i32 1490 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1491 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 1492 %1 = load float, float* %arrayidx1, align 4 1493 %conv2 = fptosi float %1 to i32 1494 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 1495 %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1 1496 %2 = load float, float* %arrayidx4, align 4 1497 %conv5 = fptosi float %2 to i32 1498 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 1499 %3 = load float, float* %ptr, align 4 1500 %conv8 = fptosi float %3 to i32 1501 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 1502 ret <4 x i32> %vecinit9 1503} 1504 1505define <4 x i32> @fromDiffMemVarAConvftoi(float* nocapture readonly %arr, i32 signext %elem) { 1506; P9BE-LABEL: fromDiffMemVarAConvftoi: 1507; P9BE: # %bb.0: # %entry 1508; P9BE-NEXT: sldi r4, r4, 2 1509; P9BE-NEXT: lfsux f0, r3, r4 1510; P9BE-NEXT: lfs f1, 12(r3) 1511; P9BE-NEXT: lfs f2, 4(r3) 1512; P9BE-NEXT: xxmrghd vs1, vs2, vs1 1513; P9BE-NEXT: xvcvdpsp v2, vs1 1514; P9BE-NEXT: lfs f1, 8(r3) 1515; P9BE-NEXT: xxmrghd vs0, vs0, vs1 1516; P9BE-NEXT: xvcvdpsp v3, vs0 1517; P9BE-NEXT: vmrgew v2, v3, v2 1518; P9BE-NEXT: xvcvspsxws v2, v2 1519; P9BE-NEXT: blr 1520; 1521; P9LE-LABEL: fromDiffMemVarAConvftoi: 1522; P9LE: # %bb.0: # %entry 1523; P9LE-NEXT: sldi r4, r4, 2 1524; P9LE-NEXT: lfsux f0, r3, r4 1525; P9LE-NEXT: lfs f1, 8(r3) 1526; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1527; P9LE-NEXT: lfs f1, 12(r3) 1528; P9LE-NEXT: xvcvdpsp v2, vs0 1529; P9LE-NEXT: lfs f0, 4(r3) 1530; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1531; P9LE-NEXT: xvcvdpsp v3, vs0 1532; P9LE-NEXT: vmrgew v2, v3, v2 1533; P9LE-NEXT: xvcvspsxws v2, v2 1534; P9LE-NEXT: blr 1535; 1536; P8BE-LABEL: fromDiffMemVarAConvftoi: 1537; P8BE: # %bb.0: # %entry 1538; P8BE-NEXT: sldi r4, r4, 2 1539; P8BE-NEXT: lfsux f0, r3, r4 1540; P8BE-NEXT: lfs f1, 12(r3) 1541; P8BE-NEXT: lfs f2, 4(r3) 1542; P8BE-NEXT: lfs f3, 8(r3) 1543; P8BE-NEXT: xxmrghd vs1, vs2, vs1 1544; P8BE-NEXT: xxmrghd vs0, vs0, vs3 1545; P8BE-NEXT: xvcvdpsp v2, vs1 1546; P8BE-NEXT: xvcvdpsp v3, vs0 1547; P8BE-NEXT: vmrgew v2, v3, v2 1548; P8BE-NEXT: xvcvspsxws v2, v2 1549; P8BE-NEXT: blr 1550; 1551; P8LE-LABEL: fromDiffMemVarAConvftoi: 1552; P8LE: # %bb.0: # %entry 1553; P8LE-NEXT: sldi r4, r4, 2 1554; P8LE-NEXT: lfsux f0, r3, r4 1555; P8LE-NEXT: lfs f1, 8(r3) 1556; P8LE-NEXT: lfs f2, 4(r3) 1557; P8LE-NEXT: lfs f3, 12(r3) 1558; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1559; P8LE-NEXT: xxmrghd vs1, vs3, vs2 1560; P8LE-NEXT: xvcvdpsp v2, vs0 1561; P8LE-NEXT: xvcvdpsp v3, vs1 1562; P8LE-NEXT: vmrgew v2, v3, v2 1563; P8LE-NEXT: xvcvspsxws v2, v2 1564; P8LE-NEXT: blr 1565entry: 1566 %idxprom = sext i32 %elem to i64 1567 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 1568 %0 = load float, float* %arrayidx, align 4 1569 %conv = fptosi float %0 to i32 1570 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1571 %add = add nsw i32 %elem, 1 1572 %idxprom1 = sext i32 %add to i64 1573 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 1574 %1 = load float, float* %arrayidx2, align 4 1575 %conv3 = fptosi float %1 to i32 1576 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1577 %add5 = add nsw i32 %elem, 2 1578 %idxprom6 = sext i32 %add5 to i64 1579 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 1580 %2 = load float, float* %arrayidx7, align 4 1581 %conv8 = fptosi float %2 to i32 1582 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1583 %add10 = add nsw i32 %elem, 3 1584 %idxprom11 = sext i32 %add10 to i64 1585 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 1586 %3 = load float, float* %arrayidx12, align 4 1587 %conv13 = fptosi float %3 to i32 1588 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1589 ret <4 x i32> %vecinit14 1590} 1591 1592define <4 x i32> @fromDiffMemVarDConvftoi(float* nocapture readonly %arr, i32 signext %elem) { 1593; P9BE-LABEL: fromDiffMemVarDConvftoi: 1594; P9BE: # %bb.0: # %entry 1595; P9BE-NEXT: sldi r4, r4, 2 1596; P9BE-NEXT: lfsux f0, r3, r4 1597; P9BE-NEXT: lfs f1, -12(r3) 1598; P9BE-NEXT: lfs f2, -4(r3) 1599; P9BE-NEXT: xxmrghd vs1, vs2, vs1 1600; P9BE-NEXT: xvcvdpsp v2, vs1 1601; P9BE-NEXT: lfs f1, -8(r3) 1602; P9BE-NEXT: xxmrghd vs0, vs0, vs1 1603; P9BE-NEXT: xvcvdpsp v3, vs0 1604; P9BE-NEXT: vmrgew v2, v3, v2 1605; P9BE-NEXT: xvcvspsxws v2, v2 1606; P9BE-NEXT: blr 1607; 1608; P9LE-LABEL: fromDiffMemVarDConvftoi: 1609; P9LE: # %bb.0: # %entry 1610; P9LE-NEXT: sldi r4, r4, 2 1611; P9LE-NEXT: lfsux f0, r3, r4 1612; P9LE-NEXT: lfs f1, -8(r3) 1613; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1614; P9LE-NEXT: lfs f1, -12(r3) 1615; P9LE-NEXT: xvcvdpsp v2, vs0 1616; P9LE-NEXT: lfs f0, -4(r3) 1617; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1618; P9LE-NEXT: xvcvdpsp v3, vs0 1619; P9LE-NEXT: vmrgew v2, v3, v2 1620; P9LE-NEXT: xvcvspsxws v2, v2 1621; P9LE-NEXT: blr 1622; 1623; P8BE-LABEL: fromDiffMemVarDConvftoi: 1624; P8BE: # %bb.0: # %entry 1625; P8BE-NEXT: sldi r4, r4, 2 1626; P8BE-NEXT: lfsux f0, r3, r4 1627; P8BE-NEXT: lfs f1, -12(r3) 1628; P8BE-NEXT: lfs f2, -4(r3) 1629; P8BE-NEXT: lfs f3, -8(r3) 1630; P8BE-NEXT: xxmrghd vs1, vs2, vs1 1631; P8BE-NEXT: xxmrghd vs0, vs0, vs3 1632; P8BE-NEXT: xvcvdpsp v2, vs1 1633; P8BE-NEXT: xvcvdpsp v3, vs0 1634; P8BE-NEXT: vmrgew v2, v3, v2 1635; P8BE-NEXT: xvcvspsxws v2, v2 1636; P8BE-NEXT: blr 1637; 1638; P8LE-LABEL: fromDiffMemVarDConvftoi: 1639; P8LE: # %bb.0: # %entry 1640; P8LE-NEXT: sldi r4, r4, 2 1641; P8LE-NEXT: lfsux f0, r3, r4 1642; P8LE-NEXT: lfs f1, -8(r3) 1643; P8LE-NEXT: lfs f2, -4(r3) 1644; P8LE-NEXT: lfs f3, -12(r3) 1645; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1646; P8LE-NEXT: xxmrghd vs1, vs3, vs2 1647; P8LE-NEXT: xvcvdpsp v2, vs0 1648; P8LE-NEXT: xvcvdpsp v3, vs1 1649; P8LE-NEXT: vmrgew v2, v3, v2 1650; P8LE-NEXT: xvcvspsxws v2, v2 1651; P8LE-NEXT: blr 1652entry: 1653 %idxprom = sext i32 %elem to i64 1654 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 1655 %0 = load float, float* %arrayidx, align 4 1656 %conv = fptosi float %0 to i32 1657 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1658 %sub = add nsw i32 %elem, -1 1659 %idxprom1 = sext i32 %sub to i64 1660 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 1661 %1 = load float, float* %arrayidx2, align 4 1662 %conv3 = fptosi float %1 to i32 1663 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1664 %sub5 = add nsw i32 %elem, -2 1665 %idxprom6 = sext i32 %sub5 to i64 1666 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 1667 %2 = load float, float* %arrayidx7, align 4 1668 %conv8 = fptosi float %2 to i32 1669 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1670 %sub10 = add nsw i32 %elem, -3 1671 %idxprom11 = sext i32 %sub10 to i64 1672 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 1673 %3 = load float, float* %arrayidx12, align 4 1674 %conv13 = fptosi float %3 to i32 1675 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1676 ret <4 x i32> %vecinit14 1677; FIXME: implement finding consecutive loads with pre-inc 1678} 1679 1680define <4 x i32> @spltRegValConvftoi(float %val) { 1681; P9BE-LABEL: spltRegValConvftoi: 1682; P9BE: # %bb.0: # %entry 1683; P9BE-NEXT: xscvdpsxws f0, f1 1684; P9BE-NEXT: xxspltw v2, vs0, 1 1685; P9BE-NEXT: blr 1686; 1687; P9LE-LABEL: spltRegValConvftoi: 1688; P9LE: # %bb.0: # %entry 1689; P9LE-NEXT: xscvdpsxws f0, f1 1690; P9LE-NEXT: xxspltw v2, vs0, 1 1691; P9LE-NEXT: blr 1692; 1693; P8BE-LABEL: spltRegValConvftoi: 1694; P8BE: # %bb.0: # %entry 1695; P8BE-NEXT: xscvdpsxws f0, f1 1696; P8BE-NEXT: xxspltw v2, vs0, 1 1697; P8BE-NEXT: blr 1698; 1699; P8LE-LABEL: spltRegValConvftoi: 1700; P8LE: # %bb.0: # %entry 1701; P8LE-NEXT: xscvdpsxws f0, f1 1702; P8LE-NEXT: xxspltw v2, vs0, 1 1703; P8LE-NEXT: blr 1704entry: 1705 %conv = fptosi float %val to i32 1706 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1707 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1708 ret <4 x i32> %splat.splat 1709} 1710 1711define <4 x i32> @spltMemValConvftoi(float* nocapture readonly %ptr) { 1712; P9BE-LABEL: spltMemValConvftoi: 1713; P9BE: # %bb.0: # %entry 1714; P9BE-NEXT: lfiwzx f0, 0, r3 1715; P9BE-NEXT: xvcvspsxws vs0, vs0 1716; P9BE-NEXT: xxspltw v2, vs0, 1 1717; P9BE-NEXT: blr 1718; 1719; P9LE-LABEL: spltMemValConvftoi: 1720; P9LE: # %bb.0: # %entry 1721; P9LE-NEXT: lfiwzx f0, 0, r3 1722; P9LE-NEXT: xvcvspsxws vs0, vs0 1723; P9LE-NEXT: xxspltw v2, vs0, 1 1724; P9LE-NEXT: blr 1725; 1726; P8BE-LABEL: spltMemValConvftoi: 1727; P8BE: # %bb.0: # %entry 1728; P8BE-NEXT: lfsx f0, 0, r3 1729; P8BE-NEXT: xscvdpsxws f0, f0 1730; P8BE-NEXT: xxspltw v2, vs0, 1 1731; P8BE-NEXT: blr 1732; 1733; P8LE-LABEL: spltMemValConvftoi: 1734; P8LE: # %bb.0: # %entry 1735; P8LE-NEXT: lfsx f0, 0, r3 1736; P8LE-NEXT: xscvdpsxws f0, f0 1737; P8LE-NEXT: xxspltw v2, vs0, 1 1738; P8LE-NEXT: blr 1739entry: 1740 %0 = load float, float* %ptr, align 4 1741 %conv = fptosi float %0 to i32 1742 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1743 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1744 ret <4 x i32> %splat.splat 1745} 1746 1747define <4 x i32> @spltCnstConvdtoi() { 1748; P9BE-LABEL: spltCnstConvdtoi: 1749; P9BE: # %bb.0: # %entry 1750; P9BE-NEXT: vspltisw v2, 4 1751; P9BE-NEXT: blr 1752; 1753; P9LE-LABEL: spltCnstConvdtoi: 1754; P9LE: # %bb.0: # %entry 1755; P9LE-NEXT: vspltisw v2, 4 1756; P9LE-NEXT: blr 1757; 1758; P8BE-LABEL: spltCnstConvdtoi: 1759; P8BE: # %bb.0: # %entry 1760; P8BE-NEXT: vspltisw v2, 4 1761; P8BE-NEXT: blr 1762; 1763; P8LE-LABEL: spltCnstConvdtoi: 1764; P8LE: # %bb.0: # %entry 1765; P8LE-NEXT: vspltisw v2, 4 1766; P8LE-NEXT: blr 1767entry: 1768 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 1769} 1770 1771define <4 x i32> @fromRegsConvdtoi(double %a, double %b, double %c, double %d) { 1772; P9BE-LABEL: fromRegsConvdtoi: 1773; P9BE: # %bb.0: # %entry 1774; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1775; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1776; P9BE-NEXT: xxmrghd vs0, vs2, vs4 1777; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1778; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1779; P9BE-NEXT: xvcvdpsxws v2, vs0 1780; P9BE-NEXT: xxmrghd vs0, vs1, vs3 1781; P9BE-NEXT: xvcvdpsxws v3, vs0 1782; P9BE-NEXT: vmrgew v2, v3, v2 1783; P9BE-NEXT: blr 1784; 1785; P9LE-LABEL: fromRegsConvdtoi: 1786; P9LE: # %bb.0: # %entry 1787; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1788; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1789; P9LE-NEXT: xxmrghd vs0, vs3, vs1 1790; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1791; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1792; P9LE-NEXT: xvcvdpsxws v2, vs0 1793; P9LE-NEXT: xxmrghd vs0, vs4, vs2 1794; P9LE-NEXT: xvcvdpsxws v3, vs0 1795; P9LE-NEXT: vmrgew v2, v3, v2 1796; P9LE-NEXT: blr 1797; 1798; P8BE-LABEL: fromRegsConvdtoi: 1799; P8BE: # %bb.0: # %entry 1800; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1801; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1802; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1803; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1804; P8BE-NEXT: xxmrghd vs0, vs2, vs4 1805; P8BE-NEXT: xxmrghd vs1, vs1, vs3 1806; P8BE-NEXT: xvcvdpsxws v2, vs0 1807; P8BE-NEXT: xvcvdpsxws v3, vs1 1808; P8BE-NEXT: vmrgew v2, v3, v2 1809; P8BE-NEXT: blr 1810; 1811; P8LE-LABEL: fromRegsConvdtoi: 1812; P8LE: # %bb.0: # %entry 1813; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1814; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1815; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1816; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1817; P8LE-NEXT: xxmrghd vs0, vs3, vs1 1818; P8LE-NEXT: xxmrghd vs1, vs4, vs2 1819; P8LE-NEXT: xvcvdpsxws v2, vs0 1820; P8LE-NEXT: xvcvdpsxws v3, vs1 1821; P8LE-NEXT: vmrgew v2, v3, v2 1822; P8LE-NEXT: blr 1823entry: 1824 %conv = fptosi double %a to i32 1825 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1826 %conv1 = fptosi double %b to i32 1827 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 1828 %conv3 = fptosi double %c to i32 1829 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 1830 %conv5 = fptosi double %d to i32 1831 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 1832 ret <4 x i32> %vecinit6 1833} 1834 1835define <4 x i32> @fromDiffConstsConvdtoi() { 1836; P9BE-LABEL: fromDiffConstsConvdtoi: 1837; P9BE: # %bb.0: # %entry 1838; P9BE-NEXT: addis r3, r2, .LCPI25_0@toc@ha 1839; P9BE-NEXT: addi r3, r3, .LCPI25_0@toc@l 1840; P9BE-NEXT: lxv v2, 0(r3) 1841; P9BE-NEXT: blr 1842; 1843; P9LE-LABEL: fromDiffConstsConvdtoi: 1844; P9LE: # %bb.0: # %entry 1845; P9LE-NEXT: addis r3, r2, .LCPI25_0@toc@ha 1846; P9LE-NEXT: addi r3, r3, .LCPI25_0@toc@l 1847; P9LE-NEXT: lxv v2, 0(r3) 1848; P9LE-NEXT: blr 1849; 1850; P8BE-LABEL: fromDiffConstsConvdtoi: 1851; P8BE: # %bb.0: # %entry 1852; P8BE-NEXT: addis r3, r2, .LCPI25_0@toc@ha 1853; P8BE-NEXT: addi r3, r3, .LCPI25_0@toc@l 1854; P8BE-NEXT: lxvw4x v2, 0, r3 1855; P8BE-NEXT: blr 1856; 1857; P8LE-LABEL: fromDiffConstsConvdtoi: 1858; P8LE: # %bb.0: # %entry 1859; P8LE-NEXT: addis r3, r2, .LCPI25_0@toc@ha 1860; P8LE-NEXT: addi r3, r3, .LCPI25_0@toc@l 1861; P8LE-NEXT: lvx v2, 0, r3 1862; P8LE-NEXT: blr 1863entry: 1864 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 1865} 1866 1867define <4 x i32> @fromDiffMemConsAConvdtoi(double* nocapture readonly %ptr) { 1868; P9BE-LABEL: fromDiffMemConsAConvdtoi: 1869; P9BE: # %bb.0: # %entry 1870; P9BE-NEXT: lxv vs0, 0(r3) 1871; P9BE-NEXT: lxv vs1, 16(r3) 1872; P9BE-NEXT: xxmrgld vs2, vs0, vs1 1873; P9BE-NEXT: xxmrghd vs0, vs0, vs1 1874; P9BE-NEXT: xvcvdpsxws v2, vs2 1875; P9BE-NEXT: xvcvdpsxws v3, vs0 1876; P9BE-NEXT: vmrgew v2, v3, v2 1877; P9BE-NEXT: blr 1878; 1879; P9LE-LABEL: fromDiffMemConsAConvdtoi: 1880; P9LE: # %bb.0: # %entry 1881; P9LE-NEXT: lxv vs0, 0(r3) 1882; P9LE-NEXT: lxv vs1, 16(r3) 1883; P9LE-NEXT: xxmrgld vs2, vs1, vs0 1884; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1885; P9LE-NEXT: xvcvdpsxws v2, vs2 1886; P9LE-NEXT: xvcvdpsxws v3, vs0 1887; P9LE-NEXT: vmrgew v2, v3, v2 1888; P9LE-NEXT: blr 1889; 1890; P8BE-LABEL: fromDiffMemConsAConvdtoi: 1891; P8BE: # %bb.0: # %entry 1892; P8BE-NEXT: li r4, 16 1893; P8BE-NEXT: lxvd2x vs0, 0, r3 1894; P8BE-NEXT: lxvd2x vs1, r3, r4 1895; P8BE-NEXT: xxmrgld vs2, vs0, vs1 1896; P8BE-NEXT: xxmrghd vs0, vs0, vs1 1897; P8BE-NEXT: xvcvdpsxws v2, vs2 1898; P8BE-NEXT: xvcvdpsxws v3, vs0 1899; P8BE-NEXT: vmrgew v2, v3, v2 1900; P8BE-NEXT: blr 1901; 1902; P8LE-LABEL: fromDiffMemConsAConvdtoi: 1903; P8LE: # %bb.0: # %entry 1904; P8LE-NEXT: li r4, 16 1905; P8LE-NEXT: lxvd2x vs0, 0, r3 1906; P8LE-NEXT: lxvd2x vs1, r3, r4 1907; P8LE-NEXT: xxswapd vs0, vs0 1908; P8LE-NEXT: xxswapd vs1, vs1 1909; P8LE-NEXT: xxmrgld vs2, vs1, vs0 1910; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1911; P8LE-NEXT: xvcvdpsxws v2, vs2 1912; P8LE-NEXT: xvcvdpsxws v3, vs0 1913; P8LE-NEXT: vmrgew v2, v3, v2 1914; P8LE-NEXT: blr 1915entry: 1916 %0 = bitcast double* %ptr to <2 x double>* 1917 %1 = load <2 x double>, <2 x double>* %0, align 8 1918 %2 = fptosi <2 x double> %1 to <2 x i32> 1919 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 2 1920 %3 = bitcast double* %arrayidx4 to <2 x double>* 1921 %4 = load <2 x double>, <2 x double>* %3, align 8 1922 %5 = fptosi <2 x double> %4 to <2 x i32> 1923 %vecinit9 = shufflevector <2 x i32> %2, <2 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 1924 ret <4 x i32> %vecinit9 1925} 1926 1927define <4 x i32> @fromDiffMemConsDConvdtoi(double* nocapture readonly %ptr) { 1928; P9BE-LABEL: fromDiffMemConsDConvdtoi: 1929; P9BE: # %bb.0: # %entry 1930; P9BE-NEXT: lfd f0, 24(r3) 1931; P9BE-NEXT: lfd f1, 16(r3) 1932; P9BE-NEXT: lfd f2, 8(r3) 1933; P9BE-NEXT: xxmrghd vs0, vs0, vs2 1934; P9BE-NEXT: lfd f3, 0(r3) 1935; P9BE-NEXT: xxmrghd vs1, vs1, vs3 1936; P9BE-NEXT: xvcvdpsxws v2, vs1 1937; P9BE-NEXT: xvcvdpsxws v3, vs0 1938; P9BE-NEXT: vmrgew v2, v3, v2 1939; P9BE-NEXT: blr 1940; 1941; P9LE-LABEL: fromDiffMemConsDConvdtoi: 1942; P9LE: # %bb.0: # %entry 1943; P9LE-NEXT: lfd f0, 24(r3) 1944; P9LE-NEXT: lfd f2, 8(r3) 1945; P9LE-NEXT: xxmrghd vs0, vs2, vs0 1946; P9LE-NEXT: lfd f1, 16(r3) 1947; P9LE-NEXT: lfd f3, 0(r3) 1948; P9LE-NEXT: xvcvdpsxws v2, vs0 1949; P9LE-NEXT: xxmrghd vs0, vs3, vs1 1950; P9LE-NEXT: xvcvdpsxws v3, vs0 1951; P9LE-NEXT: vmrgew v2, v3, v2 1952; P9LE-NEXT: blr 1953; 1954; P8BE-LABEL: fromDiffMemConsDConvdtoi: 1955; P8BE: # %bb.0: # %entry 1956; P8BE-NEXT: lfd f0, 16(r3) 1957; P8BE-NEXT: lfd f1, 0(r3) 1958; P8BE-NEXT: lfd f2, 24(r3) 1959; P8BE-NEXT: lfd f3, 8(r3) 1960; P8BE-NEXT: xxmrghd vs0, vs0, vs1 1961; P8BE-NEXT: xxmrghd vs1, vs2, vs3 1962; P8BE-NEXT: xvcvdpsxws v2, vs0 1963; P8BE-NEXT: xvcvdpsxws v3, vs1 1964; P8BE-NEXT: vmrgew v2, v3, v2 1965; P8BE-NEXT: blr 1966; 1967; P8LE-LABEL: fromDiffMemConsDConvdtoi: 1968; P8LE: # %bb.0: # %entry 1969; P8LE-NEXT: lfd f0, 24(r3) 1970; P8LE-NEXT: lfd f1, 8(r3) 1971; P8LE-NEXT: lfd f2, 16(r3) 1972; P8LE-NEXT: lfd f3, 0(r3) 1973; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1974; P8LE-NEXT: xxmrghd vs1, vs3, vs2 1975; P8LE-NEXT: xvcvdpsxws v2, vs0 1976; P8LE-NEXT: xvcvdpsxws v3, vs1 1977; P8LE-NEXT: vmrgew v2, v3, v2 1978; P8LE-NEXT: blr 1979entry: 1980 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 1981 %0 = load double, double* %arrayidx, align 8 1982 %conv = fptosi double %0 to i32 1983 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1984 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 1985 %1 = load double, double* %arrayidx1, align 8 1986 %conv2 = fptosi double %1 to i32 1987 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 1988 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 1 1989 %2 = load double, double* %arrayidx4, align 8 1990 %conv5 = fptosi double %2 to i32 1991 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 1992 %3 = load double, double* %ptr, align 8 1993 %conv8 = fptosi double %3 to i32 1994 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 1995 ret <4 x i32> %vecinit9 1996} 1997 1998define <4 x i32> @fromDiffMemVarAConvdtoi(double* nocapture readonly %arr, i32 signext %elem) { 1999; P9BE-LABEL: fromDiffMemVarAConvdtoi: 2000; P9BE: # %bb.0: # %entry 2001; P9BE-NEXT: sldi r4, r4, 3 2002; P9BE-NEXT: lfdux f0, r3, r4 2003; P9BE-NEXT: lfd f1, 8(r3) 2004; P9BE-NEXT: lfd f2, 16(r3) 2005; P9BE-NEXT: lfd f3, 24(r3) 2006; P9BE-NEXT: xxmrghd vs1, vs1, vs3 2007; P9BE-NEXT: xxmrghd vs0, vs0, vs2 2008; P9BE-NEXT: xvcvdpsxws v2, vs1 2009; P9BE-NEXT: xvcvdpsxws v3, vs0 2010; P9BE-NEXT: vmrgew v2, v3, v2 2011; P9BE-NEXT: blr 2012; 2013; P9LE-LABEL: fromDiffMemVarAConvdtoi: 2014; P9LE: # %bb.0: # %entry 2015; P9LE-NEXT: sldi r4, r4, 3 2016; P9LE-NEXT: lfdux f0, r3, r4 2017; P9LE-NEXT: lfd f2, 16(r3) 2018; P9LE-NEXT: lfd f1, 8(r3) 2019; P9LE-NEXT: lfd f3, 24(r3) 2020; P9LE-NEXT: xxmrghd vs0, vs2, vs0 2021; P9LE-NEXT: xvcvdpsxws v2, vs0 2022; P9LE-NEXT: xxmrghd vs0, vs3, vs1 2023; P9LE-NEXT: xvcvdpsxws v3, vs0 2024; P9LE-NEXT: vmrgew v2, v3, v2 2025; P9LE-NEXT: blr 2026; 2027; P8BE-LABEL: fromDiffMemVarAConvdtoi: 2028; P8BE: # %bb.0: # %entry 2029; P8BE-NEXT: sldi r4, r4, 3 2030; P8BE-NEXT: lfdux f0, r3, r4 2031; P8BE-NEXT: lfd f1, 8(r3) 2032; P8BE-NEXT: lfd f2, 24(r3) 2033; P8BE-NEXT: lfd f3, 16(r3) 2034; P8BE-NEXT: xxmrghd vs1, vs1, vs2 2035; P8BE-NEXT: xxmrghd vs0, vs0, vs3 2036; P8BE-NEXT: xvcvdpsxws v2, vs1 2037; P8BE-NEXT: xvcvdpsxws v3, vs0 2038; P8BE-NEXT: vmrgew v2, v3, v2 2039; P8BE-NEXT: blr 2040; 2041; P8LE-LABEL: fromDiffMemVarAConvdtoi: 2042; P8LE: # %bb.0: # %entry 2043; P8LE-NEXT: sldi r4, r4, 3 2044; P8LE-NEXT: lfdux f0, r3, r4 2045; P8LE-NEXT: lfd f1, 16(r3) 2046; P8LE-NEXT: lfd f2, 8(r3) 2047; P8LE-NEXT: lfd f3, 24(r3) 2048; P8LE-NEXT: xxmrghd vs0, vs1, vs0 2049; P8LE-NEXT: xxmrghd vs1, vs3, vs2 2050; P8LE-NEXT: xvcvdpsxws v2, vs0 2051; P8LE-NEXT: xvcvdpsxws v3, vs1 2052; P8LE-NEXT: vmrgew v2, v3, v2 2053; P8LE-NEXT: blr 2054entry: 2055 %idxprom = sext i32 %elem to i64 2056 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 2057 %0 = load double, double* %arrayidx, align 8 2058 %conv = fptosi double %0 to i32 2059 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2060 %add = add nsw i32 %elem, 1 2061 %idxprom1 = sext i32 %add to i64 2062 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 2063 %1 = load double, double* %arrayidx2, align 8 2064 %conv3 = fptosi double %1 to i32 2065 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2066 %add5 = add nsw i32 %elem, 2 2067 %idxprom6 = sext i32 %add5 to i64 2068 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 2069 %2 = load double, double* %arrayidx7, align 8 2070 %conv8 = fptosi double %2 to i32 2071 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2072 %add10 = add nsw i32 %elem, 3 2073 %idxprom11 = sext i32 %add10 to i64 2074 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 2075 %3 = load double, double* %arrayidx12, align 8 2076 %conv13 = fptosi double %3 to i32 2077 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2078 ret <4 x i32> %vecinit14 2079} 2080 2081define <4 x i32> @fromDiffMemVarDConvdtoi(double* nocapture readonly %arr, i32 signext %elem) { 2082; P9BE-LABEL: fromDiffMemVarDConvdtoi: 2083; P9BE: # %bb.0: # %entry 2084; P9BE-NEXT: sldi r4, r4, 3 2085; P9BE-NEXT: lfdux f0, r3, r4 2086; P9BE-NEXT: lfd f1, -8(r3) 2087; P9BE-NEXT: lfd f2, -16(r3) 2088; P9BE-NEXT: lfd f3, -24(r3) 2089; P9BE-NEXT: xxmrghd vs1, vs1, vs3 2090; P9BE-NEXT: xxmrghd vs0, vs0, vs2 2091; P9BE-NEXT: xvcvdpsxws v2, vs1 2092; P9BE-NEXT: xvcvdpsxws v3, vs0 2093; P9BE-NEXT: vmrgew v2, v3, v2 2094; P9BE-NEXT: blr 2095; 2096; P9LE-LABEL: fromDiffMemVarDConvdtoi: 2097; P9LE: # %bb.0: # %entry 2098; P9LE-NEXT: sldi r4, r4, 3 2099; P9LE-NEXT: lfdux f0, r3, r4 2100; P9LE-NEXT: lfd f2, -16(r3) 2101; P9LE-NEXT: lfd f1, -8(r3) 2102; P9LE-NEXT: lfd f3, -24(r3) 2103; P9LE-NEXT: xxmrghd vs0, vs2, vs0 2104; P9LE-NEXT: xvcvdpsxws v2, vs0 2105; P9LE-NEXT: xxmrghd vs0, vs3, vs1 2106; P9LE-NEXT: xvcvdpsxws v3, vs0 2107; P9LE-NEXT: vmrgew v2, v3, v2 2108; P9LE-NEXT: blr 2109; 2110; P8BE-LABEL: fromDiffMemVarDConvdtoi: 2111; P8BE: # %bb.0: # %entry 2112; P8BE-NEXT: sldi r4, r4, 3 2113; P8BE-NEXT: lfdux f0, r3, r4 2114; P8BE-NEXT: lfd f1, -8(r3) 2115; P8BE-NEXT: lfd f2, -24(r3) 2116; P8BE-NEXT: lfd f3, -16(r3) 2117; P8BE-NEXT: xxmrghd vs1, vs1, vs2 2118; P8BE-NEXT: xxmrghd vs0, vs0, vs3 2119; P8BE-NEXT: xvcvdpsxws v2, vs1 2120; P8BE-NEXT: xvcvdpsxws v3, vs0 2121; P8BE-NEXT: vmrgew v2, v3, v2 2122; P8BE-NEXT: blr 2123; 2124; P8LE-LABEL: fromDiffMemVarDConvdtoi: 2125; P8LE: # %bb.0: # %entry 2126; P8LE-NEXT: sldi r4, r4, 3 2127; P8LE-NEXT: lfdux f0, r3, r4 2128; P8LE-NEXT: lfd f1, -16(r3) 2129; P8LE-NEXT: lfd f2, -8(r3) 2130; P8LE-NEXT: lfd f3, -24(r3) 2131; P8LE-NEXT: xxmrghd vs0, vs1, vs0 2132; P8LE-NEXT: xxmrghd vs1, vs3, vs2 2133; P8LE-NEXT: xvcvdpsxws v2, vs0 2134; P8LE-NEXT: xvcvdpsxws v3, vs1 2135; P8LE-NEXT: vmrgew v2, v3, v2 2136; P8LE-NEXT: blr 2137entry: 2138 %idxprom = sext i32 %elem to i64 2139 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 2140 %0 = load double, double* %arrayidx, align 8 2141 %conv = fptosi double %0 to i32 2142 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2143 %sub = add nsw i32 %elem, -1 2144 %idxprom1 = sext i32 %sub to i64 2145 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 2146 %1 = load double, double* %arrayidx2, align 8 2147 %conv3 = fptosi double %1 to i32 2148 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2149 %sub5 = add nsw i32 %elem, -2 2150 %idxprom6 = sext i32 %sub5 to i64 2151 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 2152 %2 = load double, double* %arrayidx7, align 8 2153 %conv8 = fptosi double %2 to i32 2154 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2155 %sub10 = add nsw i32 %elem, -3 2156 %idxprom11 = sext i32 %sub10 to i64 2157 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 2158 %3 = load double, double* %arrayidx12, align 8 2159 %conv13 = fptosi double %3 to i32 2160 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2161 ret <4 x i32> %vecinit14 2162} 2163 2164define <4 x i32> @spltRegValConvdtoi(double %val) { 2165; P9BE-LABEL: spltRegValConvdtoi: 2166; P9BE: # %bb.0: # %entry 2167; P9BE-NEXT: xscvdpsxws f0, f1 2168; P9BE-NEXT: xxspltw v2, vs0, 1 2169; P9BE-NEXT: blr 2170; 2171; P9LE-LABEL: spltRegValConvdtoi: 2172; P9LE: # %bb.0: # %entry 2173; P9LE-NEXT: xscvdpsxws f0, f1 2174; P9LE-NEXT: xxspltw v2, vs0, 1 2175; P9LE-NEXT: blr 2176; 2177; P8BE-LABEL: spltRegValConvdtoi: 2178; P8BE: # %bb.0: # %entry 2179; P8BE-NEXT: xscvdpsxws f0, f1 2180; P8BE-NEXT: xxspltw v2, vs0, 1 2181; P8BE-NEXT: blr 2182; 2183; P8LE-LABEL: spltRegValConvdtoi: 2184; P8LE: # %bb.0: # %entry 2185; P8LE-NEXT: xscvdpsxws f0, f1 2186; P8LE-NEXT: xxspltw v2, vs0, 1 2187; P8LE-NEXT: blr 2188entry: 2189 %conv = fptosi double %val to i32 2190 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2191 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2192 ret <4 x i32> %splat.splat 2193} 2194 2195define <4 x i32> @spltMemValConvdtoi(double* nocapture readonly %ptr) { 2196; P9BE-LABEL: spltMemValConvdtoi: 2197; P9BE: # %bb.0: # %entry 2198; P9BE-NEXT: lfd f0, 0(r3) 2199; P9BE-NEXT: xscvdpsxws f0, f0 2200; P9BE-NEXT: xxspltw v2, vs0, 1 2201; P9BE-NEXT: blr 2202; 2203; P9LE-LABEL: spltMemValConvdtoi: 2204; P9LE: # %bb.0: # %entry 2205; P9LE-NEXT: lfd f0, 0(r3) 2206; P9LE-NEXT: xscvdpsxws f0, f0 2207; P9LE-NEXT: xxspltw v2, vs0, 1 2208; P9LE-NEXT: blr 2209; 2210; P8BE-LABEL: spltMemValConvdtoi: 2211; P8BE: # %bb.0: # %entry 2212; P8BE-NEXT: lfdx f0, 0, r3 2213; P8BE-NEXT: xscvdpsxws f0, f0 2214; P8BE-NEXT: xxspltw v2, vs0, 1 2215; P8BE-NEXT: blr 2216; 2217; P8LE-LABEL: spltMemValConvdtoi: 2218; P8LE: # %bb.0: # %entry 2219; P8LE-NEXT: lfdx f0, 0, r3 2220; P8LE-NEXT: xscvdpsxws f0, f0 2221; P8LE-NEXT: xxspltw v2, vs0, 1 2222; P8LE-NEXT: blr 2223entry: 2224 %0 = load double, double* %ptr, align 8 2225 %conv = fptosi double %0 to i32 2226 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2227 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2228 ret <4 x i32> %splat.splat 2229} 2230 2231define <4 x i32> @allZeroui() { 2232; P9BE-LABEL: allZeroui: 2233; P9BE: # %bb.0: # %entry 2234; P9BE-NEXT: xxlxor v2, v2, v2 2235; P9BE-NEXT: blr 2236; 2237; P9LE-LABEL: allZeroui: 2238; P9LE: # %bb.0: # %entry 2239; P9LE-NEXT: xxlxor v2, v2, v2 2240; P9LE-NEXT: blr 2241; 2242; P8BE-LABEL: allZeroui: 2243; P8BE: # %bb.0: # %entry 2244; P8BE-NEXT: xxlxor v2, v2, v2 2245; P8BE-NEXT: blr 2246; 2247; P8LE-LABEL: allZeroui: 2248; P8LE: # %bb.0: # %entry 2249; P8LE-NEXT: xxlxor v2, v2, v2 2250; P8LE-NEXT: blr 2251entry: 2252 ret <4 x i32> zeroinitializer 2253} 2254 2255define <4 x i32> @spltConst1ui() { 2256; P9BE-LABEL: spltConst1ui: 2257; P9BE: # %bb.0: # %entry 2258; P9BE-NEXT: vspltisw v2, 1 2259; P9BE-NEXT: blr 2260; 2261; P9LE-LABEL: spltConst1ui: 2262; P9LE: # %bb.0: # %entry 2263; P9LE-NEXT: vspltisw v2, 1 2264; P9LE-NEXT: blr 2265; 2266; P8BE-LABEL: spltConst1ui: 2267; P8BE: # %bb.0: # %entry 2268; P8BE-NEXT: vspltisw v2, 1 2269; P8BE-NEXT: blr 2270; 2271; P8LE-LABEL: spltConst1ui: 2272; P8LE: # %bb.0: # %entry 2273; P8LE-NEXT: vspltisw v2, 1 2274; P8LE-NEXT: blr 2275entry: 2276 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1> 2277} 2278 2279define <4 x i32> @spltConst16kui() { 2280; P9BE-LABEL: spltConst16kui: 2281; P9BE: # %bb.0: # %entry 2282; P9BE-NEXT: vspltisw v2, -15 2283; P9BE-NEXT: vsrw v2, v2, v2 2284; P9BE-NEXT: blr 2285; 2286; P9LE-LABEL: spltConst16kui: 2287; P9LE: # %bb.0: # %entry 2288; P9LE-NEXT: vspltisw v2, -15 2289; P9LE-NEXT: vsrw v2, v2, v2 2290; P9LE-NEXT: blr 2291; 2292; P8BE-LABEL: spltConst16kui: 2293; P8BE: # %bb.0: # %entry 2294; P8BE-NEXT: vspltisw v2, -15 2295; P8BE-NEXT: vsrw v2, v2, v2 2296; P8BE-NEXT: blr 2297; 2298; P8LE-LABEL: spltConst16kui: 2299; P8LE: # %bb.0: # %entry 2300; P8LE-NEXT: vspltisw v2, -15 2301; P8LE-NEXT: vsrw v2, v2, v2 2302; P8LE-NEXT: blr 2303entry: 2304 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 2305} 2306 2307define <4 x i32> @spltConst32kui() { 2308; P9BE-LABEL: spltConst32kui: 2309; P9BE: # %bb.0: # %entry 2310; P9BE-NEXT: vspltisw v2, -16 2311; P9BE-NEXT: vsrw v2, v2, v2 2312; P9BE-NEXT: blr 2313; 2314; P9LE-LABEL: spltConst32kui: 2315; P9LE: # %bb.0: # %entry 2316; P9LE-NEXT: vspltisw v2, -16 2317; P9LE-NEXT: vsrw v2, v2, v2 2318; P9LE-NEXT: blr 2319; 2320; P8BE-LABEL: spltConst32kui: 2321; P8BE: # %bb.0: # %entry 2322; P8BE-NEXT: vspltisw v2, -16 2323; P8BE-NEXT: vsrw v2, v2, v2 2324; P8BE-NEXT: blr 2325; 2326; P8LE-LABEL: spltConst32kui: 2327; P8LE: # %bb.0: # %entry 2328; P8LE-NEXT: vspltisw v2, -16 2329; P8LE-NEXT: vsrw v2, v2, v2 2330; P8LE-NEXT: blr 2331entry: 2332 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 2333} 2334 2335define <4 x i32> @fromRegsui(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c, i32 zeroext %d) { 2336; P9BE-LABEL: fromRegsui: 2337; P9BE: # %bb.0: # %entry 2338; P9BE-NEXT: rldimi r6, r5, 32, 0 2339; P9BE-NEXT: rldimi r4, r3, 32, 0 2340; P9BE-NEXT: mtvsrdd v2, r4, r6 2341; P9BE-NEXT: blr 2342; 2343; P9LE-LABEL: fromRegsui: 2344; P9LE: # %bb.0: # %entry 2345; P9LE-NEXT: rldimi r3, r4, 32, 0 2346; P9LE-NEXT: rldimi r5, r6, 32, 0 2347; P9LE-NEXT: mtvsrdd v2, r5, r3 2348; P9LE-NEXT: blr 2349; 2350; P8BE-LABEL: fromRegsui: 2351; P8BE: # %bb.0: # %entry 2352; P8BE-NEXT: rldimi r6, r5, 32, 0 2353; P8BE-NEXT: rldimi r4, r3, 32, 0 2354; P8BE-NEXT: mtfprd f0, r6 2355; P8BE-NEXT: mtfprd f1, r4 2356; P8BE-NEXT: xxmrghd v2, vs1, vs0 2357; P8BE-NEXT: blr 2358; 2359; P8LE-LABEL: fromRegsui: 2360; P8LE: # %bb.0: # %entry 2361; P8LE-NEXT: rldimi r3, r4, 32, 0 2362; P8LE-NEXT: rldimi r5, r6, 32, 0 2363; P8LE-NEXT: mtfprd f0, r3 2364; P8LE-NEXT: mtfprd f1, r5 2365; P8LE-NEXT: xxmrghd v2, vs1, vs0 2366; P8LE-NEXT: blr 2367entry: 2368 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 2369 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 2370 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 2371 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3 2372 ret <4 x i32> %vecinit3 2373} 2374 2375define <4 x i32> @fromDiffConstsui() { 2376; P9BE-LABEL: fromDiffConstsui: 2377; P9BE: # %bb.0: # %entry 2378; P9BE-NEXT: addis r3, r2, .LCPI37_0@toc@ha 2379; P9BE-NEXT: addi r3, r3, .LCPI37_0@toc@l 2380; P9BE-NEXT: lxv v2, 0(r3) 2381; P9BE-NEXT: blr 2382; 2383; P9LE-LABEL: fromDiffConstsui: 2384; P9LE: # %bb.0: # %entry 2385; P9LE-NEXT: addis r3, r2, .LCPI37_0@toc@ha 2386; P9LE-NEXT: addi r3, r3, .LCPI37_0@toc@l 2387; P9LE-NEXT: lxv v2, 0(r3) 2388; P9LE-NEXT: blr 2389; 2390; P8BE-LABEL: fromDiffConstsui: 2391; P8BE: # %bb.0: # %entry 2392; P8BE-NEXT: addis r3, r2, .LCPI37_0@toc@ha 2393; P8BE-NEXT: addi r3, r3, .LCPI37_0@toc@l 2394; P8BE-NEXT: lxvw4x v2, 0, r3 2395; P8BE-NEXT: blr 2396; 2397; P8LE-LABEL: fromDiffConstsui: 2398; P8LE: # %bb.0: # %entry 2399; P8LE-NEXT: addis r3, r2, .LCPI37_0@toc@ha 2400; P8LE-NEXT: addi r3, r3, .LCPI37_0@toc@l 2401; P8LE-NEXT: lvx v2, 0, r3 2402; P8LE-NEXT: blr 2403entry: 2404 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19> 2405} 2406 2407define <4 x i32> @fromDiffMemConsAui(i32* nocapture readonly %arr) { 2408; P9BE-LABEL: fromDiffMemConsAui: 2409; P9BE: # %bb.0: # %entry 2410; P9BE-NEXT: lxv v2, 0(r3) 2411; P9BE-NEXT: blr 2412; 2413; P9LE-LABEL: fromDiffMemConsAui: 2414; P9LE: # %bb.0: # %entry 2415; P9LE-NEXT: lxv v2, 0(r3) 2416; P9LE-NEXT: blr 2417; 2418; P8BE-LABEL: fromDiffMemConsAui: 2419; P8BE: # %bb.0: # %entry 2420; P8BE-NEXT: lxvw4x v2, 0, r3 2421; P8BE-NEXT: blr 2422; 2423; P8LE-LABEL: fromDiffMemConsAui: 2424; P8LE: # %bb.0: # %entry 2425; P8LE-NEXT: lxvd2x vs0, 0, r3 2426; P8LE-NEXT: xxswapd v2, vs0 2427; P8LE-NEXT: blr 2428entry: 2429 %0 = load i32, i32* %arr, align 4 2430 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2431 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 1 2432 %1 = load i32, i32* %arrayidx1, align 4 2433 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2434 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 2435 %2 = load i32, i32* %arrayidx3, align 4 2436 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2437 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 3 2438 %3 = load i32, i32* %arrayidx5, align 4 2439 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2440 ret <4 x i32> %vecinit6 2441} 2442 2443define <4 x i32> @fromDiffMemConsDui(i32* nocapture readonly %arr) { 2444; P9BE-LABEL: fromDiffMemConsDui: 2445; P9BE: # %bb.0: # %entry 2446; P9BE-NEXT: lxv v2, 0(r3) 2447; P9BE-NEXT: addis r3, r2, .LCPI39_0@toc@ha 2448; P9BE-NEXT: addi r3, r3, .LCPI39_0@toc@l 2449; P9BE-NEXT: lxv v3, 0(r3) 2450; P9BE-NEXT: vperm v2, v2, v2, v3 2451; P9BE-NEXT: blr 2452; 2453; P9LE-LABEL: fromDiffMemConsDui: 2454; P9LE: # %bb.0: # %entry 2455; P9LE-NEXT: lxvw4x v2, 0, r3 2456; P9LE-NEXT: blr 2457; 2458; P8BE-LABEL: fromDiffMemConsDui: 2459; P8BE: # %bb.0: # %entry 2460; P8BE-NEXT: addis r4, r2, .LCPI39_0@toc@ha 2461; P8BE-NEXT: lxvw4x v2, 0, r3 2462; P8BE-NEXT: addi r4, r4, .LCPI39_0@toc@l 2463; P8BE-NEXT: lxvw4x v3, 0, r4 2464; P8BE-NEXT: vperm v2, v2, v2, v3 2465; P8BE-NEXT: blr 2466; 2467; P8LE-LABEL: fromDiffMemConsDui: 2468; P8LE: # %bb.0: # %entry 2469; P8LE-NEXT: lxvd2x vs0, 0, r3 2470; P8LE-NEXT: addis r4, r2, .LCPI39_0@toc@ha 2471; P8LE-NEXT: addi r3, r4, .LCPI39_0@toc@l 2472; P8LE-NEXT: lvx v2, 0, r3 2473; P8LE-NEXT: xxswapd v3, vs0 2474; P8LE-NEXT: vperm v2, v3, v3, v2 2475; P8LE-NEXT: blr 2476entry: 2477 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3 2478 %0 = load i32, i32* %arrayidx, align 4 2479 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2480 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 2481 %1 = load i32, i32* %arrayidx1, align 4 2482 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2483 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 1 2484 %2 = load i32, i32* %arrayidx3, align 4 2485 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2486 %3 = load i32, i32* %arr, align 4 2487 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2488 ret <4 x i32> %vecinit6 2489} 2490 2491define <4 x i32> @fromDiffMemVarAui(i32* nocapture readonly %arr, i32 signext %elem) { 2492; P9BE-LABEL: fromDiffMemVarAui: 2493; P9BE: # %bb.0: # %entry 2494; P9BE-NEXT: sldi r4, r4, 2 2495; P9BE-NEXT: lxvx v2, r3, r4 2496; P9BE-NEXT: blr 2497; 2498; P9LE-LABEL: fromDiffMemVarAui: 2499; P9LE: # %bb.0: # %entry 2500; P9LE-NEXT: sldi r4, r4, 2 2501; P9LE-NEXT: lxvx v2, r3, r4 2502; P9LE-NEXT: blr 2503; 2504; P8BE-LABEL: fromDiffMemVarAui: 2505; P8BE: # %bb.0: # %entry 2506; P8BE-NEXT: sldi r4, r4, 2 2507; P8BE-NEXT: lxvw4x v2, r3, r4 2508; P8BE-NEXT: blr 2509; 2510; P8LE-LABEL: fromDiffMemVarAui: 2511; P8LE: # %bb.0: # %entry 2512; P8LE-NEXT: sldi r4, r4, 2 2513; P8LE-NEXT: lxvd2x vs0, r3, r4 2514; P8LE-NEXT: xxswapd v2, vs0 2515; P8LE-NEXT: blr 2516entry: 2517 %idxprom = sext i32 %elem to i64 2518 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2519 %0 = load i32, i32* %arrayidx, align 4 2520 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2521 %add = add nsw i32 %elem, 1 2522 %idxprom1 = sext i32 %add to i64 2523 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 2524 %1 = load i32, i32* %arrayidx2, align 4 2525 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2526 %add4 = add nsw i32 %elem, 2 2527 %idxprom5 = sext i32 %add4 to i64 2528 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 2529 %2 = load i32, i32* %arrayidx6, align 4 2530 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 2531 %add8 = add nsw i32 %elem, 3 2532 %idxprom9 = sext i32 %add8 to i64 2533 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 2534 %3 = load i32, i32* %arrayidx10, align 4 2535 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 2536 ret <4 x i32> %vecinit11 2537} 2538 2539define <4 x i32> @fromDiffMemVarDui(i32* nocapture readonly %arr, i32 signext %elem) { 2540; P9BE-LABEL: fromDiffMemVarDui: 2541; P9BE: # %bb.0: # %entry 2542; P9BE-NEXT: sldi r4, r4, 2 2543; P9BE-NEXT: add r3, r3, r4 2544; P9BE-NEXT: li r4, -12 2545; P9BE-NEXT: lxvx v2, r3, r4 2546; P9BE-NEXT: addis r3, r2, .LCPI41_0@toc@ha 2547; P9BE-NEXT: addi r3, r3, .LCPI41_0@toc@l 2548; P9BE-NEXT: lxv v3, 0(r3) 2549; P9BE-NEXT: vperm v2, v2, v2, v3 2550; P9BE-NEXT: blr 2551; 2552; P9LE-LABEL: fromDiffMemVarDui: 2553; P9LE: # %bb.0: # %entry 2554; P9LE-NEXT: sldi r4, r4, 2 2555; P9LE-NEXT: add r3, r3, r4 2556; P9LE-NEXT: li r4, -12 2557; P9LE-NEXT: lxvx v2, r3, r4 2558; P9LE-NEXT: addis r3, r2, .LCPI41_0@toc@ha 2559; P9LE-NEXT: addi r3, r3, .LCPI41_0@toc@l 2560; P9LE-NEXT: lxv v3, 0(r3) 2561; P9LE-NEXT: vperm v2, v2, v2, v3 2562; P9LE-NEXT: blr 2563; 2564; P8BE-LABEL: fromDiffMemVarDui: 2565; P8BE: # %bb.0: # %entry 2566; P8BE-NEXT: sldi r4, r4, 2 2567; P8BE-NEXT: addis r5, r2, .LCPI41_0@toc@ha 2568; P8BE-NEXT: add r3, r3, r4 2569; P8BE-NEXT: addi r4, r5, .LCPI41_0@toc@l 2570; P8BE-NEXT: addi r3, r3, -12 2571; P8BE-NEXT: lxvw4x v3, 0, r4 2572; P8BE-NEXT: lxvw4x v2, 0, r3 2573; P8BE-NEXT: vperm v2, v2, v2, v3 2574; P8BE-NEXT: blr 2575; 2576; P8LE-LABEL: fromDiffMemVarDui: 2577; P8LE: # %bb.0: # %entry 2578; P8LE-NEXT: sldi r4, r4, 2 2579; P8LE-NEXT: addis r5, r2, .LCPI41_0@toc@ha 2580; P8LE-NEXT: add r3, r3, r4 2581; P8LE-NEXT: addi r3, r3, -12 2582; P8LE-NEXT: lxvd2x vs0, 0, r3 2583; P8LE-NEXT: addi r3, r5, .LCPI41_0@toc@l 2584; P8LE-NEXT: lvx v3, 0, r3 2585; P8LE-NEXT: xxswapd v2, vs0 2586; P8LE-NEXT: vperm v2, v2, v2, v3 2587; P8LE-NEXT: blr 2588entry: 2589 %idxprom = sext i32 %elem to i64 2590 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2591 %0 = load i32, i32* %arrayidx, align 4 2592 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2593 %sub = add nsw i32 %elem, -1 2594 %idxprom1 = sext i32 %sub to i64 2595 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 2596 %1 = load i32, i32* %arrayidx2, align 4 2597 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2598 %sub4 = add nsw i32 %elem, -2 2599 %idxprom5 = sext i32 %sub4 to i64 2600 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 2601 %2 = load i32, i32* %arrayidx6, align 4 2602 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 2603 %sub8 = add nsw i32 %elem, -3 2604 %idxprom9 = sext i32 %sub8 to i64 2605 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 2606 %3 = load i32, i32* %arrayidx10, align 4 2607 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 2608 ret <4 x i32> %vecinit11 2609} 2610 2611define <4 x i32> @fromRandMemConsui(i32* nocapture readonly %arr) { 2612; P9BE-LABEL: fromRandMemConsui: 2613; P9BE: # %bb.0: # %entry 2614; P9BE-NEXT: lwz r4, 16(r3) 2615; P9BE-NEXT: lwz r5, 72(r3) 2616; P9BE-NEXT: lwz r6, 8(r3) 2617; P9BE-NEXT: lwz r3, 352(r3) 2618; P9BE-NEXT: rldimi r3, r6, 32, 0 2619; P9BE-NEXT: rldimi r5, r4, 32, 0 2620; P9BE-NEXT: mtvsrdd v2, r5, r3 2621; P9BE-NEXT: blr 2622; 2623; P9LE-LABEL: fromRandMemConsui: 2624; P9LE: # %bb.0: # %entry 2625; P9LE-NEXT: lwz r4, 16(r3) 2626; P9LE-NEXT: lwz r5, 72(r3) 2627; P9LE-NEXT: lwz r6, 8(r3) 2628; P9LE-NEXT: lwz r3, 352(r3) 2629; P9LE-NEXT: rldimi r4, r5, 32, 0 2630; P9LE-NEXT: rldimi r6, r3, 32, 0 2631; P9LE-NEXT: mtvsrdd v2, r6, r4 2632; P9LE-NEXT: blr 2633; 2634; P8BE-LABEL: fromRandMemConsui: 2635; P8BE: # %bb.0: # %entry 2636; P8BE-NEXT: lwz r4, 8(r3) 2637; P8BE-NEXT: lwz r5, 352(r3) 2638; P8BE-NEXT: lwz r6, 16(r3) 2639; P8BE-NEXT: lwz r3, 72(r3) 2640; P8BE-NEXT: rldimi r5, r4, 32, 0 2641; P8BE-NEXT: rldimi r3, r6, 32, 0 2642; P8BE-NEXT: mtfprd f0, r5 2643; P8BE-NEXT: mtfprd f1, r3 2644; P8BE-NEXT: xxmrghd v2, vs1, vs0 2645; P8BE-NEXT: blr 2646; 2647; P8LE-LABEL: fromRandMemConsui: 2648; P8LE: # %bb.0: # %entry 2649; P8LE-NEXT: lwz r4, 16(r3) 2650; P8LE-NEXT: lwz r5, 72(r3) 2651; P8LE-NEXT: lwz r6, 8(r3) 2652; P8LE-NEXT: lwz r3, 352(r3) 2653; P8LE-NEXT: rldimi r4, r5, 32, 0 2654; P8LE-NEXT: rldimi r6, r3, 32, 0 2655; P8LE-NEXT: mtfprd f0, r4 2656; P8LE-NEXT: mtfprd f1, r6 2657; P8LE-NEXT: xxmrghd v2, vs1, vs0 2658; P8LE-NEXT: blr 2659entry: 2660 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4 2661 %0 = load i32, i32* %arrayidx, align 4 2662 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2663 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18 2664 %1 = load i32, i32* %arrayidx1, align 4 2665 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2666 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 2667 %2 = load i32, i32* %arrayidx3, align 4 2668 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2669 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 88 2670 %3 = load i32, i32* %arrayidx5, align 4 2671 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2672 ret <4 x i32> %vecinit6 2673} 2674 2675define <4 x i32> @fromRandMemVarui(i32* nocapture readonly %arr, i32 signext %elem) { 2676; P9BE-LABEL: fromRandMemVarui: 2677; P9BE: # %bb.0: # %entry 2678; P9BE-NEXT: sldi r4, r4, 2 2679; P9BE-NEXT: add r3, r3, r4 2680; P9BE-NEXT: lwz r4, 16(r3) 2681; P9BE-NEXT: lwz r5, 4(r3) 2682; P9BE-NEXT: lwz r6, 8(r3) 2683; P9BE-NEXT: lwz r3, 32(r3) 2684; P9BE-NEXT: rldimi r3, r6, 32, 0 2685; P9BE-NEXT: rldimi r5, r4, 32, 0 2686; P9BE-NEXT: mtvsrdd v2, r5, r3 2687; P9BE-NEXT: blr 2688; 2689; P9LE-LABEL: fromRandMemVarui: 2690; P9LE: # %bb.0: # %entry 2691; P9LE-NEXT: sldi r4, r4, 2 2692; P9LE-NEXT: add r3, r3, r4 2693; P9LE-NEXT: lwz r4, 16(r3) 2694; P9LE-NEXT: lwz r5, 4(r3) 2695; P9LE-NEXT: lwz r6, 8(r3) 2696; P9LE-NEXT: lwz r3, 32(r3) 2697; P9LE-NEXT: rldimi r4, r5, 32, 0 2698; P9LE-NEXT: rldimi r6, r3, 32, 0 2699; P9LE-NEXT: mtvsrdd v2, r6, r4 2700; P9LE-NEXT: blr 2701; 2702; P8BE-LABEL: fromRandMemVarui: 2703; P8BE: # %bb.0: # %entry 2704; P8BE-NEXT: sldi r4, r4, 2 2705; P8BE-NEXT: add r3, r3, r4 2706; P8BE-NEXT: lwz r4, 8(r3) 2707; P8BE-NEXT: lwz r5, 32(r3) 2708; P8BE-NEXT: lwz r6, 16(r3) 2709; P8BE-NEXT: lwz r3, 4(r3) 2710; P8BE-NEXT: rldimi r5, r4, 32, 0 2711; P8BE-NEXT: rldimi r3, r6, 32, 0 2712; P8BE-NEXT: mtfprd f0, r5 2713; P8BE-NEXT: mtfprd f1, r3 2714; P8BE-NEXT: xxmrghd v2, vs1, vs0 2715; P8BE-NEXT: blr 2716; 2717; P8LE-LABEL: fromRandMemVarui: 2718; P8LE: # %bb.0: # %entry 2719; P8LE-NEXT: sldi r4, r4, 2 2720; P8LE-NEXT: add r3, r3, r4 2721; P8LE-NEXT: lwz r4, 16(r3) 2722; P8LE-NEXT: lwz r5, 4(r3) 2723; P8LE-NEXT: lwz r6, 8(r3) 2724; P8LE-NEXT: lwz r3, 32(r3) 2725; P8LE-NEXT: rldimi r4, r5, 32, 0 2726; P8LE-NEXT: rldimi r6, r3, 32, 0 2727; P8LE-NEXT: mtfprd f0, r4 2728; P8LE-NEXT: mtfprd f1, r6 2729; P8LE-NEXT: xxmrghd v2, vs1, vs0 2730; P8LE-NEXT: blr 2731entry: 2732 %add = add nsw i32 %elem, 4 2733 %idxprom = sext i32 %add to i64 2734 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2735 %0 = load i32, i32* %arrayidx, align 4 2736 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2737 %add1 = add nsw i32 %elem, 1 2738 %idxprom2 = sext i32 %add1 to i64 2739 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 %idxprom2 2740 %1 = load i32, i32* %arrayidx3, align 4 2741 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2742 %add5 = add nsw i32 %elem, 2 2743 %idxprom6 = sext i32 %add5 to i64 2744 %arrayidx7 = getelementptr inbounds i32, i32* %arr, i64 %idxprom6 2745 %2 = load i32, i32* %arrayidx7, align 4 2746 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2 2747 %add9 = add nsw i32 %elem, 8 2748 %idxprom10 = sext i32 %add9 to i64 2749 %arrayidx11 = getelementptr inbounds i32, i32* %arr, i64 %idxprom10 2750 %3 = load i32, i32* %arrayidx11, align 4 2751 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3 2752 ret <4 x i32> %vecinit12 2753} 2754 2755define <4 x i32> @spltRegValui(i32 zeroext %val) { 2756; P9BE-LABEL: spltRegValui: 2757; P9BE: # %bb.0: # %entry 2758; P9BE-NEXT: mtvsrws v2, r3 2759; P9BE-NEXT: blr 2760; 2761; P9LE-LABEL: spltRegValui: 2762; P9LE: # %bb.0: # %entry 2763; P9LE-NEXT: mtvsrws v2, r3 2764; P9LE-NEXT: blr 2765; 2766; P8BE-LABEL: spltRegValui: 2767; P8BE: # %bb.0: # %entry 2768; P8BE-NEXT: mtfprwz f0, r3 2769; P8BE-NEXT: xxspltw v2, vs0, 1 2770; P8BE-NEXT: blr 2771; 2772; P8LE-LABEL: spltRegValui: 2773; P8LE: # %bb.0: # %entry 2774; P8LE-NEXT: mtfprwz f0, r3 2775; P8LE-NEXT: xxspltw v2, vs0, 1 2776; P8LE-NEXT: blr 2777entry: 2778 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0 2779 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2780 ret <4 x i32> %splat.splat 2781} 2782 2783define <4 x i32> @spltMemValui(i32* nocapture readonly %ptr) { 2784; P9BE-LABEL: spltMemValui: 2785; P9BE: # %bb.0: # %entry 2786; P9BE-NEXT: lxvwsx v2, 0, r3 2787; P9BE-NEXT: blr 2788; 2789; P9LE-LABEL: spltMemValui: 2790; P9LE: # %bb.0: # %entry 2791; P9LE-NEXT: lxvwsx v2, 0, r3 2792; P9LE-NEXT: blr 2793; 2794; P8BE-LABEL: spltMemValui: 2795; P8BE: # %bb.0: # %entry 2796; P8BE-NEXT: lfiwzx f0, 0, r3 2797; P8BE-NEXT: xxspltw v2, vs0, 1 2798; P8BE-NEXT: blr 2799; 2800; P8LE-LABEL: spltMemValui: 2801; P8LE: # %bb.0: # %entry 2802; P8LE-NEXT: lfiwzx f0, 0, r3 2803; P8LE-NEXT: xxspltw v2, vs0, 1 2804; P8LE-NEXT: blr 2805entry: 2806 %0 = load i32, i32* %ptr, align 4 2807 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 2808 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2809 ret <4 x i32> %splat.splat 2810} 2811 2812define <4 x i32> @spltCnstConvftoui() { 2813; P9BE-LABEL: spltCnstConvftoui: 2814; P9BE: # %bb.0: # %entry 2815; P9BE-NEXT: vspltisw v2, 4 2816; P9BE-NEXT: blr 2817; 2818; P9LE-LABEL: spltCnstConvftoui: 2819; P9LE: # %bb.0: # %entry 2820; P9LE-NEXT: vspltisw v2, 4 2821; P9LE-NEXT: blr 2822; 2823; P8BE-LABEL: spltCnstConvftoui: 2824; P8BE: # %bb.0: # %entry 2825; P8BE-NEXT: vspltisw v2, 4 2826; P8BE-NEXT: blr 2827; 2828; P8LE-LABEL: spltCnstConvftoui: 2829; P8LE: # %bb.0: # %entry 2830; P8LE-NEXT: vspltisw v2, 4 2831; P8LE-NEXT: blr 2832entry: 2833 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 2834} 2835 2836define <4 x i32> @fromRegsConvftoui(float %a, float %b, float %c, float %d) { 2837; P9BE-LABEL: fromRegsConvftoui: 2838; P9BE: # %bb.0: # %entry 2839; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2840; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 2841; P9BE-NEXT: xxmrghd vs0, vs2, vs4 2842; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2843; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2844; P9BE-NEXT: xvcvdpuxws v2, vs0 2845; P9BE-NEXT: xxmrghd vs0, vs1, vs3 2846; P9BE-NEXT: xvcvdpuxws v3, vs0 2847; P9BE-NEXT: vmrgew v2, v3, v2 2848; P9BE-NEXT: blr 2849; 2850; P9LE-LABEL: fromRegsConvftoui: 2851; P9LE: # %bb.0: # %entry 2852; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2853; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2854; P9LE-NEXT: xxmrghd vs0, vs3, vs1 2855; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2856; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 2857; P9LE-NEXT: xvcvdpuxws v2, vs0 2858; P9LE-NEXT: xxmrghd vs0, vs4, vs2 2859; P9LE-NEXT: xvcvdpuxws v3, vs0 2860; P9LE-NEXT: vmrgew v2, v3, v2 2861; P9LE-NEXT: blr 2862; 2863; P8BE-LABEL: fromRegsConvftoui: 2864; P8BE: # %bb.0: # %entry 2865; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2866; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2867; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2868; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 2869; P8BE-NEXT: xxmrghd vs0, vs2, vs4 2870; P8BE-NEXT: xxmrghd vs1, vs1, vs3 2871; P8BE-NEXT: xvcvdpuxws v2, vs0 2872; P8BE-NEXT: xvcvdpuxws v3, vs1 2873; P8BE-NEXT: vmrgew v2, v3, v2 2874; P8BE-NEXT: blr 2875; 2876; P8LE-LABEL: fromRegsConvftoui: 2877; P8LE: # %bb.0: # %entry 2878; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2879; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2880; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2881; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 2882; P8LE-NEXT: xxmrghd vs0, vs3, vs1 2883; P8LE-NEXT: xxmrghd vs1, vs4, vs2 2884; P8LE-NEXT: xvcvdpuxws v2, vs0 2885; P8LE-NEXT: xvcvdpuxws v3, vs1 2886; P8LE-NEXT: vmrgew v2, v3, v2 2887; P8LE-NEXT: blr 2888entry: 2889 %conv = fptoui float %a to i32 2890 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2891 %conv1 = fptoui float %b to i32 2892 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 2893 %conv3 = fptoui float %c to i32 2894 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 2895 %conv5 = fptoui float %d to i32 2896 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 2897 ret <4 x i32> %vecinit6 2898} 2899 2900define <4 x i32> @fromDiffConstsConvftoui() { 2901; P9BE-LABEL: fromDiffConstsConvftoui: 2902; P9BE: # %bb.0: # %entry 2903; P9BE-NEXT: addis r3, r2, .LCPI48_0@toc@ha 2904; P9BE-NEXT: addi r3, r3, .LCPI48_0@toc@l 2905; P9BE-NEXT: lxv v2, 0(r3) 2906; P9BE-NEXT: blr 2907; 2908; P9LE-LABEL: fromDiffConstsConvftoui: 2909; P9LE: # %bb.0: # %entry 2910; P9LE-NEXT: addis r3, r2, .LCPI48_0@toc@ha 2911; P9LE-NEXT: addi r3, r3, .LCPI48_0@toc@l 2912; P9LE-NEXT: lxv v2, 0(r3) 2913; P9LE-NEXT: blr 2914; 2915; P8BE-LABEL: fromDiffConstsConvftoui: 2916; P8BE: # %bb.0: # %entry 2917; P8BE-NEXT: addis r3, r2, .LCPI48_0@toc@ha 2918; P8BE-NEXT: addi r3, r3, .LCPI48_0@toc@l 2919; P8BE-NEXT: lxvw4x v2, 0, r3 2920; P8BE-NEXT: blr 2921; 2922; P8LE-LABEL: fromDiffConstsConvftoui: 2923; P8LE: # %bb.0: # %entry 2924; P8LE-NEXT: addis r3, r2, .LCPI48_0@toc@ha 2925; P8LE-NEXT: addi r3, r3, .LCPI48_0@toc@l 2926; P8LE-NEXT: lvx v2, 0, r3 2927; P8LE-NEXT: blr 2928entry: 2929 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 2930} 2931 2932define <4 x i32> @fromDiffMemConsAConvftoui(float* nocapture readonly %ptr) { 2933; P9BE-LABEL: fromDiffMemConsAConvftoui: 2934; P9BE: # %bb.0: # %entry 2935; P9BE-NEXT: lxv vs0, 0(r3) 2936; P9BE-NEXT: xvcvspuxws v2, vs0 2937; P9BE-NEXT: blr 2938; 2939; P9LE-LABEL: fromDiffMemConsAConvftoui: 2940; P9LE: # %bb.0: # %entry 2941; P9LE-NEXT: lxv vs0, 0(r3) 2942; P9LE-NEXT: xvcvspuxws v2, vs0 2943; P9LE-NEXT: blr 2944; 2945; P8BE-LABEL: fromDiffMemConsAConvftoui: 2946; P8BE: # %bb.0: # %entry 2947; P8BE-NEXT: lxvw4x vs0, 0, r3 2948; P8BE-NEXT: xvcvspuxws v2, vs0 2949; P8BE-NEXT: blr 2950; 2951; P8LE-LABEL: fromDiffMemConsAConvftoui: 2952; P8LE: # %bb.0: # %entry 2953; P8LE-NEXT: lxvd2x vs0, 0, r3 2954; P8LE-NEXT: xxswapd v2, vs0 2955; P8LE-NEXT: xvcvspuxws v2, v2 2956; P8LE-NEXT: blr 2957entry: 2958 %0 = bitcast float* %ptr to <4 x float>* 2959 %1 = load <4 x float>, <4 x float>* %0, align 4 2960 %2 = fptoui <4 x float> %1 to <4 x i32> 2961 ret <4 x i32> %2 2962} 2963 2964define <4 x i32> @fromDiffMemConsDConvftoui(float* nocapture readonly %ptr) { 2965; P9BE-LABEL: fromDiffMemConsDConvftoui: 2966; P9BE: # %bb.0: # %entry 2967; P9BE-NEXT: lxv v2, 0(r3) 2968; P9BE-NEXT: addis r3, r2, .LCPI50_0@toc@ha 2969; P9BE-NEXT: addi r3, r3, .LCPI50_0@toc@l 2970; P9BE-NEXT: lxv v3, 0(r3) 2971; P9BE-NEXT: vperm v2, v2, v2, v3 2972; P9BE-NEXT: xvcvspuxws v2, v2 2973; P9BE-NEXT: blr 2974; 2975; P9LE-LABEL: fromDiffMemConsDConvftoui: 2976; P9LE: # %bb.0: # %entry 2977; P9LE-NEXT: lxv v2, 0(r3) 2978; P9LE-NEXT: addis r3, r2, .LCPI50_0@toc@ha 2979; P9LE-NEXT: addi r3, r3, .LCPI50_0@toc@l 2980; P9LE-NEXT: lxv v3, 0(r3) 2981; P9LE-NEXT: vperm v2, v2, v2, v3 2982; P9LE-NEXT: xvcvspuxws v2, v2 2983; P9LE-NEXT: blr 2984; 2985; P8BE-LABEL: fromDiffMemConsDConvftoui: 2986; P8BE: # %bb.0: # %entry 2987; P8BE-NEXT: addis r4, r2, .LCPI50_0@toc@ha 2988; P8BE-NEXT: lxvw4x v2, 0, r3 2989; P8BE-NEXT: addi r4, r4, .LCPI50_0@toc@l 2990; P8BE-NEXT: lxvw4x v3, 0, r4 2991; P8BE-NEXT: vperm v2, v2, v2, v3 2992; P8BE-NEXT: xvcvspuxws v2, v2 2993; P8BE-NEXT: blr 2994; 2995; P8LE-LABEL: fromDiffMemConsDConvftoui: 2996; P8LE: # %bb.0: # %entry 2997; P8LE-NEXT: lxvd2x vs0, 0, r3 2998; P8LE-NEXT: addis r4, r2, .LCPI50_0@toc@ha 2999; P8LE-NEXT: addi r3, r4, .LCPI50_0@toc@l 3000; P8LE-NEXT: lvx v2, 0, r3 3001; P8LE-NEXT: xxswapd v3, vs0 3002; P8LE-NEXT: vperm v2, v3, v3, v2 3003; P8LE-NEXT: xvcvspuxws v2, v2 3004; P8LE-NEXT: blr 3005entry: 3006 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 3007 %0 = load float, float* %arrayidx, align 4 3008 %conv = fptoui float %0 to i32 3009 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3010 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 3011 %1 = load float, float* %arrayidx1, align 4 3012 %conv2 = fptoui float %1 to i32 3013 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 3014 %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1 3015 %2 = load float, float* %arrayidx4, align 4 3016 %conv5 = fptoui float %2 to i32 3017 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 3018 %3 = load float, float* %ptr, align 4 3019 %conv8 = fptoui float %3 to i32 3020 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 3021 ret <4 x i32> %vecinit9 3022} 3023 3024define <4 x i32> @fromDiffMemVarAConvftoui(float* nocapture readonly %arr, i32 signext %elem) { 3025; P9BE-LABEL: fromDiffMemVarAConvftoui: 3026; P9BE: # %bb.0: # %entry 3027; P9BE-NEXT: sldi r4, r4, 2 3028; P9BE-NEXT: lfsux f0, r3, r4 3029; P9BE-NEXT: lfs f1, 12(r3) 3030; P9BE-NEXT: lfs f2, 4(r3) 3031; P9BE-NEXT: xxmrghd vs1, vs2, vs1 3032; P9BE-NEXT: xvcvdpsp v2, vs1 3033; P9BE-NEXT: lfs f1, 8(r3) 3034; P9BE-NEXT: xxmrghd vs0, vs0, vs1 3035; P9BE-NEXT: xvcvdpsp v3, vs0 3036; P9BE-NEXT: vmrgew v2, v3, v2 3037; P9BE-NEXT: xvcvspuxws v2, v2 3038; P9BE-NEXT: blr 3039; 3040; P9LE-LABEL: fromDiffMemVarAConvftoui: 3041; P9LE: # %bb.0: # %entry 3042; P9LE-NEXT: sldi r4, r4, 2 3043; P9LE-NEXT: lfsux f0, r3, r4 3044; P9LE-NEXT: lfs f1, 8(r3) 3045; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3046; P9LE-NEXT: lfs f1, 12(r3) 3047; P9LE-NEXT: xvcvdpsp v2, vs0 3048; P9LE-NEXT: lfs f0, 4(r3) 3049; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3050; P9LE-NEXT: xvcvdpsp v3, vs0 3051; P9LE-NEXT: vmrgew v2, v3, v2 3052; P9LE-NEXT: xvcvspuxws v2, v2 3053; P9LE-NEXT: blr 3054; 3055; P8BE-LABEL: fromDiffMemVarAConvftoui: 3056; P8BE: # %bb.0: # %entry 3057; P8BE-NEXT: sldi r4, r4, 2 3058; P8BE-NEXT: lfsux f0, r3, r4 3059; P8BE-NEXT: lfs f1, 12(r3) 3060; P8BE-NEXT: lfs f2, 4(r3) 3061; P8BE-NEXT: lfs f3, 8(r3) 3062; P8BE-NEXT: xxmrghd vs1, vs2, vs1 3063; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3064; P8BE-NEXT: xvcvdpsp v2, vs1 3065; P8BE-NEXT: xvcvdpsp v3, vs0 3066; P8BE-NEXT: vmrgew v2, v3, v2 3067; P8BE-NEXT: xvcvspuxws v2, v2 3068; P8BE-NEXT: blr 3069; 3070; P8LE-LABEL: fromDiffMemVarAConvftoui: 3071; P8LE: # %bb.0: # %entry 3072; P8LE-NEXT: sldi r4, r4, 2 3073; P8LE-NEXT: lfsux f0, r3, r4 3074; P8LE-NEXT: lfs f1, 8(r3) 3075; P8LE-NEXT: lfs f2, 4(r3) 3076; P8LE-NEXT: lfs f3, 12(r3) 3077; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3078; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3079; P8LE-NEXT: xvcvdpsp v2, vs0 3080; P8LE-NEXT: xvcvdpsp v3, vs1 3081; P8LE-NEXT: vmrgew v2, v3, v2 3082; P8LE-NEXT: xvcvspuxws v2, v2 3083; P8LE-NEXT: blr 3084entry: 3085 %idxprom = sext i32 %elem to i64 3086 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 3087 %0 = load float, float* %arrayidx, align 4 3088 %conv = fptoui float %0 to i32 3089 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3090 %add = add nsw i32 %elem, 1 3091 %idxprom1 = sext i32 %add to i64 3092 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 3093 %1 = load float, float* %arrayidx2, align 4 3094 %conv3 = fptoui float %1 to i32 3095 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3096 %add5 = add nsw i32 %elem, 2 3097 %idxprom6 = sext i32 %add5 to i64 3098 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 3099 %2 = load float, float* %arrayidx7, align 4 3100 %conv8 = fptoui float %2 to i32 3101 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3102 %add10 = add nsw i32 %elem, 3 3103 %idxprom11 = sext i32 %add10 to i64 3104 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 3105 %3 = load float, float* %arrayidx12, align 4 3106 %conv13 = fptoui float %3 to i32 3107 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3108 ret <4 x i32> %vecinit14 3109; FIXME: implement finding consecutive loads with pre-inc 3110} 3111 3112define <4 x i32> @fromDiffMemVarDConvftoui(float* nocapture readonly %arr, i32 signext %elem) { 3113; P9BE-LABEL: fromDiffMemVarDConvftoui: 3114; P9BE: # %bb.0: # %entry 3115; P9BE-NEXT: sldi r4, r4, 2 3116; P9BE-NEXT: lfsux f0, r3, r4 3117; P9BE-NEXT: lfs f1, -12(r3) 3118; P9BE-NEXT: lfs f2, -4(r3) 3119; P9BE-NEXT: xxmrghd vs1, vs2, vs1 3120; P9BE-NEXT: xvcvdpsp v2, vs1 3121; P9BE-NEXT: lfs f1, -8(r3) 3122; P9BE-NEXT: xxmrghd vs0, vs0, vs1 3123; P9BE-NEXT: xvcvdpsp v3, vs0 3124; P9BE-NEXT: vmrgew v2, v3, v2 3125; P9BE-NEXT: xvcvspuxws v2, v2 3126; P9BE-NEXT: blr 3127; 3128; P9LE-LABEL: fromDiffMemVarDConvftoui: 3129; P9LE: # %bb.0: # %entry 3130; P9LE-NEXT: sldi r4, r4, 2 3131; P9LE-NEXT: lfsux f0, r3, r4 3132; P9LE-NEXT: lfs f1, -8(r3) 3133; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3134; P9LE-NEXT: lfs f1, -12(r3) 3135; P9LE-NEXT: xvcvdpsp v2, vs0 3136; P9LE-NEXT: lfs f0, -4(r3) 3137; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3138; P9LE-NEXT: xvcvdpsp v3, vs0 3139; P9LE-NEXT: vmrgew v2, v3, v2 3140; P9LE-NEXT: xvcvspuxws v2, v2 3141; P9LE-NEXT: blr 3142; 3143; P8BE-LABEL: fromDiffMemVarDConvftoui: 3144; P8BE: # %bb.0: # %entry 3145; P8BE-NEXT: sldi r4, r4, 2 3146; P8BE-NEXT: lfsux f0, r3, r4 3147; P8BE-NEXT: lfs f1, -12(r3) 3148; P8BE-NEXT: lfs f2, -4(r3) 3149; P8BE-NEXT: lfs f3, -8(r3) 3150; P8BE-NEXT: xxmrghd vs1, vs2, vs1 3151; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3152; P8BE-NEXT: xvcvdpsp v2, vs1 3153; P8BE-NEXT: xvcvdpsp v3, vs0 3154; P8BE-NEXT: vmrgew v2, v3, v2 3155; P8BE-NEXT: xvcvspuxws v2, v2 3156; P8BE-NEXT: blr 3157; 3158; P8LE-LABEL: fromDiffMemVarDConvftoui: 3159; P8LE: # %bb.0: # %entry 3160; P8LE-NEXT: sldi r4, r4, 2 3161; P8LE-NEXT: lfsux f0, r3, r4 3162; P8LE-NEXT: lfs f1, -8(r3) 3163; P8LE-NEXT: lfs f2, -4(r3) 3164; P8LE-NEXT: lfs f3, -12(r3) 3165; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3166; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3167; P8LE-NEXT: xvcvdpsp v2, vs0 3168; P8LE-NEXT: xvcvdpsp v3, vs1 3169; P8LE-NEXT: vmrgew v2, v3, v2 3170; P8LE-NEXT: xvcvspuxws v2, v2 3171; P8LE-NEXT: blr 3172entry: 3173 %idxprom = sext i32 %elem to i64 3174 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 3175 %0 = load float, float* %arrayidx, align 4 3176 %conv = fptoui float %0 to i32 3177 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3178 %sub = add nsw i32 %elem, -1 3179 %idxprom1 = sext i32 %sub to i64 3180 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 3181 %1 = load float, float* %arrayidx2, align 4 3182 %conv3 = fptoui float %1 to i32 3183 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3184 %sub5 = add nsw i32 %elem, -2 3185 %idxprom6 = sext i32 %sub5 to i64 3186 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 3187 %2 = load float, float* %arrayidx7, align 4 3188 %conv8 = fptoui float %2 to i32 3189 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3190 %sub10 = add nsw i32 %elem, -3 3191 %idxprom11 = sext i32 %sub10 to i64 3192 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 3193 %3 = load float, float* %arrayidx12, align 4 3194 %conv13 = fptoui float %3 to i32 3195 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3196 ret <4 x i32> %vecinit14 3197; FIXME: implement finding consecutive loads with pre-inc 3198} 3199 3200define <4 x i32> @spltRegValConvftoui(float %val) { 3201; P9BE-LABEL: spltRegValConvftoui: 3202; P9BE: # %bb.0: # %entry 3203; P9BE-NEXT: xscvdpuxws f0, f1 3204; P9BE-NEXT: xxspltw v2, vs0, 1 3205; P9BE-NEXT: blr 3206; 3207; P9LE-LABEL: spltRegValConvftoui: 3208; P9LE: # %bb.0: # %entry 3209; P9LE-NEXT: xscvdpuxws f0, f1 3210; P9LE-NEXT: xxspltw v2, vs0, 1 3211; P9LE-NEXT: blr 3212; 3213; P8BE-LABEL: spltRegValConvftoui: 3214; P8BE: # %bb.0: # %entry 3215; P8BE-NEXT: xscvdpuxws f0, f1 3216; P8BE-NEXT: xxspltw v2, vs0, 1 3217; P8BE-NEXT: blr 3218; 3219; P8LE-LABEL: spltRegValConvftoui: 3220; P8LE: # %bb.0: # %entry 3221; P8LE-NEXT: xscvdpuxws f0, f1 3222; P8LE-NEXT: xxspltw v2, vs0, 1 3223; P8LE-NEXT: blr 3224entry: 3225 %conv = fptoui float %val to i32 3226 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3227 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3228 ret <4 x i32> %splat.splat 3229} 3230 3231define <4 x i32> @spltMemValConvftoui(float* nocapture readonly %ptr) { 3232; P9BE-LABEL: spltMemValConvftoui: 3233; P9BE: # %bb.0: # %entry 3234; P9BE-NEXT: lfiwzx f0, 0, r3 3235; P9BE-NEXT: xvcvspuxws vs0, vs0 3236; P9BE-NEXT: xxspltw v2, vs0, 1 3237; P9BE-NEXT: blr 3238; 3239; P9LE-LABEL: spltMemValConvftoui: 3240; P9LE: # %bb.0: # %entry 3241; P9LE-NEXT: lfiwzx f0, 0, r3 3242; P9LE-NEXT: xvcvspuxws vs0, vs0 3243; P9LE-NEXT: xxspltw v2, vs0, 1 3244; P9LE-NEXT: blr 3245; 3246; P8BE-LABEL: spltMemValConvftoui: 3247; P8BE: # %bb.0: # %entry 3248; P8BE-NEXT: lfsx f0, 0, r3 3249; P8BE-NEXT: xscvdpuxws f0, f0 3250; P8BE-NEXT: xxspltw v2, vs0, 1 3251; P8BE-NEXT: blr 3252; 3253; P8LE-LABEL: spltMemValConvftoui: 3254; P8LE: # %bb.0: # %entry 3255; P8LE-NEXT: lfsx f0, 0, r3 3256; P8LE-NEXT: xscvdpuxws f0, f0 3257; P8LE-NEXT: xxspltw v2, vs0, 1 3258; P8LE-NEXT: blr 3259entry: 3260 %0 = load float, float* %ptr, align 4 3261 %conv = fptoui float %0 to i32 3262 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3263 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3264 ret <4 x i32> %splat.splat 3265} 3266 3267define <4 x i32> @spltCnstConvdtoui() { 3268; P9BE-LABEL: spltCnstConvdtoui: 3269; P9BE: # %bb.0: # %entry 3270; P9BE-NEXT: vspltisw v2, 4 3271; P9BE-NEXT: blr 3272; 3273; P9LE-LABEL: spltCnstConvdtoui: 3274; P9LE: # %bb.0: # %entry 3275; P9LE-NEXT: vspltisw v2, 4 3276; P9LE-NEXT: blr 3277; 3278; P8BE-LABEL: spltCnstConvdtoui: 3279; P8BE: # %bb.0: # %entry 3280; P8BE-NEXT: vspltisw v2, 4 3281; P8BE-NEXT: blr 3282; 3283; P8LE-LABEL: spltCnstConvdtoui: 3284; P8LE: # %bb.0: # %entry 3285; P8LE-NEXT: vspltisw v2, 4 3286; P8LE-NEXT: blr 3287entry: 3288 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 3289} 3290 3291define <4 x i32> @fromRegsConvdtoui(double %a, double %b, double %c, double %d) { 3292; P9BE-LABEL: fromRegsConvdtoui: 3293; P9BE: # %bb.0: # %entry 3294; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3295; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3296; P9BE-NEXT: xxmrghd vs0, vs2, vs4 3297; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3298; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3299; P9BE-NEXT: xvcvdpuxws v2, vs0 3300; P9BE-NEXT: xxmrghd vs0, vs1, vs3 3301; P9BE-NEXT: xvcvdpuxws v3, vs0 3302; P9BE-NEXT: vmrgew v2, v3, v2 3303; P9BE-NEXT: blr 3304; 3305; P9LE-LABEL: fromRegsConvdtoui: 3306; P9LE: # %bb.0: # %entry 3307; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3308; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3309; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3310; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3311; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3312; P9LE-NEXT: xvcvdpuxws v2, vs0 3313; P9LE-NEXT: xxmrghd vs0, vs4, vs2 3314; P9LE-NEXT: xvcvdpuxws v3, vs0 3315; P9LE-NEXT: vmrgew v2, v3, v2 3316; P9LE-NEXT: blr 3317; 3318; P8BE-LABEL: fromRegsConvdtoui: 3319; P8BE: # %bb.0: # %entry 3320; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3321; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3322; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3323; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3324; P8BE-NEXT: xxmrghd vs0, vs2, vs4 3325; P8BE-NEXT: xxmrghd vs1, vs1, vs3 3326; P8BE-NEXT: xvcvdpuxws v2, vs0 3327; P8BE-NEXT: xvcvdpuxws v3, vs1 3328; P8BE-NEXT: vmrgew v2, v3, v2 3329; P8BE-NEXT: blr 3330; 3331; P8LE-LABEL: fromRegsConvdtoui: 3332; P8LE: # %bb.0: # %entry 3333; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3334; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3335; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3336; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3337; P8LE-NEXT: xxmrghd vs0, vs3, vs1 3338; P8LE-NEXT: xxmrghd vs1, vs4, vs2 3339; P8LE-NEXT: xvcvdpuxws v2, vs0 3340; P8LE-NEXT: xvcvdpuxws v3, vs1 3341; P8LE-NEXT: vmrgew v2, v3, v2 3342; P8LE-NEXT: blr 3343entry: 3344 %conv = fptoui double %a to i32 3345 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3346 %conv1 = fptoui double %b to i32 3347 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 3348 %conv3 = fptoui double %c to i32 3349 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 3350 %conv5 = fptoui double %d to i32 3351 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 3352 ret <4 x i32> %vecinit6 3353} 3354 3355define <4 x i32> @fromDiffConstsConvdtoui() { 3356; P9BE-LABEL: fromDiffConstsConvdtoui: 3357; P9BE: # %bb.0: # %entry 3358; P9BE-NEXT: addis r3, r2, .LCPI57_0@toc@ha 3359; P9BE-NEXT: addi r3, r3, .LCPI57_0@toc@l 3360; P9BE-NEXT: lxv v2, 0(r3) 3361; P9BE-NEXT: blr 3362; 3363; P9LE-LABEL: fromDiffConstsConvdtoui: 3364; P9LE: # %bb.0: # %entry 3365; P9LE-NEXT: addis r3, r2, .LCPI57_0@toc@ha 3366; P9LE-NEXT: addi r3, r3, .LCPI57_0@toc@l 3367; P9LE-NEXT: lxv v2, 0(r3) 3368; P9LE-NEXT: blr 3369; 3370; P8BE-LABEL: fromDiffConstsConvdtoui: 3371; P8BE: # %bb.0: # %entry 3372; P8BE-NEXT: addis r3, r2, .LCPI57_0@toc@ha 3373; P8BE-NEXT: addi r3, r3, .LCPI57_0@toc@l 3374; P8BE-NEXT: lxvw4x v2, 0, r3 3375; P8BE-NEXT: blr 3376; 3377; P8LE-LABEL: fromDiffConstsConvdtoui: 3378; P8LE: # %bb.0: # %entry 3379; P8LE-NEXT: addis r3, r2, .LCPI57_0@toc@ha 3380; P8LE-NEXT: addi r3, r3, .LCPI57_0@toc@l 3381; P8LE-NEXT: lvx v2, 0, r3 3382; P8LE-NEXT: blr 3383entry: 3384 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 3385} 3386 3387define <4 x i32> @fromDiffMemConsAConvdtoui(double* nocapture readonly %ptr) { 3388; P9BE-LABEL: fromDiffMemConsAConvdtoui: 3389; P9BE: # %bb.0: # %entry 3390; P9BE-NEXT: lxv vs0, 0(r3) 3391; P9BE-NEXT: lxv vs1, 16(r3) 3392; P9BE-NEXT: xxmrgld vs2, vs0, vs1 3393; P9BE-NEXT: xxmrghd vs0, vs0, vs1 3394; P9BE-NEXT: xvcvdpuxws v2, vs2 3395; P9BE-NEXT: xvcvdpuxws v3, vs0 3396; P9BE-NEXT: vmrgew v2, v3, v2 3397; P9BE-NEXT: blr 3398; 3399; P9LE-LABEL: fromDiffMemConsAConvdtoui: 3400; P9LE: # %bb.0: # %entry 3401; P9LE-NEXT: lxv vs0, 0(r3) 3402; P9LE-NEXT: lxv vs1, 16(r3) 3403; P9LE-NEXT: xxmrgld vs2, vs1, vs0 3404; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3405; P9LE-NEXT: xvcvdpuxws v2, vs2 3406; P9LE-NEXT: xvcvdpuxws v3, vs0 3407; P9LE-NEXT: vmrgew v2, v3, v2 3408; P9LE-NEXT: blr 3409; 3410; P8BE-LABEL: fromDiffMemConsAConvdtoui: 3411; P8BE: # %bb.0: # %entry 3412; P8BE-NEXT: li r4, 16 3413; P8BE-NEXT: lxvd2x vs0, 0, r3 3414; P8BE-NEXT: lxvd2x vs1, r3, r4 3415; P8BE-NEXT: xxmrgld vs2, vs0, vs1 3416; P8BE-NEXT: xxmrghd vs0, vs0, vs1 3417; P8BE-NEXT: xvcvdpuxws v2, vs2 3418; P8BE-NEXT: xvcvdpuxws v3, vs0 3419; P8BE-NEXT: vmrgew v2, v3, v2 3420; P8BE-NEXT: blr 3421; 3422; P8LE-LABEL: fromDiffMemConsAConvdtoui: 3423; P8LE: # %bb.0: # %entry 3424; P8LE-NEXT: li r4, 16 3425; P8LE-NEXT: lxvd2x vs0, 0, r3 3426; P8LE-NEXT: lxvd2x vs1, r3, r4 3427; P8LE-NEXT: xxswapd vs0, vs0 3428; P8LE-NEXT: xxswapd vs1, vs1 3429; P8LE-NEXT: xxmrgld vs2, vs1, vs0 3430; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3431; P8LE-NEXT: xvcvdpuxws v2, vs2 3432; P8LE-NEXT: xvcvdpuxws v3, vs0 3433; P8LE-NEXT: vmrgew v2, v3, v2 3434; P8LE-NEXT: blr 3435entry: 3436 %0 = bitcast double* %ptr to <2 x double>* 3437 %1 = load <2 x double>, <2 x double>* %0, align 8 3438 %2 = fptoui <2 x double> %1 to <2 x i32> 3439 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 2 3440 %3 = bitcast double* %arrayidx4 to <2 x double>* 3441 %4 = load <2 x double>, <2 x double>* %3, align 8 3442 %5 = fptoui <2 x double> %4 to <2 x i32> 3443 %vecinit9 = shufflevector <2 x i32> %2, <2 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 3444 ret <4 x i32> %vecinit9 3445} 3446 3447define <4 x i32> @fromDiffMemConsDConvdtoui(double* nocapture readonly %ptr) { 3448; P9BE-LABEL: fromDiffMemConsDConvdtoui: 3449; P9BE: # %bb.0: # %entry 3450; P9BE-NEXT: lfd f0, 24(r3) 3451; P9BE-NEXT: lfd f1, 16(r3) 3452; P9BE-NEXT: lfd f2, 8(r3) 3453; P9BE-NEXT: xxmrghd vs0, vs0, vs2 3454; P9BE-NEXT: lfd f3, 0(r3) 3455; P9BE-NEXT: xxmrghd vs1, vs1, vs3 3456; P9BE-NEXT: xvcvdpuxws v2, vs1 3457; P9BE-NEXT: xvcvdpuxws v3, vs0 3458; P9BE-NEXT: vmrgew v2, v3, v2 3459; P9BE-NEXT: blr 3460; 3461; P9LE-LABEL: fromDiffMemConsDConvdtoui: 3462; P9LE: # %bb.0: # %entry 3463; P9LE-NEXT: lfd f0, 24(r3) 3464; P9LE-NEXT: lfd f2, 8(r3) 3465; P9LE-NEXT: xxmrghd vs0, vs2, vs0 3466; P9LE-NEXT: lfd f1, 16(r3) 3467; P9LE-NEXT: lfd f3, 0(r3) 3468; P9LE-NEXT: xvcvdpuxws v2, vs0 3469; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3470; P9LE-NEXT: xvcvdpuxws v3, vs0 3471; P9LE-NEXT: vmrgew v2, v3, v2 3472; P9LE-NEXT: blr 3473; 3474; P8BE-LABEL: fromDiffMemConsDConvdtoui: 3475; P8BE: # %bb.0: # %entry 3476; P8BE-NEXT: lfd f0, 16(r3) 3477; P8BE-NEXT: lfd f1, 0(r3) 3478; P8BE-NEXT: lfd f2, 24(r3) 3479; P8BE-NEXT: lfd f3, 8(r3) 3480; P8BE-NEXT: xxmrghd vs0, vs0, vs1 3481; P8BE-NEXT: xxmrghd vs1, vs2, vs3 3482; P8BE-NEXT: xvcvdpuxws v2, vs0 3483; P8BE-NEXT: xvcvdpuxws v3, vs1 3484; P8BE-NEXT: vmrgew v2, v3, v2 3485; P8BE-NEXT: blr 3486; 3487; P8LE-LABEL: fromDiffMemConsDConvdtoui: 3488; P8LE: # %bb.0: # %entry 3489; P8LE-NEXT: lfd f0, 24(r3) 3490; P8LE-NEXT: lfd f1, 8(r3) 3491; P8LE-NEXT: lfd f2, 16(r3) 3492; P8LE-NEXT: lfd f3, 0(r3) 3493; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3494; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3495; P8LE-NEXT: xvcvdpuxws v2, vs0 3496; P8LE-NEXT: xvcvdpuxws v3, vs1 3497; P8LE-NEXT: vmrgew v2, v3, v2 3498; P8LE-NEXT: blr 3499entry: 3500 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 3501 %0 = load double, double* %arrayidx, align 8 3502 %conv = fptoui double %0 to i32 3503 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3504 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 3505 %1 = load double, double* %arrayidx1, align 8 3506 %conv2 = fptoui double %1 to i32 3507 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 3508 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 1 3509 %2 = load double, double* %arrayidx4, align 8 3510 %conv5 = fptoui double %2 to i32 3511 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 3512 %3 = load double, double* %ptr, align 8 3513 %conv8 = fptoui double %3 to i32 3514 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 3515 ret <4 x i32> %vecinit9 3516} 3517 3518define <4 x i32> @fromDiffMemVarAConvdtoui(double* nocapture readonly %arr, i32 signext %elem) { 3519; P9BE-LABEL: fromDiffMemVarAConvdtoui: 3520; P9BE: # %bb.0: # %entry 3521; P9BE-NEXT: sldi r4, r4, 3 3522; P9BE-NEXT: lfdux f0, r3, r4 3523; P9BE-NEXT: lfd f1, 8(r3) 3524; P9BE-NEXT: lfd f2, 16(r3) 3525; P9BE-NEXT: lfd f3, 24(r3) 3526; P9BE-NEXT: xxmrghd vs1, vs1, vs3 3527; P9BE-NEXT: xxmrghd vs0, vs0, vs2 3528; P9BE-NEXT: xvcvdpuxws v2, vs1 3529; P9BE-NEXT: xvcvdpuxws v3, vs0 3530; P9BE-NEXT: vmrgew v2, v3, v2 3531; P9BE-NEXT: blr 3532; 3533; P9LE-LABEL: fromDiffMemVarAConvdtoui: 3534; P9LE: # %bb.0: # %entry 3535; P9LE-NEXT: sldi r4, r4, 3 3536; P9LE-NEXT: lfdux f0, r3, r4 3537; P9LE-NEXT: lfd f2, 16(r3) 3538; P9LE-NEXT: lfd f1, 8(r3) 3539; P9LE-NEXT: lfd f3, 24(r3) 3540; P9LE-NEXT: xxmrghd vs0, vs2, vs0 3541; P9LE-NEXT: xvcvdpuxws v2, vs0 3542; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3543; P9LE-NEXT: xvcvdpuxws v3, vs0 3544; P9LE-NEXT: vmrgew v2, v3, v2 3545; P9LE-NEXT: blr 3546; 3547; P8BE-LABEL: fromDiffMemVarAConvdtoui: 3548; P8BE: # %bb.0: # %entry 3549; P8BE-NEXT: sldi r4, r4, 3 3550; P8BE-NEXT: lfdux f0, r3, r4 3551; P8BE-NEXT: lfd f1, 8(r3) 3552; P8BE-NEXT: lfd f2, 24(r3) 3553; P8BE-NEXT: lfd f3, 16(r3) 3554; P8BE-NEXT: xxmrghd vs1, vs1, vs2 3555; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3556; P8BE-NEXT: xvcvdpuxws v2, vs1 3557; P8BE-NEXT: xvcvdpuxws v3, vs0 3558; P8BE-NEXT: vmrgew v2, v3, v2 3559; P8BE-NEXT: blr 3560; 3561; P8LE-LABEL: fromDiffMemVarAConvdtoui: 3562; P8LE: # %bb.0: # %entry 3563; P8LE-NEXT: sldi r4, r4, 3 3564; P8LE-NEXT: lfdux f0, r3, r4 3565; P8LE-NEXT: lfd f1, 16(r3) 3566; P8LE-NEXT: lfd f2, 8(r3) 3567; P8LE-NEXT: lfd f3, 24(r3) 3568; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3569; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3570; P8LE-NEXT: xvcvdpuxws v2, vs0 3571; P8LE-NEXT: xvcvdpuxws v3, vs1 3572; P8LE-NEXT: vmrgew v2, v3, v2 3573; P8LE-NEXT: blr 3574entry: 3575 %idxprom = sext i32 %elem to i64 3576 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 3577 %0 = load double, double* %arrayidx, align 8 3578 %conv = fptoui double %0 to i32 3579 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3580 %add = add nsw i32 %elem, 1 3581 %idxprom1 = sext i32 %add to i64 3582 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 3583 %1 = load double, double* %arrayidx2, align 8 3584 %conv3 = fptoui double %1 to i32 3585 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3586 %add5 = add nsw i32 %elem, 2 3587 %idxprom6 = sext i32 %add5 to i64 3588 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 3589 %2 = load double, double* %arrayidx7, align 8 3590 %conv8 = fptoui double %2 to i32 3591 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3592 %add10 = add nsw i32 %elem, 3 3593 %idxprom11 = sext i32 %add10 to i64 3594 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 3595 %3 = load double, double* %arrayidx12, align 8 3596 %conv13 = fptoui double %3 to i32 3597 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3598 ret <4 x i32> %vecinit14 3599} 3600 3601define <4 x i32> @fromDiffMemVarDConvdtoui(double* nocapture readonly %arr, i32 signext %elem) { 3602; P9BE-LABEL: fromDiffMemVarDConvdtoui: 3603; P9BE: # %bb.0: # %entry 3604; P9BE-NEXT: sldi r4, r4, 3 3605; P9BE-NEXT: lfdux f0, r3, r4 3606; P9BE-NEXT: lfd f1, -8(r3) 3607; P9BE-NEXT: lfd f2, -16(r3) 3608; P9BE-NEXT: lfd f3, -24(r3) 3609; P9BE-NEXT: xxmrghd vs1, vs1, vs3 3610; P9BE-NEXT: xxmrghd vs0, vs0, vs2 3611; P9BE-NEXT: xvcvdpuxws v2, vs1 3612; P9BE-NEXT: xvcvdpuxws v3, vs0 3613; P9BE-NEXT: vmrgew v2, v3, v2 3614; P9BE-NEXT: blr 3615; 3616; P9LE-LABEL: fromDiffMemVarDConvdtoui: 3617; P9LE: # %bb.0: # %entry 3618; P9LE-NEXT: sldi r4, r4, 3 3619; P9LE-NEXT: lfdux f0, r3, r4 3620; P9LE-NEXT: lfd f2, -16(r3) 3621; P9LE-NEXT: lfd f1, -8(r3) 3622; P9LE-NEXT: lfd f3, -24(r3) 3623; P9LE-NEXT: xxmrghd vs0, vs2, vs0 3624; P9LE-NEXT: xvcvdpuxws v2, vs0 3625; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3626; P9LE-NEXT: xvcvdpuxws v3, vs0 3627; P9LE-NEXT: vmrgew v2, v3, v2 3628; P9LE-NEXT: blr 3629; 3630; P8BE-LABEL: fromDiffMemVarDConvdtoui: 3631; P8BE: # %bb.0: # %entry 3632; P8BE-NEXT: sldi r4, r4, 3 3633; P8BE-NEXT: lfdux f0, r3, r4 3634; P8BE-NEXT: lfd f1, -8(r3) 3635; P8BE-NEXT: lfd f2, -24(r3) 3636; P8BE-NEXT: lfd f3, -16(r3) 3637; P8BE-NEXT: xxmrghd vs1, vs1, vs2 3638; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3639; P8BE-NEXT: xvcvdpuxws v2, vs1 3640; P8BE-NEXT: xvcvdpuxws v3, vs0 3641; P8BE-NEXT: vmrgew v2, v3, v2 3642; P8BE-NEXT: blr 3643; 3644; P8LE-LABEL: fromDiffMemVarDConvdtoui: 3645; P8LE: # %bb.0: # %entry 3646; P8LE-NEXT: sldi r4, r4, 3 3647; P8LE-NEXT: lfdux f0, r3, r4 3648; P8LE-NEXT: lfd f1, -16(r3) 3649; P8LE-NEXT: lfd f2, -8(r3) 3650; P8LE-NEXT: lfd f3, -24(r3) 3651; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3652; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3653; P8LE-NEXT: xvcvdpuxws v2, vs0 3654; P8LE-NEXT: xvcvdpuxws v3, vs1 3655; P8LE-NEXT: vmrgew v2, v3, v2 3656; P8LE-NEXT: blr 3657entry: 3658 %idxprom = sext i32 %elem to i64 3659 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 3660 %0 = load double, double* %arrayidx, align 8 3661 %conv = fptoui double %0 to i32 3662 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3663 %sub = add nsw i32 %elem, -1 3664 %idxprom1 = sext i32 %sub to i64 3665 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 3666 %1 = load double, double* %arrayidx2, align 8 3667 %conv3 = fptoui double %1 to i32 3668 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3669 %sub5 = add nsw i32 %elem, -2 3670 %idxprom6 = sext i32 %sub5 to i64 3671 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 3672 %2 = load double, double* %arrayidx7, align 8 3673 %conv8 = fptoui double %2 to i32 3674 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3675 %sub10 = add nsw i32 %elem, -3 3676 %idxprom11 = sext i32 %sub10 to i64 3677 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 3678 %3 = load double, double* %arrayidx12, align 8 3679 %conv13 = fptoui double %3 to i32 3680 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3681 ret <4 x i32> %vecinit14 3682} 3683 3684define <4 x i32> @spltRegValConvdtoui(double %val) { 3685; P9BE-LABEL: spltRegValConvdtoui: 3686; P9BE: # %bb.0: # %entry 3687; P9BE-NEXT: xscvdpuxws f0, f1 3688; P9BE-NEXT: xxspltw v2, vs0, 1 3689; P9BE-NEXT: blr 3690; 3691; P9LE-LABEL: spltRegValConvdtoui: 3692; P9LE: # %bb.0: # %entry 3693; P9LE-NEXT: xscvdpuxws f0, f1 3694; P9LE-NEXT: xxspltw v2, vs0, 1 3695; P9LE-NEXT: blr 3696; 3697; P8BE-LABEL: spltRegValConvdtoui: 3698; P8BE: # %bb.0: # %entry 3699; P8BE-NEXT: xscvdpuxws f0, f1 3700; P8BE-NEXT: xxspltw v2, vs0, 1 3701; P8BE-NEXT: blr 3702; 3703; P8LE-LABEL: spltRegValConvdtoui: 3704; P8LE: # %bb.0: # %entry 3705; P8LE-NEXT: xscvdpuxws f0, f1 3706; P8LE-NEXT: xxspltw v2, vs0, 1 3707; P8LE-NEXT: blr 3708entry: 3709 %conv = fptoui double %val to i32 3710 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3711 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3712 ret <4 x i32> %splat.splat 3713} 3714 3715define <4 x i32> @spltMemValConvdtoui(double* nocapture readonly %ptr) { 3716; P9BE-LABEL: spltMemValConvdtoui: 3717; P9BE: # %bb.0: # %entry 3718; P9BE-NEXT: lfd f0, 0(r3) 3719; P9BE-NEXT: xscvdpuxws f0, f0 3720; P9BE-NEXT: xxspltw v2, vs0, 1 3721; P9BE-NEXT: blr 3722; 3723; P9LE-LABEL: spltMemValConvdtoui: 3724; P9LE: # %bb.0: # %entry 3725; P9LE-NEXT: lfd f0, 0(r3) 3726; P9LE-NEXT: xscvdpuxws f0, f0 3727; P9LE-NEXT: xxspltw v2, vs0, 1 3728; P9LE-NEXT: blr 3729; 3730; P8BE-LABEL: spltMemValConvdtoui: 3731; P8BE: # %bb.0: # %entry 3732; P8BE-NEXT: lfdx f0, 0, r3 3733; P8BE-NEXT: xscvdpuxws f0, f0 3734; P8BE-NEXT: xxspltw v2, vs0, 1 3735; P8BE-NEXT: blr 3736; 3737; P8LE-LABEL: spltMemValConvdtoui: 3738; P8LE: # %bb.0: # %entry 3739; P8LE-NEXT: lfdx f0, 0, r3 3740; P8LE-NEXT: xscvdpuxws f0, f0 3741; P8LE-NEXT: xxspltw v2, vs0, 1 3742; P8LE-NEXT: blr 3743entry: 3744 %0 = load double, double* %ptr, align 8 3745 %conv = fptoui double %0 to i32 3746 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3747 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3748 ret <4 x i32> %splat.splat 3749} 3750 3751define <2 x i64> @allZeroll() { 3752; P9BE-LABEL: allZeroll: 3753; P9BE: # %bb.0: # %entry 3754; P9BE-NEXT: xxlxor v2, v2, v2 3755; P9BE-NEXT: blr 3756; 3757; P9LE-LABEL: allZeroll: 3758; P9LE: # %bb.0: # %entry 3759; P9LE-NEXT: xxlxor v2, v2, v2 3760; P9LE-NEXT: blr 3761; 3762; P8BE-LABEL: allZeroll: 3763; P8BE: # %bb.0: # %entry 3764; P8BE-NEXT: xxlxor v2, v2, v2 3765; P8BE-NEXT: blr 3766; 3767; P8LE-LABEL: allZeroll: 3768; P8LE: # %bb.0: # %entry 3769; P8LE-NEXT: xxlxor v2, v2, v2 3770; P8LE-NEXT: blr 3771entry: 3772 ret <2 x i64> zeroinitializer 3773} 3774 3775define <2 x i64> @spltConst1ll() { 3776; P9BE-LABEL: spltConst1ll: 3777; P9BE: # %bb.0: # %entry 3778; P9BE-NEXT: addis r3, r2, .LCPI65_0@toc@ha 3779; P9BE-NEXT: addi r3, r3, .LCPI65_0@toc@l 3780; P9BE-NEXT: lxv v2, 0(r3) 3781; P9BE-NEXT: blr 3782; 3783; P9LE-LABEL: spltConst1ll: 3784; P9LE: # %bb.0: # %entry 3785; P9LE-NEXT: addis r3, r2, .LCPI65_0@toc@ha 3786; P9LE-NEXT: addi r3, r3, .LCPI65_0@toc@l 3787; P9LE-NEXT: lxv v2, 0(r3) 3788; P9LE-NEXT: blr 3789; 3790; P8BE-LABEL: spltConst1ll: 3791; P8BE: # %bb.0: # %entry 3792; P8BE-NEXT: addis r3, r2, .LCPI65_0@toc@ha 3793; P8BE-NEXT: addi r3, r3, .LCPI65_0@toc@l 3794; P8BE-NEXT: lxvd2x v2, 0, r3 3795; P8BE-NEXT: blr 3796; 3797; P8LE-LABEL: spltConst1ll: 3798; P8LE: # %bb.0: # %entry 3799; P8LE-NEXT: addis r3, r2, .LCPI65_0@toc@ha 3800; P8LE-NEXT: addi r3, r3, .LCPI65_0@toc@l 3801; P8LE-NEXT: lxvd2x vs0, 0, r3 3802; P8LE-NEXT: xxswapd v2, vs0 3803; P8LE-NEXT: blr 3804entry: 3805 ret <2 x i64> <i64 1, i64 1> 3806} 3807 3808define <2 x i64> @spltConst16kll() { 3809; P9BE-LABEL: spltConst16kll: 3810; P9BE: # %bb.0: # %entry 3811; P9BE-NEXT: addis r3, r2, .LCPI66_0@toc@ha 3812; P9BE-NEXT: addi r3, r3, .LCPI66_0@toc@l 3813; P9BE-NEXT: lxv v2, 0(r3) 3814; P9BE-NEXT: blr 3815; 3816; P9LE-LABEL: spltConst16kll: 3817; P9LE: # %bb.0: # %entry 3818; P9LE-NEXT: addis r3, r2, .LCPI66_0@toc@ha 3819; P9LE-NEXT: addi r3, r3, .LCPI66_0@toc@l 3820; P9LE-NEXT: lxv v2, 0(r3) 3821; P9LE-NEXT: blr 3822; 3823; P8BE-LABEL: spltConst16kll: 3824; P8BE: # %bb.0: # %entry 3825; P8BE-NEXT: addis r3, r2, .LCPI66_0@toc@ha 3826; P8BE-NEXT: addi r3, r3, .LCPI66_0@toc@l 3827; P8BE-NEXT: lxvd2x v2, 0, r3 3828; P8BE-NEXT: blr 3829; 3830; P8LE-LABEL: spltConst16kll: 3831; P8LE: # %bb.0: # %entry 3832; P8LE-NEXT: addis r3, r2, .LCPI66_0@toc@ha 3833; P8LE-NEXT: addi r3, r3, .LCPI66_0@toc@l 3834; P8LE-NEXT: lxvd2x vs0, 0, r3 3835; P8LE-NEXT: xxswapd v2, vs0 3836; P8LE-NEXT: blr 3837entry: 3838 ret <2 x i64> <i64 32767, i64 32767> 3839} 3840 3841define <2 x i64> @spltConst32kll() { 3842; P9BE-LABEL: spltConst32kll: 3843; P9BE: # %bb.0: # %entry 3844; P9BE-NEXT: addis r3, r2, .LCPI67_0@toc@ha 3845; P9BE-NEXT: addi r3, r3, .LCPI67_0@toc@l 3846; P9BE-NEXT: lxv v2, 0(r3) 3847; P9BE-NEXT: blr 3848; 3849; P9LE-LABEL: spltConst32kll: 3850; P9LE: # %bb.0: # %entry 3851; P9LE-NEXT: addis r3, r2, .LCPI67_0@toc@ha 3852; P9LE-NEXT: addi r3, r3, .LCPI67_0@toc@l 3853; P9LE-NEXT: lxv v2, 0(r3) 3854; P9LE-NEXT: blr 3855; 3856; P8BE-LABEL: spltConst32kll: 3857; P8BE: # %bb.0: # %entry 3858; P8BE-NEXT: addis r3, r2, .LCPI67_0@toc@ha 3859; P8BE-NEXT: addi r3, r3, .LCPI67_0@toc@l 3860; P8BE-NEXT: lxvd2x v2, 0, r3 3861; P8BE-NEXT: blr 3862; 3863; P8LE-LABEL: spltConst32kll: 3864; P8LE: # %bb.0: # %entry 3865; P8LE-NEXT: addis r3, r2, .LCPI67_0@toc@ha 3866; P8LE-NEXT: addi r3, r3, .LCPI67_0@toc@l 3867; P8LE-NEXT: lxvd2x vs0, 0, r3 3868; P8LE-NEXT: xxswapd v2, vs0 3869; P8LE-NEXT: blr 3870entry: 3871 ret <2 x i64> <i64 65535, i64 65535> 3872} 3873 3874define <2 x i64> @fromRegsll(i64 %a, i64 %b) { 3875; P9BE-LABEL: fromRegsll: 3876; P9BE: # %bb.0: # %entry 3877; P9BE-NEXT: mtvsrdd v2, r3, r4 3878; P9BE-NEXT: blr 3879; 3880; P9LE-LABEL: fromRegsll: 3881; P9LE: # %bb.0: # %entry 3882; P9LE-NEXT: mtvsrdd v2, r4, r3 3883; P9LE-NEXT: blr 3884; 3885; P8BE-LABEL: fromRegsll: 3886; P8BE: # %bb.0: # %entry 3887; P8BE-NEXT: mtfprd f0, r4 3888; P8BE-NEXT: mtfprd f1, r3 3889; P8BE-NEXT: xxmrghd v2, vs1, vs0 3890; P8BE-NEXT: blr 3891; 3892; P8LE-LABEL: fromRegsll: 3893; P8LE: # %bb.0: # %entry 3894; P8LE-NEXT: mtfprd f0, r3 3895; P8LE-NEXT: mtfprd f1, r4 3896; P8LE-NEXT: xxmrghd v2, vs1, vs0 3897; P8LE-NEXT: blr 3898entry: 3899 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 3900 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 3901 ret <2 x i64> %vecinit1 3902} 3903 3904define <2 x i64> @fromDiffConstsll() { 3905; P9BE-LABEL: fromDiffConstsll: 3906; P9BE: # %bb.0: # %entry 3907; P9BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3908; P9BE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3909; P9BE-NEXT: lxv v2, 0(r3) 3910; P9BE-NEXT: blr 3911; 3912; P9LE-LABEL: fromDiffConstsll: 3913; P9LE: # %bb.0: # %entry 3914; P9LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3915; P9LE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3916; P9LE-NEXT: lxv v2, 0(r3) 3917; P9LE-NEXT: blr 3918; 3919; P8BE-LABEL: fromDiffConstsll: 3920; P8BE: # %bb.0: # %entry 3921; P8BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3922; P8BE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3923; P8BE-NEXT: lxvd2x v2, 0, r3 3924; P8BE-NEXT: blr 3925; 3926; P8LE-LABEL: fromDiffConstsll: 3927; P8LE: # %bb.0: # %entry 3928; P8LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3929; P8LE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3930; P8LE-NEXT: lxvd2x vs0, 0, r3 3931; P8LE-NEXT: xxswapd v2, vs0 3932; P8LE-NEXT: blr 3933entry: 3934 ret <2 x i64> <i64 242, i64 -113> 3935} 3936 3937define <2 x i64> @fromDiffMemConsAll(i64* nocapture readonly %arr) { 3938; P9BE-LABEL: fromDiffMemConsAll: 3939; P9BE: # %bb.0: # %entry 3940; P9BE-NEXT: lxv v2, 0(r3) 3941; P9BE-NEXT: blr 3942; 3943; P9LE-LABEL: fromDiffMemConsAll: 3944; P9LE: # %bb.0: # %entry 3945; P9LE-NEXT: lxv v2, 0(r3) 3946; P9LE-NEXT: blr 3947; 3948; P8BE-LABEL: fromDiffMemConsAll: 3949; P8BE: # %bb.0: # %entry 3950; P8BE-NEXT: lxvd2x v2, 0, r3 3951; P8BE-NEXT: blr 3952; 3953; P8LE-LABEL: fromDiffMemConsAll: 3954; P8LE: # %bb.0: # %entry 3955; P8LE-NEXT: lxvd2x vs0, 0, r3 3956; P8LE-NEXT: xxswapd v2, vs0 3957; P8LE-NEXT: blr 3958entry: 3959 %0 = load i64, i64* %arr, align 8 3960 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3961 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 1 3962 %1 = load i64, i64* %arrayidx1, align 8 3963 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3964 ret <2 x i64> %vecinit2 3965} 3966 3967define <2 x i64> @fromDiffMemConsDll(i64* nocapture readonly %arr) { 3968; P9BE-LABEL: fromDiffMemConsDll: 3969; P9BE: # %bb.0: # %entry 3970; P9BE-NEXT: lxv v2, 16(r3) 3971; P9BE-NEXT: xxswapd v2, v2 3972; P9BE-NEXT: blr 3973; 3974; P9LE-LABEL: fromDiffMemConsDll: 3975; P9LE: # %bb.0: # %entry 3976; P9LE-NEXT: addi r3, r3, 16 3977; P9LE-NEXT: lxvd2x v2, 0, r3 3978; P9LE-NEXT: blr 3979; 3980; P8BE-LABEL: fromDiffMemConsDll: 3981; P8BE: # %bb.0: # %entry 3982; P8BE-NEXT: addi r3, r3, 16 3983; P8BE-NEXT: lxvd2x v2, 0, r3 3984; P8BE-NEXT: xxswapd v2, v2 3985; P8BE-NEXT: blr 3986; 3987; P8LE-LABEL: fromDiffMemConsDll: 3988; P8LE: # %bb.0: # %entry 3989; P8LE-NEXT: addi r3, r3, 16 3990; P8LE-NEXT: lxvd2x v2, 0, r3 3991; P8LE-NEXT: blr 3992entry: 3993 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 3 3994 %0 = load i64, i64* %arrayidx, align 8 3995 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3996 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 2 3997 %1 = load i64, i64* %arrayidx1, align 8 3998 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3999 ret <2 x i64> %vecinit2 4000} 4001 4002define <2 x i64> @fromDiffMemVarAll(i64* nocapture readonly %arr, i32 signext %elem) { 4003; P9BE-LABEL: fromDiffMemVarAll: 4004; P9BE: # %bb.0: # %entry 4005; P9BE-NEXT: sldi r4, r4, 3 4006; P9BE-NEXT: lxvx v2, r3, r4 4007; P9BE-NEXT: blr 4008; 4009; P9LE-LABEL: fromDiffMemVarAll: 4010; P9LE: # %bb.0: # %entry 4011; P9LE-NEXT: sldi r4, r4, 3 4012; P9LE-NEXT: lxvx v2, r3, r4 4013; P9LE-NEXT: blr 4014; 4015; P8BE-LABEL: fromDiffMemVarAll: 4016; P8BE: # %bb.0: # %entry 4017; P8BE-NEXT: sldi r4, r4, 3 4018; P8BE-NEXT: lxvd2x v2, r3, r4 4019; P8BE-NEXT: blr 4020; 4021; P8LE-LABEL: fromDiffMemVarAll: 4022; P8LE: # %bb.0: # %entry 4023; P8LE-NEXT: sldi r4, r4, 3 4024; P8LE-NEXT: lxvd2x vs0, r3, r4 4025; P8LE-NEXT: xxswapd v2, vs0 4026; P8LE-NEXT: blr 4027entry: 4028 %idxprom = sext i32 %elem to i64 4029 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4030 %0 = load i64, i64* %arrayidx, align 8 4031 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4032 %add = add nsw i32 %elem, 1 4033 %idxprom1 = sext i32 %add to i64 4034 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 4035 %1 = load i64, i64* %arrayidx2, align 8 4036 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4037 ret <2 x i64> %vecinit3 4038} 4039 4040define <2 x i64> @fromDiffMemVarDll(i64* nocapture readonly %arr, i32 signext %elem) { 4041; P9BE-LABEL: fromDiffMemVarDll: 4042; P9BE: # %bb.0: # %entry 4043; P9BE-NEXT: sldi r4, r4, 3 4044; P9BE-NEXT: add r3, r3, r4 4045; P9BE-NEXT: li r4, -8 4046; P9BE-NEXT: lxvx v2, r3, r4 4047; P9BE-NEXT: xxswapd v2, v2 4048; P9BE-NEXT: blr 4049; 4050; P9LE-LABEL: fromDiffMemVarDll: 4051; P9LE: # %bb.0: # %entry 4052; P9LE-NEXT: sldi r4, r4, 3 4053; P9LE-NEXT: add r3, r3, r4 4054; P9LE-NEXT: addi r3, r3, -8 4055; P9LE-NEXT: lxvd2x v2, 0, r3 4056; P9LE-NEXT: blr 4057; 4058; P8BE-LABEL: fromDiffMemVarDll: 4059; P8BE: # %bb.0: # %entry 4060; P8BE-NEXT: sldi r4, r4, 3 4061; P8BE-NEXT: add r3, r3, r4 4062; P8BE-NEXT: addi r3, r3, -8 4063; P8BE-NEXT: lxvd2x v2, 0, r3 4064; P8BE-NEXT: xxswapd v2, v2 4065; P8BE-NEXT: blr 4066; 4067; P8LE-LABEL: fromDiffMemVarDll: 4068; P8LE: # %bb.0: # %entry 4069; P8LE-NEXT: sldi r4, r4, 3 4070; P8LE-NEXT: add r3, r3, r4 4071; P8LE-NEXT: addi r3, r3, -8 4072; P8LE-NEXT: lxvd2x v2, 0, r3 4073; P8LE-NEXT: blr 4074entry: 4075 %idxprom = sext i32 %elem to i64 4076 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4077 %0 = load i64, i64* %arrayidx, align 8 4078 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4079 %sub = add nsw i32 %elem, -1 4080 %idxprom1 = sext i32 %sub to i64 4081 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 4082 %1 = load i64, i64* %arrayidx2, align 8 4083 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4084 ret <2 x i64> %vecinit3 4085} 4086 4087define <2 x i64> @fromRandMemConsll(i64* nocapture readonly %arr) { 4088; P9BE-LABEL: fromRandMemConsll: 4089; P9BE: # %bb.0: # %entry 4090; P9BE-NEXT: ld r4, 32(r3) 4091; P9BE-NEXT: ld r3, 144(r3) 4092; P9BE-NEXT: mtvsrdd v2, r4, r3 4093; P9BE-NEXT: blr 4094; 4095; P9LE-LABEL: fromRandMemConsll: 4096; P9LE: # %bb.0: # %entry 4097; P9LE-NEXT: ld r4, 32(r3) 4098; P9LE-NEXT: ld r3, 144(r3) 4099; P9LE-NEXT: mtvsrdd v2, r3, r4 4100; P9LE-NEXT: blr 4101; 4102; P8BE-LABEL: fromRandMemConsll: 4103; P8BE: # %bb.0: # %entry 4104; P8BE-NEXT: ld r4, 144(r3) 4105; P8BE-NEXT: ld r3, 32(r3) 4106; P8BE-NEXT: mtfprd f0, r4 4107; P8BE-NEXT: mtfprd f1, r3 4108; P8BE-NEXT: xxmrghd v2, vs1, vs0 4109; P8BE-NEXT: blr 4110; 4111; P8LE-LABEL: fromRandMemConsll: 4112; P8LE: # %bb.0: # %entry 4113; P8LE-NEXT: ld r4, 32(r3) 4114; P8LE-NEXT: ld r3, 144(r3) 4115; P8LE-NEXT: mtfprd f0, r4 4116; P8LE-NEXT: mtfprd f1, r3 4117; P8LE-NEXT: xxmrghd v2, vs1, vs0 4118; P8LE-NEXT: blr 4119entry: 4120 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4 4121 %0 = load i64, i64* %arrayidx, align 8 4122 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4123 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18 4124 %1 = load i64, i64* %arrayidx1, align 8 4125 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4126 ret <2 x i64> %vecinit2 4127} 4128 4129define <2 x i64> @fromRandMemVarll(i64* nocapture readonly %arr, i32 signext %elem) { 4130; P9BE-LABEL: fromRandMemVarll: 4131; P9BE: # %bb.0: # %entry 4132; P9BE-NEXT: sldi r4, r4, 3 4133; P9BE-NEXT: add r3, r3, r4 4134; P9BE-NEXT: ld r4, 32(r3) 4135; P9BE-NEXT: ld r3, 8(r3) 4136; P9BE-NEXT: mtvsrdd v2, r4, r3 4137; P9BE-NEXT: blr 4138; 4139; P9LE-LABEL: fromRandMemVarll: 4140; P9LE: # %bb.0: # %entry 4141; P9LE-NEXT: sldi r4, r4, 3 4142; P9LE-NEXT: add r3, r3, r4 4143; P9LE-NEXT: ld r4, 32(r3) 4144; P9LE-NEXT: ld r3, 8(r3) 4145; P9LE-NEXT: mtvsrdd v2, r3, r4 4146; P9LE-NEXT: blr 4147; 4148; P8BE-LABEL: fromRandMemVarll: 4149; P8BE: # %bb.0: # %entry 4150; P8BE-NEXT: sldi r4, r4, 3 4151; P8BE-NEXT: add r3, r3, r4 4152; P8BE-NEXT: ld r4, 8(r3) 4153; P8BE-NEXT: ld r3, 32(r3) 4154; P8BE-NEXT: mtfprd f0, r4 4155; P8BE-NEXT: mtfprd f1, r3 4156; P8BE-NEXT: xxmrghd v2, vs1, vs0 4157; P8BE-NEXT: blr 4158; 4159; P8LE-LABEL: fromRandMemVarll: 4160; P8LE: # %bb.0: # %entry 4161; P8LE-NEXT: sldi r4, r4, 3 4162; P8LE-NEXT: add r3, r3, r4 4163; P8LE-NEXT: ld r4, 32(r3) 4164; P8LE-NEXT: ld r3, 8(r3) 4165; P8LE-NEXT: mtfprd f0, r4 4166; P8LE-NEXT: mtfprd f1, r3 4167; P8LE-NEXT: xxmrghd v2, vs1, vs0 4168; P8LE-NEXT: blr 4169entry: 4170 %add = add nsw i32 %elem, 4 4171 %idxprom = sext i32 %add to i64 4172 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4173 %0 = load i64, i64* %arrayidx, align 8 4174 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4175 %add1 = add nsw i32 %elem, 1 4176 %idxprom2 = sext i32 %add1 to i64 4177 %arrayidx3 = getelementptr inbounds i64, i64* %arr, i64 %idxprom2 4178 %1 = load i64, i64* %arrayidx3, align 8 4179 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4180 ret <2 x i64> %vecinit4 4181} 4182 4183define <2 x i64> @spltRegValll(i64 %val) { 4184; P9BE-LABEL: spltRegValll: 4185; P9BE: # %bb.0: # %entry 4186; P9BE-NEXT: mtvsrdd v2, r3, r3 4187; P9BE-NEXT: blr 4188; 4189; P9LE-LABEL: spltRegValll: 4190; P9LE: # %bb.0: # %entry 4191; P9LE-NEXT: mtvsrdd v2, r3, r3 4192; P9LE-NEXT: blr 4193; 4194; P8BE-LABEL: spltRegValll: 4195; P8BE: # %bb.0: # %entry 4196; P8BE-NEXT: mtfprd f0, r3 4197; P8BE-NEXT: xxspltd v2, vs0, 0 4198; P8BE-NEXT: blr 4199; 4200; P8LE-LABEL: spltRegValll: 4201; P8LE: # %bb.0: # %entry 4202; P8LE-NEXT: mtfprd f0, r3 4203; P8LE-NEXT: xxspltd v2, vs0, 0 4204; P8LE-NEXT: blr 4205entry: 4206 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0 4207 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4208 ret <2 x i64> %splat.splat 4209} 4210 4211define <2 x i64> @spltMemValll(i64* nocapture readonly %ptr) { 4212; P9BE-LABEL: spltMemValll: 4213; P9BE: # %bb.0: # %entry 4214; P9BE-NEXT: lxvdsx v2, 0, r3 4215; P9BE-NEXT: blr 4216; 4217; P9LE-LABEL: spltMemValll: 4218; P9LE: # %bb.0: # %entry 4219; P9LE-NEXT: lxvdsx v2, 0, r3 4220; P9LE-NEXT: blr 4221; 4222; P8BE-LABEL: spltMemValll: 4223; P8BE: # %bb.0: # %entry 4224; P8BE-NEXT: lxvdsx v2, 0, r3 4225; P8BE-NEXT: blr 4226; 4227; P8LE-LABEL: spltMemValll: 4228; P8LE: # %bb.0: # %entry 4229; P8LE-NEXT: lxvdsx v2, 0, r3 4230; P8LE-NEXT: blr 4231entry: 4232 %0 = load i64, i64* %ptr, align 8 4233 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 4234 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4235 ret <2 x i64> %splat.splat 4236} 4237 4238define <2 x i64> @spltCnstConvftoll() { 4239; P9BE-LABEL: spltCnstConvftoll: 4240; P9BE: # %bb.0: # %entry 4241; P9BE-NEXT: addis r3, r2, .LCPI78_0@toc@ha 4242; P9BE-NEXT: addi r3, r3, .LCPI78_0@toc@l 4243; P9BE-NEXT: lxv v2, 0(r3) 4244; P9BE-NEXT: blr 4245; 4246; P9LE-LABEL: spltCnstConvftoll: 4247; P9LE: # %bb.0: # %entry 4248; P9LE-NEXT: addis r3, r2, .LCPI78_0@toc@ha 4249; P9LE-NEXT: addi r3, r3, .LCPI78_0@toc@l 4250; P9LE-NEXT: lxv v2, 0(r3) 4251; P9LE-NEXT: blr 4252; 4253; P8BE-LABEL: spltCnstConvftoll: 4254; P8BE: # %bb.0: # %entry 4255; P8BE-NEXT: addis r3, r2, .LCPI78_0@toc@ha 4256; P8BE-NEXT: addi r3, r3, .LCPI78_0@toc@l 4257; P8BE-NEXT: lxvd2x v2, 0, r3 4258; P8BE-NEXT: blr 4259; 4260; P8LE-LABEL: spltCnstConvftoll: 4261; P8LE: # %bb.0: # %entry 4262; P8LE-NEXT: addis r3, r2, .LCPI78_0@toc@ha 4263; P8LE-NEXT: addi r3, r3, .LCPI78_0@toc@l 4264; P8LE-NEXT: lxvd2x vs0, 0, r3 4265; P8LE-NEXT: xxswapd v2, vs0 4266; P8LE-NEXT: blr 4267entry: 4268 ret <2 x i64> <i64 4, i64 4> 4269} 4270 4271define <2 x i64> @fromRegsConvftoll(float %a, float %b) { 4272; P9BE-LABEL: fromRegsConvftoll: 4273; P9BE: # %bb.0: # %entry 4274; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4275; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4276; P9BE-NEXT: xxmrghd vs0, vs1, vs2 4277; P9BE-NEXT: xvcvdpsxds v2, vs0 4278; P9BE-NEXT: blr 4279; 4280; P9LE-LABEL: fromRegsConvftoll: 4281; P9LE: # %bb.0: # %entry 4282; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4283; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4284; P9LE-NEXT: xxmrghd vs0, vs2, vs1 4285; P9LE-NEXT: xvcvdpsxds v2, vs0 4286; P9LE-NEXT: blr 4287; 4288; P8BE-LABEL: fromRegsConvftoll: 4289; P8BE: # %bb.0: # %entry 4290; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4291; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4292; P8BE-NEXT: xxmrghd vs0, vs1, vs2 4293; P8BE-NEXT: xvcvdpsxds v2, vs0 4294; P8BE-NEXT: blr 4295; 4296; P8LE-LABEL: fromRegsConvftoll: 4297; P8LE: # %bb.0: # %entry 4298; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4299; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4300; P8LE-NEXT: xxmrghd vs0, vs2, vs1 4301; P8LE-NEXT: xvcvdpsxds v2, vs0 4302; P8LE-NEXT: blr 4303entry: 4304 %conv = fptosi float %a to i64 4305 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4306 %conv1 = fptosi float %b to i64 4307 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 4308 ret <2 x i64> %vecinit2 4309} 4310 4311define <2 x i64> @fromDiffConstsConvftoll() { 4312; P9BE-LABEL: fromDiffConstsConvftoll: 4313; P9BE: # %bb.0: # %entry 4314; P9BE-NEXT: addis r3, r2, .LCPI80_0@toc@ha 4315; P9BE-NEXT: addi r3, r3, .LCPI80_0@toc@l 4316; P9BE-NEXT: lxv v2, 0(r3) 4317; P9BE-NEXT: blr 4318; 4319; P9LE-LABEL: fromDiffConstsConvftoll: 4320; P9LE: # %bb.0: # %entry 4321; P9LE-NEXT: addis r3, r2, .LCPI80_0@toc@ha 4322; P9LE-NEXT: addi r3, r3, .LCPI80_0@toc@l 4323; P9LE-NEXT: lxv v2, 0(r3) 4324; P9LE-NEXT: blr 4325; 4326; P8BE-LABEL: fromDiffConstsConvftoll: 4327; P8BE: # %bb.0: # %entry 4328; P8BE-NEXT: addis r3, r2, .LCPI80_0@toc@ha 4329; P8BE-NEXT: addi r3, r3, .LCPI80_0@toc@l 4330; P8BE-NEXT: lxvd2x v2, 0, r3 4331; P8BE-NEXT: blr 4332; 4333; P8LE-LABEL: fromDiffConstsConvftoll: 4334; P8LE: # %bb.0: # %entry 4335; P8LE-NEXT: addis r3, r2, .LCPI80_0@toc@ha 4336; P8LE-NEXT: addi r3, r3, .LCPI80_0@toc@l 4337; P8LE-NEXT: lxvd2x vs0, 0, r3 4338; P8LE-NEXT: xxswapd v2, vs0 4339; P8LE-NEXT: blr 4340entry: 4341 ret <2 x i64> <i64 24, i64 234> 4342} 4343 4344define <2 x i64> @fromDiffMemConsAConvftoll(float* nocapture readonly %ptr) { 4345; P9BE-LABEL: fromDiffMemConsAConvftoll: 4346; P9BE: # %bb.0: # %entry 4347; P9BE-NEXT: lfs f0, 0(r3) 4348; P9BE-NEXT: lfs f1, 4(r3) 4349; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4350; P9BE-NEXT: xvcvdpsxds v2, vs0 4351; P9BE-NEXT: blr 4352; 4353; P9LE-LABEL: fromDiffMemConsAConvftoll: 4354; P9LE: # %bb.0: # %entry 4355; P9LE-NEXT: lfs f0, 0(r3) 4356; P9LE-NEXT: lfs f1, 4(r3) 4357; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4358; P9LE-NEXT: xvcvdpsxds v2, vs0 4359; P9LE-NEXT: blr 4360; 4361; P8BE-LABEL: fromDiffMemConsAConvftoll: 4362; P8BE: # %bb.0: # %entry 4363; P8BE-NEXT: lfs f0, 0(r3) 4364; P8BE-NEXT: lfs f1, 4(r3) 4365; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4366; P8BE-NEXT: xvcvdpsxds v2, vs0 4367; P8BE-NEXT: blr 4368; 4369; P8LE-LABEL: fromDiffMemConsAConvftoll: 4370; P8LE: # %bb.0: # %entry 4371; P8LE-NEXT: lfs f0, 0(r3) 4372; P8LE-NEXT: lfs f1, 4(r3) 4373; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4374; P8LE-NEXT: xvcvdpsxds v2, vs0 4375; P8LE-NEXT: blr 4376entry: 4377 %0 = load float, float* %ptr, align 4 4378 %conv = fptosi float %0 to i64 4379 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4380 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1 4381 %1 = load float, float* %arrayidx1, align 4 4382 %conv2 = fptosi float %1 to i64 4383 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4384 ret <2 x i64> %vecinit3 4385} 4386 4387define <2 x i64> @fromDiffMemConsDConvftoll(float* nocapture readonly %ptr) { 4388; P9BE-LABEL: fromDiffMemConsDConvftoll: 4389; P9BE: # %bb.0: # %entry 4390; P9BE-NEXT: lfs f0, 12(r3) 4391; P9BE-NEXT: lfs f1, 8(r3) 4392; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4393; P9BE-NEXT: xvcvdpsxds v2, vs0 4394; P9BE-NEXT: blr 4395; 4396; P9LE-LABEL: fromDiffMemConsDConvftoll: 4397; P9LE: # %bb.0: # %entry 4398; P9LE-NEXT: lfs f0, 12(r3) 4399; P9LE-NEXT: lfs f1, 8(r3) 4400; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4401; P9LE-NEXT: xvcvdpsxds v2, vs0 4402; P9LE-NEXT: blr 4403; 4404; P8BE-LABEL: fromDiffMemConsDConvftoll: 4405; P8BE: # %bb.0: # %entry 4406; P8BE-NEXT: lfs f0, 12(r3) 4407; P8BE-NEXT: lfs f1, 8(r3) 4408; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4409; P8BE-NEXT: xvcvdpsxds v2, vs0 4410; P8BE-NEXT: blr 4411; 4412; P8LE-LABEL: fromDiffMemConsDConvftoll: 4413; P8LE: # %bb.0: # %entry 4414; P8LE-NEXT: lfs f0, 12(r3) 4415; P8LE-NEXT: lfs f1, 8(r3) 4416; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4417; P8LE-NEXT: xvcvdpsxds v2, vs0 4418; P8LE-NEXT: blr 4419entry: 4420 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 4421 %0 = load float, float* %arrayidx, align 4 4422 %conv = fptosi float %0 to i64 4423 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4424 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 4425 %1 = load float, float* %arrayidx1, align 4 4426 %conv2 = fptosi float %1 to i64 4427 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4428 ret <2 x i64> %vecinit3 4429} 4430 4431define <2 x i64> @fromDiffMemVarAConvftoll(float* nocapture readonly %arr, i32 signext %elem) { 4432; P9BE-LABEL: fromDiffMemVarAConvftoll: 4433; P9BE: # %bb.0: # %entry 4434; P9BE-NEXT: sldi r4, r4, 2 4435; P9BE-NEXT: lfsux f0, r3, r4 4436; P9BE-NEXT: lfs f1, 4(r3) 4437; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4438; P9BE-NEXT: xvcvdpsxds v2, vs0 4439; P9BE-NEXT: blr 4440; 4441; P9LE-LABEL: fromDiffMemVarAConvftoll: 4442; P9LE: # %bb.0: # %entry 4443; P9LE-NEXT: sldi r4, r4, 2 4444; P9LE-NEXT: lfsux f0, r3, r4 4445; P9LE-NEXT: lfs f1, 4(r3) 4446; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4447; P9LE-NEXT: xvcvdpsxds v2, vs0 4448; P9LE-NEXT: blr 4449; 4450; P8BE-LABEL: fromDiffMemVarAConvftoll: 4451; P8BE: # %bb.0: # %entry 4452; P8BE-NEXT: sldi r4, r4, 2 4453; P8BE-NEXT: lfsux f0, r3, r4 4454; P8BE-NEXT: lfs f1, 4(r3) 4455; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4456; P8BE-NEXT: xvcvdpsxds v2, vs0 4457; P8BE-NEXT: blr 4458; 4459; P8LE-LABEL: fromDiffMemVarAConvftoll: 4460; P8LE: # %bb.0: # %entry 4461; P8LE-NEXT: sldi r4, r4, 2 4462; P8LE-NEXT: lfsux f0, r3, r4 4463; P8LE-NEXT: lfs f1, 4(r3) 4464; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4465; P8LE-NEXT: xvcvdpsxds v2, vs0 4466; P8LE-NEXT: blr 4467entry: 4468 %idxprom = sext i32 %elem to i64 4469 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 4470 %0 = load float, float* %arrayidx, align 4 4471 %conv = fptosi float %0 to i64 4472 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4473 %add = add nsw i32 %elem, 1 4474 %idxprom1 = sext i32 %add to i64 4475 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 4476 %1 = load float, float* %arrayidx2, align 4 4477 %conv3 = fptosi float %1 to i64 4478 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4479 ret <2 x i64> %vecinit4 4480} 4481 4482define <2 x i64> @fromDiffMemVarDConvftoll(float* nocapture readonly %arr, i32 signext %elem) { 4483; P9BE-LABEL: fromDiffMemVarDConvftoll: 4484; P9BE: # %bb.0: # %entry 4485; P9BE-NEXT: sldi r4, r4, 2 4486; P9BE-NEXT: lfsux f0, r3, r4 4487; P9BE-NEXT: lfs f1, -4(r3) 4488; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4489; P9BE-NEXT: xvcvdpsxds v2, vs0 4490; P9BE-NEXT: blr 4491; 4492; P9LE-LABEL: fromDiffMemVarDConvftoll: 4493; P9LE: # %bb.0: # %entry 4494; P9LE-NEXT: sldi r4, r4, 2 4495; P9LE-NEXT: lfsux f0, r3, r4 4496; P9LE-NEXT: lfs f1, -4(r3) 4497; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4498; P9LE-NEXT: xvcvdpsxds v2, vs0 4499; P9LE-NEXT: blr 4500; 4501; P8BE-LABEL: fromDiffMemVarDConvftoll: 4502; P8BE: # %bb.0: # %entry 4503; P8BE-NEXT: sldi r4, r4, 2 4504; P8BE-NEXT: lfsux f0, r3, r4 4505; P8BE-NEXT: lfs f1, -4(r3) 4506; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4507; P8BE-NEXT: xvcvdpsxds v2, vs0 4508; P8BE-NEXT: blr 4509; 4510; P8LE-LABEL: fromDiffMemVarDConvftoll: 4511; P8LE: # %bb.0: # %entry 4512; P8LE-NEXT: sldi r4, r4, 2 4513; P8LE-NEXT: lfsux f0, r3, r4 4514; P8LE-NEXT: lfs f1, -4(r3) 4515; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4516; P8LE-NEXT: xvcvdpsxds v2, vs0 4517; P8LE-NEXT: blr 4518entry: 4519 %idxprom = sext i32 %elem to i64 4520 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 4521 %0 = load float, float* %arrayidx, align 4 4522 %conv = fptosi float %0 to i64 4523 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4524 %sub = add nsw i32 %elem, -1 4525 %idxprom1 = sext i32 %sub to i64 4526 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 4527 %1 = load float, float* %arrayidx2, align 4 4528 %conv3 = fptosi float %1 to i64 4529 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4530 ret <2 x i64> %vecinit4 4531} 4532 4533define <2 x i64> @spltRegValConvftoll(float %val) { 4534; P9BE-LABEL: spltRegValConvftoll: 4535; P9BE: # %bb.0: # %entry 4536; P9BE-NEXT: xscvdpsxds f0, f1 4537; P9BE-NEXT: xxspltd v2, f0, 0 4538; P9BE-NEXT: blr 4539; 4540; P9LE-LABEL: spltRegValConvftoll: 4541; P9LE: # %bb.0: # %entry 4542; P9LE-NEXT: xscvdpsxds f0, f1 4543; P9LE-NEXT: xxspltd v2, f0, 0 4544; P9LE-NEXT: blr 4545; 4546; P8BE-LABEL: spltRegValConvftoll: 4547; P8BE: # %bb.0: # %entry 4548; P8BE-NEXT: xscvdpsxds f0, f1 4549; P8BE-NEXT: xxspltd v2, f0, 0 4550; P8BE-NEXT: blr 4551; 4552; P8LE-LABEL: spltRegValConvftoll: 4553; P8LE: # %bb.0: # %entry 4554; P8LE-NEXT: xscvdpsxds f0, f1 4555; P8LE-NEXT: xxspltd v2, f0, 0 4556; P8LE-NEXT: blr 4557entry: 4558 %conv = fptosi float %val to i64 4559 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4560 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4561 ret <2 x i64> %splat.splat 4562} 4563 4564define <2 x i64> @spltMemValConvftoll(float* nocapture readonly %ptr) { 4565; P9BE-LABEL: spltMemValConvftoll: 4566; P9BE: # %bb.0: # %entry 4567; P9BE-NEXT: lfs f0, 0(r3) 4568; P9BE-NEXT: xscvdpsxds f0, f0 4569; P9BE-NEXT: xxspltd v2, f0, 0 4570; P9BE-NEXT: blr 4571; 4572; P9LE-LABEL: spltMemValConvftoll: 4573; P9LE: # %bb.0: # %entry 4574; P9LE-NEXT: lfs f0, 0(r3) 4575; P9LE-NEXT: xscvdpsxds f0, f0 4576; P9LE-NEXT: xxspltd v2, vs0, 0 4577; P9LE-NEXT: blr 4578; 4579; P8BE-LABEL: spltMemValConvftoll: 4580; P8BE: # %bb.0: # %entry 4581; P8BE-NEXT: lfsx f0, 0, r3 4582; P8BE-NEXT: xscvdpsxds f0, f0 4583; P8BE-NEXT: xxspltd v2, f0, 0 4584; P8BE-NEXT: blr 4585; 4586; P8LE-LABEL: spltMemValConvftoll: 4587; P8LE: # %bb.0: # %entry 4588; P8LE-NEXT: lfsx f0, 0, r3 4589; P8LE-NEXT: xscvdpsxds f0, f0 4590; P8LE-NEXT: xxspltd v2, vs0, 0 4591; P8LE-NEXT: blr 4592entry: 4593 %0 = load float, float* %ptr, align 4 4594 %conv = fptosi float %0 to i64 4595 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4596 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4597 ret <2 x i64> %splat.splat 4598} 4599 4600define <2 x i64> @spltCnstConvdtoll() { 4601; P9BE-LABEL: spltCnstConvdtoll: 4602; P9BE: # %bb.0: # %entry 4603; P9BE-NEXT: addis r3, r2, .LCPI87_0@toc@ha 4604; P9BE-NEXT: addi r3, r3, .LCPI87_0@toc@l 4605; P9BE-NEXT: lxv v2, 0(r3) 4606; P9BE-NEXT: blr 4607; 4608; P9LE-LABEL: spltCnstConvdtoll: 4609; P9LE: # %bb.0: # %entry 4610; P9LE-NEXT: addis r3, r2, .LCPI87_0@toc@ha 4611; P9LE-NEXT: addi r3, r3, .LCPI87_0@toc@l 4612; P9LE-NEXT: lxv v2, 0(r3) 4613; P9LE-NEXT: blr 4614; 4615; P8BE-LABEL: spltCnstConvdtoll: 4616; P8BE: # %bb.0: # %entry 4617; P8BE-NEXT: addis r3, r2, .LCPI87_0@toc@ha 4618; P8BE-NEXT: addi r3, r3, .LCPI87_0@toc@l 4619; P8BE-NEXT: lxvd2x v2, 0, r3 4620; P8BE-NEXT: blr 4621; 4622; P8LE-LABEL: spltCnstConvdtoll: 4623; P8LE: # %bb.0: # %entry 4624; P8LE-NEXT: addis r3, r2, .LCPI87_0@toc@ha 4625; P8LE-NEXT: addi r3, r3, .LCPI87_0@toc@l 4626; P8LE-NEXT: lxvd2x vs0, 0, r3 4627; P8LE-NEXT: xxswapd v2, vs0 4628; P8LE-NEXT: blr 4629entry: 4630 ret <2 x i64> <i64 4, i64 4> 4631} 4632 4633define <2 x i64> @fromRegsConvdtoll(double %a, double %b) { 4634; P9BE-LABEL: fromRegsConvdtoll: 4635; P9BE: # %bb.0: # %entry 4636; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4637; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4638; P9BE-NEXT: xxmrghd vs0, vs1, vs2 4639; P9BE-NEXT: xvcvdpsxds v2, vs0 4640; P9BE-NEXT: blr 4641; 4642; P9LE-LABEL: fromRegsConvdtoll: 4643; P9LE: # %bb.0: # %entry 4644; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4645; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4646; P9LE-NEXT: xxmrghd vs0, vs2, vs1 4647; P9LE-NEXT: xvcvdpsxds v2, vs0 4648; P9LE-NEXT: blr 4649; 4650; P8BE-LABEL: fromRegsConvdtoll: 4651; P8BE: # %bb.0: # %entry 4652; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4653; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4654; P8BE-NEXT: xxmrghd vs0, vs1, vs2 4655; P8BE-NEXT: xvcvdpsxds v2, vs0 4656; P8BE-NEXT: blr 4657; 4658; P8LE-LABEL: fromRegsConvdtoll: 4659; P8LE: # %bb.0: # %entry 4660; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4661; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4662; P8LE-NEXT: xxmrghd vs0, vs2, vs1 4663; P8LE-NEXT: xvcvdpsxds v2, vs0 4664; P8LE-NEXT: blr 4665entry: 4666 %conv = fptosi double %a to i64 4667 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4668 %conv1 = fptosi double %b to i64 4669 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 4670 ret <2 x i64> %vecinit2 4671} 4672 4673define <2 x i64> @fromDiffConstsConvdtoll() { 4674; P9BE-LABEL: fromDiffConstsConvdtoll: 4675; P9BE: # %bb.0: # %entry 4676; P9BE-NEXT: addis r3, r2, .LCPI89_0@toc@ha 4677; P9BE-NEXT: addi r3, r3, .LCPI89_0@toc@l 4678; P9BE-NEXT: lxv v2, 0(r3) 4679; P9BE-NEXT: blr 4680; 4681; P9LE-LABEL: fromDiffConstsConvdtoll: 4682; P9LE: # %bb.0: # %entry 4683; P9LE-NEXT: addis r3, r2, .LCPI89_0@toc@ha 4684; P9LE-NEXT: addi r3, r3, .LCPI89_0@toc@l 4685; P9LE-NEXT: lxv v2, 0(r3) 4686; P9LE-NEXT: blr 4687; 4688; P8BE-LABEL: fromDiffConstsConvdtoll: 4689; P8BE: # %bb.0: # %entry 4690; P8BE-NEXT: addis r3, r2, .LCPI89_0@toc@ha 4691; P8BE-NEXT: addi r3, r3, .LCPI89_0@toc@l 4692; P8BE-NEXT: lxvd2x v2, 0, r3 4693; P8BE-NEXT: blr 4694; 4695; P8LE-LABEL: fromDiffConstsConvdtoll: 4696; P8LE: # %bb.0: # %entry 4697; P8LE-NEXT: addis r3, r2, .LCPI89_0@toc@ha 4698; P8LE-NEXT: addi r3, r3, .LCPI89_0@toc@l 4699; P8LE-NEXT: lxvd2x vs0, 0, r3 4700; P8LE-NEXT: xxswapd v2, vs0 4701; P8LE-NEXT: blr 4702entry: 4703 ret <2 x i64> <i64 24, i64 234> 4704} 4705 4706define <2 x i64> @fromDiffMemConsAConvdtoll(double* nocapture readonly %ptr) { 4707; P9BE-LABEL: fromDiffMemConsAConvdtoll: 4708; P9BE: # %bb.0: # %entry 4709; P9BE-NEXT: lxv vs0, 0(r3) 4710; P9BE-NEXT: xvcvdpsxds v2, vs0 4711; P9BE-NEXT: blr 4712; 4713; P9LE-LABEL: fromDiffMemConsAConvdtoll: 4714; P9LE: # %bb.0: # %entry 4715; P9LE-NEXT: lxv vs0, 0(r3) 4716; P9LE-NEXT: xvcvdpsxds v2, vs0 4717; P9LE-NEXT: blr 4718; 4719; P8BE-LABEL: fromDiffMemConsAConvdtoll: 4720; P8BE: # %bb.0: # %entry 4721; P8BE-NEXT: lxvd2x vs0, 0, r3 4722; P8BE-NEXT: xvcvdpsxds v2, vs0 4723; P8BE-NEXT: blr 4724; 4725; P8LE-LABEL: fromDiffMemConsAConvdtoll: 4726; P8LE: # %bb.0: # %entry 4727; P8LE-NEXT: lxvd2x vs0, 0, r3 4728; P8LE-NEXT: xxswapd vs0, vs0 4729; P8LE-NEXT: xvcvdpsxds v2, vs0 4730; P8LE-NEXT: blr 4731entry: 4732 %0 = bitcast double* %ptr to <2 x double>* 4733 %1 = load <2 x double>, <2 x double>* %0, align 8 4734 %2 = fptosi <2 x double> %1 to <2 x i64> 4735 ret <2 x i64> %2 4736} 4737 4738define <2 x i64> @fromDiffMemConsDConvdtoll(double* nocapture readonly %ptr) { 4739; P9BE-LABEL: fromDiffMemConsDConvdtoll: 4740; P9BE: # %bb.0: # %entry 4741; P9BE-NEXT: lxv vs0, 16(r3) 4742; P9BE-NEXT: xxswapd vs0, vs0 4743; P9BE-NEXT: xvcvdpsxds v2, vs0 4744; P9BE-NEXT: blr 4745; 4746; P9LE-LABEL: fromDiffMemConsDConvdtoll: 4747; P9LE: # %bb.0: # %entry 4748; P9LE-NEXT: addi r3, r3, 16 4749; P9LE-NEXT: lxvd2x vs0, 0, r3 4750; P9LE-NEXT: xvcvdpsxds v2, vs0 4751; P9LE-NEXT: blr 4752; 4753; P8BE-LABEL: fromDiffMemConsDConvdtoll: 4754; P8BE: # %bb.0: # %entry 4755; P8BE-NEXT: addi r3, r3, 16 4756; P8BE-NEXT: lxvd2x vs0, 0, r3 4757; P8BE-NEXT: xxswapd vs0, vs0 4758; P8BE-NEXT: xvcvdpsxds v2, vs0 4759; P8BE-NEXT: blr 4760; 4761; P8LE-LABEL: fromDiffMemConsDConvdtoll: 4762; P8LE: # %bb.0: # %entry 4763; P8LE-NEXT: addi r3, r3, 16 4764; P8LE-NEXT: lxvd2x vs0, 0, r3 4765; P8LE-NEXT: xvcvdpsxds v2, vs0 4766; P8LE-NEXT: blr 4767entry: 4768 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 4769 %0 = load double, double* %arrayidx, align 8 4770 %conv = fptosi double %0 to i64 4771 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4772 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 4773 %1 = load double, double* %arrayidx1, align 8 4774 %conv2 = fptosi double %1 to i64 4775 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4776 ret <2 x i64> %vecinit3 4777} 4778 4779define <2 x i64> @fromDiffMemVarAConvdtoll(double* nocapture readonly %arr, i32 signext %elem) { 4780; P9BE-LABEL: fromDiffMemVarAConvdtoll: 4781; P9BE: # %bb.0: # %entry 4782; P9BE-NEXT: sldi r4, r4, 3 4783; P9BE-NEXT: lxvx vs0, r3, r4 4784; P9BE-NEXT: xvcvdpsxds v2, vs0 4785; P9BE-NEXT: blr 4786; 4787; P9LE-LABEL: fromDiffMemVarAConvdtoll: 4788; P9LE: # %bb.0: # %entry 4789; P9LE-NEXT: sldi r4, r4, 3 4790; P9LE-NEXT: lxvx vs0, r3, r4 4791; P9LE-NEXT: xvcvdpsxds v2, vs0 4792; P9LE-NEXT: blr 4793; 4794; P8BE-LABEL: fromDiffMemVarAConvdtoll: 4795; P8BE: # %bb.0: # %entry 4796; P8BE-NEXT: sldi r4, r4, 3 4797; P8BE-NEXT: lxvd2x vs0, r3, r4 4798; P8BE-NEXT: xvcvdpsxds v2, vs0 4799; P8BE-NEXT: blr 4800; 4801; P8LE-LABEL: fromDiffMemVarAConvdtoll: 4802; P8LE: # %bb.0: # %entry 4803; P8LE-NEXT: sldi r4, r4, 3 4804; P8LE-NEXT: lxvd2x vs0, r3, r4 4805; P8LE-NEXT: xxswapd vs0, vs0 4806; P8LE-NEXT: xvcvdpsxds v2, vs0 4807; P8LE-NEXT: blr 4808entry: 4809 %idxprom = sext i32 %elem to i64 4810 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 4811 %0 = load double, double* %arrayidx, align 8 4812 %conv = fptosi double %0 to i64 4813 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4814 %add = add nsw i32 %elem, 1 4815 %idxprom1 = sext i32 %add to i64 4816 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 4817 %1 = load double, double* %arrayidx2, align 8 4818 %conv3 = fptosi double %1 to i64 4819 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4820 ret <2 x i64> %vecinit4 4821} 4822 4823define <2 x i64> @fromDiffMemVarDConvdtoll(double* nocapture readonly %arr, i32 signext %elem) { 4824; P9BE-LABEL: fromDiffMemVarDConvdtoll: 4825; P9BE: # %bb.0: # %entry 4826; P9BE-NEXT: sldi r4, r4, 3 4827; P9BE-NEXT: add r3, r3, r4 4828; P9BE-NEXT: li r4, -8 4829; P9BE-NEXT: lxvx vs0, r3, r4 4830; P9BE-NEXT: xxswapd vs0, vs0 4831; P9BE-NEXT: xvcvdpsxds v2, vs0 4832; P9BE-NEXT: blr 4833; 4834; P9LE-LABEL: fromDiffMemVarDConvdtoll: 4835; P9LE: # %bb.0: # %entry 4836; P9LE-NEXT: sldi r4, r4, 3 4837; P9LE-NEXT: add r3, r3, r4 4838; P9LE-NEXT: addi r3, r3, -8 4839; P9LE-NEXT: lxvd2x vs0, 0, r3 4840; P9LE-NEXT: xvcvdpsxds v2, vs0 4841; P9LE-NEXT: blr 4842; 4843; P8BE-LABEL: fromDiffMemVarDConvdtoll: 4844; P8BE: # %bb.0: # %entry 4845; P8BE-NEXT: sldi r4, r4, 3 4846; P8BE-NEXT: add r3, r3, r4 4847; P8BE-NEXT: addi r3, r3, -8 4848; P8BE-NEXT: lxvd2x vs0, 0, r3 4849; P8BE-NEXT: xxswapd vs0, vs0 4850; P8BE-NEXT: xvcvdpsxds v2, vs0 4851; P8BE-NEXT: blr 4852; 4853; P8LE-LABEL: fromDiffMemVarDConvdtoll: 4854; P8LE: # %bb.0: # %entry 4855; P8LE-NEXT: sldi r4, r4, 3 4856; P8LE-NEXT: add r3, r3, r4 4857; P8LE-NEXT: addi r3, r3, -8 4858; P8LE-NEXT: lxvd2x vs0, 0, r3 4859; P8LE-NEXT: xvcvdpsxds v2, vs0 4860; P8LE-NEXT: blr 4861entry: 4862 %idxprom = sext i32 %elem to i64 4863 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 4864 %0 = load double, double* %arrayidx, align 8 4865 %conv = fptosi double %0 to i64 4866 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4867 %sub = add nsw i32 %elem, -1 4868 %idxprom1 = sext i32 %sub to i64 4869 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 4870 %1 = load double, double* %arrayidx2, align 8 4871 %conv3 = fptosi double %1 to i64 4872 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4873 ret <2 x i64> %vecinit4 4874} 4875 4876define <2 x i64> @spltRegValConvdtoll(double %val) { 4877; P9BE-LABEL: spltRegValConvdtoll: 4878; P9BE: # %bb.0: # %entry 4879; P9BE-NEXT: xscvdpsxds f0, f1 4880; P9BE-NEXT: xxspltd v2, vs0, 0 4881; P9BE-NEXT: blr 4882; 4883; P9LE-LABEL: spltRegValConvdtoll: 4884; P9LE: # %bb.0: # %entry 4885; P9LE-NEXT: xscvdpsxds f0, f1 4886; P9LE-NEXT: xxspltd v2, vs0, 0 4887; P9LE-NEXT: blr 4888; 4889; P8BE-LABEL: spltRegValConvdtoll: 4890; P8BE: # %bb.0: # %entry 4891; P8BE-NEXT: xscvdpsxds f0, f1 4892; P8BE-NEXT: xxspltd v2, vs0, 0 4893; P8BE-NEXT: blr 4894; 4895; P8LE-LABEL: spltRegValConvdtoll: 4896; P8LE: # %bb.0: # %entry 4897; P8LE-NEXT: xscvdpsxds f0, f1 4898; P8LE-NEXT: xxspltd v2, vs0, 0 4899; P8LE-NEXT: blr 4900entry: 4901 %conv = fptosi double %val to i64 4902 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4903 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4904 ret <2 x i64> %splat.splat 4905} 4906 4907define <2 x i64> @spltMemValConvdtoll(double* nocapture readonly %ptr) { 4908; P9BE-LABEL: spltMemValConvdtoll: 4909; P9BE: # %bb.0: # %entry 4910; P9BE-NEXT: lxvdsx vs0, 0, r3 4911; P9BE-NEXT: xvcvdpsxds v2, vs0 4912; P9BE-NEXT: blr 4913; 4914; P9LE-LABEL: spltMemValConvdtoll: 4915; P9LE: # %bb.0: # %entry 4916; P9LE-NEXT: lxvdsx vs0, 0, r3 4917; P9LE-NEXT: xvcvdpsxds v2, vs0 4918; P9LE-NEXT: blr 4919; 4920; P8BE-LABEL: spltMemValConvdtoll: 4921; P8BE: # %bb.0: # %entry 4922; P8BE-NEXT: lxvdsx vs0, 0, r3 4923; P8BE-NEXT: xvcvdpsxds v2, vs0 4924; P8BE-NEXT: blr 4925; 4926; P8LE-LABEL: spltMemValConvdtoll: 4927; P8LE: # %bb.0: # %entry 4928; P8LE-NEXT: lxvdsx vs0, 0, r3 4929; P8LE-NEXT: xvcvdpsxds v2, vs0 4930; P8LE-NEXT: blr 4931entry: 4932 %0 = load double, double* %ptr, align 8 4933 %conv = fptosi double %0 to i64 4934 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4935 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4936 ret <2 x i64> %splat.splat 4937} 4938 4939define <2 x i64> @allZeroull() { 4940; P9BE-LABEL: allZeroull: 4941; P9BE: # %bb.0: # %entry 4942; P9BE-NEXT: xxlxor v2, v2, v2 4943; P9BE-NEXT: blr 4944; 4945; P9LE-LABEL: allZeroull: 4946; P9LE: # %bb.0: # %entry 4947; P9LE-NEXT: xxlxor v2, v2, v2 4948; P9LE-NEXT: blr 4949; 4950; P8BE-LABEL: allZeroull: 4951; P8BE: # %bb.0: # %entry 4952; P8BE-NEXT: xxlxor v2, v2, v2 4953; P8BE-NEXT: blr 4954; 4955; P8LE-LABEL: allZeroull: 4956; P8LE: # %bb.0: # %entry 4957; P8LE-NEXT: xxlxor v2, v2, v2 4958; P8LE-NEXT: blr 4959entry: 4960 ret <2 x i64> zeroinitializer 4961} 4962 4963define <2 x i64> @spltConst1ull() { 4964; P9BE-LABEL: spltConst1ull: 4965; P9BE: # %bb.0: # %entry 4966; P9BE-NEXT: addis r3, r2, .LCPI97_0@toc@ha 4967; P9BE-NEXT: addi r3, r3, .LCPI97_0@toc@l 4968; P9BE-NEXT: lxv v2, 0(r3) 4969; P9BE-NEXT: blr 4970; 4971; P9LE-LABEL: spltConst1ull: 4972; P9LE: # %bb.0: # %entry 4973; P9LE-NEXT: addis r3, r2, .LCPI97_0@toc@ha 4974; P9LE-NEXT: addi r3, r3, .LCPI97_0@toc@l 4975; P9LE-NEXT: lxv v2, 0(r3) 4976; P9LE-NEXT: blr 4977; 4978; P8BE-LABEL: spltConst1ull: 4979; P8BE: # %bb.0: # %entry 4980; P8BE-NEXT: addis r3, r2, .LCPI97_0@toc@ha 4981; P8BE-NEXT: addi r3, r3, .LCPI97_0@toc@l 4982; P8BE-NEXT: lxvd2x v2, 0, r3 4983; P8BE-NEXT: blr 4984; 4985; P8LE-LABEL: spltConst1ull: 4986; P8LE: # %bb.0: # %entry 4987; P8LE-NEXT: addis r3, r2, .LCPI97_0@toc@ha 4988; P8LE-NEXT: addi r3, r3, .LCPI97_0@toc@l 4989; P8LE-NEXT: lxvd2x vs0, 0, r3 4990; P8LE-NEXT: xxswapd v2, vs0 4991; P8LE-NEXT: blr 4992entry: 4993 ret <2 x i64> <i64 1, i64 1> 4994} 4995 4996define <2 x i64> @spltConst16kull() { 4997; P9BE-LABEL: spltConst16kull: 4998; P9BE: # %bb.0: # %entry 4999; P9BE-NEXT: addis r3, r2, .LCPI98_0@toc@ha 5000; P9BE-NEXT: addi r3, r3, .LCPI98_0@toc@l 5001; P9BE-NEXT: lxv v2, 0(r3) 5002; P9BE-NEXT: blr 5003; 5004; P9LE-LABEL: spltConst16kull: 5005; P9LE: # %bb.0: # %entry 5006; P9LE-NEXT: addis r3, r2, .LCPI98_0@toc@ha 5007; P9LE-NEXT: addi r3, r3, .LCPI98_0@toc@l 5008; P9LE-NEXT: lxv v2, 0(r3) 5009; P9LE-NEXT: blr 5010; 5011; P8BE-LABEL: spltConst16kull: 5012; P8BE: # %bb.0: # %entry 5013; P8BE-NEXT: addis r3, r2, .LCPI98_0@toc@ha 5014; P8BE-NEXT: addi r3, r3, .LCPI98_0@toc@l 5015; P8BE-NEXT: lxvd2x v2, 0, r3 5016; P8BE-NEXT: blr 5017; 5018; P8LE-LABEL: spltConst16kull: 5019; P8LE: # %bb.0: # %entry 5020; P8LE-NEXT: addis r3, r2, .LCPI98_0@toc@ha 5021; P8LE-NEXT: addi r3, r3, .LCPI98_0@toc@l 5022; P8LE-NEXT: lxvd2x vs0, 0, r3 5023; P8LE-NEXT: xxswapd v2, vs0 5024; P8LE-NEXT: blr 5025entry: 5026 ret <2 x i64> <i64 32767, i64 32767> 5027} 5028 5029define <2 x i64> @spltConst32kull() { 5030; P9BE-LABEL: spltConst32kull: 5031; P9BE: # %bb.0: # %entry 5032; P9BE-NEXT: addis r3, r2, .LCPI99_0@toc@ha 5033; P9BE-NEXT: addi r3, r3, .LCPI99_0@toc@l 5034; P9BE-NEXT: lxv v2, 0(r3) 5035; P9BE-NEXT: blr 5036; 5037; P9LE-LABEL: spltConst32kull: 5038; P9LE: # %bb.0: # %entry 5039; P9LE-NEXT: addis r3, r2, .LCPI99_0@toc@ha 5040; P9LE-NEXT: addi r3, r3, .LCPI99_0@toc@l 5041; P9LE-NEXT: lxv v2, 0(r3) 5042; P9LE-NEXT: blr 5043; 5044; P8BE-LABEL: spltConst32kull: 5045; P8BE: # %bb.0: # %entry 5046; P8BE-NEXT: addis r3, r2, .LCPI99_0@toc@ha 5047; P8BE-NEXT: addi r3, r3, .LCPI99_0@toc@l 5048; P8BE-NEXT: lxvd2x v2, 0, r3 5049; P8BE-NEXT: blr 5050; 5051; P8LE-LABEL: spltConst32kull: 5052; P8LE: # %bb.0: # %entry 5053; P8LE-NEXT: addis r3, r2, .LCPI99_0@toc@ha 5054; P8LE-NEXT: addi r3, r3, .LCPI99_0@toc@l 5055; P8LE-NEXT: lxvd2x vs0, 0, r3 5056; P8LE-NEXT: xxswapd v2, vs0 5057; P8LE-NEXT: blr 5058entry: 5059 ret <2 x i64> <i64 65535, i64 65535> 5060} 5061 5062define <2 x i64> @fromRegsull(i64 %a, i64 %b) { 5063; P9BE-LABEL: fromRegsull: 5064; P9BE: # %bb.0: # %entry 5065; P9BE-NEXT: mtvsrdd v2, r3, r4 5066; P9BE-NEXT: blr 5067; 5068; P9LE-LABEL: fromRegsull: 5069; P9LE: # %bb.0: # %entry 5070; P9LE-NEXT: mtvsrdd v2, r4, r3 5071; P9LE-NEXT: blr 5072; 5073; P8BE-LABEL: fromRegsull: 5074; P8BE: # %bb.0: # %entry 5075; P8BE-NEXT: mtfprd f0, r4 5076; P8BE-NEXT: mtfprd f1, r3 5077; P8BE-NEXT: xxmrghd v2, vs1, vs0 5078; P8BE-NEXT: blr 5079; 5080; P8LE-LABEL: fromRegsull: 5081; P8LE: # %bb.0: # %entry 5082; P8LE-NEXT: mtfprd f0, r3 5083; P8LE-NEXT: mtfprd f1, r4 5084; P8LE-NEXT: xxmrghd v2, vs1, vs0 5085; P8LE-NEXT: blr 5086entry: 5087 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 5088 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 5089 ret <2 x i64> %vecinit1 5090} 5091 5092define <2 x i64> @fromDiffConstsull() { 5093; P9BE-LABEL: fromDiffConstsull: 5094; P9BE: # %bb.0: # %entry 5095; P9BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5096; P9BE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5097; P9BE-NEXT: lxv v2, 0(r3) 5098; P9BE-NEXT: blr 5099; 5100; P9LE-LABEL: fromDiffConstsull: 5101; P9LE: # %bb.0: # %entry 5102; P9LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5103; P9LE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5104; P9LE-NEXT: lxv v2, 0(r3) 5105; P9LE-NEXT: blr 5106; 5107; P8BE-LABEL: fromDiffConstsull: 5108; P8BE: # %bb.0: # %entry 5109; P8BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5110; P8BE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5111; P8BE-NEXT: lxvd2x v2, 0, r3 5112; P8BE-NEXT: blr 5113; 5114; P8LE-LABEL: fromDiffConstsull: 5115; P8LE: # %bb.0: # %entry 5116; P8LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5117; P8LE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5118; P8LE-NEXT: lxvd2x vs0, 0, r3 5119; P8LE-NEXT: xxswapd v2, vs0 5120; P8LE-NEXT: blr 5121entry: 5122 ret <2 x i64> <i64 242, i64 -113> 5123} 5124 5125define <2 x i64> @fromDiffMemConsAull(i64* nocapture readonly %arr) { 5126; P9BE-LABEL: fromDiffMemConsAull: 5127; P9BE: # %bb.0: # %entry 5128; P9BE-NEXT: lxv v2, 0(r3) 5129; P9BE-NEXT: blr 5130; 5131; P9LE-LABEL: fromDiffMemConsAull: 5132; P9LE: # %bb.0: # %entry 5133; P9LE-NEXT: lxv v2, 0(r3) 5134; P9LE-NEXT: blr 5135; 5136; P8BE-LABEL: fromDiffMemConsAull: 5137; P8BE: # %bb.0: # %entry 5138; P8BE-NEXT: lxvd2x v2, 0, r3 5139; P8BE-NEXT: blr 5140; 5141; P8LE-LABEL: fromDiffMemConsAull: 5142; P8LE: # %bb.0: # %entry 5143; P8LE-NEXT: lxvd2x vs0, 0, r3 5144; P8LE-NEXT: xxswapd v2, vs0 5145; P8LE-NEXT: blr 5146entry: 5147 %0 = load i64, i64* %arr, align 8 5148 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5149 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 1 5150 %1 = load i64, i64* %arrayidx1, align 8 5151 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5152 ret <2 x i64> %vecinit2 5153} 5154 5155define <2 x i64> @fromDiffMemConsDull(i64* nocapture readonly %arr) { 5156; P9BE-LABEL: fromDiffMemConsDull: 5157; P9BE: # %bb.0: # %entry 5158; P9BE-NEXT: lxv v2, 16(r3) 5159; P9BE-NEXT: xxswapd v2, v2 5160; P9BE-NEXT: blr 5161; 5162; P9LE-LABEL: fromDiffMemConsDull: 5163; P9LE: # %bb.0: # %entry 5164; P9LE-NEXT: addi r3, r3, 16 5165; P9LE-NEXT: lxvd2x v2, 0, r3 5166; P9LE-NEXT: blr 5167; 5168; P8BE-LABEL: fromDiffMemConsDull: 5169; P8BE: # %bb.0: # %entry 5170; P8BE-NEXT: addi r3, r3, 16 5171; P8BE-NEXT: lxvd2x v2, 0, r3 5172; P8BE-NEXT: xxswapd v2, v2 5173; P8BE-NEXT: blr 5174; 5175; P8LE-LABEL: fromDiffMemConsDull: 5176; P8LE: # %bb.0: # %entry 5177; P8LE-NEXT: addi r3, r3, 16 5178; P8LE-NEXT: lxvd2x v2, 0, r3 5179; P8LE-NEXT: blr 5180entry: 5181 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 3 5182 %0 = load i64, i64* %arrayidx, align 8 5183 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5184 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 2 5185 %1 = load i64, i64* %arrayidx1, align 8 5186 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5187 ret <2 x i64> %vecinit2 5188} 5189 5190define <2 x i64> @fromDiffMemVarAull(i64* nocapture readonly %arr, i32 signext %elem) { 5191; P9BE-LABEL: fromDiffMemVarAull: 5192; P9BE: # %bb.0: # %entry 5193; P9BE-NEXT: sldi r4, r4, 3 5194; P9BE-NEXT: lxvx v2, r3, r4 5195; P9BE-NEXT: blr 5196; 5197; P9LE-LABEL: fromDiffMemVarAull: 5198; P9LE: # %bb.0: # %entry 5199; P9LE-NEXT: sldi r4, r4, 3 5200; P9LE-NEXT: lxvx v2, r3, r4 5201; P9LE-NEXT: blr 5202; 5203; P8BE-LABEL: fromDiffMemVarAull: 5204; P8BE: # %bb.0: # %entry 5205; P8BE-NEXT: sldi r4, r4, 3 5206; P8BE-NEXT: lxvd2x v2, r3, r4 5207; P8BE-NEXT: blr 5208; 5209; P8LE-LABEL: fromDiffMemVarAull: 5210; P8LE: # %bb.0: # %entry 5211; P8LE-NEXT: sldi r4, r4, 3 5212; P8LE-NEXT: lxvd2x vs0, r3, r4 5213; P8LE-NEXT: xxswapd v2, vs0 5214; P8LE-NEXT: blr 5215entry: 5216 %idxprom = sext i32 %elem to i64 5217 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 5218 %0 = load i64, i64* %arrayidx, align 8 5219 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5220 %add = add nsw i32 %elem, 1 5221 %idxprom1 = sext i32 %add to i64 5222 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 5223 %1 = load i64, i64* %arrayidx2, align 8 5224 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5225 ret <2 x i64> %vecinit3 5226} 5227 5228define <2 x i64> @fromDiffMemVarDull(i64* nocapture readonly %arr, i32 signext %elem) { 5229; P9BE-LABEL: fromDiffMemVarDull: 5230; P9BE: # %bb.0: # %entry 5231; P9BE-NEXT: sldi r4, r4, 3 5232; P9BE-NEXT: add r3, r3, r4 5233; P9BE-NEXT: li r4, -8 5234; P9BE-NEXT: lxvx v2, r3, r4 5235; P9BE-NEXT: xxswapd v2, v2 5236; P9BE-NEXT: blr 5237; 5238; P9LE-LABEL: fromDiffMemVarDull: 5239; P9LE: # %bb.0: # %entry 5240; P9LE-NEXT: sldi r4, r4, 3 5241; P9LE-NEXT: add r3, r3, r4 5242; P9LE-NEXT: addi r3, r3, -8 5243; P9LE-NEXT: lxvd2x v2, 0, r3 5244; P9LE-NEXT: blr 5245; 5246; P8BE-LABEL: fromDiffMemVarDull: 5247; P8BE: # %bb.0: # %entry 5248; P8BE-NEXT: sldi r4, r4, 3 5249; P8BE-NEXT: add r3, r3, r4 5250; P8BE-NEXT: addi r3, r3, -8 5251; P8BE-NEXT: lxvd2x v2, 0, r3 5252; P8BE-NEXT: xxswapd v2, v2 5253; P8BE-NEXT: blr 5254; 5255; P8LE-LABEL: fromDiffMemVarDull: 5256; P8LE: # %bb.0: # %entry 5257; P8LE-NEXT: sldi r4, r4, 3 5258; P8LE-NEXT: add r3, r3, r4 5259; P8LE-NEXT: addi r3, r3, -8 5260; P8LE-NEXT: lxvd2x v2, 0, r3 5261; P8LE-NEXT: blr 5262entry: 5263 %idxprom = sext i32 %elem to i64 5264 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 5265 %0 = load i64, i64* %arrayidx, align 8 5266 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5267 %sub = add nsw i32 %elem, -1 5268 %idxprom1 = sext i32 %sub to i64 5269 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 5270 %1 = load i64, i64* %arrayidx2, align 8 5271 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5272 ret <2 x i64> %vecinit3 5273} 5274 5275define <2 x i64> @fromRandMemConsull(i64* nocapture readonly %arr) { 5276; P9BE-LABEL: fromRandMemConsull: 5277; P9BE: # %bb.0: # %entry 5278; P9BE-NEXT: ld r4, 32(r3) 5279; P9BE-NEXT: ld r3, 144(r3) 5280; P9BE-NEXT: mtvsrdd v2, r4, r3 5281; P9BE-NEXT: blr 5282; 5283; P9LE-LABEL: fromRandMemConsull: 5284; P9LE: # %bb.0: # %entry 5285; P9LE-NEXT: ld r4, 32(r3) 5286; P9LE-NEXT: ld r3, 144(r3) 5287; P9LE-NEXT: mtvsrdd v2, r3, r4 5288; P9LE-NEXT: blr 5289; 5290; P8BE-LABEL: fromRandMemConsull: 5291; P8BE: # %bb.0: # %entry 5292; P8BE-NEXT: ld r4, 144(r3) 5293; P8BE-NEXT: ld r3, 32(r3) 5294; P8BE-NEXT: mtfprd f0, r4 5295; P8BE-NEXT: mtfprd f1, r3 5296; P8BE-NEXT: xxmrghd v2, vs1, vs0 5297; P8BE-NEXT: blr 5298; 5299; P8LE-LABEL: fromRandMemConsull: 5300; P8LE: # %bb.0: # %entry 5301; P8LE-NEXT: ld r4, 32(r3) 5302; P8LE-NEXT: ld r3, 144(r3) 5303; P8LE-NEXT: mtfprd f0, r4 5304; P8LE-NEXT: mtfprd f1, r3 5305; P8LE-NEXT: xxmrghd v2, vs1, vs0 5306; P8LE-NEXT: blr 5307entry: 5308 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4 5309 %0 = load i64, i64* %arrayidx, align 8 5310 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5311 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18 5312 %1 = load i64, i64* %arrayidx1, align 8 5313 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5314 ret <2 x i64> %vecinit2 5315} 5316 5317define <2 x i64> @fromRandMemVarull(i64* nocapture readonly %arr, i32 signext %elem) { 5318; P9BE-LABEL: fromRandMemVarull: 5319; P9BE: # %bb.0: # %entry 5320; P9BE-NEXT: sldi r4, r4, 3 5321; P9BE-NEXT: add r3, r3, r4 5322; P9BE-NEXT: ld r4, 32(r3) 5323; P9BE-NEXT: ld r3, 8(r3) 5324; P9BE-NEXT: mtvsrdd v2, r4, r3 5325; P9BE-NEXT: blr 5326; 5327; P9LE-LABEL: fromRandMemVarull: 5328; P9LE: # %bb.0: # %entry 5329; P9LE-NEXT: sldi r4, r4, 3 5330; P9LE-NEXT: add r3, r3, r4 5331; P9LE-NEXT: ld r4, 32(r3) 5332; P9LE-NEXT: ld r3, 8(r3) 5333; P9LE-NEXT: mtvsrdd v2, r3, r4 5334; P9LE-NEXT: blr 5335; 5336; P8BE-LABEL: fromRandMemVarull: 5337; P8BE: # %bb.0: # %entry 5338; P8BE-NEXT: sldi r4, r4, 3 5339; P8BE-NEXT: add r3, r3, r4 5340; P8BE-NEXT: ld r4, 8(r3) 5341; P8BE-NEXT: ld r3, 32(r3) 5342; P8BE-NEXT: mtfprd f0, r4 5343; P8BE-NEXT: mtfprd f1, r3 5344; P8BE-NEXT: xxmrghd v2, vs1, vs0 5345; P8BE-NEXT: blr 5346; 5347; P8LE-LABEL: fromRandMemVarull: 5348; P8LE: # %bb.0: # %entry 5349; P8LE-NEXT: sldi r4, r4, 3 5350; P8LE-NEXT: add r3, r3, r4 5351; P8LE-NEXT: ld r4, 32(r3) 5352; P8LE-NEXT: ld r3, 8(r3) 5353; P8LE-NEXT: mtfprd f0, r4 5354; P8LE-NEXT: mtfprd f1, r3 5355; P8LE-NEXT: xxmrghd v2, vs1, vs0 5356; P8LE-NEXT: blr 5357entry: 5358 %add = add nsw i32 %elem, 4 5359 %idxprom = sext i32 %add to i64 5360 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 5361 %0 = load i64, i64* %arrayidx, align 8 5362 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5363 %add1 = add nsw i32 %elem, 1 5364 %idxprom2 = sext i32 %add1 to i64 5365 %arrayidx3 = getelementptr inbounds i64, i64* %arr, i64 %idxprom2 5366 %1 = load i64, i64* %arrayidx3, align 8 5367 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5368 ret <2 x i64> %vecinit4 5369} 5370 5371define <2 x i64> @spltRegValull(i64 %val) { 5372; P9BE-LABEL: spltRegValull: 5373; P9BE: # %bb.0: # %entry 5374; P9BE-NEXT: mtvsrdd v2, r3, r3 5375; P9BE-NEXT: blr 5376; 5377; P9LE-LABEL: spltRegValull: 5378; P9LE: # %bb.0: # %entry 5379; P9LE-NEXT: mtvsrdd v2, r3, r3 5380; P9LE-NEXT: blr 5381; 5382; P8BE-LABEL: spltRegValull: 5383; P8BE: # %bb.0: # %entry 5384; P8BE-NEXT: mtfprd f0, r3 5385; P8BE-NEXT: xxspltd v2, vs0, 0 5386; P8BE-NEXT: blr 5387; 5388; P8LE-LABEL: spltRegValull: 5389; P8LE: # %bb.0: # %entry 5390; P8LE-NEXT: mtfprd f0, r3 5391; P8LE-NEXT: xxspltd v2, vs0, 0 5392; P8LE-NEXT: blr 5393entry: 5394 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0 5395 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5396 ret <2 x i64> %splat.splat 5397} 5398 5399define <2 x i64> @spltMemValull(i64* nocapture readonly %ptr) { 5400; P9BE-LABEL: spltMemValull: 5401; P9BE: # %bb.0: # %entry 5402; P9BE-NEXT: lxvdsx v2, 0, r3 5403; P9BE-NEXT: blr 5404; 5405; P9LE-LABEL: spltMemValull: 5406; P9LE: # %bb.0: # %entry 5407; P9LE-NEXT: lxvdsx v2, 0, r3 5408; P9LE-NEXT: blr 5409; 5410; P8BE-LABEL: spltMemValull: 5411; P8BE: # %bb.0: # %entry 5412; P8BE-NEXT: lxvdsx v2, 0, r3 5413; P8BE-NEXT: blr 5414; 5415; P8LE-LABEL: spltMemValull: 5416; P8LE: # %bb.0: # %entry 5417; P8LE-NEXT: lxvdsx v2, 0, r3 5418; P8LE-NEXT: blr 5419entry: 5420 %0 = load i64, i64* %ptr, align 8 5421 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 5422 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5423 ret <2 x i64> %splat.splat 5424} 5425 5426define <2 x i64> @spltCnstConvftoull() { 5427; P9BE-LABEL: spltCnstConvftoull: 5428; P9BE: # %bb.0: # %entry 5429; P9BE-NEXT: addis r3, r2, .LCPI110_0@toc@ha 5430; P9BE-NEXT: addi r3, r3, .LCPI110_0@toc@l 5431; P9BE-NEXT: lxv v2, 0(r3) 5432; P9BE-NEXT: blr 5433; 5434; P9LE-LABEL: spltCnstConvftoull: 5435; P9LE: # %bb.0: # %entry 5436; P9LE-NEXT: addis r3, r2, .LCPI110_0@toc@ha 5437; P9LE-NEXT: addi r3, r3, .LCPI110_0@toc@l 5438; P9LE-NEXT: lxv v2, 0(r3) 5439; P9LE-NEXT: blr 5440; 5441; P8BE-LABEL: spltCnstConvftoull: 5442; P8BE: # %bb.0: # %entry 5443; P8BE-NEXT: addis r3, r2, .LCPI110_0@toc@ha 5444; P8BE-NEXT: addi r3, r3, .LCPI110_0@toc@l 5445; P8BE-NEXT: lxvd2x v2, 0, r3 5446; P8BE-NEXT: blr 5447; 5448; P8LE-LABEL: spltCnstConvftoull: 5449; P8LE: # %bb.0: # %entry 5450; P8LE-NEXT: addis r3, r2, .LCPI110_0@toc@ha 5451; P8LE-NEXT: addi r3, r3, .LCPI110_0@toc@l 5452; P8LE-NEXT: lxvd2x vs0, 0, r3 5453; P8LE-NEXT: xxswapd v2, vs0 5454; P8LE-NEXT: blr 5455entry: 5456 ret <2 x i64> <i64 4, i64 4> 5457} 5458 5459define <2 x i64> @fromRegsConvftoull(float %a, float %b) { 5460; P9BE-LABEL: fromRegsConvftoull: 5461; P9BE: # %bb.0: # %entry 5462; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5463; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5464; P9BE-NEXT: xxmrghd vs0, vs1, vs2 5465; P9BE-NEXT: xvcvdpuxds v2, vs0 5466; P9BE-NEXT: blr 5467; 5468; P9LE-LABEL: fromRegsConvftoull: 5469; P9LE: # %bb.0: # %entry 5470; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5471; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5472; P9LE-NEXT: xxmrghd vs0, vs2, vs1 5473; P9LE-NEXT: xvcvdpuxds v2, vs0 5474; P9LE-NEXT: blr 5475; 5476; P8BE-LABEL: fromRegsConvftoull: 5477; P8BE: # %bb.0: # %entry 5478; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5479; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5480; P8BE-NEXT: xxmrghd vs0, vs1, vs2 5481; P8BE-NEXT: xvcvdpuxds v2, vs0 5482; P8BE-NEXT: blr 5483; 5484; P8LE-LABEL: fromRegsConvftoull: 5485; P8LE: # %bb.0: # %entry 5486; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5487; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5488; P8LE-NEXT: xxmrghd vs0, vs2, vs1 5489; P8LE-NEXT: xvcvdpuxds v2, vs0 5490; P8LE-NEXT: blr 5491entry: 5492 %conv = fptoui float %a to i64 5493 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5494 %conv1 = fptoui float %b to i64 5495 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 5496 ret <2 x i64> %vecinit2 5497} 5498 5499define <2 x i64> @fromDiffConstsConvftoull() { 5500; P9BE-LABEL: fromDiffConstsConvftoull: 5501; P9BE: # %bb.0: # %entry 5502; P9BE-NEXT: addis r3, r2, .LCPI112_0@toc@ha 5503; P9BE-NEXT: addi r3, r3, .LCPI112_0@toc@l 5504; P9BE-NEXT: lxv v2, 0(r3) 5505; P9BE-NEXT: blr 5506; 5507; P9LE-LABEL: fromDiffConstsConvftoull: 5508; P9LE: # %bb.0: # %entry 5509; P9LE-NEXT: addis r3, r2, .LCPI112_0@toc@ha 5510; P9LE-NEXT: addi r3, r3, .LCPI112_0@toc@l 5511; P9LE-NEXT: lxv v2, 0(r3) 5512; P9LE-NEXT: blr 5513; 5514; P8BE-LABEL: fromDiffConstsConvftoull: 5515; P8BE: # %bb.0: # %entry 5516; P8BE-NEXT: addis r3, r2, .LCPI112_0@toc@ha 5517; P8BE-NEXT: addi r3, r3, .LCPI112_0@toc@l 5518; P8BE-NEXT: lxvd2x v2, 0, r3 5519; P8BE-NEXT: blr 5520; 5521; P8LE-LABEL: fromDiffConstsConvftoull: 5522; P8LE: # %bb.0: # %entry 5523; P8LE-NEXT: addis r3, r2, .LCPI112_0@toc@ha 5524; P8LE-NEXT: addi r3, r3, .LCPI112_0@toc@l 5525; P8LE-NEXT: lxvd2x vs0, 0, r3 5526; P8LE-NEXT: xxswapd v2, vs0 5527; P8LE-NEXT: blr 5528entry: 5529 ret <2 x i64> <i64 24, i64 234> 5530} 5531 5532define <2 x i64> @fromDiffMemConsAConvftoull(float* nocapture readonly %ptr) { 5533; P9BE-LABEL: fromDiffMemConsAConvftoull: 5534; P9BE: # %bb.0: # %entry 5535; P9BE-NEXT: lfs f0, 0(r3) 5536; P9BE-NEXT: lfs f1, 4(r3) 5537; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5538; P9BE-NEXT: xvcvdpuxds v2, vs0 5539; P9BE-NEXT: blr 5540; 5541; P9LE-LABEL: fromDiffMemConsAConvftoull: 5542; P9LE: # %bb.0: # %entry 5543; P9LE-NEXT: lfs f0, 0(r3) 5544; P9LE-NEXT: lfs f1, 4(r3) 5545; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5546; P9LE-NEXT: xvcvdpuxds v2, vs0 5547; P9LE-NEXT: blr 5548; 5549; P8BE-LABEL: fromDiffMemConsAConvftoull: 5550; P8BE: # %bb.0: # %entry 5551; P8BE-NEXT: lfs f0, 0(r3) 5552; P8BE-NEXT: lfs f1, 4(r3) 5553; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5554; P8BE-NEXT: xvcvdpuxds v2, vs0 5555; P8BE-NEXT: blr 5556; 5557; P8LE-LABEL: fromDiffMemConsAConvftoull: 5558; P8LE: # %bb.0: # %entry 5559; P8LE-NEXT: lfs f0, 0(r3) 5560; P8LE-NEXT: lfs f1, 4(r3) 5561; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5562; P8LE-NEXT: xvcvdpuxds v2, vs0 5563; P8LE-NEXT: blr 5564entry: 5565 %0 = load float, float* %ptr, align 4 5566 %conv = fptoui float %0 to i64 5567 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5568 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1 5569 %1 = load float, float* %arrayidx1, align 4 5570 %conv2 = fptoui float %1 to i64 5571 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 5572 ret <2 x i64> %vecinit3 5573} 5574 5575define <2 x i64> @fromDiffMemConsDConvftoull(float* nocapture readonly %ptr) { 5576; P9BE-LABEL: fromDiffMemConsDConvftoull: 5577; P9BE: # %bb.0: # %entry 5578; P9BE-NEXT: lfs f0, 12(r3) 5579; P9BE-NEXT: lfs f1, 8(r3) 5580; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5581; P9BE-NEXT: xvcvdpuxds v2, vs0 5582; P9BE-NEXT: blr 5583; 5584; P9LE-LABEL: fromDiffMemConsDConvftoull: 5585; P9LE: # %bb.0: # %entry 5586; P9LE-NEXT: lfs f0, 12(r3) 5587; P9LE-NEXT: lfs f1, 8(r3) 5588; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5589; P9LE-NEXT: xvcvdpuxds v2, vs0 5590; P9LE-NEXT: blr 5591; 5592; P8BE-LABEL: fromDiffMemConsDConvftoull: 5593; P8BE: # %bb.0: # %entry 5594; P8BE-NEXT: lfs f0, 12(r3) 5595; P8BE-NEXT: lfs f1, 8(r3) 5596; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5597; P8BE-NEXT: xvcvdpuxds v2, vs0 5598; P8BE-NEXT: blr 5599; 5600; P8LE-LABEL: fromDiffMemConsDConvftoull: 5601; P8LE: # %bb.0: # %entry 5602; P8LE-NEXT: lfs f0, 12(r3) 5603; P8LE-NEXT: lfs f1, 8(r3) 5604; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5605; P8LE-NEXT: xvcvdpuxds v2, vs0 5606; P8LE-NEXT: blr 5607entry: 5608 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 5609 %0 = load float, float* %arrayidx, align 4 5610 %conv = fptoui float %0 to i64 5611 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5612 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 5613 %1 = load float, float* %arrayidx1, align 4 5614 %conv2 = fptoui float %1 to i64 5615 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 5616 ret <2 x i64> %vecinit3 5617} 5618 5619define <2 x i64> @fromDiffMemVarAConvftoull(float* nocapture readonly %arr, i32 signext %elem) { 5620; P9BE-LABEL: fromDiffMemVarAConvftoull: 5621; P9BE: # %bb.0: # %entry 5622; P9BE-NEXT: sldi r4, r4, 2 5623; P9BE-NEXT: lfsux f0, r3, r4 5624; P9BE-NEXT: lfs f1, 4(r3) 5625; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5626; P9BE-NEXT: xvcvdpuxds v2, vs0 5627; P9BE-NEXT: blr 5628; 5629; P9LE-LABEL: fromDiffMemVarAConvftoull: 5630; P9LE: # %bb.0: # %entry 5631; P9LE-NEXT: sldi r4, r4, 2 5632; P9LE-NEXT: lfsux f0, r3, r4 5633; P9LE-NEXT: lfs f1, 4(r3) 5634; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5635; P9LE-NEXT: xvcvdpuxds v2, vs0 5636; P9LE-NEXT: blr 5637; 5638; P8BE-LABEL: fromDiffMemVarAConvftoull: 5639; P8BE: # %bb.0: # %entry 5640; P8BE-NEXT: sldi r4, r4, 2 5641; P8BE-NEXT: lfsux f0, r3, r4 5642; P8BE-NEXT: lfs f1, 4(r3) 5643; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5644; P8BE-NEXT: xvcvdpuxds v2, vs0 5645; P8BE-NEXT: blr 5646; 5647; P8LE-LABEL: fromDiffMemVarAConvftoull: 5648; P8LE: # %bb.0: # %entry 5649; P8LE-NEXT: sldi r4, r4, 2 5650; P8LE-NEXT: lfsux f0, r3, r4 5651; P8LE-NEXT: lfs f1, 4(r3) 5652; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5653; P8LE-NEXT: xvcvdpuxds v2, vs0 5654; P8LE-NEXT: blr 5655entry: 5656 %idxprom = sext i32 %elem to i64 5657 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 5658 %0 = load float, float* %arrayidx, align 4 5659 %conv = fptoui float %0 to i64 5660 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5661 %add = add nsw i32 %elem, 1 5662 %idxprom1 = sext i32 %add to i64 5663 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 5664 %1 = load float, float* %arrayidx2, align 4 5665 %conv3 = fptoui float %1 to i64 5666 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 5667 ret <2 x i64> %vecinit4 5668} 5669 5670define <2 x i64> @fromDiffMemVarDConvftoull(float* nocapture readonly %arr, i32 signext %elem) { 5671; P9BE-LABEL: fromDiffMemVarDConvftoull: 5672; P9BE: # %bb.0: # %entry 5673; P9BE-NEXT: sldi r4, r4, 2 5674; P9BE-NEXT: lfsux f0, r3, r4 5675; P9BE-NEXT: lfs f1, -4(r3) 5676; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5677; P9BE-NEXT: xvcvdpuxds v2, vs0 5678; P9BE-NEXT: blr 5679; 5680; P9LE-LABEL: fromDiffMemVarDConvftoull: 5681; P9LE: # %bb.0: # %entry 5682; P9LE-NEXT: sldi r4, r4, 2 5683; P9LE-NEXT: lfsux f0, r3, r4 5684; P9LE-NEXT: lfs f1, -4(r3) 5685; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5686; P9LE-NEXT: xvcvdpuxds v2, vs0 5687; P9LE-NEXT: blr 5688; 5689; P8BE-LABEL: fromDiffMemVarDConvftoull: 5690; P8BE: # %bb.0: # %entry 5691; P8BE-NEXT: sldi r4, r4, 2 5692; P8BE-NEXT: lfsux f0, r3, r4 5693; P8BE-NEXT: lfs f1, -4(r3) 5694; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5695; P8BE-NEXT: xvcvdpuxds v2, vs0 5696; P8BE-NEXT: blr 5697; 5698; P8LE-LABEL: fromDiffMemVarDConvftoull: 5699; P8LE: # %bb.0: # %entry 5700; P8LE-NEXT: sldi r4, r4, 2 5701; P8LE-NEXT: lfsux f0, r3, r4 5702; P8LE-NEXT: lfs f1, -4(r3) 5703; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5704; P8LE-NEXT: xvcvdpuxds v2, vs0 5705; P8LE-NEXT: blr 5706entry: 5707 %idxprom = sext i32 %elem to i64 5708 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 5709 %0 = load float, float* %arrayidx, align 4 5710 %conv = fptoui float %0 to i64 5711 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5712 %sub = add nsw i32 %elem, -1 5713 %idxprom1 = sext i32 %sub to i64 5714 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 5715 %1 = load float, float* %arrayidx2, align 4 5716 %conv3 = fptoui float %1 to i64 5717 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 5718 ret <2 x i64> %vecinit4 5719} 5720 5721define <2 x i64> @spltRegValConvftoull(float %val) { 5722; P9BE-LABEL: spltRegValConvftoull: 5723; P9BE: # %bb.0: # %entry 5724; P9BE-NEXT: xscvdpuxds f0, f1 5725; P9BE-NEXT: xxspltd v2, f0, 0 5726; P9BE-NEXT: blr 5727; 5728; P9LE-LABEL: spltRegValConvftoull: 5729; P9LE: # %bb.0: # %entry 5730; P9LE-NEXT: xscvdpuxds f0, f1 5731; P9LE-NEXT: xxspltd v2, f0, 0 5732; P9LE-NEXT: blr 5733; 5734; P8BE-LABEL: spltRegValConvftoull: 5735; P8BE: # %bb.0: # %entry 5736; P8BE-NEXT: xscvdpuxds f0, f1 5737; P8BE-NEXT: xxspltd v2, f0, 0 5738; P8BE-NEXT: blr 5739; 5740; P8LE-LABEL: spltRegValConvftoull: 5741; P8LE: # %bb.0: # %entry 5742; P8LE-NEXT: xscvdpuxds f0, f1 5743; P8LE-NEXT: xxspltd v2, f0, 0 5744; P8LE-NEXT: blr 5745entry: 5746 %conv = fptoui float %val to i64 5747 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 5748 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5749 ret <2 x i64> %splat.splat 5750} 5751 5752define <2 x i64> @spltMemValConvftoull(float* nocapture readonly %ptr) { 5753; P9BE-LABEL: spltMemValConvftoull: 5754; P9BE: # %bb.0: # %entry 5755; P9BE-NEXT: lfs f0, 0(r3) 5756; P9BE-NEXT: xscvdpuxds f0, f0 5757; P9BE-NEXT: xxspltd v2, f0, 0 5758; P9BE-NEXT: blr 5759; 5760; P9LE-LABEL: spltMemValConvftoull: 5761; P9LE: # %bb.0: # %entry 5762; P9LE-NEXT: lfs f0, 0(r3) 5763; P9LE-NEXT: xscvdpuxds f0, f0 5764; P9LE-NEXT: xxspltd v2, vs0, 0 5765; P9LE-NEXT: blr 5766; 5767; P8BE-LABEL: spltMemValConvftoull: 5768; P8BE: # %bb.0: # %entry 5769; P8BE-NEXT: lfsx f0, 0, r3 5770; P8BE-NEXT: xscvdpuxds f0, f0 5771; P8BE-NEXT: xxspltd v2, f0, 0 5772; P8BE-NEXT: blr 5773; 5774; P8LE-LABEL: spltMemValConvftoull: 5775; P8LE: # %bb.0: # %entry 5776; P8LE-NEXT: lfsx f0, 0, r3 5777; P8LE-NEXT: xscvdpuxds f0, f0 5778; P8LE-NEXT: xxspltd v2, vs0, 0 5779; P8LE-NEXT: blr 5780entry: 5781 %0 = load float, float* %ptr, align 4 5782 %conv = fptoui float %0 to i64 5783 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 5784 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5785 ret <2 x i64> %splat.splat 5786} 5787 5788define <2 x i64> @spltCnstConvdtoull() { 5789; P9BE-LABEL: spltCnstConvdtoull: 5790; P9BE: # %bb.0: # %entry 5791; P9BE-NEXT: addis r3, r2, .LCPI119_0@toc@ha 5792; P9BE-NEXT: addi r3, r3, .LCPI119_0@toc@l 5793; P9BE-NEXT: lxv v2, 0(r3) 5794; P9BE-NEXT: blr 5795; 5796; P9LE-LABEL: spltCnstConvdtoull: 5797; P9LE: # %bb.0: # %entry 5798; P9LE-NEXT: addis r3, r2, .LCPI119_0@toc@ha 5799; P9LE-NEXT: addi r3, r3, .LCPI119_0@toc@l 5800; P9LE-NEXT: lxv v2, 0(r3) 5801; P9LE-NEXT: blr 5802; 5803; P8BE-LABEL: spltCnstConvdtoull: 5804; P8BE: # %bb.0: # %entry 5805; P8BE-NEXT: addis r3, r2, .LCPI119_0@toc@ha 5806; P8BE-NEXT: addi r3, r3, .LCPI119_0@toc@l 5807; P8BE-NEXT: lxvd2x v2, 0, r3 5808; P8BE-NEXT: blr 5809; 5810; P8LE-LABEL: spltCnstConvdtoull: 5811; P8LE: # %bb.0: # %entry 5812; P8LE-NEXT: addis r3, r2, .LCPI119_0@toc@ha 5813; P8LE-NEXT: addi r3, r3, .LCPI119_0@toc@l 5814; P8LE-NEXT: lxvd2x vs0, 0, r3 5815; P8LE-NEXT: xxswapd v2, vs0 5816; P8LE-NEXT: blr 5817entry: 5818 ret <2 x i64> <i64 4, i64 4> 5819} 5820 5821define <2 x i64> @fromRegsConvdtoull(double %a, double %b) { 5822; P9BE-LABEL: fromRegsConvdtoull: 5823; P9BE: # %bb.0: # %entry 5824; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5825; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5826; P9BE-NEXT: xxmrghd vs0, vs1, vs2 5827; P9BE-NEXT: xvcvdpuxds v2, vs0 5828; P9BE-NEXT: blr 5829; 5830; P9LE-LABEL: fromRegsConvdtoull: 5831; P9LE: # %bb.0: # %entry 5832; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5833; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5834; P9LE-NEXT: xxmrghd vs0, vs2, vs1 5835; P9LE-NEXT: xvcvdpuxds v2, vs0 5836; P9LE-NEXT: blr 5837; 5838; P8BE-LABEL: fromRegsConvdtoull: 5839; P8BE: # %bb.0: # %entry 5840; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5841; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5842; P8BE-NEXT: xxmrghd vs0, vs1, vs2 5843; P8BE-NEXT: xvcvdpuxds v2, vs0 5844; P8BE-NEXT: blr 5845; 5846; P8LE-LABEL: fromRegsConvdtoull: 5847; P8LE: # %bb.0: # %entry 5848; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5849; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5850; P8LE-NEXT: xxmrghd vs0, vs2, vs1 5851; P8LE-NEXT: xvcvdpuxds v2, vs0 5852; P8LE-NEXT: blr 5853entry: 5854 %conv = fptoui double %a to i64 5855 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5856 %conv1 = fptoui double %b to i64 5857 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 5858 ret <2 x i64> %vecinit2 5859} 5860 5861define <2 x i64> @fromDiffConstsConvdtoull() { 5862; P9BE-LABEL: fromDiffConstsConvdtoull: 5863; P9BE: # %bb.0: # %entry 5864; P9BE-NEXT: addis r3, r2, .LCPI121_0@toc@ha 5865; P9BE-NEXT: addi r3, r3, .LCPI121_0@toc@l 5866; P9BE-NEXT: lxv v2, 0(r3) 5867; P9BE-NEXT: blr 5868; 5869; P9LE-LABEL: fromDiffConstsConvdtoull: 5870; P9LE: # %bb.0: # %entry 5871; P9LE-NEXT: addis r3, r2, .LCPI121_0@toc@ha 5872; P9LE-NEXT: addi r3, r3, .LCPI121_0@toc@l 5873; P9LE-NEXT: lxv v2, 0(r3) 5874; P9LE-NEXT: blr 5875; 5876; P8BE-LABEL: fromDiffConstsConvdtoull: 5877; P8BE: # %bb.0: # %entry 5878; P8BE-NEXT: addis r3, r2, .LCPI121_0@toc@ha 5879; P8BE-NEXT: addi r3, r3, .LCPI121_0@toc@l 5880; P8BE-NEXT: lxvd2x v2, 0, r3 5881; P8BE-NEXT: blr 5882; 5883; P8LE-LABEL: fromDiffConstsConvdtoull: 5884; P8LE: # %bb.0: # %entry 5885; P8LE-NEXT: addis r3, r2, .LCPI121_0@toc@ha 5886; P8LE-NEXT: addi r3, r3, .LCPI121_0@toc@l 5887; P8LE-NEXT: lxvd2x vs0, 0, r3 5888; P8LE-NEXT: xxswapd v2, vs0 5889; P8LE-NEXT: blr 5890entry: 5891 ret <2 x i64> <i64 24, i64 234> 5892} 5893 5894define <2 x i64> @fromDiffMemConsAConvdtoull(double* nocapture readonly %ptr) { 5895; P9BE-LABEL: fromDiffMemConsAConvdtoull: 5896; P9BE: # %bb.0: # %entry 5897; P9BE-NEXT: lxv vs0, 0(r3) 5898; P9BE-NEXT: xvcvdpuxds v2, vs0 5899; P9BE-NEXT: blr 5900; 5901; P9LE-LABEL: fromDiffMemConsAConvdtoull: 5902; P9LE: # %bb.0: # %entry 5903; P9LE-NEXT: lxv vs0, 0(r3) 5904; P9LE-NEXT: xvcvdpuxds v2, vs0 5905; P9LE-NEXT: blr 5906; 5907; P8BE-LABEL: fromDiffMemConsAConvdtoull: 5908; P8BE: # %bb.0: # %entry 5909; P8BE-NEXT: lxvd2x vs0, 0, r3 5910; P8BE-NEXT: xvcvdpuxds v2, vs0 5911; P8BE-NEXT: blr 5912; 5913; P8LE-LABEL: fromDiffMemConsAConvdtoull: 5914; P8LE: # %bb.0: # %entry 5915; P8LE-NEXT: lxvd2x vs0, 0, r3 5916; P8LE-NEXT: xxswapd vs0, vs0 5917; P8LE-NEXT: xvcvdpuxds v2, vs0 5918; P8LE-NEXT: blr 5919entry: 5920 %0 = bitcast double* %ptr to <2 x double>* 5921 %1 = load <2 x double>, <2 x double>* %0, align 8 5922 %2 = fptoui <2 x double> %1 to <2 x i64> 5923 ret <2 x i64> %2 5924} 5925 5926define <2 x i64> @fromDiffMemConsDConvdtoull(double* nocapture readonly %ptr) { 5927; P9BE-LABEL: fromDiffMemConsDConvdtoull: 5928; P9BE: # %bb.0: # %entry 5929; P9BE-NEXT: lxv vs0, 16(r3) 5930; P9BE-NEXT: xxswapd vs0, vs0 5931; P9BE-NEXT: xvcvdpuxds v2, vs0 5932; P9BE-NEXT: blr 5933; 5934; P9LE-LABEL: fromDiffMemConsDConvdtoull: 5935; P9LE: # %bb.0: # %entry 5936; P9LE-NEXT: addi r3, r3, 16 5937; P9LE-NEXT: lxvd2x vs0, 0, r3 5938; P9LE-NEXT: xvcvdpuxds v2, vs0 5939; P9LE-NEXT: blr 5940; 5941; P8BE-LABEL: fromDiffMemConsDConvdtoull: 5942; P8BE: # %bb.0: # %entry 5943; P8BE-NEXT: addi r3, r3, 16 5944; P8BE-NEXT: lxvd2x vs0, 0, r3 5945; P8BE-NEXT: xxswapd vs0, vs0 5946; P8BE-NEXT: xvcvdpuxds v2, vs0 5947; P8BE-NEXT: blr 5948; 5949; P8LE-LABEL: fromDiffMemConsDConvdtoull: 5950; P8LE: # %bb.0: # %entry 5951; P8LE-NEXT: addi r3, r3, 16 5952; P8LE-NEXT: lxvd2x vs0, 0, r3 5953; P8LE-NEXT: xvcvdpuxds v2, vs0 5954; P8LE-NEXT: blr 5955entry: 5956 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 5957 %0 = load double, double* %arrayidx, align 8 5958 %conv = fptoui double %0 to i64 5959 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5960 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 5961 %1 = load double, double* %arrayidx1, align 8 5962 %conv2 = fptoui double %1 to i64 5963 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 5964 ret <2 x i64> %vecinit3 5965} 5966 5967define <2 x i64> @fromDiffMemVarAConvdtoull(double* nocapture readonly %arr, i32 signext %elem) { 5968; P9BE-LABEL: fromDiffMemVarAConvdtoull: 5969; P9BE: # %bb.0: # %entry 5970; P9BE-NEXT: sldi r4, r4, 3 5971; P9BE-NEXT: lxvx vs0, r3, r4 5972; P9BE-NEXT: xvcvdpuxds v2, vs0 5973; P9BE-NEXT: blr 5974; 5975; P9LE-LABEL: fromDiffMemVarAConvdtoull: 5976; P9LE: # %bb.0: # %entry 5977; P9LE-NEXT: sldi r4, r4, 3 5978; P9LE-NEXT: lxvx vs0, r3, r4 5979; P9LE-NEXT: xvcvdpuxds v2, vs0 5980; P9LE-NEXT: blr 5981; 5982; P8BE-LABEL: fromDiffMemVarAConvdtoull: 5983; P8BE: # %bb.0: # %entry 5984; P8BE-NEXT: sldi r4, r4, 3 5985; P8BE-NEXT: lxvd2x vs0, r3, r4 5986; P8BE-NEXT: xvcvdpuxds v2, vs0 5987; P8BE-NEXT: blr 5988; 5989; P8LE-LABEL: fromDiffMemVarAConvdtoull: 5990; P8LE: # %bb.0: # %entry 5991; P8LE-NEXT: sldi r4, r4, 3 5992; P8LE-NEXT: lxvd2x vs0, r3, r4 5993; P8LE-NEXT: xxswapd vs0, vs0 5994; P8LE-NEXT: xvcvdpuxds v2, vs0 5995; P8LE-NEXT: blr 5996entry: 5997 %idxprom = sext i32 %elem to i64 5998 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 5999 %0 = load double, double* %arrayidx, align 8 6000 %conv = fptoui double %0 to i64 6001 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6002 %add = add nsw i32 %elem, 1 6003 %idxprom1 = sext i32 %add to i64 6004 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 6005 %1 = load double, double* %arrayidx2, align 8 6006 %conv3 = fptoui double %1 to i64 6007 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 6008 ret <2 x i64> %vecinit4 6009} 6010 6011define <2 x i64> @fromDiffMemVarDConvdtoull(double* nocapture readonly %arr, i32 signext %elem) { 6012; P9BE-LABEL: fromDiffMemVarDConvdtoull: 6013; P9BE: # %bb.0: # %entry 6014; P9BE-NEXT: sldi r4, r4, 3 6015; P9BE-NEXT: add r3, r3, r4 6016; P9BE-NEXT: li r4, -8 6017; P9BE-NEXT: lxvx vs0, r3, r4 6018; P9BE-NEXT: xxswapd vs0, vs0 6019; P9BE-NEXT: xvcvdpuxds v2, vs0 6020; P9BE-NEXT: blr 6021; 6022; P9LE-LABEL: fromDiffMemVarDConvdtoull: 6023; P9LE: # %bb.0: # %entry 6024; P9LE-NEXT: sldi r4, r4, 3 6025; P9LE-NEXT: add r3, r3, r4 6026; P9LE-NEXT: addi r3, r3, -8 6027; P9LE-NEXT: lxvd2x vs0, 0, r3 6028; P9LE-NEXT: xvcvdpuxds v2, vs0 6029; P9LE-NEXT: blr 6030; 6031; P8BE-LABEL: fromDiffMemVarDConvdtoull: 6032; P8BE: # %bb.0: # %entry 6033; P8BE-NEXT: sldi r4, r4, 3 6034; P8BE-NEXT: add r3, r3, r4 6035; P8BE-NEXT: addi r3, r3, -8 6036; P8BE-NEXT: lxvd2x vs0, 0, r3 6037; P8BE-NEXT: xxswapd vs0, vs0 6038; P8BE-NEXT: xvcvdpuxds v2, vs0 6039; P8BE-NEXT: blr 6040; 6041; P8LE-LABEL: fromDiffMemVarDConvdtoull: 6042; P8LE: # %bb.0: # %entry 6043; P8LE-NEXT: sldi r4, r4, 3 6044; P8LE-NEXT: add r3, r3, r4 6045; P8LE-NEXT: addi r3, r3, -8 6046; P8LE-NEXT: lxvd2x vs0, 0, r3 6047; P8LE-NEXT: xvcvdpuxds v2, vs0 6048; P8LE-NEXT: blr 6049entry: 6050 %idxprom = sext i32 %elem to i64 6051 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 6052 %0 = load double, double* %arrayidx, align 8 6053 %conv = fptoui double %0 to i64 6054 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6055 %sub = add nsw i32 %elem, -1 6056 %idxprom1 = sext i32 %sub to i64 6057 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 6058 %1 = load double, double* %arrayidx2, align 8 6059 %conv3 = fptoui double %1 to i64 6060 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 6061 ret <2 x i64> %vecinit4 6062} 6063 6064define <2 x i64> @spltRegValConvdtoull(double %val) { 6065; P9BE-LABEL: spltRegValConvdtoull: 6066; P9BE: # %bb.0: # %entry 6067; P9BE-NEXT: xscvdpuxds f0, f1 6068; P9BE-NEXT: xxspltd v2, vs0, 0 6069; P9BE-NEXT: blr 6070; 6071; P9LE-LABEL: spltRegValConvdtoull: 6072; P9LE: # %bb.0: # %entry 6073; P9LE-NEXT: xscvdpuxds f0, f1 6074; P9LE-NEXT: xxspltd v2, vs0, 0 6075; P9LE-NEXT: blr 6076; 6077; P8BE-LABEL: spltRegValConvdtoull: 6078; P8BE: # %bb.0: # %entry 6079; P8BE-NEXT: xscvdpuxds f0, f1 6080; P8BE-NEXT: xxspltd v2, vs0, 0 6081; P8BE-NEXT: blr 6082; 6083; P8LE-LABEL: spltRegValConvdtoull: 6084; P8LE: # %bb.0: # %entry 6085; P8LE-NEXT: xscvdpuxds f0, f1 6086; P8LE-NEXT: xxspltd v2, vs0, 0 6087; P8LE-NEXT: blr 6088entry: 6089 %conv = fptoui double %val to i64 6090 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 6091 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 6092 ret <2 x i64> %splat.splat 6093} 6094 6095define <2 x i64> @spltMemValConvdtoull(double* nocapture readonly %ptr) { 6096; P9BE-LABEL: spltMemValConvdtoull: 6097; P9BE: # %bb.0: # %entry 6098; P9BE-NEXT: lxvdsx vs0, 0, r3 6099; P9BE-NEXT: xvcvdpuxds v2, vs0 6100; P9BE-NEXT: blr 6101; 6102; P9LE-LABEL: spltMemValConvdtoull: 6103; P9LE: # %bb.0: # %entry 6104; P9LE-NEXT: lxvdsx vs0, 0, r3 6105; P9LE-NEXT: xvcvdpuxds v2, vs0 6106; P9LE-NEXT: blr 6107; 6108; P8BE-LABEL: spltMemValConvdtoull: 6109; P8BE: # %bb.0: # %entry 6110; P8BE-NEXT: lxvdsx vs0, 0, r3 6111; P8BE-NEXT: xvcvdpuxds v2, vs0 6112; P8BE-NEXT: blr 6113; 6114; P8LE-LABEL: spltMemValConvdtoull: 6115; P8LE: # %bb.0: # %entry 6116; P8LE-NEXT: lxvdsx vs0, 0, r3 6117; P8LE-NEXT: xvcvdpuxds v2, vs0 6118; P8LE-NEXT: blr 6119entry: 6120 %0 = load double, double* %ptr, align 8 6121 %conv = fptoui double %0 to i64 6122 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 6123 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 6124 ret <2 x i64> %splat.splat 6125} 6126 6127; Some additional patterns that come up in real code. 6128define dso_local <2 x double> @sint_to_fp_widen02(<4 x i32> %a) { 6129; P9BE-LABEL: sint_to_fp_widen02: 6130; P9BE: # %bb.0: # %entry 6131; P9BE-NEXT: xvcvsxwdp v2, v2 6132; P9BE-NEXT: blr 6133; 6134; P9LE-LABEL: sint_to_fp_widen02: 6135; P9LE: # %bb.0: # %entry 6136; P9LE-NEXT: xxsldwi vs0, v2, v2, 1 6137; P9LE-NEXT: xvcvsxwdp v2, vs0 6138; P9LE-NEXT: blr 6139; 6140; P8BE-LABEL: sint_to_fp_widen02: 6141; P8BE: # %bb.0: # %entry 6142; P8BE-NEXT: xvcvsxwdp v2, v2 6143; P8BE-NEXT: blr 6144; 6145; P8LE-LABEL: sint_to_fp_widen02: 6146; P8LE: # %bb.0: # %entry 6147; P8LE-NEXT: xxsldwi vs0, v2, v2, 1 6148; P8LE-NEXT: xvcvsxwdp v2, vs0 6149; P8LE-NEXT: blr 6150entry: 6151 %vecext = extractelement <4 x i32> %a, i32 0 6152 %conv = sitofp i32 %vecext to double 6153 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6154 %vecext1 = extractelement <4 x i32> %a, i32 2 6155 %conv2 = sitofp i32 %vecext1 to double 6156 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6157 ret <2 x double> %vecinit3 6158} 6159 6160define dso_local <2 x double> @sint_to_fp_widen13(<4 x i32> %a) { 6161; P9BE-LABEL: sint_to_fp_widen13: 6162; P9BE: # %bb.0: # %entry 6163; P9BE-NEXT: xxsldwi vs0, v2, v2, 1 6164; P9BE-NEXT: xvcvsxwdp v2, vs0 6165; P9BE-NEXT: blr 6166; 6167; P9LE-LABEL: sint_to_fp_widen13: 6168; P9LE: # %bb.0: # %entry 6169; P9LE-NEXT: xvcvsxwdp v2, v2 6170; P9LE-NEXT: blr 6171; 6172; P8BE-LABEL: sint_to_fp_widen13: 6173; P8BE: # %bb.0: # %entry 6174; P8BE-NEXT: xxsldwi vs0, v2, v2, 1 6175; P8BE-NEXT: xvcvsxwdp v2, vs0 6176; P8BE-NEXT: blr 6177; 6178; P8LE-LABEL: sint_to_fp_widen13: 6179; P8LE: # %bb.0: # %entry 6180; P8LE-NEXT: xvcvsxwdp v2, v2 6181; P8LE-NEXT: blr 6182entry: 6183 %vecext = extractelement <4 x i32> %a, i32 1 6184 %conv = sitofp i32 %vecext to double 6185 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6186 %vecext1 = extractelement <4 x i32> %a, i32 3 6187 %conv2 = sitofp i32 %vecext1 to double 6188 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6189 ret <2 x double> %vecinit3 6190} 6191 6192define dso_local <2 x double> @uint_to_fp_widen02(<4 x i32> %a) { 6193; P9BE-LABEL: uint_to_fp_widen02: 6194; P9BE: # %bb.0: # %entry 6195; P9BE-NEXT: xvcvuxwdp v2, v2 6196; P9BE-NEXT: blr 6197; 6198; P9LE-LABEL: uint_to_fp_widen02: 6199; P9LE: # %bb.0: # %entry 6200; P9LE-NEXT: xxsldwi vs0, v2, v2, 1 6201; P9LE-NEXT: xvcvuxwdp v2, vs0 6202; P9LE-NEXT: blr 6203; 6204; P8BE-LABEL: uint_to_fp_widen02: 6205; P8BE: # %bb.0: # %entry 6206; P8BE-NEXT: xvcvuxwdp v2, v2 6207; P8BE-NEXT: blr 6208; 6209; P8LE-LABEL: uint_to_fp_widen02: 6210; P8LE: # %bb.0: # %entry 6211; P8LE-NEXT: xxsldwi vs0, v2, v2, 1 6212; P8LE-NEXT: xvcvuxwdp v2, vs0 6213; P8LE-NEXT: blr 6214entry: 6215 %vecext = extractelement <4 x i32> %a, i32 0 6216 %conv = uitofp i32 %vecext to double 6217 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6218 %vecext1 = extractelement <4 x i32> %a, i32 2 6219 %conv2 = uitofp i32 %vecext1 to double 6220 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6221 ret <2 x double> %vecinit3 6222} 6223 6224define dso_local <2 x double> @uint_to_fp_widen13(<4 x i32> %a) { 6225; P9BE-LABEL: uint_to_fp_widen13: 6226; P9BE: # %bb.0: # %entry 6227; P9BE-NEXT: xxsldwi vs0, v2, v2, 1 6228; P9BE-NEXT: xvcvuxwdp v2, vs0 6229; P9BE-NEXT: blr 6230; 6231; P9LE-LABEL: uint_to_fp_widen13: 6232; P9LE: # %bb.0: # %entry 6233; P9LE-NEXT: xvcvuxwdp v2, v2 6234; P9LE-NEXT: blr 6235; 6236; P8BE-LABEL: uint_to_fp_widen13: 6237; P8BE: # %bb.0: # %entry 6238; P8BE-NEXT: xxsldwi vs0, v2, v2, 1 6239; P8BE-NEXT: xvcvuxwdp v2, vs0 6240; P8BE-NEXT: blr 6241; 6242; P8LE-LABEL: uint_to_fp_widen13: 6243; P8LE: # %bb.0: # %entry 6244; P8LE-NEXT: xvcvuxwdp v2, v2 6245; P8LE-NEXT: blr 6246entry: 6247 %vecext = extractelement <4 x i32> %a, i32 1 6248 %conv = uitofp i32 %vecext to double 6249 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6250 %vecext1 = extractelement <4 x i32> %a, i32 3 6251 %conv2 = uitofp i32 %vecext1 to double 6252 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6253 ret <2 x double> %vecinit3 6254} 6255 6256define dso_local <2 x double> @fp_extend01(<4 x float> %a) { 6257; P9BE-LABEL: fp_extend01: 6258; P9BE: # %bb.0: # %entry 6259; P9BE-NEXT: xxmrghw vs0, v2, v2 6260; P9BE-NEXT: xvcvspdp v2, vs0 6261; P9BE-NEXT: blr 6262; 6263; P9LE-LABEL: fp_extend01: 6264; P9LE: # %bb.0: # %entry 6265; P9LE-NEXT: xxmrglw vs0, v2, v2 6266; P9LE-NEXT: xvcvspdp v2, vs0 6267; P9LE-NEXT: blr 6268; 6269; P8BE-LABEL: fp_extend01: 6270; P8BE: # %bb.0: # %entry 6271; P8BE-NEXT: xxmrghw vs0, v2, v2 6272; P8BE-NEXT: xvcvspdp v2, vs0 6273; P8BE-NEXT: blr 6274; 6275; P8LE-LABEL: fp_extend01: 6276; P8LE: # %bb.0: # %entry 6277; P8LE-NEXT: xxmrglw vs0, v2, v2 6278; P8LE-NEXT: xvcvspdp v2, vs0 6279; P8LE-NEXT: blr 6280entry: 6281 %vecext = extractelement <4 x float> %a, i32 0 6282 %conv = fpext float %vecext to double 6283 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6284 %vecext1 = extractelement <4 x float> %a, i32 1 6285 %conv2 = fpext float %vecext1 to double 6286 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6287 ret <2 x double> %vecinit3 6288} 6289 6290define dso_local <2 x double> @fp_extend10(<4 x float> %a) { 6291; P9BE-LABEL: fp_extend10: 6292; P9BE: # %bb.0: # %entry 6293; P9BE-NEXT: xxmrghw vs0, v2, v2 6294; P9BE-NEXT: xvcvspdp vs0, vs0 6295; P9BE-NEXT: xxswapd v2, vs0 6296; P9BE-NEXT: blr 6297; 6298; P9LE-LABEL: fp_extend10: 6299; P9LE: # %bb.0: # %entry 6300; P9LE-NEXT: xxmrglw vs0, v2, v2 6301; P9LE-NEXT: xvcvspdp vs0, vs0 6302; P9LE-NEXT: xxswapd v2, vs0 6303; P9LE-NEXT: blr 6304; 6305; P8BE-LABEL: fp_extend10: 6306; P8BE: # %bb.0: # %entry 6307; P8BE-NEXT: xxmrghw vs0, v2, v2 6308; P8BE-NEXT: xvcvspdp vs0, vs0 6309; P8BE-NEXT: xxswapd v2, vs0 6310; P8BE-NEXT: blr 6311; 6312; P8LE-LABEL: fp_extend10: 6313; P8LE: # %bb.0: # %entry 6314; P8LE-NEXT: xxmrglw vs0, v2, v2 6315; P8LE-NEXT: xvcvspdp vs0, vs0 6316; P8LE-NEXT: xxswapd v2, vs0 6317; P8LE-NEXT: blr 6318entry: 6319 %vecext = extractelement <4 x float> %a, i32 1 6320 %conv = fpext float %vecext to double 6321 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6322 %vecext1 = extractelement <4 x float> %a, i32 0 6323 %conv2 = fpext float %vecext1 to double 6324 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6325 ret <2 x double> %vecinit3 6326} 6327 6328define dso_local <2 x double> @fp_extend02(<4 x float> %a) { 6329; P9BE-LABEL: fp_extend02: 6330; P9BE: # %bb.0: # %entry 6331; P9BE-NEXT: xvcvspdp v2, v2 6332; P9BE-NEXT: blr 6333; 6334; P9LE-LABEL: fp_extend02: 6335; P9LE: # %bb.0: # %entry 6336; P9LE-NEXT: xxsldwi vs0, v2, v2, 1 6337; P9LE-NEXT: xvcvspdp v2, vs0 6338; P9LE-NEXT: blr 6339; 6340; P8BE-LABEL: fp_extend02: 6341; P8BE: # %bb.0: # %entry 6342; P8BE-NEXT: xvcvspdp v2, v2 6343; P8BE-NEXT: blr 6344; 6345; P8LE-LABEL: fp_extend02: 6346; P8LE: # %bb.0: # %entry 6347; P8LE-NEXT: xxsldwi vs0, v2, v2, 1 6348; P8LE-NEXT: xvcvspdp v2, vs0 6349; P8LE-NEXT: blr 6350entry: 6351 %vecext = extractelement <4 x float> %a, i32 0 6352 %conv = fpext float %vecext to double 6353 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6354 %vecext1 = extractelement <4 x float> %a, i32 2 6355 %conv2 = fpext float %vecext1 to double 6356 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6357 ret <2 x double> %vecinit3 6358} 6359 6360define dso_local <2 x double> @fp_extend13(<4 x float> %a) { 6361; P9BE-LABEL: fp_extend13: 6362; P9BE: # %bb.0: # %entry 6363; P9BE-NEXT: xxsldwi vs0, v2, v2, 3 6364; P9BE-NEXT: xvcvspdp v2, vs0 6365; P9BE-NEXT: blr 6366; 6367; P9LE-LABEL: fp_extend13: 6368; P9LE: # %bb.0: # %entry 6369; P9LE-NEXT: xvcvspdp v2, v2 6370; P9LE-NEXT: blr 6371; 6372; P8BE-LABEL: fp_extend13: 6373; P8BE: # %bb.0: # %entry 6374; P8BE-NEXT: xxsldwi vs0, v2, v2, 3 6375; P8BE-NEXT: xvcvspdp v2, vs0 6376; P8BE-NEXT: blr 6377; 6378; P8LE-LABEL: fp_extend13: 6379; P8LE: # %bb.0: # %entry 6380; P8LE-NEXT: xvcvspdp v2, v2 6381; P8LE-NEXT: blr 6382entry: 6383 %vecext = extractelement <4 x float> %a, i32 1 6384 %conv = fpext float %vecext to double 6385 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6386 %vecext1 = extractelement <4 x float> %a, i32 3 6387 %conv2 = fpext float %vecext1 to double 6388 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6389 ret <2 x double> %vecinit3 6390} 6391 6392define dso_local <2 x double> @fp_extend23(<4 x float> %a) { 6393; P9BE-LABEL: fp_extend23: 6394; P9BE: # %bb.0: # %entry 6395; P9BE-NEXT: xxmrglw vs0, v2, v2 6396; P9BE-NEXT: xvcvspdp v2, vs0 6397; P9BE-NEXT: blr 6398; 6399; P9LE-LABEL: fp_extend23: 6400; P9LE: # %bb.0: # %entry 6401; P9LE-NEXT: xxmrghw vs0, v2, v2 6402; P9LE-NEXT: xvcvspdp v2, vs0 6403; P9LE-NEXT: blr 6404; 6405; P8BE-LABEL: fp_extend23: 6406; P8BE: # %bb.0: # %entry 6407; P8BE-NEXT: xxmrglw vs0, v2, v2 6408; P8BE-NEXT: xvcvspdp v2, vs0 6409; P8BE-NEXT: blr 6410; 6411; P8LE-LABEL: fp_extend23: 6412; P8LE: # %bb.0: # %entry 6413; P8LE-NEXT: xxmrghw vs0, v2, v2 6414; P8LE-NEXT: xvcvspdp v2, vs0 6415; P8LE-NEXT: blr 6416entry: 6417 %vecext = extractelement <4 x float> %a, i32 2 6418 %conv = fpext float %vecext to double 6419 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6420 %vecext1 = extractelement <4 x float> %a, i32 3 6421 %conv2 = fpext float %vecext1 to double 6422 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6423 ret <2 x double> %vecinit3 6424} 6425 6426define dso_local <2 x double> @fp_extend32(<4 x float> %a) { 6427; P9BE-LABEL: fp_extend32: 6428; P9BE: # %bb.0: # %entry 6429; P9BE-NEXT: xxmrglw vs0, v2, v2 6430; P9BE-NEXT: xvcvspdp vs0, vs0 6431; P9BE-NEXT: xxswapd v2, vs0 6432; P9BE-NEXT: blr 6433; 6434; P9LE-LABEL: fp_extend32: 6435; P9LE: # %bb.0: # %entry 6436; P9LE-NEXT: xxmrghw vs0, v2, v2 6437; P9LE-NEXT: xvcvspdp vs0, vs0 6438; P9LE-NEXT: xxswapd v2, vs0 6439; P9LE-NEXT: blr 6440; 6441; P8BE-LABEL: fp_extend32: 6442; P8BE: # %bb.0: # %entry 6443; P8BE-NEXT: xxmrglw vs0, v2, v2 6444; P8BE-NEXT: xvcvspdp vs0, vs0 6445; P8BE-NEXT: xxswapd v2, vs0 6446; P8BE-NEXT: blr 6447; 6448; P8LE-LABEL: fp_extend32: 6449; P8LE: # %bb.0: # %entry 6450; P8LE-NEXT: xxmrghw vs0, v2, v2 6451; P8LE-NEXT: xvcvspdp vs0, vs0 6452; P8LE-NEXT: xxswapd v2, vs0 6453; P8LE-NEXT: blr 6454entry: 6455 %vecext = extractelement <4 x float> %a, i32 3 6456 %conv = fpext float %vecext to double 6457 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6458 %vecext1 = extractelement <4 x float> %a, i32 2 6459 %conv2 = fpext float %vecext1 to double 6460 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6461 ret <2 x double> %vecinit3 6462} 6463 6464define dso_local <2 x double> @fp_extend_two00(<4 x float> %a, <4 x float> %b) { 6465; P9BE-LABEL: fp_extend_two00: 6466; P9BE: # %bb.0: # %entry 6467; P9BE-NEXT: xxmrghd vs0, v2, v3 6468; P9BE-NEXT: xvcvspdp v2, vs0 6469; P9BE-NEXT: blr 6470; 6471; P9LE-LABEL: fp_extend_two00: 6472; P9LE: # %bb.0: # %entry 6473; P9LE-NEXT: xxmrgld vs0, v3, v2 6474; P9LE-NEXT: xxsldwi vs0, vs0, vs0, 1 6475; P9LE-NEXT: xvcvspdp v2, vs0 6476; P9LE-NEXT: blr 6477; 6478; P8BE-LABEL: fp_extend_two00: 6479; P8BE: # %bb.0: # %entry 6480; P8BE-NEXT: xxmrghd vs0, v2, v3 6481; P8BE-NEXT: xvcvspdp v2, vs0 6482; P8BE-NEXT: blr 6483; 6484; P8LE-LABEL: fp_extend_two00: 6485; P8LE: # %bb.0: # %entry 6486; P8LE-NEXT: xxmrgld vs0, v3, v2 6487; P8LE-NEXT: xxsldwi vs0, vs0, vs0, 1 6488; P8LE-NEXT: xvcvspdp v2, vs0 6489; P8LE-NEXT: blr 6490entry: 6491 %vecext = extractelement <4 x float> %a, i32 0 6492 %conv = fpext float %vecext to double 6493 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6494 %vecext1 = extractelement <4 x float> %b, i32 0 6495 %conv2 = fpext float %vecext1 to double 6496 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6497 ret <2 x double> %vecinit3 6498} 6499 6500define dso_local <2 x double> @fp_extend_two33(<4 x float> %a, <4 x float> %b) { 6501; P9BE-LABEL: fp_extend_two33: 6502; P9BE: # %bb.0: # %entry 6503; P9BE-NEXT: xxmrgld vs0, v2, v3 6504; P9BE-NEXT: xxsldwi vs0, vs0, vs0, 1 6505; P9BE-NEXT: xvcvspdp v2, vs0 6506; P9BE-NEXT: blr 6507; 6508; P9LE-LABEL: fp_extend_two33: 6509; P9LE: # %bb.0: # %entry 6510; P9LE-NEXT: xxmrghd vs0, v3, v2 6511; P9LE-NEXT: xvcvspdp v2, vs0 6512; P9LE-NEXT: blr 6513; 6514; P8BE-LABEL: fp_extend_two33: 6515; P8BE: # %bb.0: # %entry 6516; P8BE-NEXT: xxmrgld vs0, v2, v3 6517; P8BE-NEXT: xxsldwi vs0, vs0, vs0, 1 6518; P8BE-NEXT: xvcvspdp v2, vs0 6519; P8BE-NEXT: blr 6520; 6521; P8LE-LABEL: fp_extend_two33: 6522; P8LE: # %bb.0: # %entry 6523; P8LE-NEXT: xxmrghd vs0, v3, v2 6524; P8LE-NEXT: xvcvspdp v2, vs0 6525; P8LE-NEXT: blr 6526entry: 6527 %vecext = extractelement <4 x float> %a, i32 3 6528 %conv = fpext float %vecext to double 6529 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6530 %vecext1 = extractelement <4 x float> %b, i32 3 6531 %conv2 = fpext float %vecext1 to double 6532 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6533 ret <2 x double> %vecinit3 6534} 6535 6536define dso_local <2 x i64> @test_xvcvspsxds13(<4 x float> %a) local_unnamed_addr { 6537; P9BE-LABEL: test_xvcvspsxds13: 6538; P9BE: # %bb.0: # %entry 6539; P9BE-NEXT: xxsldwi vs0, v2, v2, 1 6540; P9BE-NEXT: xvcvspsxds v2, vs0 6541; P9BE-NEXT: blr 6542; 6543; P9LE-LABEL: test_xvcvspsxds13: 6544; P9LE: # %bb.0: # %entry 6545; P9LE-NEXT: xvcvspsxds v2, v2 6546; P9LE-NEXT: blr 6547; 6548; P8BE-LABEL: test_xvcvspsxds13: 6549; P8BE: # %bb.0: # %entry 6550; P8BE-NEXT: xxsldwi vs0, v2, v2, 1 6551; P8BE-NEXT: xvcvspsxds v2, vs0 6552; P8BE-NEXT: blr 6553; 6554; P8LE-LABEL: test_xvcvspsxds13: 6555; P8LE: # %bb.0: # %entry 6556; P8LE-NEXT: xvcvspsxds v2, v2 6557; P8LE-NEXT: blr 6558entry: 6559 %vecext = extractelement <4 x float> %a, i32 1 6560 %conv = fptosi float %vecext to i64 6561 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6562 %vecext1 = extractelement <4 x float> %a, i32 3 6563 %conv2 = fptosi float %vecext1 to i64 6564 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 6565 ret <2 x i64> %vecinit3 6566} 6567 6568define dso_local <2 x i64> @test_xvcvspuxds13(<4 x float> %a) local_unnamed_addr { 6569; P9BE-LABEL: test_xvcvspuxds13: 6570; P9BE: # %bb.0: # %entry 6571; P9BE-NEXT: xxsldwi vs0, v2, v2, 1 6572; P9BE-NEXT: xvcvspuxds v2, vs0 6573; P9BE-NEXT: blr 6574; 6575; P9LE-LABEL: test_xvcvspuxds13: 6576; P9LE: # %bb.0: # %entry 6577; P9LE-NEXT: xvcvspuxds v2, v2 6578; P9LE-NEXT: blr 6579; 6580; P8BE-LABEL: test_xvcvspuxds13: 6581; P8BE: # %bb.0: # %entry 6582; P8BE-NEXT: xxsldwi vs0, v2, v2, 1 6583; P8BE-NEXT: xvcvspuxds v2, vs0 6584; P8BE-NEXT: blr 6585; 6586; P8LE-LABEL: test_xvcvspuxds13: 6587; P8LE: # %bb.0: # %entry 6588; P8LE-NEXT: xvcvspuxds v2, v2 6589; P8LE-NEXT: blr 6590entry: 6591 %vecext = extractelement <4 x float> %a, i32 1 6592 %conv = fptoui float %vecext to i64 6593 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6594 %vecext1 = extractelement <4 x float> %a, i32 3 6595 %conv2 = fptoui float %vecext1 to i64 6596 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 6597 ret <2 x i64> %vecinit3 6598} 6599 6600define dso_local <2 x i64> @test_xvcvspsxds02(<4 x float> %a) local_unnamed_addr { 6601; P9BE-LABEL: test_xvcvspsxds02: 6602; P9BE: # %bb.0: # %entry 6603; P9BE-NEXT: xvcvspsxds v2, v2 6604; P9BE-NEXT: blr 6605; 6606; P9LE-LABEL: test_xvcvspsxds02: 6607; P9LE: # %bb.0: # %entry 6608; P9LE-NEXT: xxsldwi vs0, v2, v2, 1 6609; P9LE-NEXT: xvcvspsxds v2, vs0 6610; P9LE-NEXT: blr 6611; 6612; P8BE-LABEL: test_xvcvspsxds02: 6613; P8BE: # %bb.0: # %entry 6614; P8BE-NEXT: xvcvspsxds v2, v2 6615; P8BE-NEXT: blr 6616; 6617; P8LE-LABEL: test_xvcvspsxds02: 6618; P8LE: # %bb.0: # %entry 6619; P8LE-NEXT: xxsldwi vs0, v2, v2, 1 6620; P8LE-NEXT: xvcvspsxds v2, vs0 6621; P8LE-NEXT: blr 6622entry: 6623 %vecext = extractelement <4 x float> %a, i32 0 6624 %conv = fptosi float %vecext to i64 6625 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6626 %vecext1 = extractelement <4 x float> %a, i32 2 6627 %conv2 = fptosi float %vecext1 to i64 6628 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 6629 ret <2 x i64> %vecinit3 6630} 6631 6632define dso_local <2 x i64> @test_xvcvspuxds02(<4 x float> %a) local_unnamed_addr { 6633; P9BE-LABEL: test_xvcvspuxds02: 6634; P9BE: # %bb.0: # %entry 6635; P9BE-NEXT: xvcvspuxds v2, v2 6636; P9BE-NEXT: blr 6637; 6638; P9LE-LABEL: test_xvcvspuxds02: 6639; P9LE: # %bb.0: # %entry 6640; P9LE-NEXT: xxsldwi vs0, v2, v2, 1 6641; P9LE-NEXT: xvcvspuxds v2, vs0 6642; P9LE-NEXT: blr 6643; 6644; P8BE-LABEL: test_xvcvspuxds02: 6645; P8BE: # %bb.0: # %entry 6646; P8BE-NEXT: xvcvspuxds v2, v2 6647; P8BE-NEXT: blr 6648; 6649; P8LE-LABEL: test_xvcvspuxds02: 6650; P8LE: # %bb.0: # %entry 6651; P8LE-NEXT: xxsldwi vs0, v2, v2, 1 6652; P8LE-NEXT: xvcvspuxds v2, vs0 6653; P8LE-NEXT: blr 6654entry: 6655 %vecext = extractelement <4 x float> %a, i32 0 6656 %conv = fptoui float %vecext to i64 6657 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6658 %vecext1 = extractelement <4 x float> %a, i32 2 6659 %conv2 = fptoui float %vecext1 to i64 6660 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 6661 ret <2 x i64> %vecinit3 6662} 6663