1; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 2; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \ 3; RUN: -check-prefix=P9BE -implicit-check-not frsp 4; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 5; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \ 6; RUN: -check-prefix=P9LE -implicit-check-not frsp 7; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 8; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \ 9; RUN: -check-prefix=P8BE -implicit-check-not frsp 10; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 11; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \ 12; RUN: -check-prefix=P8LE -implicit-check-not frsp 13 14; This test case comes from the following C test case (included as it may be 15; slightly more readable than the LLVM IR. 16 17;/* This test case provides various ways of building vectors to ensure we 18; produce optimal code for all cases. The cases are (for each type): 19; - All zeros 20; - All ones 21; - Splat of a constant 22; - From different values already in registers 23; - From different constants 24; - From different values in memory 25; - Splat of a value in register 26; - Splat of a value in memory 27; - Inserting element into existing vector 28; - Inserting element from existing vector into existing vector 29; 30; With conversions (float <-> int) 31; - Splat of a constant 32; - From different values already in registers 33; - From different constants 34; - From different values in memory 35; - Splat of a value in register 36; - Splat of a value in memory 37; - Inserting element into existing vector 38; - Inserting element from existing vector into existing vector 39;*/ 40; 41;/*=================================== int ===================================*/ 42;// P8: xxlxor // 43;// P9: xxlxor // 44;vector int allZeroi() { // 45; return (vector int)0; // 46;} // 47;// P8: vspltisb -1 // 48;// P9: xxspltisb 255 // 49;vector int allOnei() { // 50; return (vector int)-1; // 51;} // 52;// P8: vspltisw 1 // 53;// P9: vspltisw 1 // 54;vector int spltConst1i() { // 55; return (vector int)1; // 56;} // 57;// P8: vspltisw -15; vsrw // 58;// P9: vspltisw -15; vsrw // 59;vector int spltConst16ki() { // 60; return (vector int)((1<<15) - 1); // 61;} // 62;// P8: vspltisw -16; vsrw // 63;// P9: vspltisw -16; vsrw // 64;vector int spltConst32ki() { // 65; return (vector int)((1<<16) - 1); // 66;} // 67;// P8: 4 x mtvsrwz, 2 x xxmrgh, vmrgow // 68;// P9: 2 x mtvsrdd, vmrgow // 69;vector int fromRegsi(int a, int b, int c, int d) { // 70; return (vector int){ a, b, c, d }; // 71;} // 72;// P8: lxvd2x, xxswapd // 73;// P9: lxvx (or even lxv) // 74;vector int fromDiffConstsi() { // 75; return (vector int) { 242, -113, 889, 19 }; // 76;} // 77;// P8: lxvd2x, xxswapd // 78;// P9: lxvx // 79;vector int fromDiffMemConsAi(int *arr) { // 80; return (vector int) { arr[0], arr[1], arr[2], arr[3] }; // 81;} // 82;// P8: 2 x lxvd2x, 2 x xxswapd, vperm // 83;// P9: 2 x lxvx, vperm // 84;vector int fromDiffMemConsDi(int *arr) { // 85; return (vector int) { arr[3], arr[2], arr[1], arr[0] }; // 86;} // 87;// P8: sldi 2, lxvd2x, xxswapd // 88;// P9: sldi 2, lxvx // 89;vector int fromDiffMemVarAi(int *arr, int elem) { // 90; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 91;} // 92;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm // 93;// P9: sldi 2, 2 x lxvx, vperm // 94;vector int fromDiffMemVarDi(int *arr, int elem) { // 95; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 96;} // 97;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 98;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow // 99;vector int fromRandMemConsi(int *arr) { // 100; return (vector int) { arr[4], arr[18], arr[2], arr[88] }; // 101;} // 102;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 103;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow // 104;vector int fromRandMemVari(int *arr, int elem) { // 105; return (vector int) { arr[elem+4], arr[elem+1], arr[elem+2], arr[elem+8] };// 106;} // 107;// P8: mtvsrwz, xxspltw // 108;// P9: mtvsrws // 109;vector int spltRegVali(int val) { // 110; return (vector int) val; // 111;} // 112;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 113;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 114;vector int spltMemVali(int *ptr) { // 115; return (vector int)*ptr; // 116;} // 117;// P8: vspltisw // 118;// P9: vspltisw // 119;vector int spltCnstConvftoi() { // 120; return (vector int) 4.74f; // 121;} // 122;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 123;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 124;vector int fromRegsConvftoi(float a, float b, float c, float d) { // 125; return (vector int) { a, b, c, d }; // 126;} // 127;// P8: lxvd2x, xxswapd // 128;// P9: lxvx (even lxv) // 129;vector int fromDiffConstsConvftoi() { // 130; return (vector int) { 24.46f, 234.f, 988.19f, 422.39f }; // 131;} // 132;// P8: lxvd2x, xxswapd, xvcvspsxws // 133;// P9: lxvx, xvcvspsxws // 134;vector int fromDiffMemConsAConvftoi(float *ptr) { // 135; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 136;} // 137;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspsxws // 138;// P9: 2 x lxvx, vperm, xvcvspsxws // 139;vector int fromDiffMemConsDConvftoi(float *ptr) { // 140; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 141;} // 142;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 143;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 144;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 145;// sldi 2, load, xvcvspuxws // 146;vector int fromDiffMemVarAConvftoi(float *arr, int elem) { // 147; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 148;} // 149;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 150;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 151;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 152;// sldi 2, 2 x load, vperm, xvcvspuxws // 153;vector int fromDiffMemVarDConvftoi(float *arr, int elem) { // 154; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 155;} // 156;// P8: xscvdpsxws, xxspltw // 157;// P9: xscvdpsxws, xxspltw // 158;vector int spltRegValConvftoi(float val) { // 159; return (vector int) val; // 160;} // 161;// P8: lxsspx, xscvdpsxws, xxspltw // 162;// P9: lxvwsx, xvcvspsxws // 163;vector int spltMemValConvftoi(float *ptr) { // 164; return (vector int)*ptr; // 165;} // 166;// P8: vspltisw // 167;// P9: vspltisw // 168;vector int spltCnstConvdtoi() { // 169; return (vector int) 4.74; // 170;} // 171;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 172;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 173;vector int fromRegsConvdtoi(double a, double b, double c, double d) { // 174; return (vector int) { a, b, c, d }; // 175;} // 176;// P8: lxvd2x, xxswapd // 177;// P9: lxvx (even lxv) // 178;vector int fromDiffConstsConvdtoi() { // 179; return (vector int) { 24.46, 234., 988.19, 422.39 }; // 180;} // 181;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew // 182;// P9: 2 x lxvx, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew // 183;vector int fromDiffMemConsAConvdtoi(double *ptr) { // 184; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 185;} // 186;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 187;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 188;vector int fromDiffMemConsDConvdtoi(double *ptr) { // 189; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 190;} // 191;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 192;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 193;vector int fromDiffMemVarAConvdtoi(double *arr, int elem) { // 194; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 195;} // 196;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 197;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 198;vector int fromDiffMemVarDConvdtoi(double *arr, int elem) { // 199; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 200;} // 201;// P8: xscvdpsxws, xxspltw // 202;// P9: xscvdpsxws, xxspltw // 203;vector int spltRegValConvdtoi(double val) { // 204; return (vector int) val; // 205;} // 206;// P8: lxsdx, xscvdpsxws, xxspltw // 207;// P9: lxssp, xscvdpsxws, xxspltw // 208;vector int spltMemValConvdtoi(double *ptr) { // 209; return (vector int)*ptr; // 210;} // 211;/*=================================== int ===================================*/ 212;/*=============================== unsigned int ==============================*/ 213;// P8: xxlxor // 214;// P9: xxlxor // 215;vector unsigned int allZeroui() { // 216; return (vector unsigned int)0; // 217;} // 218;// P8: vspltisb -1 // 219;// P9: xxspltisb 255 // 220;vector unsigned int allOneui() { // 221; return (vector unsigned int)-1; // 222;} // 223;// P8: vspltisw 1 // 224;// P9: vspltisw 1 // 225;vector unsigned int spltConst1ui() { // 226; return (vector unsigned int)1; // 227;} // 228;// P8: vspltisw -15; vsrw // 229;// P9: vspltisw -15; vsrw // 230;vector unsigned int spltConst16kui() { // 231; return (vector unsigned int)((1<<15) - 1); // 232;} // 233;// P8: vspltisw -16; vsrw // 234;// P9: vspltisw -16; vsrw // 235;vector unsigned int spltConst32kui() { // 236; return (vector unsigned int)((1<<16) - 1); // 237;} // 238;// P8: 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 239;// P9: 2 x mtvsrdd, vmrgow // 240;vector unsigned int fromRegsui(unsigned int a, unsigned int b, // 241; unsigned int c, unsigned int d) { // 242; return (vector unsigned int){ a, b, c, d }; // 243;} // 244;// P8: lxvd2x, xxswapd // 245;// P9: lxvx (or even lxv) // 246;vector unsigned int fromDiffConstsui() { // 247; return (vector unsigned int) { 242, -113, 889, 19 }; // 248;} // 249;// P8: lxvd2x, xxswapd // 250;// P9: lxvx // 251;vector unsigned int fromDiffMemConsAui(unsigned int *arr) { // 252; return (vector unsigned int) { arr[0], arr[1], arr[2], arr[3] }; // 253;} // 254;// P8: 2 x lxvd2x, 2 x xxswapd, vperm // 255;// P9: 2 x lxvx, vperm // 256;vector unsigned int fromDiffMemConsDui(unsigned int *arr) { // 257; return (vector unsigned int) { arr[3], arr[2], arr[1], arr[0] }; // 258;} // 259;// P8: sldi 2, lxvd2x, xxswapd // 260;// P9: sldi 2, lxvx // 261;vector unsigned int fromDiffMemVarAui(unsigned int *arr, int elem) { // 262; return (vector unsigned int) { arr[elem], arr[elem+1], // 263; arr[elem+2], arr[elem+3] }; // 264;} // 265;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm // 266;// P9: sldi 2, 2 x lxvx, vperm // 267;vector unsigned int fromDiffMemVarDui(unsigned int *arr, int elem) { // 268; return (vector unsigned int) { arr[elem], arr[elem-1], // 269; arr[elem-2], arr[elem-3] }; // 270;} // 271;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 272;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow // 273;vector unsigned int fromRandMemConsui(unsigned int *arr) { // 274; return (vector unsigned int) { arr[4], arr[18], arr[2], arr[88] }; // 275;} // 276;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 277;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow // 278;vector unsigned int fromRandMemVarui(unsigned int *arr, int elem) { // 279; return (vector unsigned int) { arr[elem+4], arr[elem+1], // 280; arr[elem+2], arr[elem+8] }; // 281;} // 282;// P8: mtvsrwz, xxspltw // 283;// P9: mtvsrws // 284;vector unsigned int spltRegValui(unsigned int val) { // 285; return (vector unsigned int) val; // 286;} // 287;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 288;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 289;vector unsigned int spltMemValui(unsigned int *ptr) { // 290; return (vector unsigned int)*ptr; // 291;} // 292;// P8: vspltisw // 293;// P9: vspltisw // 294;vector unsigned int spltCnstConvftoui() { // 295; return (vector unsigned int) 4.74f; // 296;} // 297;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 298;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 299;vector unsigned int fromRegsConvftoui(float a, float b, float c, float d) { // 300; return (vector unsigned int) { a, b, c, d }; // 301;} // 302;// P8: lxvd2x, xxswapd // 303;// P9: lxvx (even lxv) // 304;vector unsigned int fromDiffConstsConvftoui() { // 305; return (vector unsigned int) { 24.46f, 234.f, 988.19f, 422.39f }; // 306;} // 307;// P8: lxvd2x, xxswapd, xvcvspuxws // 308;// P9: lxvx, xvcvspuxws // 309;vector unsigned int fromDiffMemConsAConvftoui(float *ptr) { // 310; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 311;} // 312;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspuxws // 313;// P9: 2 x lxvx, vperm, xvcvspuxws // 314;vector unsigned int fromDiffMemConsDConvftoui(float *ptr) { // 315; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 316;} // 317;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 318;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 319;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 320;// sldi 2, load, xvcvspuxws // 321;vector unsigned int fromDiffMemVarAConvftoui(float *arr, int elem) { // 322; return (vector unsigned int) { arr[elem], arr[elem+1], // 323; arr[elem+2], arr[elem+3] }; // 324;} // 325;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 326;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 327;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 328;// sldi 2, 2 x load, vperm, xvcvspuxws // 329;vector unsigned int fromDiffMemVarDConvftoui(float *arr, int elem) { // 330; return (vector unsigned int) { arr[elem], arr[elem-1], // 331; arr[elem-2], arr[elem-3] }; // 332;} // 333;// P8: xscvdpuxws, xxspltw // 334;// P9: xscvdpuxws, xxspltw // 335;vector unsigned int spltRegValConvftoui(float val) { // 336; return (vector unsigned int) val; // 337;} // 338;// P8: lxsspx, xscvdpuxws, xxspltw // 339;// P9: lxvwsx, xvcvspuxws // 340;vector unsigned int spltMemValConvftoui(float *ptr) { // 341; return (vector unsigned int)*ptr; // 342;} // 343;// P8: vspltisw // 344;// P9: vspltisw // 345;vector unsigned int spltCnstConvdtoui() { // 346; return (vector unsigned int) 4.74; // 347;} // 348;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 349;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 350;vector unsigned int fromRegsConvdtoui(double a, double b, // 351; double c, double d) { // 352; return (vector unsigned int) { a, b, c, d }; // 353;} // 354;// P8: lxvd2x, xxswapd // 355;// P9: lxvx (even lxv) // 356;vector unsigned int fromDiffConstsConvdtoui() { // 357; return (vector unsigned int) { 24.46, 234., 988.19, 422.39 }; // 358;} // 359;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew // 360;// P9: 2 x lxvx, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew // 361;vector unsigned int fromDiffMemConsAConvdtoui(double *ptr) { // 362; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 363;} // 364;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 365;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 366;vector unsigned int fromDiffMemConsDConvdtoui(double *ptr) { // 367; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 368;} // 369;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 370;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 371;vector unsigned int fromDiffMemVarAConvdtoui(double *arr, int elem) { // 372; return (vector unsigned int) { arr[elem], arr[elem+1], // 373; arr[elem+2], arr[elem+3] }; // 374;} // 375;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 376;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 377;vector unsigned int fromDiffMemVarDConvdtoui(double *arr, int elem) { // 378; return (vector unsigned int) { arr[elem], arr[elem-1], // 379; arr[elem-2], arr[elem-3] }; // 380;} // 381;// P8: xscvdpuxws, xxspltw // 382;// P9: xscvdpuxws, xxspltw // 383;vector unsigned int spltRegValConvdtoui(double val) { // 384; return (vector unsigned int) val; // 385;} // 386;// P8: lxsspx, xscvdpuxws, xxspltw // 387;// P9: lfd, xscvdpuxws, xxspltw // 388;vector unsigned int spltMemValConvdtoui(double *ptr) { // 389; return (vector unsigned int)*ptr; // 390;} // 391;/*=============================== unsigned int ==============================*/ 392;/*=============================== long long =================================*/ 393;// P8: xxlxor // 394;// P9: xxlxor // 395;vector long long allZeroll() { // 396; return (vector long long)0; // 397;} // 398;// P8: vspltisb -1 // 399;// P9: xxspltisb 255 // 400;vector long long allOnell() { // 401; return (vector long long)-1; // 402;} // 403;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 404;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 405;vector long long spltConst1ll() { // 406; return (vector long long)1; // 407;} // 408;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 409;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 410;vector long long spltConst16kll() { // 411; return (vector long long)((1<<15) - 1); // 412;} // 413;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 414;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 415;vector long long spltConst32kll() { // 416; return (vector long long)((1<<16) - 1); // 417;} // 418;// P8: 2 x mtvsrd, xxmrghd // 419;// P9: mtvsrdd // 420;vector long long fromRegsll(long long a, long long b) { // 421; return (vector long long){ a, b }; // 422;} // 423;// P8: lxvd2x, xxswapd // 424;// P9: lxvx (or even lxv) // 425;vector long long fromDiffConstsll() { // 426; return (vector long long) { 242, -113 }; // 427;} // 428;// P8: lxvd2x, xxswapd // 429;// P9: lxvx // 430;vector long long fromDiffMemConsAll(long long *arr) { // 431; return (vector long long) { arr[0], arr[1] }; // 432;} // 433;// P8: lxvd2x // 434;// P9: lxvx, xxswapd (maybe just use lxvd2x) // 435;vector long long fromDiffMemConsDll(long long *arr) { // 436; return (vector long long) { arr[3], arr[2] }; // 437;} // 438;// P8: sldi 3, lxvd2x, xxswapd // 439;// P9: sldi 3, lxvx // 440;vector long long fromDiffMemVarAll(long long *arr, int elem) { // 441; return (vector long long) { arr[elem], arr[elem+1] }; // 442;} // 443;// P8: sldi 3, lxvd2x // 444;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) // 445;vector long long fromDiffMemVarDll(long long *arr, int elem) { // 446; return (vector long long) { arr[elem], arr[elem-1] }; // 447;} // 448;// P8: 2 x ld, 2 x mtvsrd, xxmrghd // 449;// P9: 2 x ld, mtvsrdd // 450;vector long long fromRandMemConsll(long long *arr) { // 451; return (vector long long) { arr[4], arr[18] }; // 452;} // 453;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd // 454;// P9: sldi 3, add, 2 x ld, mtvsrdd // 455;vector long long fromRandMemVarll(long long *arr, int elem) { // 456; return (vector long long) { arr[elem+4], arr[elem+1] }; // 457;} // 458;// P8: mtvsrd, xxspltd // 459;// P9: mtvsrdd // 460;vector long long spltRegValll(long long val) { // 461; return (vector long long) val; // 462;} // 463;// P8: lxvdsx // 464;// P9: lxvdsx // 465;vector long long spltMemValll(long long *ptr) { // 466; return (vector long long)*ptr; // 467;} // 468;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 469;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 470;vector long long spltCnstConvftoll() { // 471; return (vector long long) 4.74f; // 472;} // 473;// P8: xxmrghd, xvcvdpsxds // 474;// P9: xxmrghd, xvcvdpsxds // 475;vector long long fromRegsConvftoll(float a, float b) { // 476; return (vector long long) { a, b }; // 477;} // 478;// P8: lxvd2x, xxswapd // 479;// P9: lxvx (even lxv) // 480;vector long long fromDiffConstsConvftoll() { // 481; return (vector long long) { 24.46f, 234.f }; // 482;} // 483;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds // 484;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds // 485;vector long long fromDiffMemConsAConvftoll(float *ptr) { // 486; return (vector long long) { ptr[0], ptr[1] }; // 487;} // 488;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds // 489;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds // 490;vector long long fromDiffMemConsDConvftoll(float *ptr) { // 491; return (vector long long) { ptr[3], ptr[2] }; // 492;} // 493;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds // 494;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds // 495;vector long long fromDiffMemVarAConvftoll(float *arr, int elem) { // 496; return (vector long long) { arr[elem], arr[elem+1] }; // 497;} // 498;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds // 499;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds // 500;vector long long fromDiffMemVarDConvftoll(float *arr, int elem) { // 501; return (vector long long) { arr[elem], arr[elem-1] }; // 502;} // 503;// P8: xscvdpsxds, xxspltd // 504;// P9: xscvdpsxds, xxspltd // 505;vector long long spltRegValConvftoll(float val) { // 506; return (vector long long) val; // 507;} // 508;// P8: lxsspx, xscvdpsxds, xxspltd // 509;// P9: lfs, xscvdpsxds, xxspltd // 510;vector long long spltMemValConvftoll(float *ptr) { // 511; return (vector long long)*ptr; // 512;} // 513;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 514;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 515;vector long long spltCnstConvdtoll() { // 516; return (vector long long) 4.74; // 517;} // 518;// P8: xxmrghd, xvcvdpsxds // 519;// P9: xxmrghd, xvcvdpsxds // 520;vector long long fromRegsConvdtoll(double a, double b) { // 521; return (vector long long) { a, b }; // 522;} // 523;// P8: lxvd2x, xxswapd // 524;// P9: lxvx (even lxv) // 525;vector long long fromDiffConstsConvdtoll() { // 526; return (vector long long) { 24.46, 234. }; // 527;} // 528;// P8: lxvd2x, xxswapd, xvcvdpsxds // 529;// P9: lxvx, xvcvdpsxds // 530;vector long long fromDiffMemConsAConvdtoll(double *ptr) { // 531; return (vector long long) { ptr[0], ptr[1] }; // 532;} // 533;// P8: lxvd2x, xvcvdpsxds // 534;// P9: lxvx, xxswapd, xvcvdpsxds // 535;vector long long fromDiffMemConsDConvdtoll(double *ptr) { // 536; return (vector long long) { ptr[3], ptr[2] }; // 537;} // 538;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpsxds // 539;// P9: sldi 3, lxvx, xvcvdpsxds // 540;vector long long fromDiffMemVarAConvdtoll(double *arr, int elem) { // 541; return (vector long long) { arr[elem], arr[elem+1] }; // 542;} // 543;// P8: sldi 3, lxvd2x, xvcvdpsxds // 544;// P9: sldi 3, lxvx, xxswapd, xvcvdpsxds // 545;vector long long fromDiffMemVarDConvdtoll(double *arr, int elem) { // 546; return (vector long long) { arr[elem], arr[elem-1] }; // 547;} // 548;// P8: xscvdpsxds, xxspltd // 549;// P9: xscvdpsxds, xxspltd // 550;vector long long spltRegValConvdtoll(double val) { // 551; return (vector long long) val; // 552;} // 553;// P8: lxvdsx, xvcvdpsxds // 554;// P9: lxvdsx, xvcvdpsxds // 555;vector long long spltMemValConvdtoll(double *ptr) { // 556; return (vector long long)*ptr; // 557;} // 558;/*=============================== long long =================================*/ 559;/*========================== unsigned long long =============================*/ 560;// P8: xxlxor // 561;// P9: xxlxor // 562;vector unsigned long long allZeroull() { // 563; return (vector unsigned long long)0; // 564;} // 565;// P8: vspltisb -1 // 566;// P9: xxspltisb 255 // 567;vector unsigned long long allOneull() { // 568; return (vector unsigned long long)-1; // 569;} // 570;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 571;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 572;vector unsigned long long spltConst1ull() { // 573; return (vector unsigned long long)1; // 574;} // 575;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 576;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 577;vector unsigned long long spltConst16kull() { // 578; return (vector unsigned long long)((1<<15) - 1); // 579;} // 580;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 581;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 582;vector unsigned long long spltConst32kull() { // 583; return (vector unsigned long long)((1<<16) - 1); // 584;} // 585;// P8: 2 x mtvsrd, xxmrghd // 586;// P9: mtvsrdd // 587;vector unsigned long long fromRegsull(unsigned long long a, // 588; unsigned long long b) { // 589; return (vector unsigned long long){ a, b }; // 590;} // 591;// P8: lxvd2x, xxswapd // 592;// P9: lxvx (or even lxv) // 593;vector unsigned long long fromDiffConstsull() { // 594; return (vector unsigned long long) { 242, -113 }; // 595;} // 596;// P8: lxvd2x, xxswapd // 597;// P9: lxvx // 598;vector unsigned long long fromDiffMemConsAull(unsigned long long *arr) { // 599; return (vector unsigned long long) { arr[0], arr[1] }; // 600;} // 601;// P8: lxvd2x // 602;// P9: lxvx, xxswapd (maybe just use lxvd2x) // 603;vector unsigned long long fromDiffMemConsDull(unsigned long long *arr) { // 604; return (vector unsigned long long) { arr[3], arr[2] }; // 605;} // 606;// P8: sldi 3, lxvd2x, xxswapd // 607;// P9: sldi 3, lxvx // 608;vector unsigned long long fromDiffMemVarAull(unsigned long long *arr, // 609; int elem) { // 610; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 611;} // 612;// P8: sldi 3, lxvd2x // 613;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) // 614;vector unsigned long long fromDiffMemVarDull(unsigned long long *arr, // 615; int elem) { // 616; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 617;} // 618;// P8: 2 x ld, 2 x mtvsrd, xxmrghd // 619;// P9: 2 x ld, mtvsrdd // 620;vector unsigned long long fromRandMemConsull(unsigned long long *arr) { // 621; return (vector unsigned long long) { arr[4], arr[18] }; // 622;} // 623;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd // 624;// P9: sldi 3, add, 2 x ld, mtvsrdd // 625;vector unsigned long long fromRandMemVarull(unsigned long long *arr, // 626; int elem) { // 627; return (vector unsigned long long) { arr[elem+4], arr[elem+1] }; // 628;} // 629;// P8: mtvsrd, xxspltd // 630;// P9: mtvsrdd // 631;vector unsigned long long spltRegValull(unsigned long long val) { // 632; return (vector unsigned long long) val; // 633;} // 634;// P8: lxvdsx // 635;// P9: lxvdsx // 636;vector unsigned long long spltMemValull(unsigned long long *ptr) { // 637; return (vector unsigned long long)*ptr; // 638;} // 639;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 640;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 641;vector unsigned long long spltCnstConvftoull() { // 642; return (vector unsigned long long) 4.74f; // 643;} // 644;// P8: xxmrghd, xvcvdpuxds // 645;// P9: xxmrghd, xvcvdpuxds // 646;vector unsigned long long fromRegsConvftoull(float a, float b) { // 647; return (vector unsigned long long) { a, b }; // 648;} // 649;// P8: lxvd2x, xxswapd // 650;// P9: lxvx (even lxv) // 651;vector unsigned long long fromDiffConstsConvftoull() { // 652; return (vector unsigned long long) { 24.46f, 234.f }; // 653;} // 654;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds // 655;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds // 656;vector unsigned long long fromDiffMemConsAConvftoull(float *ptr) { // 657; return (vector unsigned long long) { ptr[0], ptr[1] }; // 658;} // 659;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds // 660;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds // 661;vector unsigned long long fromDiffMemConsDConvftoull(float *ptr) { // 662; return (vector unsigned long long) { ptr[3], ptr[2] }; // 663;} // 664;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds // 665;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds // 666;vector unsigned long long fromDiffMemVarAConvftoull(float *arr, int elem) { // 667; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 668;} // 669;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds // 670;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds // 671;vector unsigned long long fromDiffMemVarDConvftoull(float *arr, int elem) { // 672; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 673;} // 674;// P8: xscvdpuxds, xxspltd // 675;// P9: xscvdpuxds, xxspltd // 676;vector unsigned long long spltRegValConvftoull(float val) { // 677; return (vector unsigned long long) val; // 678;} // 679;// P8: lxsspx, xscvdpuxds, xxspltd // 680;// P9: lfs, xscvdpuxds, xxspltd // 681;vector unsigned long long spltMemValConvftoull(float *ptr) { // 682; return (vector unsigned long long)*ptr; // 683;} // 684;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 685;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 686;vector unsigned long long spltCnstConvdtoull() { // 687; return (vector unsigned long long) 4.74; // 688;} // 689;// P8: xxmrghd, xvcvdpuxds // 690;// P9: xxmrghd, xvcvdpuxds // 691;vector unsigned long long fromRegsConvdtoull(double a, double b) { // 692; return (vector unsigned long long) { a, b }; // 693;} // 694;// P8: lxvd2x, xxswapd // 695;// P9: lxvx (even lxv) // 696;vector unsigned long long fromDiffConstsConvdtoull() { // 697; return (vector unsigned long long) { 24.46, 234. }; // 698;} // 699;// P8: lxvd2x, xxswapd, xvcvdpuxds // 700;// P9: lxvx, xvcvdpuxds // 701;vector unsigned long long fromDiffMemConsAConvdtoull(double *ptr) { // 702; return (vector unsigned long long) { ptr[0], ptr[1] }; // 703;} // 704;// P8: lxvd2x, xvcvdpuxds // 705;// P9: lxvx, xxswapd, xvcvdpuxds // 706;vector unsigned long long fromDiffMemConsDConvdtoull(double *ptr) { // 707; return (vector unsigned long long) { ptr[3], ptr[2] }; // 708;} // 709;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpuxds // 710;// P9: sldi 3, lxvx, xvcvdpuxds // 711;vector unsigned long long fromDiffMemVarAConvdtoull(double *arr, int elem) { // 712; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 713;} // 714;// P8: sldi 3, lxvd2x, xvcvdpuxds // 715;// P9: sldi 3, lxvx, xxswapd, xvcvdpuxds // 716;vector unsigned long long fromDiffMemVarDConvdtoull(double *arr, int elem) { // 717; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 718;} // 719;// P8: xscvdpuxds, xxspltd // 720;// P9: xscvdpuxds, xxspltd // 721;vector unsigned long long spltRegValConvdtoull(double val) { // 722; return (vector unsigned long long) val; // 723;} // 724;// P8: lxvdsx, xvcvdpuxds // 725;// P9: lxvdsx, xvcvdpuxds // 726;vector unsigned long long spltMemValConvdtoull(double *ptr) { // 727; return (vector unsigned long long)*ptr; // 728;} // 729;/*========================== unsigned long long ==============================*/ 730 731; Function Attrs: norecurse nounwind readnone 732define <4 x i32> @allZeroi() { 733entry: 734 ret <4 x i32> zeroinitializer 735; P9BE-LABEL: allZeroi 736; P9LE-LABEL: allZeroi 737; P8BE-LABEL: allZeroi 738; P8LE-LABEL: allZeroi 739; P9BE: xxlxor v2, v2, v2 740; P9BE: blr 741; P9LE: xxlxor v2, v2, v2 742; P9LE: blr 743; P8BE: xxlxor v2, v2, v2 744; P8BE: blr 745; P8LE: xxlxor v2, v2, v2 746; P8LE: blr 747} 748 749; Function Attrs: norecurse nounwind readnone 750define <4 x i32> @allOnei() { 751entry: 752 ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> 753; P9BE-LABEL: allOnei 754; P9LE-LABEL: allOnei 755; P8BE-LABEL: allOnei 756; P8LE-LABEL: allOnei 757; P9BE: xxspltib v2, 255 758; P9BE: blr 759; P9LE: xxspltib v2, 255 760; P9LE: blr 761; P8BE: vspltisb v2, -1 762; P8BE: blr 763; P8LE: vspltisb v2, -1 764; P8LE: blr 765} 766 767; Function Attrs: norecurse nounwind readnone 768define <4 x i32> @spltConst1i() { 769entry: 770 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1> 771; P9BE-LABEL: spltConst1i 772; P9LE-LABEL: spltConst1i 773; P8BE-LABEL: spltConst1i 774; P8LE-LABEL: spltConst1i 775; P9BE: vspltisw v2, 1 776; P9BE: blr 777; P9LE: vspltisw v2, 1 778; P9LE: blr 779; P8BE: vspltisw v2, 1 780; P8BE: blr 781; P8LE: vspltisw v2, 1 782; P8LE: blr 783} 784 785; Function Attrs: norecurse nounwind readnone 786define <4 x i32> @spltConst16ki() { 787entry: 788 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 789; P9BE-LABEL: spltConst16ki 790; P9LE-LABEL: spltConst16ki 791; P8BE-LABEL: spltConst16ki 792; P8LE-LABEL: spltConst16ki 793; P9BE: vspltisw v2, -15 794; P9BE: vsrw v2, v2, v2 795; P9BE: blr 796; P9LE: vspltisw v2, -15 797; P9LE: vsrw v2, v2, v2 798; P9LE: blr 799; P8BE: vspltisw v2, -15 800; P8BE: vsrw v2, v2, v2 801; P8BE: blr 802; P8LE: vspltisw v2, -15 803; P8LE: vsrw v2, v2, v2 804; P8LE: blr 805} 806 807; Function Attrs: norecurse nounwind readnone 808define <4 x i32> @spltConst32ki() { 809entry: 810 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 811; P9BE-LABEL: spltConst32ki 812; P9LE-LABEL: spltConst32ki 813; P8BE-LABEL: spltConst32ki 814; P8LE-LABEL: spltConst32ki 815; P9BE: vspltisw v2, -16 816; P9BE: vsrw v2, v2, v2 817; P9BE: blr 818; P9LE: vspltisw v2, -16 819; P9LE: vsrw v2, v2, v2 820; P9LE: blr 821; P8BE: vspltisw v2, -16 822; P8BE: vsrw v2, v2, v2 823; P8BE: blr 824; P8LE: vspltisw v2, -16 825; P8LE: vsrw v2, v2, v2 826; P8LE: blr 827} 828 829; Function Attrs: norecurse nounwind readnone 830define <4 x i32> @fromRegsi(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) { 831entry: 832 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 833 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 834 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 835 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3 836 ret <4 x i32> %vecinit3 837; P9BE-LABEL: fromRegsi 838; P9LE-LABEL: fromRegsi 839; P8BE-LABEL: fromRegsi 840; P8LE-LABEL: fromRegsi 841; P9BE-DAG: mtvsrdd [[REG1:v[0-9]+]], r3, r5 842; P9BE-DAG: mtvsrdd [[REG2:v[0-9]+]], r4, r6 843; P9BE: vmrgow v2, [[REG1]], [[REG2]] 844; P9BE: blr 845; P9LE-DAG: mtvsrdd [[REG1:v[0-9]+]], r5, r3 846; P9LE-DAG: mtvsrdd [[REG2:v[0-9]+]], r6, r4 847; P9LE: vmrgow v2, [[REG2]], [[REG1]] 848; P9LE: blr 849; P8BE-DAG: mtvsrwz {{[vf]}}[[REG1:[0-9]+]], r3 850; P8BE-DAG: mtvsrwz {{[vf]}}[[REG2:[0-9]+]], r4 851; P8BE-DAG: mtvsrwz {{[vf]}}[[REG3:[0-9]+]], r5 852; P8BE-DAG: mtvsrwz {{[vf]}}[[REG4:[0-9]+]], r6 853; P8BE-DAG: xxmrghd [[REG5:v[0-9]+]], {{[v][s]*}}[[REG1]], {{[v][s]*}}[[REG3]] 854; P8BE-DAG: xxmrghd [[REG6:v[0-9]+]], {{[v][s]*}}[[REG2]], {{[v][s]*}}[[REG4]] 855; P8BE: vmrgow v2, [[REG5]], [[REG6]] 856; P8LE-DAG: mtvsrwz {{[vf]}}[[REG1:[0-9]+]], r3 857; P8LE-DAG: mtvsrwz {{[vf]}}[[REG2:[0-9]+]], r4 858; P8LE-DAG: mtvsrwz {{[vf]}}[[REG3:[0-9]+]], r5 859; P8LE-DAG: mtvsrwz {{[vf]}}[[REG4:[0-9]+]], r6 860; P8LE: xxmrghd [[REG5:v[0-9]+]], {{[v][s]*}}[[REG3]], {{[v][s]*}}[[REG1]] 861; P8LE: xxmrghd [[REG6:v[0-9]+]], {{[v][s]*}}[[REG4]], {{[v][s]*}}[[REG2]] 862; P8LE: vmrgow v2, [[REG6]], [[REG5]] 863} 864 865; Function Attrs: norecurse nounwind readnone 866define <4 x i32> @fromDiffConstsi() { 867entry: 868 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19> 869; P9BE-LABEL: fromDiffConstsi 870; P9LE-LABEL: fromDiffConstsi 871; P8BE-LABEL: fromDiffConstsi 872; P8LE-LABEL: fromDiffConstsi 873; P9BE: lxv 874; P9BE: blr 875; P9LE: lxv 876; P9LE: blr 877; P8BE: lxvw4x 878; P8BE: blr 879; P8LE: lvx 880; P8LE-NOT: xxswapd 881; P8LE: blr 882} 883 884; Function Attrs: norecurse nounwind readonly 885define <4 x i32> @fromDiffMemConsAi(i32* nocapture readonly %arr) { 886entry: 887 %0 = load i32, i32* %arr, align 4 888 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 889 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 1 890 %1 = load i32, i32* %arrayidx1, align 4 891 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 892 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 893 %2 = load i32, i32* %arrayidx3, align 4 894 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 895 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 3 896 %3 = load i32, i32* %arrayidx5, align 4 897 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 898 ret <4 x i32> %vecinit6 899; P9BE-LABEL: fromDiffMemConsAi 900; P9LE-LABEL: fromDiffMemConsAi 901; P8BE-LABEL: fromDiffMemConsAi 902; P8LE-LABEL: fromDiffMemConsAi 903; P9BE: lxv 904; P9BE: blr 905; P9LE: lxv 906; P9LE: blr 907; P8BE: lxvw4x 908; P8BE: blr 909; P8LE: lxvd2x 910; P8LE: xxswapd 911; P8LE: blr 912} 913 914; Function Attrs: norecurse nounwind readonly 915define <4 x i32> @fromDiffMemConsDi(i32* nocapture readonly %arr) { 916entry: 917 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3 918 %0 = load i32, i32* %arrayidx, align 4 919 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 920 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 921 %1 = load i32, i32* %arrayidx1, align 4 922 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 923 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 1 924 %2 = load i32, i32* %arrayidx3, align 4 925 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 926 %3 = load i32, i32* %arr, align 4 927 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 928 ret <4 x i32> %vecinit6 929; P9BE-LABEL: fromDiffMemConsDi 930; P9LE-LABEL: fromDiffMemConsDi 931; P8BE-LABEL: fromDiffMemConsDi 932; P8LE-LABEL: fromDiffMemConsDi 933; P9BE: lxv 934; P9BE: lxv 935; P9BE: vperm 936; P9BE: blr 937; P9LE: lxv 938; P9LE: lxv 939; P9LE: vperm 940; P9LE: blr 941; P8BE: lxvw4x 942; P8BE: lxvw4x 943; P8BE: vperm 944; P8BE: blr 945; P8LE: lxvd2x 946; P8LE-DAG: lvx 947; P8LE: xxswapd 948; P8LE: vperm 949; P8LE: blr 950} 951 952; Function Attrs: norecurse nounwind readonly 953define <4 x i32> @fromDiffMemVarAi(i32* nocapture readonly %arr, i32 signext %elem) { 954entry: 955 %idxprom = sext i32 %elem to i64 956 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 957 %0 = load i32, i32* %arrayidx, align 4 958 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 959 %add = add nsw i32 %elem, 1 960 %idxprom1 = sext i32 %add to i64 961 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 962 %1 = load i32, i32* %arrayidx2, align 4 963 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 964 %add4 = add nsw i32 %elem, 2 965 %idxprom5 = sext i32 %add4 to i64 966 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 967 %2 = load i32, i32* %arrayidx6, align 4 968 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 969 %add8 = add nsw i32 %elem, 3 970 %idxprom9 = sext i32 %add8 to i64 971 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 972 %3 = load i32, i32* %arrayidx10, align 4 973 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 974 ret <4 x i32> %vecinit11 975; P9BE-LABEL: fromDiffMemVarAi 976; P9LE-LABEL: fromDiffMemVarAi 977; P8BE-LABEL: fromDiffMemVarAi 978; P8LE-LABEL: fromDiffMemVarAi 979; P9BE: sldi r4, r4, 2 980; P9BE: lxvx v2, r3, r4 981; P9BE: blr 982; P9LE: sldi r4, r4, 2 983; P9LE: lxvx v2, r3, r4 984; P9LE: blr 985; P8BE: sldi r4, r4, 2 986; P8BE: lxvw4x {{[vs0-9]+}}, r3, r4 987; P8BE: blr 988; P8LE: sldi r4, r4, 2 989; P8LE: lxvd2x {{[vs0-9]+}}, r3, r4 990; P8LE: xxswapd 991; P8LE: blr 992} 993 994; Function Attrs: norecurse nounwind readonly 995define <4 x i32> @fromDiffMemVarDi(i32* nocapture readonly %arr, i32 signext %elem) { 996entry: 997 %idxprom = sext i32 %elem to i64 998 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 999 %0 = load i32, i32* %arrayidx, align 4 1000 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1001 %sub = add nsw i32 %elem, -1 1002 %idxprom1 = sext i32 %sub to i64 1003 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 1004 %1 = load i32, i32* %arrayidx2, align 4 1005 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1006 %sub4 = add nsw i32 %elem, -2 1007 %idxprom5 = sext i32 %sub4 to i64 1008 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 1009 %2 = load i32, i32* %arrayidx6, align 4 1010 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 1011 %sub8 = add nsw i32 %elem, -3 1012 %idxprom9 = sext i32 %sub8 to i64 1013 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 1014 %3 = load i32, i32* %arrayidx10, align 4 1015 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 1016 ret <4 x i32> %vecinit11 1017; P9BE-LABEL: fromDiffMemVarDi 1018; P9LE-LABEL: fromDiffMemVarDi 1019; P8BE-LABEL: fromDiffMemVarDi 1020; P8LE-LABEL: fromDiffMemVarDi 1021; P9BE: sldi {{r[0-9]+}}, r4, 2 1022; P9BE-DAG: lxvx {{v[0-9]+}} 1023; P9BE-DAG: lxvx 1024; P9BE: vperm 1025; P9BE: blr 1026; P9LE: sldi {{r[0-9]+}}, r4, 2 1027; P9LE-DAG: lxvx {{v[0-9]+}} 1028; P9LE-DAG: lxvx 1029; P9LE: vperm 1030; P9LE: blr 1031; P8BE: sldi {{r[0-9]+}}, r4, 2 1032; P8BE-DAG: lxvw4x {{v[0-9]+}}, 0, r3 1033; P8BE-DAG: lxvw4x 1034; P8BE: vperm 1035; P8BE: blr 1036; P8LE: sldi {{r[0-9]+}}, r4, 2 1037; P8LE-DAG: lxvd2x 1038; P8LE-DAG: lxvd2x 1039; P8LE: xxswapd 1040; P8LE: vperm 1041; P8LE: blr 1042} 1043 1044; Function Attrs: norecurse nounwind readonly 1045define <4 x i32> @fromRandMemConsi(i32* nocapture readonly %arr) { 1046entry: 1047 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4 1048 %0 = load i32, i32* %arrayidx, align 4 1049 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1050 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18 1051 %1 = load i32, i32* %arrayidx1, align 4 1052 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1053 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 1054 %2 = load i32, i32* %arrayidx3, align 4 1055 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 1056 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 88 1057 %3 = load i32, i32* %arrayidx5, align 4 1058 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 1059 ret <4 x i32> %vecinit6 1060; P9BE-LABEL: fromRandMemConsi 1061; P9LE-LABEL: fromRandMemConsi 1062; P8BE-LABEL: fromRandMemConsi 1063; P8LE-LABEL: fromRandMemConsi 1064; P9BE: lwz 1065; P9BE: lwz 1066; P9BE: lwz 1067; P9BE: lwz 1068; P9BE: mtvsrdd 1069; P9BE: mtvsrdd 1070; P9BE: vmrgow 1071; P9LE: lwz 1072; P9LE: lwz 1073; P9LE: lwz 1074; P9LE: lwz 1075; P9LE: mtvsrdd 1076; P9LE: mtvsrdd 1077; P9LE: vmrgow 1078; P8BE: lwz 1079; P8BE: lwz 1080; P8BE: lwz 1081; P8BE: lwz 1082; P8BE: mtvsrwz 1083; P8BE: mtvsrwz 1084; P8BE: mtvsrwz 1085; P8BE: mtvsrwz 1086; P8BE: xxmrghd 1087; P8BE: xxmrghd 1088; P8BE: vmrgow 1089; P8LE: lwz 1090; P8LE: lwz 1091; P8LE: lwz 1092; P8LE: lwz 1093; P8LE: mtvsrwz 1094; P8LE: mtvsrwz 1095; P8LE: mtvsrwz 1096; P8LE: mtvsrwz 1097; P8LE: xxmrghd 1098; P8LE: xxmrghd 1099; P8LE: vmrgow 1100} 1101 1102; Function Attrs: norecurse nounwind readonly 1103define <4 x i32> @fromRandMemVari(i32* nocapture readonly %arr, i32 signext %elem) { 1104entry: 1105 %add = add nsw i32 %elem, 4 1106 %idxprom = sext i32 %add to i64 1107 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 1108 %0 = load i32, i32* %arrayidx, align 4 1109 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1110 %add1 = add nsw i32 %elem, 1 1111 %idxprom2 = sext i32 %add1 to i64 1112 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 %idxprom2 1113 %1 = load i32, i32* %arrayidx3, align 4 1114 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1115 %add5 = add nsw i32 %elem, 2 1116 %idxprom6 = sext i32 %add5 to i64 1117 %arrayidx7 = getelementptr inbounds i32, i32* %arr, i64 %idxprom6 1118 %2 = load i32, i32* %arrayidx7, align 4 1119 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2 1120 %add9 = add nsw i32 %elem, 8 1121 %idxprom10 = sext i32 %add9 to i64 1122 %arrayidx11 = getelementptr inbounds i32, i32* %arr, i64 %idxprom10 1123 %3 = load i32, i32* %arrayidx11, align 4 1124 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3 1125 ret <4 x i32> %vecinit12 1126; P9BE-LABEL: fromRandMemVari 1127; P9LE-LABEL: fromRandMemVari 1128; P8BE-LABEL: fromRandMemVari 1129; P8LE-LABEL: fromRandMemVari 1130; P9BE: sldi r4, r4, 2 1131; P9BE: lwz 1132; P9BE: lwz 1133; P9BE: lwz 1134; P9BE: lwz 1135; P9BE: mtvsrdd 1136; P9BE: mtvsrdd 1137; P9BE: vmrgow 1138; P9LE: sldi r4, r4, 2 1139; P9LE: lwz 1140; P9LE: lwz 1141; P9LE: lwz 1142; P9LE: lwz 1143; P9LE: mtvsrdd 1144; P9LE: mtvsrdd 1145; P9LE: vmrgow 1146; P8BE: sldi r4, r4, 2 1147; P8BE: lwz 1148; P8BE: lwz 1149; P8BE: lwz 1150; P8BE: lwz 1151; P8BE: mtvsrwz 1152; P8BE: mtvsrwz 1153; P8BE: mtvsrwz 1154; P8BE: mtvsrwz 1155; P8BE: xxmrghd 1156; P8BE: xxmrghd 1157; P8BE: vmrgow 1158; P8LE: sldi r4, r4, 2 1159; P8LE: lwz 1160; P8LE: lwz 1161; P8LE: lwz 1162; P8LE: lwz 1163; P8LE: mtvsrwz 1164; P8LE: mtvsrwz 1165; P8LE: mtvsrwz 1166; P8LE: mtvsrwz 1167; P8LE: xxmrghd 1168; P8LE: xxmrghd 1169; P8LE: vmrgow 1170} 1171 1172; Function Attrs: norecurse nounwind readnone 1173define <4 x i32> @spltRegVali(i32 signext %val) { 1174entry: 1175 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0 1176 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1177 ret <4 x i32> %splat.splat 1178; P9BE-LABEL: spltRegVali 1179; P9LE-LABEL: spltRegVali 1180; P8BE-LABEL: spltRegVali 1181; P8LE-LABEL: spltRegVali 1182; P9BE: mtvsrws v2, r3 1183; P9BE: blr 1184; P9LE: mtvsrws v2, r3 1185; P9LE: blr 1186; P8BE: mtvsrwz {{[vsf0-9]+}}, r3 1187; P8BE: xxspltw v2, {{[vsf0-9]+}}, 1 1188; P8BE: blr 1189; P8LE: mtvsrwz {{[vsf0-9]+}}, r3 1190; P8LE: xxspltw v2, {{[vsf0-9]+}}, 1 1191; P8LE: blr 1192} 1193 1194; Function Attrs: norecurse nounwind readonly 1195define <4 x i32> @spltMemVali(i32* nocapture readonly %ptr) { 1196entry: 1197 %0 = load i32, i32* %ptr, align 4 1198 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 1199 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1200 ret <4 x i32> %splat.splat 1201; P9BE-LABEL: spltMemVali 1202; P9LE-LABEL: spltMemVali 1203; P8BE-LABEL: spltMemVali 1204; P8LE-LABEL: spltMemVali 1205; P9BE: lfiwzx f0, 0, r3 1206; P9BE: xxsldwi vs0, f0, f0, 1 1207; P9BE: xxspltw v2, vs0, 0 1208; P9BE: blr 1209; P9LE: lfiwzx f0, 0, r3 1210; P9LE: xxpermdi vs0, f0, f0, 2 1211; P9LE: xxspltw v2, vs0, 3 1212; P9LE: blr 1213; P8BE: lfiwzx f0, 0, r3 1214; P8BE: xxsldwi vs0, f0, f0, 1 1215; P8BE: xxspltw v2, vs0, 0 1216; P8BE: blr 1217; P8LE: lfiwzx f0, 0, r3 1218; P8LE: xxpermdi vs0, f0, f0, 2 1219; P8LE: xxspltw v2, vs0, 3 1220; P8LE: blr 1221} 1222 1223; Function Attrs: norecurse nounwind readnone 1224define <4 x i32> @spltCnstConvftoi() { 1225entry: 1226 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 1227; P9BE-LABEL: spltCnstConvftoi 1228; P9LE-LABEL: spltCnstConvftoi 1229; P8BE-LABEL: spltCnstConvftoi 1230; P8LE-LABEL: spltCnstConvftoi 1231; P9BE: vspltisw v2, 4 1232; P9BE: blr 1233; P9LE: vspltisw v2, 4 1234; P9LE: blr 1235; P8BE: vspltisw v2, 4 1236; P8BE: blr 1237; P8LE: vspltisw v2, 4 1238; P8LE: blr 1239} 1240 1241; Function Attrs: norecurse nounwind readnone 1242define <4 x i32> @fromRegsConvftoi(float %a, float %b, float %c, float %d) { 1243entry: 1244 %conv = fptosi float %a to i32 1245 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1246 %conv1 = fptosi float %b to i32 1247 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 1248 %conv3 = fptosi float %c to i32 1249 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 1250 %conv5 = fptosi float %d to i32 1251 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 1252 ret <4 x i32> %vecinit6 1253; P9BE-LABEL: fromRegsConvftoi 1254; P9LE-LABEL: fromRegsConvftoi 1255; P8BE-LABEL: fromRegsConvftoi 1256; P8LE-LABEL: fromRegsConvftoi 1257; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 1258; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 1259; P9BE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1260; P9BE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1261; P9BE: vmrgew v2, [[REG3]], [[REG4]] 1262; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 1263; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 1264; P9LE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1265; P9LE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1266; P9LE: vmrgew v2, [[REG4]], [[REG3]] 1267; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 1268; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 1269; P8BE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1270; P8BE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1271; P8BE: vmrgew v2, [[REG3]], [[REG4]] 1272; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 1273; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 1274; P8LE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1275; P8LE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1276; P8LE: vmrgew v2, [[REG4]], [[REG3]] 1277} 1278 1279; Function Attrs: norecurse nounwind readnone 1280define <4 x i32> @fromDiffConstsConvftoi() { 1281entry: 1282 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 1283; P9BE-LABEL: fromDiffConstsConvftoi 1284; P9LE-LABEL: fromDiffConstsConvftoi 1285; P8BE-LABEL: fromDiffConstsConvftoi 1286; P8LE-LABEL: fromDiffConstsConvftoi 1287; P9BE: lxv 1288; P9BE: blr 1289; P9LE: lxv 1290; P9LE: blr 1291; P8BE: lxvw4x 1292; P8BE: blr 1293; P8LE: lvx 1294; P8LE-NOT: xxswapd 1295; P8LE: blr 1296} 1297 1298; Function Attrs: norecurse nounwind readonly 1299define <4 x i32> @fromDiffMemConsAConvftoi(float* nocapture readonly %ptr) { 1300entry: 1301 %0 = bitcast float* %ptr to <4 x float>* 1302 %1 = load <4 x float>, <4 x float>* %0, align 4 1303 %2 = fptosi <4 x float> %1 to <4 x i32> 1304 ret <4 x i32> %2 1305; P9BE-LABEL: fromDiffMemConsAConvftoi 1306; P9LE-LABEL: fromDiffMemConsAConvftoi 1307; P8BE-LABEL: fromDiffMemConsAConvftoi 1308; P8LE-LABEL: fromDiffMemConsAConvftoi 1309; P9BE: lxv [[REG1:[vs0-9]+]], 0(r3) 1310; P9BE: xvcvspsxws v2, [[REG1]] 1311; P9BE: blr 1312; P9LE: lxv [[REG1:[vs0-9]+]], 0(r3) 1313; P9LE: xvcvspsxws v2, [[REG1]] 1314; P9LE: blr 1315; P8BE: lxvw4x [[REG1:[vs0-9]+]], 0, r3 1316; P8BE: xvcvspsxws v2, [[REG1]] 1317; P8BE: blr 1318; P8LE: lxvd2x [[REG1:[vs0-9]+]], 0, r3 1319; P8LE: xxswapd 1320; P8LE: xvcvspsxws v2, v2 1321; P8LE: blr 1322} 1323 1324; Function Attrs: norecurse nounwind readonly 1325define <4 x i32> @fromDiffMemConsDConvftoi(float* nocapture readonly %ptr) { 1326entry: 1327 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 1328 %0 = load float, float* %arrayidx, align 4 1329 %conv = fptosi float %0 to i32 1330 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1331 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 1332 %1 = load float, float* %arrayidx1, align 4 1333 %conv2 = fptosi float %1 to i32 1334 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 1335 %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1 1336 %2 = load float, float* %arrayidx4, align 4 1337 %conv5 = fptosi float %2 to i32 1338 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 1339 %3 = load float, float* %ptr, align 4 1340 %conv8 = fptosi float %3 to i32 1341 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 1342 ret <4 x i32> %vecinit9 1343; P9BE-LABEL: fromDiffMemConsDConvftoi 1344; P9LE-LABEL: fromDiffMemConsDConvftoi 1345; P8BE-LABEL: fromDiffMemConsDConvftoi 1346; P8LE-LABEL: fromDiffMemConsDConvftoi 1347; P9BE: lxv 1348; P9BE: lxv 1349; P9BE: vperm 1350; P9BE: xvcvspsxws 1351; P9BE: blr 1352; P9LE: lxv 1353; P9LE: lxv 1354; P9LE: vperm 1355; P9LE: xvcvspsxws 1356; P9LE: blr 1357; P8BE: lxvw4x 1358; P8BE: lxvw4x 1359; P8BE: vperm 1360; P8BE: xvcvspsxws 1361; P8BE: blr 1362; P8LE: lxvd2x 1363; P8LE-DAG: lvx 1364; P8LE: xxswapd 1365; P8LE: vperm 1366; P8LE: xvcvspsxws 1367; P8LE: blr 1368} 1369 1370; Function Attrs: norecurse nounwind readonly 1371define <4 x i32> @fromDiffMemVarAConvftoi(float* nocapture readonly %arr, i32 signext %elem) { 1372entry: 1373 %idxprom = sext i32 %elem to i64 1374 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 1375 %0 = load float, float* %arrayidx, align 4 1376 %conv = fptosi float %0 to i32 1377 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1378 %add = add nsw i32 %elem, 1 1379 %idxprom1 = sext i32 %add to i64 1380 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 1381 %1 = load float, float* %arrayidx2, align 4 1382 %conv3 = fptosi float %1 to i32 1383 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1384 %add5 = add nsw i32 %elem, 2 1385 %idxprom6 = sext i32 %add5 to i64 1386 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 1387 %2 = load float, float* %arrayidx7, align 4 1388 %conv8 = fptosi float %2 to i32 1389 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1390 %add10 = add nsw i32 %elem, 3 1391 %idxprom11 = sext i32 %add10 to i64 1392 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 1393 %3 = load float, float* %arrayidx12, align 4 1394 %conv13 = fptosi float %3 to i32 1395 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1396 ret <4 x i32> %vecinit14 1397; P9BE-LABEL: fromDiffMemVarAConvftoi 1398; P9LE-LABEL: fromDiffMemVarAConvftoi 1399; P8BE-LABEL: fromDiffMemVarAConvftoi 1400; P8LE-LABEL: fromDiffMemVarAConvftoi 1401; FIXME: implement finding consecutive loads with pre-inc 1402; P9BE: lfsux 1403; P9LE: lfsux 1404; P8BE: lfsux 1405; P8LE: lfsux 1406} 1407 1408; Function Attrs: norecurse nounwind readonly 1409define <4 x i32> @fromDiffMemVarDConvftoi(float* nocapture readonly %arr, i32 signext %elem) { 1410entry: 1411 %idxprom = sext i32 %elem to i64 1412 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 1413 %0 = load float, float* %arrayidx, align 4 1414 %conv = fptosi float %0 to i32 1415 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1416 %sub = add nsw i32 %elem, -1 1417 %idxprom1 = sext i32 %sub to i64 1418 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 1419 %1 = load float, float* %arrayidx2, align 4 1420 %conv3 = fptosi float %1 to i32 1421 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1422 %sub5 = add nsw i32 %elem, -2 1423 %idxprom6 = sext i32 %sub5 to i64 1424 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 1425 %2 = load float, float* %arrayidx7, align 4 1426 %conv8 = fptosi float %2 to i32 1427 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1428 %sub10 = add nsw i32 %elem, -3 1429 %idxprom11 = sext i32 %sub10 to i64 1430 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 1431 %3 = load float, float* %arrayidx12, align 4 1432 %conv13 = fptosi float %3 to i32 1433 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1434 ret <4 x i32> %vecinit14 1435; P9BE-LABEL: fromDiffMemVarDConvftoi 1436; P9LE-LABEL: fromDiffMemVarDConvftoi 1437; P8BE-LABEL: fromDiffMemVarDConvftoi 1438; P8LE-LABEL: fromDiffMemVarDConvftoi 1439; FIXME: implement finding consecutive loads with pre-inc 1440; P9BE: lfsux 1441; P9LE: lfsux 1442; P8BE: lfsux 1443; P8LE: lfsux 1444} 1445 1446; Function Attrs: norecurse nounwind readnone 1447define <4 x i32> @spltRegValConvftoi(float %val) { 1448entry: 1449 %conv = fptosi float %val to i32 1450 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1451 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1452 ret <4 x i32> %splat.splat 1453; P9BE-LABEL: spltRegValConvftoi 1454; P9LE-LABEL: spltRegValConvftoi 1455; P8BE-LABEL: spltRegValConvftoi 1456; P8LE-LABEL: spltRegValConvftoi 1457; P9BE: xscvdpsxws f[[REG1:[0-9]+]], f1 1458; P9BE: xxspltw v2, vs[[REG1]], 1 1459; P9BE: blr 1460; P9LE: xscvdpsxws f[[REG1:[0-9]+]], f1 1461; P9LE: xxspltw v2, vs[[REG1]], 1 1462; P9LE: blr 1463; P8BE: xscvdpsxws f[[REG1:[0-9]+]], f1 1464; P8BE: xxspltw v2, vs[[REG1]], 1 1465; P8BE: blr 1466; P8LE: xscvdpsxws f[[REG1:[0-9]+]], f1 1467; P8LE: xxspltw v2, vs[[REG1]], 1 1468; P8LE: blr 1469} 1470 1471; Function Attrs: norecurse nounwind readonly 1472define <4 x i32> @spltMemValConvftoi(float* nocapture readonly %ptr) { 1473entry: 1474 %0 = load float, float* %ptr, align 4 1475 %conv = fptosi float %0 to i32 1476 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1477 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1478 ret <4 x i32> %splat.splat 1479; P9BE-LABEL: spltMemValConvftoi 1480; P9LE-LABEL: spltMemValConvftoi 1481; P8BE-LABEL: spltMemValConvftoi 1482; P8LE-LABEL: spltMemValConvftoi 1483; P9BE: lxvwsx [[REG1:[vs0-9]+]], 0, r3 1484; P9BE: xvcvspsxws v2, [[REG1]] 1485; P9LE: [[REG1:[vs0-9]+]], 0, r3 1486; P9LE: xvcvspsxws v2, [[REG1]] 1487; P8BE: lfsx [[REG1:f[0-9]+]], 0, r3 1488; P8BE: xscvdpsxws f[[REG2:[0-9]+]], [[REG1]] 1489; P8BE: xxspltw v2, vs[[REG2]], 1 1490; P8LE: lfsx [[REG1:f[0-9]+]], 0, r3 1491; P8LE: xscvdpsxws f[[REG2:[vs0-9]+]], [[REG1]] 1492; P8LE: xxspltw v2, vs[[REG2]], 1 1493} 1494 1495; Function Attrs: norecurse nounwind readnone 1496define <4 x i32> @spltCnstConvdtoi() { 1497entry: 1498 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 1499; P9BE-LABEL: spltCnstConvdtoi 1500; P9LE-LABEL: spltCnstConvdtoi 1501; P8BE-LABEL: spltCnstConvdtoi 1502; P8LE-LABEL: spltCnstConvdtoi 1503; P9BE: vspltisw v2, 4 1504; P9BE: blr 1505; P9LE: vspltisw v2, 4 1506; P9LE: blr 1507; P8BE: vspltisw v2, 4 1508; P8BE: blr 1509; P8LE: vspltisw v2, 4 1510; P8LE: blr 1511} 1512 1513; Function Attrs: norecurse nounwind readnone 1514define <4 x i32> @fromRegsConvdtoi(double %a, double %b, double %c, double %d) { 1515entry: 1516 %conv = fptosi double %a to i32 1517 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1518 %conv1 = fptosi double %b to i32 1519 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 1520 %conv3 = fptosi double %c to i32 1521 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 1522 %conv5 = fptosi double %d to i32 1523 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 1524 ret <4 x i32> %vecinit6 1525; P9BE-LABEL: fromRegsConvdtoi 1526; P9LE-LABEL: fromRegsConvdtoi 1527; P8BE-LABEL: fromRegsConvdtoi 1528; P8LE-LABEL: fromRegsConvdtoi 1529; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 1530; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 1531; P9BE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1532; P9BE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1533; P9BE: vmrgew v2, [[REG3]], [[REG4]] 1534; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 1535; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 1536; P9LE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1537; P9LE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1538; P9LE: vmrgew v2, [[REG4]], [[REG3]] 1539; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 1540; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 1541; P8BE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1542; P8BE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1543; P8BE: vmrgew v2, [[REG3]], [[REG4]] 1544; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 1545; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 1546; P8LE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1547; P8LE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1548; P8LE: vmrgew v2, [[REG4]], [[REG3]] 1549} 1550 1551; Function Attrs: norecurse nounwind readnone 1552define <4 x i32> @fromDiffConstsConvdtoi() { 1553entry: 1554 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 1555; P9BE-LABEL: fromDiffConstsConvdtoi 1556; P9LE-LABEL: fromDiffConstsConvdtoi 1557; P8BE-LABEL: fromDiffConstsConvdtoi 1558; P8LE-LABEL: fromDiffConstsConvdtoi 1559; P9BE: lxv 1560; P9BE: blr 1561; P9LE: lxv 1562; P9LE: blr 1563; P8BE: lxvw4x 1564; P8BE: blr 1565; P8LE: lvx 1566; P8LE-NOT: xxswapd 1567; P8LE: blr 1568} 1569 1570; Function Attrs: norecurse nounwind readonly 1571define <4 x i32> @fromDiffMemConsAConvdtoi(double* nocapture readonly %ptr) { 1572entry: 1573 %0 = bitcast double* %ptr to <2 x double>* 1574 %1 = load <2 x double>, <2 x double>* %0, align 8 1575 %2 = fptosi <2 x double> %1 to <2 x i32> 1576 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 2 1577 %3 = bitcast double* %arrayidx4 to <2 x double>* 1578 %4 = load <2 x double>, <2 x double>* %3, align 8 1579 %5 = fptosi <2 x double> %4 to <2 x i32> 1580 %vecinit9 = shufflevector <2 x i32> %2, <2 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 1581 ret <4 x i32> %vecinit9 1582; P9BE-LABEL: fromDiffMemConsAConvdtoi 1583; P9LE-LABEL: fromDiffMemConsAConvdtoi 1584; P8BE-LABEL: fromDiffMemConsAConvdtoi 1585; P8LE-LABEL: fromDiffMemConsAConvdtoi 1586; P9BE-DAG: lxv [[REG1:[vs0-9]+]], 0(r3) 1587; P9BE-DAG: lxv [[REG2:[vs0-9]+]], 16(r3) 1588; P9BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]] 1589; P9BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]] 1590; P9BE-DAG: xvcvdpsxws [[REG5:[vs0-9]+]], [[REG3]] 1591; P9BE-DAG: xvcvdpsxws [[REG6:[vs0-9]+]], [[REG4]] 1592; P9BE: vmrgew v2, [[REG6]], [[REG5]] 1593; P9LE-DAG: lxv [[REG1:[vs0-9]+]], 0(r3) 1594; P9LE-DAG: lxv [[REG2:[vs0-9]+]], 16(r3) 1595; P9LE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG2]], [[REG1]] 1596; P9LE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG2]], [[REG1]] 1597; P9LE-DAG: xvcvdpsxws [[REG5:[vs0-9]+]], [[REG3]] 1598; P9LE-DAG: xvcvdpsxws [[REG6:[vs0-9]+]], [[REG4]] 1599; P9LE: vmrgew v2, [[REG6]], [[REG5]] 1600; P8BE: lxvd2x [[REG1:[vs0-9]+]], 0, r3 1601; P8BE: lxvd2x [[REG2:[vs0-9]+]], r3, r4 1602; P8BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]] 1603; P8BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]] 1604; P8BE-DAG: xvcvdpsxws [[REG5:[vs0-9]+]], [[REG3]] 1605; P8BE-DAG: xvcvdpsxws [[REG6:[vs0-9]+]], [[REG4]] 1606; P8BE: vmrgew v2, [[REG6]], [[REG5]] 1607; P8LE: lxvd2x [[REG1:[vs0-9]+]], 0, r3 1608; P8LE: lxvd2x [[REG2:[vs0-9]+]], r3, r4 1609; P8LE-DAG: xxswapd [[REG3:[vs0-9]+]], [[REG1]] 1610; P8LE-DAG: xxswapd [[REG4:[vs0-9]+]], [[REG2]] 1611; P8LE-DAG: xxmrgld [[REG5:[vs0-9]+]], [[REG4]], [[REG3]] 1612; P8LE-DAG: xxmrghd [[REG6:[vs0-9]+]], [[REG4]], [[REG3]] 1613; P8LE-DAG: xvcvdpsxws [[REG7:[vs0-9]+]], [[REG5]] 1614; P8LE-DAG: xvcvdpsxws [[REG8:[vs0-9]+]], [[REG6]] 1615; P8LE: vmrgew v2, [[REG8]], [[REG7]] 1616} 1617 1618; Function Attrs: norecurse nounwind readonly 1619define <4 x i32> @fromDiffMemConsDConvdtoi(double* nocapture readonly %ptr) { 1620entry: 1621 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 1622 %0 = load double, double* %arrayidx, align 8 1623 %conv = fptosi double %0 to i32 1624 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1625 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 1626 %1 = load double, double* %arrayidx1, align 8 1627 %conv2 = fptosi double %1 to i32 1628 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 1629 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 1 1630 %2 = load double, double* %arrayidx4, align 8 1631 %conv5 = fptosi double %2 to i32 1632 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 1633 %3 = load double, double* %ptr, align 8 1634 %conv8 = fptosi double %3 to i32 1635 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 1636 ret <4 x i32> %vecinit9 1637; P9BE-LABEL: fromDiffMemConsDConvdtoi 1638; P9LE-LABEL: fromDiffMemConsDConvdtoi 1639; P8BE-LABEL: fromDiffMemConsDConvdtoi 1640; P8LE-LABEL: fromDiffMemConsDConvdtoi 1641; P9BE: lfd 1642; P9BE: lfd 1643; P9BE: lfd 1644; P9BE: lfd 1645; P9BE: xxmrghd 1646; P9BE: xxmrghd 1647; P9BE: xvcvdpsxws 1648; P9BE: xvcvdpsxws 1649; P9BE: vmrgew v2 1650; P9LE: lfd 1651; P9LE: lfd 1652; P9LE: lfd 1653; P9LE: lfd 1654; P9LE: xxmrghd 1655; P9LE: xxmrghd 1656; P9LE: xvcvdpsxws 1657; P9LE: xvcvdpsxws 1658; P9LE: vmrgew v2 1659; P8BE: lfdx 1660; P8BE: lfd 1661; P8BE: lfd 1662; P8BE: lfd 1663; P8BE: xxmrghd 1664; P8BE: xxmrghd 1665; P8BE: xvcvdpsxws 1666; P8BE: xvcvdpsxws 1667; P8BE: vmrgew v2 1668; P8LE: lfdx 1669; P8LE: lfd 1670; P8LE: lfd 1671; P8LE: lfd 1672; P8LE: xxmrghd 1673; P8LE: xxmrghd 1674; P8LE: xvcvdpsxws 1675; P8LE: xvcvdpsxws 1676; P8LE: vmrgew v2 1677} 1678 1679; Function Attrs: norecurse nounwind readonly 1680define <4 x i32> @fromDiffMemVarAConvdtoi(double* nocapture readonly %arr, i32 signext %elem) { 1681entry: 1682 %idxprom = sext i32 %elem to i64 1683 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 1684 %0 = load double, double* %arrayidx, align 8 1685 %conv = fptosi double %0 to i32 1686 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1687 %add = add nsw i32 %elem, 1 1688 %idxprom1 = sext i32 %add to i64 1689 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 1690 %1 = load double, double* %arrayidx2, align 8 1691 %conv3 = fptosi double %1 to i32 1692 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1693 %add5 = add nsw i32 %elem, 2 1694 %idxprom6 = sext i32 %add5 to i64 1695 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 1696 %2 = load double, double* %arrayidx7, align 8 1697 %conv8 = fptosi double %2 to i32 1698 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1699 %add10 = add nsw i32 %elem, 3 1700 %idxprom11 = sext i32 %add10 to i64 1701 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 1702 %3 = load double, double* %arrayidx12, align 8 1703 %conv13 = fptosi double %3 to i32 1704 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1705 ret <4 x i32> %vecinit14 1706; P9BE-LABEL: fromDiffMemVarAConvdtoi 1707; P9LE-LABEL: fromDiffMemVarAConvdtoi 1708; P8BE-LABEL: fromDiffMemVarAConvdtoi 1709; P8LE-LABEL: fromDiffMemVarAConvdtoi 1710; P9BE: lfdux 1711; P9BE: lfd 1712; P9BE: lfd 1713; P9BE: lfd 1714; P9BE: xxmrghd 1715; P9BE: xxmrghd 1716; P9BE: xvcvdpsxws 1717; P9BE: xvcvdpsxws 1718; P9BE: vmrgew v2 1719; P9LE: lfdux 1720; P9LE: lfd 1721; P9LE: lfd 1722; P9LE: lfd 1723; P9LE: xxmrghd 1724; P9LE: xxmrghd 1725; P9LE: xvcvdpsxws 1726; P9LE: xvcvdpsxws 1727; P9LE: vmrgew v2 1728; P8BE: lfdux 1729; P8BE: lfd 1730; P8BE: lfd 1731; P8BE: lfd 1732; P8BE: xxmrghd 1733; P8BE: xxmrghd 1734; P8BE: xvcvdpsxws 1735; P8BE: xvcvdpsxws 1736; P8BE: vmrgew v2 1737; P8LE: lfdux 1738; P8LE: lfd 1739; P8LE: lfd 1740; P8LE: lfd 1741; P8LE: xxmrghd 1742; P8LE: xxmrghd 1743; P8LE: xvcvdpsxws 1744; P8LE: xvcvdpsxws 1745; P8LE: vmrgew v2 1746} 1747 1748; Function Attrs: norecurse nounwind readonly 1749define <4 x i32> @fromDiffMemVarDConvdtoi(double* nocapture readonly %arr, i32 signext %elem) { 1750entry: 1751 %idxprom = sext i32 %elem to i64 1752 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 1753 %0 = load double, double* %arrayidx, align 8 1754 %conv = fptosi double %0 to i32 1755 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1756 %sub = add nsw i32 %elem, -1 1757 %idxprom1 = sext i32 %sub to i64 1758 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 1759 %1 = load double, double* %arrayidx2, align 8 1760 %conv3 = fptosi double %1 to i32 1761 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1762 %sub5 = add nsw i32 %elem, -2 1763 %idxprom6 = sext i32 %sub5 to i64 1764 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 1765 %2 = load double, double* %arrayidx7, align 8 1766 %conv8 = fptosi double %2 to i32 1767 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1768 %sub10 = add nsw i32 %elem, -3 1769 %idxprom11 = sext i32 %sub10 to i64 1770 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 1771 %3 = load double, double* %arrayidx12, align 8 1772 %conv13 = fptosi double %3 to i32 1773 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1774 ret <4 x i32> %vecinit14 1775; P9BE-LABEL: fromDiffMemVarDConvdtoi 1776; P9LE-LABEL: fromDiffMemVarDConvdtoi 1777; P8BE-LABEL: fromDiffMemVarDConvdtoi 1778; P8LE-LABEL: fromDiffMemVarDConvdtoi 1779; P9BE: lfdux 1780; P9BE: lfd 1781; P9BE: lfd 1782; P9BE: lfd 1783; P9BE: xxmrghd 1784; P9BE: xxmrghd 1785; P9BE: xvcvdpsxws 1786; P9BE: xvcvdpsxws 1787; P9BE: vmrgew v2 1788; P9LE: lfdux 1789; P9LE: lfd 1790; P9LE: lfd 1791; P9LE: lfd 1792; P9LE: xxmrghd 1793; P9LE: xxmrghd 1794; P9LE: xvcvdpsxws 1795; P9LE: xvcvdpsxws 1796; P9LE: vmrgew v2 1797; P8BE: lfdux 1798; P8BE: lfd 1799; P8BE: lfd 1800; P8BE: lfd 1801; P8BE: xxmrghd 1802; P8BE: xxmrghd 1803; P8BE: xvcvdpsxws 1804; P8BE: xvcvdpsxws 1805; P8BE: vmrgew v2 1806; P8LE: lfdux 1807; P8LE: lfd 1808; P8LE: lfd 1809; P8LE: lfd 1810; P8LE: xxmrghd 1811; P8LE: xxmrghd 1812; P8LE: xvcvdpsxws 1813; P8LE: xvcvdpsxws 1814; P8LE: vmrgew v2 1815} 1816 1817; Function Attrs: norecurse nounwind readnone 1818define <4 x i32> @spltRegValConvdtoi(double %val) { 1819entry: 1820 %conv = fptosi double %val to i32 1821 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1822 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1823 ret <4 x i32> %splat.splat 1824; P9BE-LABEL: spltRegValConvdtoi 1825; P9LE-LABEL: spltRegValConvdtoi 1826; P8BE-LABEL: spltRegValConvdtoi 1827; P8LE-LABEL: spltRegValConvdtoi 1828; P9BE: xscvdpsxws 1829; P9BE: xxspltw 1830; P9BE: blr 1831; P9LE: xscvdpsxws 1832; P9LE: xxspltw 1833; P9LE: blr 1834; P8BE: xscvdpsxws 1835; P8BE: xxspltw 1836; P8BE: blr 1837; P8LE: xscvdpsxws 1838; P8LE: xxspltw 1839; P8LE: blr 1840} 1841 1842; Function Attrs: norecurse nounwind readonly 1843define <4 x i32> @spltMemValConvdtoi(double* nocapture readonly %ptr) { 1844entry: 1845 %0 = load double, double* %ptr, align 8 1846 %conv = fptosi double %0 to i32 1847 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1848 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1849 ret <4 x i32> %splat.splat 1850; P9BE-LABEL: spltMemValConvdtoi 1851; P9LE-LABEL: spltMemValConvdtoi 1852; P8BE-LABEL: spltMemValConvdtoi 1853; P8LE-LABEL: spltMemValConvdtoi 1854; P9BE: lfd 1855; P9BE: xscvdpsxws 1856; P9BE: xxspltw 1857; P9BE: blr 1858; P9LE: lfd 1859; P9LE: xscvdpsxws 1860; P9LE: xxspltw 1861; P9LE: blr 1862; P8BE: lfdx 1863; P8BE: xscvdpsxws 1864; P8BE: xxspltw 1865; P8BE: blr 1866; P8LE: lfdx 1867; P8LE: xscvdpsxws 1868; P8LE: xxspltw 1869; P8LE: blr 1870} 1871; Function Attrs: norecurse nounwind readnone 1872define <4 x i32> @allZeroui() { 1873entry: 1874 ret <4 x i32> zeroinitializer 1875; P9BE-LABEL: allZeroui 1876; P9LE-LABEL: allZeroui 1877; P8BE-LABEL: allZeroui 1878; P8LE-LABEL: allZeroui 1879; P9BE: xxlxor v2, v2, v2 1880; P9BE: blr 1881; P9LE: xxlxor v2, v2, v2 1882; P9LE: blr 1883; P8BE: xxlxor v2, v2, v2 1884; P8BE: blr 1885; P8LE: xxlxor v2, v2, v2 1886; P8LE: blr 1887} 1888 1889; Function Attrs: norecurse nounwind readnone 1890define <4 x i32> @allOneui() { 1891entry: 1892 ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> 1893; P9BE-LABEL: allOneui 1894; P9LE-LABEL: allOneui 1895; P8BE-LABEL: allOneui 1896; P8LE-LABEL: allOneui 1897; P9BE: xxspltib v2, 255 1898; P9BE: blr 1899; P9LE: xxspltib v2, 255 1900; P9LE: blr 1901; P8BE: vspltisb v2, -1 1902; P8BE: blr 1903; P8LE: vspltisb v2, -1 1904; P8LE: blr 1905} 1906 1907; Function Attrs: norecurse nounwind readnone 1908define <4 x i32> @spltConst1ui() { 1909entry: 1910 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1> 1911; P9BE-LABEL: spltConst1ui 1912; P9LE-LABEL: spltConst1ui 1913; P8BE-LABEL: spltConst1ui 1914; P8LE-LABEL: spltConst1ui 1915; P9BE: vspltisw v2, 1 1916; P9BE: blr 1917; P9LE: vspltisw v2, 1 1918; P9LE: blr 1919; P8BE: vspltisw v2, 1 1920; P8BE: blr 1921; P8LE: vspltisw v2, 1 1922; P8LE: blr 1923} 1924 1925; Function Attrs: norecurse nounwind readnone 1926define <4 x i32> @spltConst16kui() { 1927entry: 1928 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 1929; P9BE-LABEL: spltConst16kui 1930; P9LE-LABEL: spltConst16kui 1931; P8BE-LABEL: spltConst16kui 1932; P8LE-LABEL: spltConst16kui 1933; P9BE: vspltisw v2, -15 1934; P9BE: vsrw v2, v2, v2 1935; P9BE: blr 1936; P9LE: vspltisw v2, -15 1937; P9LE: vsrw v2, v2, v2 1938; P9LE: blr 1939; P8BE: vspltisw v2, -15 1940; P8BE: vsrw v2, v2, v2 1941; P8BE: blr 1942; P8LE: vspltisw v2, -15 1943; P8LE: vsrw v2, v2, v2 1944; P8LE: blr 1945} 1946 1947; Function Attrs: norecurse nounwind readnone 1948define <4 x i32> @spltConst32kui() { 1949entry: 1950 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 1951; P9BE-LABEL: spltConst32kui 1952; P9LE-LABEL: spltConst32kui 1953; P8BE-LABEL: spltConst32kui 1954; P8LE-LABEL: spltConst32kui 1955; P9BE: vspltisw v2, -16 1956; P9BE: vsrw v2, v2, v2 1957; P9BE: blr 1958; P9LE: vspltisw v2, -16 1959; P9LE: vsrw v2, v2, v2 1960; P9LE: blr 1961; P8BE: vspltisw v2, -16 1962; P8BE: vsrw v2, v2, v2 1963; P8BE: blr 1964; P8LE: vspltisw v2, -16 1965; P8LE: vsrw v2, v2, v2 1966; P8LE: blr 1967} 1968 1969; Function Attrs: norecurse nounwind readnone 1970define <4 x i32> @fromRegsui(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c, i32 zeroext %d) { 1971entry: 1972 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 1973 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 1974 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 1975 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3 1976 ret <4 x i32> %vecinit3 1977; P9BE-LABEL: fromRegsui 1978; P9LE-LABEL: fromRegsui 1979; P8BE-LABEL: fromRegsui 1980; P8LE-LABEL: fromRegsui 1981; P9BE-DAG: mtvsrdd [[REG1:v[0-9]+]], r3, r5 1982; P9BE-DAG: mtvsrdd [[REG2:v[0-9]+]], r4, r6 1983; P9BE: vmrgow v2, [[REG1]], [[REG2]] 1984; P9BE: blr 1985; P9LE-DAG: mtvsrdd [[REG1:v[0-9]+]], r5, r3 1986; P9LE-DAG: mtvsrdd [[REG2:v[0-9]+]], r6, r4 1987; P9LE: vmrgow v2, [[REG2]], [[REG1]] 1988; P9LE: blr 1989; P8BE-DAG: mtvsrwz {{[vf]}}[[REG1:[0-9]+]], r3 1990; P8BE-DAG: mtvsrwz {{[vf]}}[[REG2:[0-9]+]], r4 1991; P8BE-DAG: mtvsrwz {{[vf]}}[[REG3:[0-9]+]], r5 1992; P8BE-DAG: mtvsrwz {{[vf]}}[[REG4:[0-9]+]], r6 1993; P8BE-DAG: xxmrghd [[REG5:v[0-9]+]], {{[v][s]*}}[[REG1]], {{[v][s]*}}[[REG3]] 1994; P8BE-DAG: xxmrghd [[REG6:v[0-9]+]], {{[v][s]*}}[[REG2]], {{[v][s]*}}[[REG4]] 1995; P8BE: vmrgow v2, [[REG5]], [[REG6]] 1996; P8LE-DAG: mtvsrwz {{[vf]}}[[REG1:[0-9]+]], r3 1997; P8LE-DAG: mtvsrwz {{[vf]}}[[REG2:[0-9]+]], r4 1998; P8LE-DAG: mtvsrwz {{[vf]}}[[REG3:[0-9]+]], r5 1999; P8LE-DAG: mtvsrwz {{[vf]}}[[REG4:[0-9]+]], r6 2000; P8LE: xxmrghd [[REG5:v[0-9]+]], {{[v][s]*}}[[REG3]], {{[v][s]*}}[[REG1]] 2001; P8LE: xxmrghd [[REG6:v[0-9]+]], {{[v][s]*}}[[REG4]], {{[v][s]*}}[[REG2]] 2002; P8LE: vmrgow v2, [[REG6]], [[REG5]] 2003} 2004 2005; Function Attrs: norecurse nounwind readnone 2006define <4 x i32> @fromDiffConstsui() { 2007entry: 2008 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19> 2009; P9BE-LABEL: fromDiffConstsui 2010; P9LE-LABEL: fromDiffConstsui 2011; P8BE-LABEL: fromDiffConstsui 2012; P8LE-LABEL: fromDiffConstsui 2013; P9BE: lxv 2014; P9BE: blr 2015; P9LE: lxv 2016; P9LE: blr 2017; P8BE: lxvw4x 2018; P8BE: blr 2019; P8LE: lvx 2020; P8LE-NOT: xxswapd 2021; P8LE: blr 2022} 2023 2024; Function Attrs: norecurse nounwind readonly 2025define <4 x i32> @fromDiffMemConsAui(i32* nocapture readonly %arr) { 2026entry: 2027 %0 = load i32, i32* %arr, align 4 2028 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2029 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 1 2030 %1 = load i32, i32* %arrayidx1, align 4 2031 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2032 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 2033 %2 = load i32, i32* %arrayidx3, align 4 2034 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2035 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 3 2036 %3 = load i32, i32* %arrayidx5, align 4 2037 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2038 ret <4 x i32> %vecinit6 2039; P9BE-LABEL: fromDiffMemConsAui 2040; P9LE-LABEL: fromDiffMemConsAui 2041; P8BE-LABEL: fromDiffMemConsAui 2042; P8LE-LABEL: fromDiffMemConsAui 2043; P9BE: lxv 2044; P9BE: blr 2045; P9LE: lxv 2046; P9LE: blr 2047; P8BE: lxvw4x 2048; P8BE: blr 2049; P8LE: lxvd2x 2050; P8LE: xxswapd 2051; P8LE: blr 2052} 2053 2054; Function Attrs: norecurse nounwind readonly 2055define <4 x i32> @fromDiffMemConsDui(i32* nocapture readonly %arr) { 2056entry: 2057 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3 2058 %0 = load i32, i32* %arrayidx, align 4 2059 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2060 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 2061 %1 = load i32, i32* %arrayidx1, align 4 2062 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2063 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 1 2064 %2 = load i32, i32* %arrayidx3, align 4 2065 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2066 %3 = load i32, i32* %arr, align 4 2067 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2068 ret <4 x i32> %vecinit6 2069; P9BE-LABEL: fromDiffMemConsDui 2070; P9LE-LABEL: fromDiffMemConsDui 2071; P8BE-LABEL: fromDiffMemConsDui 2072; P8LE-LABEL: fromDiffMemConsDui 2073; P9BE: lxv 2074; P9BE: lxv 2075; P9BE: vperm 2076; P9BE: blr 2077; P9LE: lxv 2078; P9LE: lxv 2079; P9LE: vperm 2080; P9LE: blr 2081; P8BE: lxvw4x 2082; P8BE: lxvw4x 2083; P8BE: vperm 2084; P8BE: blr 2085; P8LE: lxvd2x 2086; P8LE-DAG: lvx 2087; P8LE-NOT: xxswapd 2088; P8LE: xxswapd 2089; P8LE: vperm 2090; P8LE: blr 2091} 2092 2093; Function Attrs: norecurse nounwind readonly 2094define <4 x i32> @fromDiffMemVarAui(i32* nocapture readonly %arr, i32 signext %elem) { 2095entry: 2096 %idxprom = sext i32 %elem to i64 2097 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2098 %0 = load i32, i32* %arrayidx, align 4 2099 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2100 %add = add nsw i32 %elem, 1 2101 %idxprom1 = sext i32 %add to i64 2102 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 2103 %1 = load i32, i32* %arrayidx2, align 4 2104 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2105 %add4 = add nsw i32 %elem, 2 2106 %idxprom5 = sext i32 %add4 to i64 2107 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 2108 %2 = load i32, i32* %arrayidx6, align 4 2109 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 2110 %add8 = add nsw i32 %elem, 3 2111 %idxprom9 = sext i32 %add8 to i64 2112 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 2113 %3 = load i32, i32* %arrayidx10, align 4 2114 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 2115 ret <4 x i32> %vecinit11 2116; P9BE-LABEL: fromDiffMemVarAui 2117; P9LE-LABEL: fromDiffMemVarAui 2118; P8BE-LABEL: fromDiffMemVarAui 2119; P8LE-LABEL: fromDiffMemVarAui 2120; P9BE: sldi r4, r4, 2 2121; P9BE: lxvx v2, r3, r4 2122; P9BE: blr 2123; P9LE: sldi r4, r4, 2 2124; P9LE: lxvx v2, r3, r4 2125; P9LE: blr 2126; P8BE: sldi r4, r4, 2 2127; P8BE: lxvw4x {{[vs0-9]+}}, r3, r4 2128; P8BE: blr 2129; P8LE: sldi r4, r4, 2 2130; P8LE: lxvd2x {{[vs0-9]+}}, r3, r4 2131; P8LE: xxswapd 2132; P8LE: blr 2133} 2134 2135; Function Attrs: norecurse nounwind readonly 2136define <4 x i32> @fromDiffMemVarDui(i32* nocapture readonly %arr, i32 signext %elem) { 2137entry: 2138 %idxprom = sext i32 %elem to i64 2139 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2140 %0 = load i32, i32* %arrayidx, align 4 2141 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2142 %sub = add nsw i32 %elem, -1 2143 %idxprom1 = sext i32 %sub to i64 2144 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 2145 %1 = load i32, i32* %arrayidx2, align 4 2146 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2147 %sub4 = add nsw i32 %elem, -2 2148 %idxprom5 = sext i32 %sub4 to i64 2149 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 2150 %2 = load i32, i32* %arrayidx6, align 4 2151 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 2152 %sub8 = add nsw i32 %elem, -3 2153 %idxprom9 = sext i32 %sub8 to i64 2154 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 2155 %3 = load i32, i32* %arrayidx10, align 4 2156 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 2157 ret <4 x i32> %vecinit11 2158; P9BE-LABEL: fromDiffMemVarDui 2159; P9LE-LABEL: fromDiffMemVarDui 2160; P8BE-LABEL: fromDiffMemVarDui 2161; P8LE-LABEL: fromDiffMemVarDui 2162; P9BE-DAG: sldi {{r[0-9]+}}, r4, 2 2163; P9BE-DAG: addi r3, r3, -12 2164; P9BE-DAG: lxvx {{v[0-9]+}}, 0, r3 2165; P9BE-DAG: lxvx 2166; P9BE: vperm 2167; P9BE: blr 2168; P9LE-DAG: sldi {{r[0-9]+}}, r4, 2 2169; P9LE-DAG: addi r3, r3, -12 2170; P9LE-DAG: lxvx {{v[0-9]+}}, 0, r3 2171; P9LE-DAG: lxv 2172; P9LE: vperm 2173; P9LE: blr 2174; P8BE-DAG: sldi {{r[0-9]+}}, r4, 2 2175; P8BE-DAG: lxvw4x {{v[0-9]+}}, 0, r3 2176; P8BE-DAG: lxvw4x 2177; P8BE: vperm 2178; P8BE: blr 2179; P8LE-DAG: sldi {{r[0-9]+}}, r4, 2 2180; P8LE-DAG: lvx 2181; P8LE-DAG: lvx 2182; P8LE: vperm 2183; P8LE: blr 2184} 2185 2186; Function Attrs: norecurse nounwind readonly 2187define <4 x i32> @fromRandMemConsui(i32* nocapture readonly %arr) { 2188entry: 2189 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4 2190 %0 = load i32, i32* %arrayidx, align 4 2191 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2192 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18 2193 %1 = load i32, i32* %arrayidx1, align 4 2194 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2195 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 2196 %2 = load i32, i32* %arrayidx3, align 4 2197 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2198 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 88 2199 %3 = load i32, i32* %arrayidx5, align 4 2200 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2201 ret <4 x i32> %vecinit6 2202; P9BE-LABEL: fromRandMemConsui 2203; P9LE-LABEL: fromRandMemConsui 2204; P8BE-LABEL: fromRandMemConsui 2205; P8LE-LABEL: fromRandMemConsui 2206; P9BE: lwz 2207; P9BE: lwz 2208; P9BE: lwz 2209; P9BE: lwz 2210; P9BE: mtvsrdd 2211; P9BE: mtvsrdd 2212; P9BE: vmrgow 2213; P9LE: lwz 2214; P9LE: lwz 2215; P9LE: lwz 2216; P9LE: lwz 2217; P9LE: mtvsrdd 2218; P9LE: mtvsrdd 2219; P9LE: vmrgow 2220; P8BE: lwz 2221; P8BE: lwz 2222; P8BE: lwz 2223; P8BE: lwz 2224; P8BE: mtvsrwz 2225; P8BE: mtvsrwz 2226; P8BE: mtvsrwz 2227; P8BE: mtvsrwz 2228; P8BE: xxmrghd 2229; P8BE: xxmrghd 2230; P8BE: vmrgow 2231; P8LE: lwz 2232; P8LE: lwz 2233; P8LE: lwz 2234; P8LE: lwz 2235; P8LE: mtvsrwz 2236; P8LE: mtvsrwz 2237; P8LE: mtvsrwz 2238; P8LE: mtvsrwz 2239; P8LE: xxmrghd 2240; P8LE: xxmrghd 2241; P8LE: vmrgow 2242} 2243 2244; Function Attrs: norecurse nounwind readonly 2245define <4 x i32> @fromRandMemVarui(i32* nocapture readonly %arr, i32 signext %elem) { 2246entry: 2247 %add = add nsw i32 %elem, 4 2248 %idxprom = sext i32 %add to i64 2249 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2250 %0 = load i32, i32* %arrayidx, align 4 2251 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2252 %add1 = add nsw i32 %elem, 1 2253 %idxprom2 = sext i32 %add1 to i64 2254 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 %idxprom2 2255 %1 = load i32, i32* %arrayidx3, align 4 2256 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2257 %add5 = add nsw i32 %elem, 2 2258 %idxprom6 = sext i32 %add5 to i64 2259 %arrayidx7 = getelementptr inbounds i32, i32* %arr, i64 %idxprom6 2260 %2 = load i32, i32* %arrayidx7, align 4 2261 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2 2262 %add9 = add nsw i32 %elem, 8 2263 %idxprom10 = sext i32 %add9 to i64 2264 %arrayidx11 = getelementptr inbounds i32, i32* %arr, i64 %idxprom10 2265 %3 = load i32, i32* %arrayidx11, align 4 2266 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3 2267 ret <4 x i32> %vecinit12 2268; P9BE-LABEL: fromRandMemVarui 2269; P9LE-LABEL: fromRandMemVarui 2270; P8BE-LABEL: fromRandMemVarui 2271; P8LE-LABEL: fromRandMemVarui 2272; P9BE: sldi r4, r4, 2 2273; P9BE: lwz 2274; P9BE: lwz 2275; P9BE: lwz 2276; P9BE: lwz 2277; P9BE: mtvsrdd 2278; P9BE: mtvsrdd 2279; P9BE: vmrgow 2280; P9LE: sldi r4, r4, 2 2281; P9LE: lwz 2282; P9LE: lwz 2283; P9LE: lwz 2284; P9LE: lwz 2285; P9LE: mtvsrdd 2286; P9LE: mtvsrdd 2287; P9LE: vmrgow 2288; P8BE: sldi r4, r4, 2 2289; P8BE: lwz 2290; P8BE: lwz 2291; P8BE: lwz 2292; P8BE: lwz 2293; P8BE: mtvsrwz 2294; P8BE: mtvsrwz 2295; P8BE: mtvsrwz 2296; P8BE: mtvsrwz 2297; P8BE: xxmrghd 2298; P8BE: xxmrghd 2299; P8BE: vmrgow 2300; P8LE: sldi r4, r4, 2 2301; P8LE: lwz 2302; P8LE: lwz 2303; P8LE: lwz 2304; P8LE: lwz 2305; P8LE: mtvsrwz 2306; P8LE: mtvsrwz 2307; P8LE: mtvsrwz 2308; P8LE: mtvsrwz 2309; P8LE: xxmrghd 2310; P8LE: xxmrghd 2311; P8LE: vmrgow 2312} 2313 2314; Function Attrs: norecurse nounwind readnone 2315define <4 x i32> @spltRegValui(i32 zeroext %val) { 2316entry: 2317 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0 2318 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2319 ret <4 x i32> %splat.splat 2320; P9BE-LABEL: spltRegValui 2321; P9LE-LABEL: spltRegValui 2322; P8BE-LABEL: spltRegValui 2323; P8LE-LABEL: spltRegValui 2324; P9BE: mtvsrws v2, r3 2325; P9BE: blr 2326; P9LE: mtvsrws v2, r3 2327; P9LE: blr 2328; P8BE: mtvsrwz {{[vsf0-9]+}}, r3 2329; P8BE: xxspltw v2, {{[vsf0-9]+}}, 1 2330; P8BE: blr 2331; P8LE: mtvsrwz {{[vsf0-9]+}}, r3 2332; P8LE: xxspltw v2, {{[vsf0-9]+}}, 1 2333; P8LE: blr 2334} 2335 2336; Function Attrs: norecurse nounwind readonly 2337define <4 x i32> @spltMemValui(i32* nocapture readonly %ptr) { 2338entry: 2339 %0 = load i32, i32* %ptr, align 4 2340 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 2341 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2342 ret <4 x i32> %splat.splat 2343; P9BE-LABEL: spltMemValui 2344; P9LE-LABEL: spltMemValui 2345; P8BE-LABEL: spltMemValui 2346; P8LE-LABEL: spltMemValui 2347; P9BE: lfiwzx f0, 0, r3 2348; P9BE: xxsldwi vs0, f0, f0, 1 2349; P9BE: xxspltw v2, vs0, 0 2350; P9BE: blr 2351; P9LE: lfiwzx f0, 0, r3 2352; P9LE: xxpermdi vs0, f0, f0, 2 2353; P9LE: xxspltw v2, vs0, 3 2354; P9LE: blr 2355; P8BE: lfiwzx f0, 0, r3 2356; P8BE: xxsldwi vs0, f0, f0, 1 2357; P8BE: xxspltw v2, vs0, 0 2358; P8BE: blr 2359; P8LE: lfiwzx f0, 0, r3 2360; P8LE: xxpermdi vs0, f0, f0, 2 2361; P8LE: xxspltw v2, vs0, 3 2362; P8LE: blr 2363} 2364 2365; Function Attrs: norecurse nounwind readnone 2366define <4 x i32> @spltCnstConvftoui() { 2367entry: 2368 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 2369; P9BE-LABEL: spltCnstConvftoui 2370; P9LE-LABEL: spltCnstConvftoui 2371; P8BE-LABEL: spltCnstConvftoui 2372; P8LE-LABEL: spltCnstConvftoui 2373; P9BE: vspltisw v2, 4 2374; P9BE: blr 2375; P9LE: vspltisw v2, 4 2376; P9LE: blr 2377; P8BE: vspltisw v2, 4 2378; P8BE: blr 2379; P8LE: vspltisw v2, 4 2380; P8LE: blr 2381} 2382 2383; Function Attrs: norecurse nounwind readnone 2384define <4 x i32> @fromRegsConvftoui(float %a, float %b, float %c, float %d) { 2385entry: 2386 %conv = fptoui float %a to i32 2387 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2388 %conv1 = fptoui float %b to i32 2389 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 2390 %conv3 = fptoui float %c to i32 2391 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 2392 %conv5 = fptoui float %d to i32 2393 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 2394 ret <4 x i32> %vecinit6 2395; P9BE-LABEL: fromRegsConvftoui 2396; P9LE-LABEL: fromRegsConvftoui 2397; P8BE-LABEL: fromRegsConvftoui 2398; P8LE-LABEL: fromRegsConvftoui 2399; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 2400; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 2401; P9BE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2402; P9BE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2403; P9BE: vmrgew v2, [[REG3]], [[REG4]] 2404; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 2405; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 2406; P9LE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2407; P9LE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2408; P9LE: vmrgew v2, [[REG4]], [[REG3]] 2409; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 2410; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 2411; P8BE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2412; P8BE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2413; P8BE: vmrgew v2, [[REG3]], [[REG4]] 2414; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 2415; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 2416; P8LE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2417; P8LE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2418; P8LE: vmrgew v2, [[REG4]], [[REG3]] 2419} 2420 2421; Function Attrs: norecurse nounwind readnone 2422define <4 x i32> @fromDiffConstsConvftoui() { 2423entry: 2424 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 2425; P9BE-LABEL: fromDiffConstsConvftoui 2426; P9LE-LABEL: fromDiffConstsConvftoui 2427; P8BE-LABEL: fromDiffConstsConvftoui 2428; P8LE-LABEL: fromDiffConstsConvftoui 2429; P9BE: lxv 2430; P9BE: blr 2431; P9LE: lxv 2432; P9LE: blr 2433; P8BE: lxvw4x 2434; P8BE: blr 2435; P8LE: lvx 2436; P8LE-NOT: xxswapd 2437; P8LE: blr 2438} 2439 2440; Function Attrs: norecurse nounwind readonly 2441define <4 x i32> @fromDiffMemConsAConvftoui(float* nocapture readonly %ptr) { 2442entry: 2443 %0 = bitcast float* %ptr to <4 x float>* 2444 %1 = load <4 x float>, <4 x float>* %0, align 4 2445 %2 = fptoui <4 x float> %1 to <4 x i32> 2446 ret <4 x i32> %2 2447; P9BE-LABEL: fromDiffMemConsAConvftoui 2448; P9LE-LABEL: fromDiffMemConsAConvftoui 2449; P8BE-LABEL: fromDiffMemConsAConvftoui 2450; P8LE-LABEL: fromDiffMemConsAConvftoui 2451; P9BE: lxv [[REG1:[vs0-9]+]], 0(r3) 2452; P9BE: xvcvspuxws v2, [[REG1]] 2453; P9BE: blr 2454; P9LE: lxv [[REG1:[vs0-9]+]], 0(r3) 2455; P9LE: xvcvspuxws v2, [[REG1]] 2456; P9LE: blr 2457; P8BE: lxvw4x [[REG1:[vs0-9]+]], 0, r3 2458; P8BE: xvcvspuxws v2, [[REG1]] 2459; P8BE: blr 2460; P8LE: lxvd2x [[REG1:[vs0-9]+]], 0, r3 2461; P8LE: xxswapd v2, [[REG1]] 2462; P8LE: xvcvspuxws v2, v2 2463; P8LE: blr 2464} 2465 2466; Function Attrs: norecurse nounwind readonly 2467define <4 x i32> @fromDiffMemConsDConvftoui(float* nocapture readonly %ptr) { 2468entry: 2469 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 2470 %0 = load float, float* %arrayidx, align 4 2471 %conv = fptoui float %0 to i32 2472 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2473 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 2474 %1 = load float, float* %arrayidx1, align 4 2475 %conv2 = fptoui float %1 to i32 2476 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 2477 %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1 2478 %2 = load float, float* %arrayidx4, align 4 2479 %conv5 = fptoui float %2 to i32 2480 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 2481 %3 = load float, float* %ptr, align 4 2482 %conv8 = fptoui float %3 to i32 2483 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 2484 ret <4 x i32> %vecinit9 2485; P9BE-LABEL: fromDiffMemConsDConvftoui 2486; P9LE-LABEL: fromDiffMemConsDConvftoui 2487; P8BE-LABEL: fromDiffMemConsDConvftoui 2488; P8LE-LABEL: fromDiffMemConsDConvftoui 2489; P9BE: lxv 2490; P9BE: lxv 2491; P9BE: vperm 2492; P9BE: xvcvspuxws 2493; P9BE: blr 2494; P9LE: lxv 2495; P9LE: lxv 2496; P9LE: vperm 2497; P9LE: xvcvspuxws 2498; P9LE: blr 2499; P8BE: lxvw4x 2500; P8BE: lxvw4x 2501; P8BE: vperm 2502; P8BE: xvcvspuxws 2503; P8BE: blr 2504; P8LE-DAG: lxvd2x 2505; P8LE-DAG: lvx 2506; P8LE: xxswapd 2507; P8LE: vperm 2508; P8LE: xvcvspuxws 2509; P8LE: blr 2510} 2511 2512; Function Attrs: norecurse nounwind readonly 2513define <4 x i32> @fromDiffMemVarAConvftoui(float* nocapture readonly %arr, i32 signext %elem) { 2514entry: 2515 %idxprom = sext i32 %elem to i64 2516 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 2517 %0 = load float, float* %arrayidx, align 4 2518 %conv = fptoui float %0 to i32 2519 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2520 %add = add nsw i32 %elem, 1 2521 %idxprom1 = sext i32 %add to i64 2522 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 2523 %1 = load float, float* %arrayidx2, align 4 2524 %conv3 = fptoui float %1 to i32 2525 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2526 %add5 = add nsw i32 %elem, 2 2527 %idxprom6 = sext i32 %add5 to i64 2528 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 2529 %2 = load float, float* %arrayidx7, align 4 2530 %conv8 = fptoui float %2 to i32 2531 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2532 %add10 = add nsw i32 %elem, 3 2533 %idxprom11 = sext i32 %add10 to i64 2534 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 2535 %3 = load float, float* %arrayidx12, align 4 2536 %conv13 = fptoui float %3 to i32 2537 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2538 ret <4 x i32> %vecinit14 2539; P9BE-LABEL: fromDiffMemVarAConvftoui 2540; P9LE-LABEL: fromDiffMemVarAConvftoui 2541; P8BE-LABEL: fromDiffMemVarAConvftoui 2542; P8LE-LABEL: fromDiffMemVarAConvftoui 2543; FIXME: implement finding consecutive loads with pre-inc 2544; P9BE: lfsux 2545; P9LE: lfsux 2546; P8BE: lfsux 2547; P8LE: lfsux 2548} 2549 2550; Function Attrs: norecurse nounwind readonly 2551define <4 x i32> @fromDiffMemVarDConvftoui(float* nocapture readonly %arr, i32 signext %elem) { 2552entry: 2553 %idxprom = sext i32 %elem to i64 2554 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 2555 %0 = load float, float* %arrayidx, align 4 2556 %conv = fptoui float %0 to i32 2557 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2558 %sub = add nsw i32 %elem, -1 2559 %idxprom1 = sext i32 %sub to i64 2560 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 2561 %1 = load float, float* %arrayidx2, align 4 2562 %conv3 = fptoui float %1 to i32 2563 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2564 %sub5 = add nsw i32 %elem, -2 2565 %idxprom6 = sext i32 %sub5 to i64 2566 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 2567 %2 = load float, float* %arrayidx7, align 4 2568 %conv8 = fptoui float %2 to i32 2569 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2570 %sub10 = add nsw i32 %elem, -3 2571 %idxprom11 = sext i32 %sub10 to i64 2572 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 2573 %3 = load float, float* %arrayidx12, align 4 2574 %conv13 = fptoui float %3 to i32 2575 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2576 ret <4 x i32> %vecinit14 2577; P9BE-LABEL: fromDiffMemVarDConvftoui 2578; P9LE-LABEL: fromDiffMemVarDConvftoui 2579; P8BE-LABEL: fromDiffMemVarDConvftoui 2580; P8LE-LABEL: fromDiffMemVarDConvftoui 2581; FIXME: implement finding consecutive loads with pre-inc 2582; P9BE: lfsux 2583; P9LE: lfsux 2584; P8BE: lfsux 2585; P8LE: lfsux 2586} 2587 2588; Function Attrs: norecurse nounwind readnone 2589define <4 x i32> @spltRegValConvftoui(float %val) { 2590entry: 2591 %conv = fptoui float %val to i32 2592 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2593 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2594 ret <4 x i32> %splat.splat 2595; P9BE-LABEL: spltRegValConvftoui 2596; P9LE-LABEL: spltRegValConvftoui 2597; P8BE-LABEL: spltRegValConvftoui 2598; P8LE-LABEL: spltRegValConvftoui 2599; P9BE: xscvdpuxws f[[REG1:[0-9]+]], f1 2600; P9BE: xxspltw v2, vs[[REG1]], 1 2601; P9BE: blr 2602; P9LE: xscvdpuxws f[[REG1:[0-9]+]], f1 2603; P9LE: xxspltw v2, vs[[REG1]], 1 2604; P9LE: blr 2605; P8BE: xscvdpuxws f[[REG1:[0-9]+]], f1 2606; P8BE: xxspltw v2, vs[[REG1]], 1 2607; P8BE: blr 2608; P8LE: xscvdpuxws f[[REG1:[0-9]+]], f1 2609; P8LE: xxspltw v2, vs[[REG1]], 1 2610; P8LE: blr 2611} 2612 2613; Function Attrs: norecurse nounwind readonly 2614define <4 x i32> @spltMemValConvftoui(float* nocapture readonly %ptr) { 2615entry: 2616 %0 = load float, float* %ptr, align 4 2617 %conv = fptoui float %0 to i32 2618 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2619 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2620 ret <4 x i32> %splat.splat 2621; P9BE-LABEL: spltMemValConvftoui 2622; P9LE-LABEL: spltMemValConvftoui 2623; P8BE-LABEL: spltMemValConvftoui 2624; P8LE-LABEL: spltMemValConvftoui 2625; P9BE: lxvwsx [[REG1:[vs0-9]+]], 0, r3 2626; P9BE: xvcvspuxws v2, [[REG1]] 2627; P9LE: [[REG1:[vs0-9]+]], 0, r3 2628; P9LE: xvcvspuxws v2, [[REG1]] 2629; P8BE: lfsx [[REG1:f[0-9]+]], 0, r3 2630; P8BE: xscvdpuxws f[[REG2:[0-9]+]], [[REG1]] 2631; P8BE: xxspltw v2, vs[[REG2]], 1 2632; P8LE: lfsx [[REG1:f[0-9]+]], 0, r3 2633; P8LE: xscvdpuxws f[[REG2:[vs0-9]+]], [[REG1]] 2634; P8LE: xxspltw v2, vs[[REG2]], 1 2635} 2636 2637; Function Attrs: norecurse nounwind readnone 2638define <4 x i32> @spltCnstConvdtoui() { 2639entry: 2640 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 2641; P9BE-LABEL: spltCnstConvdtoui 2642; P9LE-LABEL: spltCnstConvdtoui 2643; P8BE-LABEL: spltCnstConvdtoui 2644; P8LE-LABEL: spltCnstConvdtoui 2645; P9BE: vspltisw v2, 4 2646; P9BE: blr 2647; P9LE: vspltisw v2, 4 2648; P9LE: blr 2649; P8BE: vspltisw v2, 4 2650; P8BE: blr 2651; P8LE: vspltisw v2, 4 2652; P8LE: blr 2653} 2654 2655; Function Attrs: norecurse nounwind readnone 2656define <4 x i32> @fromRegsConvdtoui(double %a, double %b, double %c, double %d) { 2657entry: 2658 %conv = fptoui double %a to i32 2659 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2660 %conv1 = fptoui double %b to i32 2661 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 2662 %conv3 = fptoui double %c to i32 2663 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 2664 %conv5 = fptoui double %d to i32 2665 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 2666 ret <4 x i32> %vecinit6 2667; P9BE-LABEL: fromRegsConvdtoui 2668; P9LE-LABEL: fromRegsConvdtoui 2669; P8BE-LABEL: fromRegsConvdtoui 2670; P8LE-LABEL: fromRegsConvdtoui 2671; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 2672; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 2673; P9BE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2674; P9BE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2675; P9BE: vmrgew v2, [[REG3]], [[REG4]] 2676; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 2677; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 2678; P9LE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2679; P9LE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2680; P9LE: vmrgew v2, [[REG4]], [[REG3]] 2681; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 2682; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 2683; P8BE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2684; P8BE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2685; P8BE: vmrgew v2, [[REG3]], [[REG4]] 2686; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 2687; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 2688; P8LE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2689; P8LE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2690; P8LE: vmrgew v2, [[REG4]], [[REG3]] 2691} 2692 2693; Function Attrs: norecurse nounwind readnone 2694define <4 x i32> @fromDiffConstsConvdtoui() { 2695entry: 2696 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 2697; P9BE-LABEL: fromDiffConstsConvdtoui 2698; P9LE-LABEL: fromDiffConstsConvdtoui 2699; P8BE-LABEL: fromDiffConstsConvdtoui 2700; P8LE-LABEL: fromDiffConstsConvdtoui 2701; P9BE: lxv 2702; P9BE: blr 2703; P9LE: lxv 2704; P9LE: blr 2705; P8BE: lxvw4x 2706; P8BE: blr 2707; P8LE: lvx 2708; P8LE-NOT: xxswapd 2709; P8LE: blr 2710} 2711 2712; Function Attrs: norecurse nounwind readonly 2713define <4 x i32> @fromDiffMemConsAConvdtoui(double* nocapture readonly %ptr) { 2714entry: 2715 %0 = bitcast double* %ptr to <2 x double>* 2716 %1 = load <2 x double>, <2 x double>* %0, align 8 2717 %2 = fptoui <2 x double> %1 to <2 x i32> 2718 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 2 2719 %3 = bitcast double* %arrayidx4 to <2 x double>* 2720 %4 = load <2 x double>, <2 x double>* %3, align 8 2721 %5 = fptoui <2 x double> %4 to <2 x i32> 2722 %vecinit9 = shufflevector <2 x i32> %2, <2 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 2723 ret <4 x i32> %vecinit9 2724; P9BE-LABEL: fromDiffMemConsAConvdtoui 2725; P9LE-LABEL: fromDiffMemConsAConvdtoui 2726; P8BE-LABEL: fromDiffMemConsAConvdtoui 2727; P8LE-LABEL: fromDiffMemConsAConvdtoui 2728; P9BE-DAG: lxv [[REG1:[vs0-9]+]], 0(r3) 2729; P9BE-DAG: lxv [[REG2:[vs0-9]+]], 16(r3) 2730; P9BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]] 2731; P9BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]] 2732; P9BE-DAG: xvcvdpuxws [[REG5:[vs0-9]+]], [[REG3]] 2733; P9BE-DAG: xvcvdpuxws [[REG6:[vs0-9]+]], [[REG4]] 2734; P9BE: vmrgew v2, [[REG6]], [[REG5]] 2735; P9LE-DAG: lxv [[REG1:[vs0-9]+]], 0(r3) 2736; P9LE-DAG: lxv [[REG2:[vs0-9]+]], 16(r3) 2737; P9LE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG2]], [[REG1]] 2738; P9LE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG2]], [[REG1]] 2739; P9LE-DAG: xvcvdpuxws [[REG5:[vs0-9]+]], [[REG3]] 2740; P9LE-DAG: xvcvdpuxws [[REG6:[vs0-9]+]], [[REG4]] 2741; P9LE: vmrgew v2, [[REG6]], [[REG5]] 2742; P8BE: lxvd2x [[REG1:[vs0-9]+]], 0, r3 2743; P8BE: lxvd2x [[REG2:[vs0-9]+]], r3, r4 2744; P8BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]] 2745; P8BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]] 2746; P8BE-DAG: xvcvdpuxws [[REG5:[vs0-9]+]], [[REG3]] 2747; P8BE-DAG: xvcvdpuxws [[REG6:[vs0-9]+]], [[REG4]] 2748; P8BE: vmrgew v2, [[REG6]], [[REG5]] 2749; P8LE: lxvd2x [[REG1:[vs0-9]+]], 0, r3 2750; P8LE: lxvd2x [[REG2:[vs0-9]+]], r3, r4 2751; P8LE-DAG: xxswapd [[REG3:[vs0-9]+]], [[REG1]] 2752; P8LE-DAG: xxswapd [[REG4:[vs0-9]+]], [[REG2]] 2753; P8LE-DAG: xxmrgld [[REG5:[vs0-9]+]], [[REG4]], [[REG3]] 2754; P8LE-DAG: xxmrghd [[REG6:[vs0-9]+]], [[REG4]], [[REG3]] 2755; P8LE-DAG: xvcvdpuxws [[REG7:[vs0-9]+]], [[REG5]] 2756; P8LE-DAG: xvcvdpuxws [[REG8:[vs0-9]+]], [[REG6]] 2757; P8LE: vmrgew v2, [[REG8]], [[REG7]] 2758} 2759 2760; Function Attrs: norecurse nounwind readonly 2761define <4 x i32> @fromDiffMemConsDConvdtoui(double* nocapture readonly %ptr) { 2762entry: 2763 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 2764 %0 = load double, double* %arrayidx, align 8 2765 %conv = fptoui double %0 to i32 2766 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2767 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 2768 %1 = load double, double* %arrayidx1, align 8 2769 %conv2 = fptoui double %1 to i32 2770 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 2771 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 1 2772 %2 = load double, double* %arrayidx4, align 8 2773 %conv5 = fptoui double %2 to i32 2774 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 2775 %3 = load double, double* %ptr, align 8 2776 %conv8 = fptoui double %3 to i32 2777 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 2778 ret <4 x i32> %vecinit9 2779; P9BE-LABEL: fromDiffMemConsDConvdtoui 2780; P9LE-LABEL: fromDiffMemConsDConvdtoui 2781; P8BE-LABEL: fromDiffMemConsDConvdtoui 2782; P8LE-LABEL: fromDiffMemConsDConvdtoui 2783; P9BE: lfd 2784; P9BE: lfd 2785; P9BE: lfd 2786; P9BE: lfd 2787; P9BE: xxmrghd 2788; P9BE: xxmrghd 2789; P9BE: xvcvdpuxws 2790; P9BE: xvcvdpuxws 2791; P9BE: vmrgew v2 2792; P9LE: lfd 2793; P9LE: lfd 2794; P9LE: lfd 2795; P9LE: lfd 2796; P9LE: xxmrghd 2797; P9LE: xxmrghd 2798; P9LE: xvcvdpuxws 2799; P9LE: xvcvdpuxws 2800; P9LE: vmrgew v2 2801; P8BE: lfdx 2802; P8BE: lfd 2803; P8BE: lfd 2804; P8BE: lfd 2805; P8BE: xxmrghd 2806; P8BE: xxmrghd 2807; P8BE: xvcvdpuxws 2808; P8BE: xvcvdpuxws 2809; P8BE: vmrgew v2 2810; P8LE: lfdx 2811; P8LE: lfd 2812; P8LE: lfd 2813; P8LE: lfd 2814; P8LE: xxmrghd 2815; P8LE: xxmrghd 2816; P8LE: xvcvdpuxws 2817; P8LE: xvcvdpuxws 2818; P8LE: vmrgew v2 2819} 2820 2821; Function Attrs: norecurse nounwind readonly 2822define <4 x i32> @fromDiffMemVarAConvdtoui(double* nocapture readonly %arr, i32 signext %elem) { 2823entry: 2824 %idxprom = sext i32 %elem to i64 2825 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 2826 %0 = load double, double* %arrayidx, align 8 2827 %conv = fptoui double %0 to i32 2828 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2829 %add = add nsw i32 %elem, 1 2830 %idxprom1 = sext i32 %add to i64 2831 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 2832 %1 = load double, double* %arrayidx2, align 8 2833 %conv3 = fptoui double %1 to i32 2834 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2835 %add5 = add nsw i32 %elem, 2 2836 %idxprom6 = sext i32 %add5 to i64 2837 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 2838 %2 = load double, double* %arrayidx7, align 8 2839 %conv8 = fptoui double %2 to i32 2840 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2841 %add10 = add nsw i32 %elem, 3 2842 %idxprom11 = sext i32 %add10 to i64 2843 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 2844 %3 = load double, double* %arrayidx12, align 8 2845 %conv13 = fptoui double %3 to i32 2846 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2847 ret <4 x i32> %vecinit14 2848; P9BE-LABEL: fromDiffMemVarAConvdtoui 2849; P9LE-LABEL: fromDiffMemVarAConvdtoui 2850; P8BE-LABEL: fromDiffMemVarAConvdtoui 2851; P8LE-LABEL: fromDiffMemVarAConvdtoui 2852; P9BE: lfdux 2853; P9BE: lfd 2854; P9BE: lfd 2855; P9BE: lfd 2856; P9BE: xxmrghd 2857; P9BE: xxmrghd 2858; P9BE: xvcvdpuxws 2859; P9BE: xvcvdpuxws 2860; P9BE: vmrgew v2 2861; P9LE: lfdux 2862; P9LE: lfd 2863; P9LE: lfd 2864; P9LE: lfd 2865; P9LE: xxmrghd 2866; P9LE: xxmrghd 2867; P9LE: xvcvdpuxws 2868; P9LE: xvcvdpuxws 2869; P9LE: vmrgew v2 2870; P8BE: lfdux 2871; P8BE: lfd 2872; P8BE: lfd 2873; P8BE: lfd 2874; P8BE: xxmrghd 2875; P8BE: xxmrghd 2876; P8BE: xvcvdpuxws 2877; P8BE: xvcvdpuxws 2878; P8BE: vmrgew v2 2879; P8LE: lfdux 2880; P8LE: lfd 2881; P8LE: lfd 2882; P8LE: lfd 2883; P8LE: xxmrghd 2884; P8LE: xxmrghd 2885; P8LE: xvcvdpuxws 2886; P8LE: xvcvdpuxws 2887; P8LE: vmrgew v2 2888} 2889 2890; Function Attrs: norecurse nounwind readonly 2891define <4 x i32> @fromDiffMemVarDConvdtoui(double* nocapture readonly %arr, i32 signext %elem) { 2892entry: 2893 %idxprom = sext i32 %elem to i64 2894 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 2895 %0 = load double, double* %arrayidx, align 8 2896 %conv = fptoui double %0 to i32 2897 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2898 %sub = add nsw i32 %elem, -1 2899 %idxprom1 = sext i32 %sub to i64 2900 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 2901 %1 = load double, double* %arrayidx2, align 8 2902 %conv3 = fptoui double %1 to i32 2903 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2904 %sub5 = add nsw i32 %elem, -2 2905 %idxprom6 = sext i32 %sub5 to i64 2906 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 2907 %2 = load double, double* %arrayidx7, align 8 2908 %conv8 = fptoui double %2 to i32 2909 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2910 %sub10 = add nsw i32 %elem, -3 2911 %idxprom11 = sext i32 %sub10 to i64 2912 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 2913 %3 = load double, double* %arrayidx12, align 8 2914 %conv13 = fptoui double %3 to i32 2915 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2916 ret <4 x i32> %vecinit14 2917; P9BE-LABEL: fromDiffMemVarDConvdtoui 2918; P9LE-LABEL: fromDiffMemVarDConvdtoui 2919; P8BE-LABEL: fromDiffMemVarDConvdtoui 2920; P8LE-LABEL: fromDiffMemVarDConvdtoui 2921; P9BE: lfdux 2922; P9BE: lfd 2923; P9BE: lfd 2924; P9BE: lfd 2925; P9BE: xxmrghd 2926; P9BE: xxmrghd 2927; P9BE: xvcvdpuxws 2928; P9BE: xvcvdpuxws 2929; P9BE: vmrgew v2 2930; P9LE: lfdux 2931; P9LE: lfd 2932; P9LE: lfd 2933; P9LE: lfd 2934; P9LE: xxmrghd 2935; P9LE: xxmrghd 2936; P9LE: xvcvdpuxws 2937; P9LE: xvcvdpuxws 2938; P9LE: vmrgew v2 2939; P8BE: lfdux 2940; P8BE: lfd 2941; P8BE: lfd 2942; P8BE: lfd 2943; P8BE: xxmrghd 2944; P8BE: xxmrghd 2945; P8BE: xvcvdpuxws 2946; P8BE: xvcvdpuxws 2947; P8BE: vmrgew v2 2948; P8LE: lfdux 2949; P8LE: lfd 2950; P8LE: lfd 2951; P8LE: lfd 2952; P8LE: xxmrghd 2953; P8LE: xxmrghd 2954; P8LE: xvcvdpuxws 2955; P8LE: xvcvdpuxws 2956; P8LE: vmrgew v2 2957} 2958 2959; Function Attrs: norecurse nounwind readnone 2960define <4 x i32> @spltRegValConvdtoui(double %val) { 2961entry: 2962 %conv = fptoui double %val to i32 2963 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2964 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2965 ret <4 x i32> %splat.splat 2966; P9BE-LABEL: spltRegValConvdtoui 2967; P9LE-LABEL: spltRegValConvdtoui 2968; P8BE-LABEL: spltRegValConvdtoui 2969; P8LE-LABEL: spltRegValConvdtoui 2970; P9BE: xscvdpuxws 2971; P9BE: xxspltw 2972; P9BE: blr 2973; P9LE: xscvdpuxws 2974; P9LE: xxspltw 2975; P9LE: blr 2976; P8BE: xscvdpuxws 2977; P8BE: xxspltw 2978; P8BE: blr 2979; P8LE: xscvdpuxws 2980; P8LE: xxspltw 2981; P8LE: blr 2982} 2983 2984; Function Attrs: norecurse nounwind readonly 2985define <4 x i32> @spltMemValConvdtoui(double* nocapture readonly %ptr) { 2986entry: 2987 %0 = load double, double* %ptr, align 8 2988 %conv = fptoui double %0 to i32 2989 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2990 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2991 ret <4 x i32> %splat.splat 2992; P9BE-LABEL: spltMemValConvdtoui 2993; P9LE-LABEL: spltMemValConvdtoui 2994; P8BE-LABEL: spltMemValConvdtoui 2995; P8LE-LABEL: spltMemValConvdtoui 2996; P9BE: lfd 2997; P9BE: xscvdpuxws 2998; P9BE: xxspltw 2999; P9BE: blr 3000; P9LE: lfd 3001; P9LE: xscvdpuxws 3002; P9LE: xxspltw 3003; P9LE: blr 3004; P8BE: lfdx 3005; P8BE: xscvdpuxws 3006; P8BE: xxspltw 3007; P8BE: blr 3008; P8LE: lfdx 3009; P8LE: xscvdpuxws 3010; P8LE: xxspltw 3011; P8LE: blr 3012} 3013; Function Attrs: norecurse nounwind readnone 3014define <2 x i64> @allZeroll() { 3015entry: 3016 ret <2 x i64> zeroinitializer 3017; P9BE-LABEL: allZeroll 3018; P9LE-LABEL: allZeroll 3019; P8BE-LABEL: allZeroll 3020; P8LE-LABEL: allZeroll 3021; P9BE: xxlxor v2, v2, v2 3022; P9BE: blr 3023; P9LE: xxlxor v2, v2, v2 3024; P9LE: blr 3025; P8BE: xxlxor v2, v2, v2 3026; P8BE: blr 3027; P8LE: xxlxor v2, v2, v2 3028; P8LE: blr 3029} 3030 3031; Function Attrs: norecurse nounwind readnone 3032define <2 x i64> @allOnell() { 3033entry: 3034 ret <2 x i64> <i64 -1, i64 -1> 3035; P9BE-LABEL: allOnell 3036; P9LE-LABEL: allOnell 3037; P8BE-LABEL: allOnell 3038; P8LE-LABEL: allOnell 3039; P9BE: xxspltib v2, 255 3040; P9BE: blr 3041; P9LE: xxspltib v2, 255 3042; P9LE: blr 3043; P8BE: vspltisb v2, -1 3044; P8BE: blr 3045; P8LE: vspltisb v2, -1 3046; P8LE: blr 3047} 3048 3049; Function Attrs: norecurse nounwind readnone 3050define <2 x i64> @spltConst1ll() { 3051entry: 3052 ret <2 x i64> <i64 1, i64 1> 3053; P9BE-LABEL: spltConst1ll 3054; P9LE-LABEL: spltConst1ll 3055; P8BE-LABEL: spltConst1ll 3056; P8LE-LABEL: spltConst1ll 3057; P9BE: lxv 3058; P9BE: blr 3059; P9LE: lxv 3060; P9LE: blr 3061; P8BE: lxvd2x 3062; P8BE: blr 3063; P8LE: lxvd2x 3064; P8LE: blr 3065} 3066 3067; Function Attrs: norecurse nounwind readnone 3068define <2 x i64> @spltConst16kll() { 3069entry: 3070 ret <2 x i64> <i64 32767, i64 32767> 3071; P9BE-LABEL: spltConst16kll 3072; P9LE-LABEL: spltConst16kll 3073; P8BE-LABEL: spltConst16kll 3074; P8LE-LABEL: spltConst16kll 3075; P9BE: lxv 3076; P9BE: blr 3077; P9LE: lxv 3078; P9LE: blr 3079; P8BE: lxvd2x 3080; P8BE: blr 3081; P8LE: lxvd2x 3082; P8LE: blr 3083} 3084 3085; Function Attrs: norecurse nounwind readnone 3086define <2 x i64> @spltConst32kll() { 3087entry: 3088 ret <2 x i64> <i64 65535, i64 65535> 3089; P9BE-LABEL: spltConst32kll 3090; P9LE-LABEL: spltConst32kll 3091; P8BE-LABEL: spltConst32kll 3092; P8LE-LABEL: spltConst32kll 3093; P9BE: lxv 3094; P9BE: blr 3095; P9LE: lxv 3096; P9LE: blr 3097; P8BE: lxvd2x 3098; P8BE: blr 3099; P8LE: lxvd2x 3100; P8LE: blr 3101} 3102 3103; Function Attrs: norecurse nounwind readnone 3104define <2 x i64> @fromRegsll(i64 %a, i64 %b) { 3105entry: 3106 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 3107 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 3108 ret <2 x i64> %vecinit1 3109; P9BE-LABEL: fromRegsll 3110; P9LE-LABEL: fromRegsll 3111; P8BE-LABEL: fromRegsll 3112; P8LE-LABEL: fromRegsll 3113; P9BE: mtvsrdd v2, r3, r4 3114; P9BE: blr 3115; P9LE: mtvsrdd v2, r4, r3 3116; P9LE: blr 3117; P8BE-DAG: mtvsrd {{[vsf0-9]+}}, r3 3118; P8BE-DAG: mtvsrd {{[vsf0-9]+}}, r4 3119; P8BE: xxmrghd v2 3120; P8BE: blr 3121; P8LE-DAG: mtvsrd {{[vsf0-9]+}}, r3 3122; P8LE-DAG: mtvsrd {{[vsf0-9]+}}, r4 3123; P8LE: xxmrghd v2 3124; P8LE: blr 3125} 3126 3127; Function Attrs: norecurse nounwind readnone 3128define <2 x i64> @fromDiffConstsll() { 3129entry: 3130 ret <2 x i64> <i64 242, i64 -113> 3131; P9BE-LABEL: fromDiffConstsll 3132; P9LE-LABEL: fromDiffConstsll 3133; P8BE-LABEL: fromDiffConstsll 3134; P8LE-LABEL: fromDiffConstsll 3135; P9BE: lxv 3136; P9BE: blr 3137; P9LE: lxv 3138; P9LE: blr 3139; P8BE: lxvd2x 3140; P8BE: blr 3141; P8LE: lxvd2x 3142; P8LE: blr 3143} 3144 3145; Function Attrs: norecurse nounwind readonly 3146define <2 x i64> @fromDiffMemConsAll(i64* nocapture readonly %arr) { 3147entry: 3148 %0 = load i64, i64* %arr, align 8 3149 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3150 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 1 3151 %1 = load i64, i64* %arrayidx1, align 8 3152 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3153 ret <2 x i64> %vecinit2 3154; P9BE-LABEL: fromDiffMemConsAll 3155; P9LE-LABEL: fromDiffMemConsAll 3156; P8BE-LABEL: fromDiffMemConsAll 3157; P8LE-LABEL: fromDiffMemConsAll 3158; P9BE: lxv v2 3159; P9BE: blr 3160; P9LE: lxv v2 3161; P9LE: blr 3162; P8BE: lxvd2x v2 3163; P8BE: blr 3164; P8LE: lxvd2x 3165; P8LE: xxswapd v2 3166; P8LE: blr 3167} 3168 3169; Function Attrs: norecurse nounwind readonly 3170define <2 x i64> @fromDiffMemConsDll(i64* nocapture readonly %arr) { 3171entry: 3172 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 3 3173 %0 = load i64, i64* %arrayidx, align 8 3174 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3175 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 2 3176 %1 = load i64, i64* %arrayidx1, align 8 3177 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3178 ret <2 x i64> %vecinit2 3179; P9BE-LABEL: fromDiffMemConsDll 3180; P9LE-LABEL: fromDiffMemConsDll 3181; P8BE-LABEL: fromDiffMemConsDll 3182; P8LE-LABEL: fromDiffMemConsDll 3183; P9BE: lxv v2 3184; P9BE: blr 3185; P9LE: lxv 3186; P9LE: xxswapd v2 3187; P9LE: blr 3188; P8BE: lxvd2x 3189; P8BE: xxswapd v2 3190; P8BE-NEXT: blr 3191; P8LE: lxvd2x v2 3192; P8LE-NEXT: blr 3193} 3194 3195; Function Attrs: norecurse nounwind readonly 3196define <2 x i64> @fromDiffMemVarAll(i64* nocapture readonly %arr, i32 signext %elem) { 3197entry: 3198 %idxprom = sext i32 %elem to i64 3199 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 3200 %0 = load i64, i64* %arrayidx, align 8 3201 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3202 %add = add nsw i32 %elem, 1 3203 %idxprom1 = sext i32 %add to i64 3204 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 3205 %1 = load i64, i64* %arrayidx2, align 8 3206 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3207 ret <2 x i64> %vecinit3 3208; P9BE-LABEL: fromDiffMemVarAll 3209; P9LE-LABEL: fromDiffMemVarAll 3210; P8BE-LABEL: fromDiffMemVarAll 3211; P8LE-LABEL: fromDiffMemVarAll 3212; P9BE: sldi 3213; P9BE: lxvx v2 3214; P9BE-NEXT: blr 3215; P9LE: sldi 3216; P9LE: lxvx v2 3217; P9LE-NEXT: blr 3218; P8BE: sldi 3219; P8BE: lxvd2x v2 3220; P8BE-NEXT: blr 3221; P8LE: sldi 3222; P8LE: lxvd2x 3223; P8LE: xxswapd v2 3224; P8LE-NEXT: blr 3225} 3226 3227; Function Attrs: norecurse nounwind readonly 3228define <2 x i64> @fromDiffMemVarDll(i64* nocapture readonly %arr, i32 signext %elem) { 3229entry: 3230 %idxprom = sext i32 %elem to i64 3231 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 3232 %0 = load i64, i64* %arrayidx, align 8 3233 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3234 %sub = add nsw i32 %elem, -1 3235 %idxprom1 = sext i32 %sub to i64 3236 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 3237 %1 = load i64, i64* %arrayidx2, align 8 3238 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3239 ret <2 x i64> %vecinit3 3240; P9BE-LABEL: fromDiffMemVarDll 3241; P9LE-LABEL: fromDiffMemVarDll 3242; P8BE-LABEL: fromDiffMemVarDll 3243; P8LE-LABEL: fromDiffMemVarDll 3244; P9BE: sldi 3245; P9BE: lxv 3246; P9BE: xxswapd v2 3247; P9BE-NEXT: blr 3248; P9LE: sldi 3249; P9LE: lxv 3250; P9LE: xxswapd v2 3251; P9LE-NEXT: blr 3252; P8BE: sldi 3253; P8BE: lxvd2x 3254; P8BE: xxswapd v2 3255; P8BE-NEXT: blr 3256; P8LE: sldi 3257; P8LE: lxvd2x v2 3258; P8LE-NEXT: blr 3259} 3260 3261; Function Attrs: norecurse nounwind readonly 3262define <2 x i64> @fromRandMemConsll(i64* nocapture readonly %arr) { 3263entry: 3264 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4 3265 %0 = load i64, i64* %arrayidx, align 8 3266 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3267 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18 3268 %1 = load i64, i64* %arrayidx1, align 8 3269 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3270 ret <2 x i64> %vecinit2 3271; P9BE-LABEL: fromRandMemConsll 3272; P9LE-LABEL: fromRandMemConsll 3273; P8BE-LABEL: fromRandMemConsll 3274; P8LE-LABEL: fromRandMemConsll 3275; P9BE: ld 3276; P9BE: ld 3277; P9BE: mtvsrdd v2 3278; P9BE-NEXT: blr 3279; P9LE: ld 3280; P9LE: ld 3281; P9LE: mtvsrdd v2 3282; P9LE-NEXT: blr 3283; P8BE: ld 3284; P8BE: ld 3285; P8BE-DAG: mtvsrd 3286; P8BE-DAG: mtvsrd 3287; P8BE: xxmrghd v2 3288; P8BE-NEXT: blr 3289; P8LE: ld 3290; P8LE: ld 3291; P8LE-DAG: mtvsrd 3292; P8LE-DAG: mtvsrd 3293; P8LE: xxmrghd v2 3294; P8LE-NEXT: blr 3295} 3296 3297; Function Attrs: norecurse nounwind readonly 3298define <2 x i64> @fromRandMemVarll(i64* nocapture readonly %arr, i32 signext %elem) { 3299entry: 3300 %add = add nsw i32 %elem, 4 3301 %idxprom = sext i32 %add to i64 3302 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 3303 %0 = load i64, i64* %arrayidx, align 8 3304 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3305 %add1 = add nsw i32 %elem, 1 3306 %idxprom2 = sext i32 %add1 to i64 3307 %arrayidx3 = getelementptr inbounds i64, i64* %arr, i64 %idxprom2 3308 %1 = load i64, i64* %arrayidx3, align 8 3309 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3310 ret <2 x i64> %vecinit4 3311; P9BE-LABEL: fromRandMemVarll 3312; P9LE-LABEL: fromRandMemVarll 3313; P8BE-LABEL: fromRandMemVarll 3314; P8LE-LABEL: fromRandMemVarll 3315; P9BE: sldi 3316; P9BE: ld 3317; P9BE: ld 3318; P9BE: mtvsrdd v2 3319; P9BE-NEXT: blr 3320; P9LE: sldi 3321; P9LE: ld 3322; P9LE: ld 3323; P9LE: mtvsrdd v2 3324; P9LE-NEXT: blr 3325; P8BE: sldi 3326; P8BE: ld 3327; P8BE: ld 3328; P8BE: mtvsrd 3329; P8BE: mtvsrd 3330; P8BE: xxmrghd v2 3331; P8BE-NEXT: blr 3332; P8LE: sldi 3333; P8LE: ld 3334; P8LE: ld 3335; P8LE: mtvsrd 3336; P8LE: mtvsrd 3337; P8LE: xxmrghd v2 3338; P8LE-NEXT: blr 3339} 3340 3341; Function Attrs: norecurse nounwind readnone 3342define <2 x i64> @spltRegValll(i64 %val) { 3343entry: 3344 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0 3345 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 3346 ret <2 x i64> %splat.splat 3347; P9BE-LABEL: spltRegValll 3348; P9LE-LABEL: spltRegValll 3349; P8BE-LABEL: spltRegValll 3350; P8LE-LABEL: spltRegValll 3351; P9BE: mtvsrdd v2, r3, r3 3352; P9BE-NEXT: blr 3353; P9LE: mtvsrdd v2, r3, r3 3354; P9LE-NEXT: blr 3355; P8BE: mtvsrd {{[vsf]+}}[[REG1:[0-9]+]], r3 3356; P8BE: xxspltd v2, {{[vsf]+}}[[REG1]], 0 3357; P8BE-NEXT: blr 3358; P8LE: mtvsrd {{[vsf]+}}[[REG1:[0-9]+]], r3 3359; P8LE: xxspltd v2, {{[vsf]+}}[[REG1]], 0 3360; P8LE-NEXT: blr 3361} 3362 3363; Function Attrs: norecurse nounwind readonly 3364define <2 x i64> @spltMemValll(i64* nocapture readonly %ptr) { 3365entry: 3366 %0 = load i64, i64* %ptr, align 8 3367 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 3368 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 3369 ret <2 x i64> %splat.splat 3370; P9BE-LABEL: spltMemValll 3371; P9LE-LABEL: spltMemValll 3372; P8BE-LABEL: spltMemValll 3373; P8LE-LABEL: spltMemValll 3374; P9BE: lxvdsx v2 3375; P9BE-NEXT: blr 3376; P9LE: lxvdsx v2 3377; P9LE-NEXT: blr 3378; P8BE: lxvdsx v2 3379; P8BE-NEXT: blr 3380; P8LE: lxvdsx v2 3381; P8LE-NEXT: blr 3382} 3383 3384; Function Attrs: norecurse nounwind readnone 3385define <2 x i64> @spltCnstConvftoll() { 3386entry: 3387 ret <2 x i64> <i64 4, i64 4> 3388; P9BE-LABEL: spltCnstConvftoll 3389; P9LE-LABEL: spltCnstConvftoll 3390; P8BE-LABEL: spltCnstConvftoll 3391; P8LE-LABEL: spltCnstConvftoll 3392; P9BE: lxv 3393; P9BE: blr 3394; P9LE: lxv 3395; P9LE: blr 3396; P8BE: lxvd2x 3397; P8BE: blr 3398; P8LE: lxvd2x 3399; P8LE: blr 3400} 3401 3402; Function Attrs: norecurse nounwind readnone 3403define <2 x i64> @fromRegsConvftoll(float %a, float %b) { 3404entry: 3405 %conv = fptosi float %a to i64 3406 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3407 %conv1 = fptosi float %b to i64 3408 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 3409 ret <2 x i64> %vecinit2 3410; P9BE-LABEL: fromRegsConvftoll 3411; P9LE-LABEL: fromRegsConvftoll 3412; P8BE-LABEL: fromRegsConvftoll 3413; P8LE-LABEL: fromRegsConvftoll 3414; P9BE: xxmrghd 3415; P9BE: xvcvdpsxds v2 3416; P9BE-NEXT: blr 3417; P9LE: xxmrghd 3418; P9LE: xvcvdpsxds v2 3419; P9LE-NEXT: blr 3420; P8BE: xxmrghd 3421; P8BE: xvcvdpsxds v2 3422; P8BE-NEXT: blr 3423; P8LE: xxmrghd 3424; P8LE: xvcvdpsxds v2 3425; P8LE-NEXT: blr 3426} 3427 3428; Function Attrs: norecurse nounwind readnone 3429define <2 x i64> @fromDiffConstsConvftoll() { 3430entry: 3431 ret <2 x i64> <i64 24, i64 234> 3432; P9BE-LABEL: fromDiffConstsConvftoll 3433; P9LE-LABEL: fromDiffConstsConvftoll 3434; P8BE-LABEL: fromDiffConstsConvftoll 3435; P8LE-LABEL: fromDiffConstsConvftoll 3436; P9BE: lxvx v2 3437; P9BE: blr 3438; P9LE: lxvx v2 3439; P9LE: blr 3440; P8BE: lxvd2x v2 3441; P8BE: blr 3442; P8LE: lxvd2x 3443; P8LE: xxswapd v2 3444; P8LE: blr 3445} 3446 3447; Function Attrs: norecurse nounwind readonly 3448define <2 x i64> @fromDiffMemConsAConvftoll(float* nocapture readonly %ptr) { 3449entry: 3450 %0 = load float, float* %ptr, align 4 3451 %conv = fptosi float %0 to i64 3452 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3453 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1 3454 %1 = load float, float* %arrayidx1, align 4 3455 %conv2 = fptosi float %1 to i64 3456 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 3457 ret <2 x i64> %vecinit3 3458; P9BE-LABEL: fromDiffMemConsAConvftoll 3459; P9LE-LABEL: fromDiffMemConsAConvftoll 3460; P8BE-LABEL: fromDiffMemConsAConvftoll 3461; P8LE-LABEL: fromDiffMemConsAConvftoll 3462; P9BE: lfs 3463; P9BE: lfs 3464; P9BE: xxmrghd 3465; P9BE-NEXT: xvcvdpsxds v2 3466; P9BE-NEXT: blr 3467; P9LE: lfs 3468; P9LE: lfs 3469; P9LE: xxmrghd 3470; P9LE-NEXT: xvcvdpsxds v2 3471; P9LE-NEXT: blr 3472; P8BE: lfs 3473; P8BE: lfs 3474; P8BE: xxmrghd 3475; P8BE-NEXT: xvcvdpsxds v2 3476; P8BE-NEXT: blr 3477; P8LE: lfs 3478; P8LE: lfs 3479; P8LE: xxmrghd 3480; P8LE-NEXT: xvcvdpsxds v2 3481; P8LE-NEXT: blr 3482} 3483 3484; Function Attrs: norecurse nounwind readonly 3485define <2 x i64> @fromDiffMemConsDConvftoll(float* nocapture readonly %ptr) { 3486entry: 3487 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 3488 %0 = load float, float* %arrayidx, align 4 3489 %conv = fptosi float %0 to i64 3490 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3491 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 3492 %1 = load float, float* %arrayidx1, align 4 3493 %conv2 = fptosi float %1 to i64 3494 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 3495 ret <2 x i64> %vecinit3 3496; P9BE-LABEL: fromDiffMemConsDConvftoll 3497; P9LE-LABEL: fromDiffMemConsDConvftoll 3498; P8BE-LABEL: fromDiffMemConsDConvftoll 3499; P8LE-LABEL: fromDiffMemConsDConvftoll 3500; P9BE: lfs 3501; P9BE: lfs 3502; P9BE: xxmrghd 3503; P9BE-NEXT: xvcvdpsxds v2 3504; P9BE-NEXT: blr 3505; P9LE: lfs 3506; P9LE: lfs 3507; P9LE: xxmrghd 3508; P9LE-NEXT: xvcvdpsxds v2 3509; P9LE-NEXT: blr 3510; P8BE: lfs 3511; P8BE: lfs 3512; P8BE: xxmrghd 3513; P8BE-NEXT: xvcvdpsxds v2 3514; P8BE-NEXT: blr 3515; P8LE: lfs 3516; P8LE: lfs 3517; P8LE: xxmrghd 3518; P8LE-NEXT: xvcvdpsxds v2 3519; P8LE-NEXT: blr 3520} 3521 3522; Function Attrs: norecurse nounwind readonly 3523define <2 x i64> @fromDiffMemVarAConvftoll(float* nocapture readonly %arr, i32 signext %elem) { 3524entry: 3525 %idxprom = sext i32 %elem to i64 3526 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 3527 %0 = load float, float* %arrayidx, align 4 3528 %conv = fptosi float %0 to i64 3529 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3530 %add = add nsw i32 %elem, 1 3531 %idxprom1 = sext i32 %add to i64 3532 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 3533 %1 = load float, float* %arrayidx2, align 4 3534 %conv3 = fptosi float %1 to i64 3535 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 3536 ret <2 x i64> %vecinit4 3537; P9BE-LABEL: fromDiffMemVarAConvftoll 3538; P9LE-LABEL: fromDiffMemVarAConvftoll 3539; P8BE-LABEL: fromDiffMemVarAConvftoll 3540; P8LE-LABEL: fromDiffMemVarAConvftoll 3541; P9BE: sldi 3542; P9BE: lfsux 3543; P9BE: lfs 3544; P9BE: xxmrghd 3545; P9BE-NEXT: xvcvdpsxds v2 3546; P9BE-NEXT: blr 3547; P9LE: sldi 3548; P9LE: lfsux 3549; P9LE: lfs 3550; P9LE: xxmrghd 3551; P9LE-NEXT: xvcvdpsxds v2 3552; P9LE-NEXT: blr 3553; P8BE: sldi 3554; P8BE: lfsux 3555; P8BE: lfs 3556; P8BE: xxmrghd 3557; P8BE-NEXT: xvcvdpsxds v2 3558; P8BE-NEXT: blr 3559; P8LE: sldi 3560; P8LE: lfsux 3561; P8LE: lfs 3562; P8LE: xxmrghd 3563; P8LE-NEXT: xvcvdpsxds v2 3564; P8LE-NEXT: blr 3565} 3566 3567; Function Attrs: norecurse nounwind readonly 3568define <2 x i64> @fromDiffMemVarDConvftoll(float* nocapture readonly %arr, i32 signext %elem) { 3569entry: 3570 %idxprom = sext i32 %elem to i64 3571 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 3572 %0 = load float, float* %arrayidx, align 4 3573 %conv = fptosi float %0 to i64 3574 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3575 %sub = add nsw i32 %elem, -1 3576 %idxprom1 = sext i32 %sub to i64 3577 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 3578 %1 = load float, float* %arrayidx2, align 4 3579 %conv3 = fptosi float %1 to i64 3580 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 3581 ret <2 x i64> %vecinit4 3582; P9BE-LABEL: fromDiffMemVarDConvftoll 3583; P9LE-LABEL: fromDiffMemVarDConvftoll 3584; P8BE-LABEL: fromDiffMemVarDConvftoll 3585; P8LE-LABEL: fromDiffMemVarDConvftoll 3586; P9BE: sldi 3587; P9BE: lfsux 3588; P9BE: lfs 3589; P9BE: xxmrghd 3590; P9BE-NEXT: xvcvdpsxds v2 3591; P9BE-NEXT: blr 3592; P9LE: sldi 3593; P9LE: lfsux 3594; P9LE: lfs 3595; P9LE: xxmrghd 3596; P9LE-NEXT: xvcvdpsxds v2 3597; P9LE-NEXT: blr 3598; P8BE: sldi 3599; P8BE: lfsux 3600; P8BE: lfs 3601; P8BE: xxmrghd 3602; P8BE-NEXT: xvcvdpsxds v2 3603; P8BE-NEXT: blr 3604; P8LE: sldi 3605; P8LE: lfsux 3606; P8LE: lfs 3607; P8LE: xxmrghd 3608; P8LE-NEXT: xvcvdpsxds v2 3609; P8LE-NEXT: blr 3610} 3611 3612; Function Attrs: norecurse nounwind readnone 3613define <2 x i64> @spltRegValConvftoll(float %val) { 3614entry: 3615 %conv = fptosi float %val to i64 3616 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 3617 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 3618 ret <2 x i64> %splat.splat 3619; P9BE-LABEL: spltRegValConvftoll 3620; P9LE-LABEL: spltRegValConvftoll 3621; P8BE-LABEL: spltRegValConvftoll 3622; P8LE-LABEL: spltRegValConvftoll 3623; P9BE: xscvdpsxds 3624; P9BE-NEXT: xxspltd v2 3625; P9BE-NEXT: blr 3626; P9LE: xscvdpsxds 3627; P9LE-NEXT: xxspltd v2 3628; P9LE-NEXT: blr 3629; P8BE: xscvdpsxds 3630; P8BE-NEXT: xxspltd v2 3631; P8BE-NEXT: blr 3632; P8LE: xscvdpsxds 3633; P8LE-NEXT: xxspltd v2 3634; P8LE-NEXT: blr 3635} 3636 3637; Function Attrs: norecurse nounwind readonly 3638define <2 x i64> @spltMemValConvftoll(float* nocapture readonly %ptr) { 3639entry: 3640 %0 = load float, float* %ptr, align 4 3641 %conv = fptosi float %0 to i64 3642 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 3643 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 3644 ret <2 x i64> %splat.splat 3645; P9BE-LABEL: spltMemValConvftoll 3646; P9LE-LABEL: spltMemValConvftoll 3647; P8BE-LABEL: spltMemValConvftoll 3648; P8LE-LABEL: spltMemValConvftoll 3649; P9BE: lfs 3650; P9BE-NEXT: xscvdpsxds 3651; P9BE-NEXT: xxspltd v2 3652; P9BE-NEXT: blr 3653; P9LE: lfs 3654; P9LE-NEXT: xscvdpsxds 3655; P9LE-NEXT: xxspltd v2 3656; P9LE-NEXT: blr 3657; P8BE: lfs 3658; P8BE-NEXT: xscvdpsxds 3659; P8BE-NEXT: xxspltd v2 3660; P8BE-NEXT: blr 3661; P8LE: lfs 3662; P8LE-NEXT: xscvdpsxds 3663; P8LE-NEXT: xxspltd v2 3664; P8LE-NEXT: blr 3665} 3666 3667; Function Attrs: norecurse nounwind readnone 3668define <2 x i64> @spltCnstConvdtoll() { 3669entry: 3670 ret <2 x i64> <i64 4, i64 4> 3671; P9BE-LABEL: spltCnstConvdtoll 3672; P9LE-LABEL: spltCnstConvdtoll 3673; P8BE-LABEL: spltCnstConvdtoll 3674; P8LE-LABEL: spltCnstConvdtoll 3675; P9BE: lxv 3676; P9BE: blr 3677; P9LE: lxv 3678; P9LE: blr 3679; P8BE: lxvd2x 3680; P8BE: blr 3681; P8LE: lxvd2x 3682; P8LE: blr 3683} 3684 3685; Function Attrs: norecurse nounwind readnone 3686define <2 x i64> @fromRegsConvdtoll(double %a, double %b) { 3687entry: 3688 %conv = fptosi double %a to i64 3689 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3690 %conv1 = fptosi double %b to i64 3691 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 3692 ret <2 x i64> %vecinit2 3693; P9BE-LABEL: fromRegsConvdtoll 3694; P9LE-LABEL: fromRegsConvdtoll 3695; P8BE-LABEL: fromRegsConvdtoll 3696; P8LE-LABEL: fromRegsConvdtoll 3697; P9BE: xxmrghd 3698; P9BE-NEXT: xvcvdpsxds 3699; P9BE-NEXT: blr 3700; P9LE: xxmrghd 3701; P9LE-NEXT: xvcvdpsxds 3702; P9LE-NEXT: blr 3703; P8BE: xxmrghd 3704; P8BE-NEXT: xvcvdpsxds 3705; P8BE-NEXT: blr 3706; P8LE: xxmrghd 3707; P8LE-NEXT: xvcvdpsxds 3708; P8LE-NEXT: blr 3709} 3710 3711; Function Attrs: norecurse nounwind readnone 3712define <2 x i64> @fromDiffConstsConvdtoll() { 3713entry: 3714 ret <2 x i64> <i64 24, i64 234> 3715; P9BE-LABEL: fromDiffConstsConvdtoll 3716; P9LE-LABEL: fromDiffConstsConvdtoll 3717; P8BE-LABEL: fromDiffConstsConvdtoll 3718; P8LE-LABEL: fromDiffConstsConvdtoll 3719; P9BE: lxv 3720; P9BE: blr 3721; P9LE: lxv 3722; P9LE: blr 3723; P8BE: lxvd2x 3724; P8BE: blr 3725; P8LE: lxvd2x 3726; P8LE: blr 3727} 3728 3729; Function Attrs: norecurse nounwind readonly 3730define <2 x i64> @fromDiffMemConsAConvdtoll(double* nocapture readonly %ptr) { 3731entry: 3732 %0 = bitcast double* %ptr to <2 x double>* 3733 %1 = load <2 x double>, <2 x double>* %0, align 8 3734 %2 = fptosi <2 x double> %1 to <2 x i64> 3735 ret <2 x i64> %2 3736; P9BE-LABEL: fromDiffMemConsAConvdtoll 3737; P9LE-LABEL: fromDiffMemConsAConvdtoll 3738; P8BE-LABEL: fromDiffMemConsAConvdtoll 3739; P8LE-LABEL: fromDiffMemConsAConvdtoll 3740; P9BE: lxv 3741; P9BE-NEXT: xvcvdpsxds v2 3742; P9BE-NEXT: blr 3743; P9LE: lxv 3744; P9LE-NEXT: xvcvdpsxds v2 3745; P9LE-NEXT: blr 3746; P8BE: lxvd2x 3747; P8BE-NEXT: xvcvdpsxds v2 3748; P8BE-NEXT: blr 3749; P8LE: lxvd2x 3750; P8LE: xxswapd 3751; P8LE-NEXT: xvcvdpsxds v2 3752; P8LE-NEXT: blr 3753} 3754 3755; Function Attrs: norecurse nounwind readonly 3756define <2 x i64> @fromDiffMemConsDConvdtoll(double* nocapture readonly %ptr) { 3757entry: 3758 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 3759 %0 = load double, double* %arrayidx, align 8 3760 %conv = fptosi double %0 to i64 3761 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3762 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 3763 %1 = load double, double* %arrayidx1, align 8 3764 %conv2 = fptosi double %1 to i64 3765 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 3766 ret <2 x i64> %vecinit3 3767; P9BE-LABEL: fromDiffMemConsDConvdtoll 3768; P9LE-LABEL: fromDiffMemConsDConvdtoll 3769; P8BE-LABEL: fromDiffMemConsDConvdtoll 3770; P8LE-LABEL: fromDiffMemConsDConvdtoll 3771; P9BE: lxv 3772; P9BE-NEXT: xxswapd 3773; P9BE-NEXT: xvcvdpsxds v2 3774; P9BE-NEXT: blr 3775; P9LE: lxv 3776; P9LE-NEXT: xxswapd 3777; P9LE-NEXT: xvcvdpsxds v2 3778; P9LE-NEXT: blr 3779; P8BE: lxvd2x 3780; P8BE-NEXT: xxswapd 3781; P8BE-NEXT: xvcvdpsxds v2 3782; P8BE-NEXT: blr 3783; P8LE: lxvd2x 3784; P8LE-NEXT: xvcvdpsxds v2 3785; P8LE-NEXT: blr 3786} 3787 3788; Function Attrs: norecurse nounwind readonly 3789define <2 x i64> @fromDiffMemVarAConvdtoll(double* nocapture readonly %arr, i32 signext %elem) { 3790entry: 3791 %idxprom = sext i32 %elem to i64 3792 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 3793 %0 = load double, double* %arrayidx, align 8 3794 %conv = fptosi double %0 to i64 3795 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3796 %add = add nsw i32 %elem, 1 3797 %idxprom1 = sext i32 %add to i64 3798 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 3799 %1 = load double, double* %arrayidx2, align 8 3800 %conv3 = fptosi double %1 to i64 3801 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 3802 ret <2 x i64> %vecinit4 3803; P9BE-LABEL: fromDiffMemVarAConvdtoll 3804; P9LE-LABEL: fromDiffMemVarAConvdtoll 3805; P8BE-LABEL: fromDiffMemVarAConvdtoll 3806; P8LE-LABEL: fromDiffMemVarAConvdtoll 3807; P9BE: sldi 3808; P9BE: lxvx 3809; P9BE-NEXT: xvcvdpsxds v2 3810; P9BE-NEXT: blr 3811; P9LE: sldi 3812; P9LE: lxvx 3813; P9LE-NEXT: xvcvdpsxds v2 3814; P9LE-NEXT: blr 3815; P8BE: sldi 3816; P8BE: lxvd2x 3817; P8BE-NEXT: xvcvdpsxds v2 3818; P8BE-NEXT: blr 3819; P8LE: sldi 3820; P8LE: lxvd2x 3821; P8LE-NEXT: xxswapd 3822; P8LE-NEXT: xvcvdpsxds v2 3823; P8LE-NEXT: blr 3824} 3825 3826; Function Attrs: norecurse nounwind readonly 3827define <2 x i64> @fromDiffMemVarDConvdtoll(double* nocapture readonly %arr, i32 signext %elem) { 3828entry: 3829 %idxprom = sext i32 %elem to i64 3830 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 3831 %0 = load double, double* %arrayidx, align 8 3832 %conv = fptosi double %0 to i64 3833 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3834 %sub = add nsw i32 %elem, -1 3835 %idxprom1 = sext i32 %sub to i64 3836 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 3837 %1 = load double, double* %arrayidx2, align 8 3838 %conv3 = fptosi double %1 to i64 3839 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 3840 ret <2 x i64> %vecinit4 3841; P9BE-LABEL: fromDiffMemVarDConvdtoll 3842; P9LE-LABEL: fromDiffMemVarDConvdtoll 3843; P8BE-LABEL: fromDiffMemVarDConvdtoll 3844; P8LE-LABEL: fromDiffMemVarDConvdtoll 3845; P9BE: sldi 3846; P9BE: lxv 3847; P9BE-NEXT: xxswapd 3848; P9BE-NEXT: xvcvdpsxds v2 3849; P9BE-NEXT: blr 3850; P9LE: sldi 3851; P9LE: lxv 3852; P9LE-NEXT: xxswapd 3853; P9LE-NEXT: xvcvdpsxds v2 3854; P9LE-NEXT: blr 3855; P8BE: sldi 3856; P8BE: lxvd2x 3857; P8BE-NEXT: xxswapd 3858; P8BE-NEXT: xvcvdpsxds v2 3859; P8BE-NEXT: blr 3860; P8LE: sldi 3861; P8LE: lxvd2x 3862; P8LE-NEXT: xvcvdpsxds v2 3863; P8LE-NEXT: blr 3864} 3865 3866; Function Attrs: norecurse nounwind readnone 3867define <2 x i64> @spltRegValConvdtoll(double %val) { 3868entry: 3869 %conv = fptosi double %val to i64 3870 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 3871 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 3872 ret <2 x i64> %splat.splat 3873; P9BE-LABEL: spltRegValConvdtoll 3874; P9LE-LABEL: spltRegValConvdtoll 3875; P8BE-LABEL: spltRegValConvdtoll 3876; P8LE-LABEL: spltRegValConvdtoll 3877; P9BE: xscvdpsxds 3878; P9BE-NEXT: xxspltd v2 3879; P9BE-NEXT: blr 3880; P9LE: xscvdpsxds 3881; P9LE-NEXT: xxspltd v2 3882; P9LE-NEXT: blr 3883; P8BE: xscvdpsxds 3884; P8BE-NEXT: xxspltd v2 3885; P8BE-NEXT: blr 3886; P8LE: xscvdpsxds 3887; P8LE-NEXT: xxspltd v2 3888; P8LE-NEXT: blr 3889} 3890 3891; Function Attrs: norecurse nounwind readonly 3892define <2 x i64> @spltMemValConvdtoll(double* nocapture readonly %ptr) { 3893entry: 3894 %0 = load double, double* %ptr, align 8 3895 %conv = fptosi double %0 to i64 3896 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 3897 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 3898 ret <2 x i64> %splat.splat 3899; P9BE-LABEL: spltMemValConvdtoll 3900; P9LE-LABEL: spltMemValConvdtoll 3901; P8BE-LABEL: spltMemValConvdtoll 3902; P8LE-LABEL: spltMemValConvdtoll 3903; P9BE: lxvdsx 3904; P9BE-NEXT: xvcvdpsxds 3905; P9BE-NEXT: blr 3906; P9LE: lxvdsx 3907; P9LE-NEXT: xvcvdpsxds 3908; P9LE-NEXT: blr 3909; P8BE: lxvdsx 3910; P8BE-NEXT: xvcvdpsxds 3911; P8BE-NEXT: blr 3912; P8LE: lxvdsx 3913; P8LE-NEXT: xvcvdpsxds 3914; P8LE-NEXT: blr 3915} 3916 3917; Function Attrs: norecurse nounwind readnone 3918define <2 x i64> @allZeroull() { 3919entry: 3920 ret <2 x i64> zeroinitializer 3921; P9BE-LABEL: allZeroull 3922; P9LE-LABEL: allZeroull 3923; P8BE-LABEL: allZeroull 3924; P8LE-LABEL: allZeroull 3925; P9BE: xxlxor v2, v2, v2 3926; P9BE: blr 3927; P9LE: xxlxor v2, v2, v2 3928; P9LE: blr 3929; P8BE: xxlxor v2, v2, v2 3930; P8BE: blr 3931; P8LE: xxlxor v2, v2, v2 3932; P8LE: blr 3933} 3934 3935; Function Attrs: norecurse nounwind readnone 3936define <2 x i64> @allOneull() { 3937entry: 3938 ret <2 x i64> <i64 -1, i64 -1> 3939; P9BE-LABEL: allOneull 3940; P9LE-LABEL: allOneull 3941; P8BE-LABEL: allOneull 3942; P8LE-LABEL: allOneull 3943; P9BE: xxspltib v2, 255 3944; P9BE: blr 3945; P9LE: xxspltib v2, 255 3946; P9LE: blr 3947; P8BE: vspltisb v2, -1 3948; P8BE: blr 3949; P8LE: vspltisb v2, -1 3950; P8LE: blr 3951} 3952 3953; Function Attrs: norecurse nounwind readnone 3954define <2 x i64> @spltConst1ull() { 3955entry: 3956 ret <2 x i64> <i64 1, i64 1> 3957; P9BE-LABEL: spltConst1ull 3958; P9LE-LABEL: spltConst1ull 3959; P8BE-LABEL: spltConst1ull 3960; P8LE-LABEL: spltConst1ull 3961; P9BE: lxv 3962; P9BE: blr 3963; P9LE: lxv 3964; P9LE: blr 3965; P8BE: lxvd2x 3966; P8BE: blr 3967; P8LE: lxvd2x 3968; P8LE: blr 3969} 3970 3971; Function Attrs: norecurse nounwind readnone 3972define <2 x i64> @spltConst16kull() { 3973entry: 3974 ret <2 x i64> <i64 32767, i64 32767> 3975; P9BE-LABEL: spltConst16kull 3976; P9LE-LABEL: spltConst16kull 3977; P8BE-LABEL: spltConst16kull 3978; P8LE-LABEL: spltConst16kull 3979; P9BE: lxv 3980; P9BE: blr 3981; P9LE: lxv 3982; P9LE: blr 3983; P8BE: lxvd2x 3984; P8BE: blr 3985; P8LE: lxvd2x 3986; P8LE: blr 3987} 3988 3989; Function Attrs: norecurse nounwind readnone 3990define <2 x i64> @spltConst32kull() { 3991entry: 3992 ret <2 x i64> <i64 65535, i64 65535> 3993; P9BE-LABEL: spltConst32kull 3994; P9LE-LABEL: spltConst32kull 3995; P8BE-LABEL: spltConst32kull 3996; P8LE-LABEL: spltConst32kull 3997; P9BE: lxv 3998; P9BE: blr 3999; P9LE: lxv 4000; P9LE: blr 4001; P8BE: lxvd2x 4002; P8BE: blr 4003; P8LE: lxvd2x 4004; P8LE: blr 4005} 4006 4007; Function Attrs: norecurse nounwind readnone 4008define <2 x i64> @fromRegsull(i64 %a, i64 %b) { 4009entry: 4010 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 4011 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 4012 ret <2 x i64> %vecinit1 4013; P9BE-LABEL: fromRegsull 4014; P9LE-LABEL: fromRegsull 4015; P8BE-LABEL: fromRegsull 4016; P8LE-LABEL: fromRegsull 4017; P9BE: mtvsrdd v2, r3, r4 4018; P9BE: blr 4019; P9LE: mtvsrdd v2, r4, r3 4020; P9LE: blr 4021; P8BE-DAG: mtvsrd {{[vsf0-9]+}}, r3 4022; P8BE-DAG: mtvsrd {{[vsf0-9]+}}, r4 4023; P8BE: xxmrghd v2 4024; P8BE: blr 4025; P8LE-DAG: mtvsrd {{[vsf0-9]+}}, r3 4026; P8LE-DAG: mtvsrd {{[vsf0-9]+}}, r4 4027; P8LE: xxmrghd v2 4028; P8LE: blr 4029} 4030 4031; Function Attrs: norecurse nounwind readnone 4032define <2 x i64> @fromDiffConstsull() { 4033entry: 4034 ret <2 x i64> <i64 242, i64 -113> 4035; P9BE-LABEL: fromDiffConstsull 4036; P9LE-LABEL: fromDiffConstsull 4037; P8BE-LABEL: fromDiffConstsull 4038; P8LE-LABEL: fromDiffConstsull 4039; P9BE: lxv 4040; P9BE: blr 4041; P9LE: lxv 4042; P9LE: blr 4043; P8BE: lxvd2x 4044; P8BE: blr 4045; P8LE: lxvd2x 4046; P8LE: blr 4047} 4048 4049; Function Attrs: norecurse nounwind readonly 4050define <2 x i64> @fromDiffMemConsAull(i64* nocapture readonly %arr) { 4051entry: 4052 %0 = load i64, i64* %arr, align 8 4053 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4054 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 1 4055 %1 = load i64, i64* %arrayidx1, align 8 4056 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4057 ret <2 x i64> %vecinit2 4058; P9BE-LABEL: fromDiffMemConsAull 4059; P9LE-LABEL: fromDiffMemConsAull 4060; P8BE-LABEL: fromDiffMemConsAull 4061; P8LE-LABEL: fromDiffMemConsAull 4062; P9BE: lxv v2 4063; P9BE: blr 4064; P9LE: lxv v2 4065; P9LE: blr 4066; P8BE: lxvd2x v2 4067; P8BE: blr 4068; P8LE: lxvd2x 4069; P8LE: xxswapd v2 4070; P8LE: blr 4071} 4072 4073; Function Attrs: norecurse nounwind readonly 4074define <2 x i64> @fromDiffMemConsDull(i64* nocapture readonly %arr) { 4075entry: 4076 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 3 4077 %0 = load i64, i64* %arrayidx, align 8 4078 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4079 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 2 4080 %1 = load i64, i64* %arrayidx1, align 8 4081 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4082 ret <2 x i64> %vecinit2 4083; P9BE-LABEL: fromDiffMemConsDull 4084; P9LE-LABEL: fromDiffMemConsDull 4085; P8BE-LABEL: fromDiffMemConsDull 4086; P8LE-LABEL: fromDiffMemConsDull 4087; P9BE: lxv v2 4088; P9BE: blr 4089; P9LE: lxv 4090; P9LE: xxswapd v2 4091; P9LE: blr 4092; P8BE: lxvd2x 4093; P8BE: xxswapd v2 4094; P8BE-NEXT: blr 4095; P8LE: lxvd2x v2 4096; P8LE-NEXT: blr 4097} 4098 4099; Function Attrs: norecurse nounwind readonly 4100define <2 x i64> @fromDiffMemVarAull(i64* nocapture readonly %arr, i32 signext %elem) { 4101entry: 4102 %idxprom = sext i32 %elem to i64 4103 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4104 %0 = load i64, i64* %arrayidx, align 8 4105 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4106 %add = add nsw i32 %elem, 1 4107 %idxprom1 = sext i32 %add to i64 4108 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 4109 %1 = load i64, i64* %arrayidx2, align 8 4110 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4111 ret <2 x i64> %vecinit3 4112; P9BE-LABEL: fromDiffMemVarAull 4113; P9LE-LABEL: fromDiffMemVarAull 4114; P8BE-LABEL: fromDiffMemVarAull 4115; P8LE-LABEL: fromDiffMemVarAull 4116; P9BE: sldi 4117; P9BE: lxvx v2 4118; P9BE-NEXT: blr 4119; P9LE: sldi 4120; P9LE: lxvx v2 4121; P9LE-NEXT: blr 4122; P8BE: sldi 4123; P8BE: lxvd2x v2 4124; P8BE-NEXT: blr 4125; P8LE: sldi 4126; P8LE: lxvd2x 4127; P8LE: xxswapd v2 4128; P8LE-NEXT: blr 4129} 4130 4131; Function Attrs: norecurse nounwind readonly 4132define <2 x i64> @fromDiffMemVarDull(i64* nocapture readonly %arr, i32 signext %elem) { 4133entry: 4134 %idxprom = sext i32 %elem to i64 4135 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4136 %0 = load i64, i64* %arrayidx, align 8 4137 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4138 %sub = add nsw i32 %elem, -1 4139 %idxprom1 = sext i32 %sub to i64 4140 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 4141 %1 = load i64, i64* %arrayidx2, align 8 4142 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4143 ret <2 x i64> %vecinit3 4144; P9BE-LABEL: fromDiffMemVarDull 4145; P9LE-LABEL: fromDiffMemVarDull 4146; P8BE-LABEL: fromDiffMemVarDull 4147; P8LE-LABEL: fromDiffMemVarDull 4148; P9BE: sldi 4149; P9BE: lxv 4150; P9BE: xxswapd v2 4151; P9BE-NEXT: blr 4152; P9LE: sldi 4153; P9LE: lxv 4154; P9LE: xxswapd v2 4155; P9LE-NEXT: blr 4156; P8BE: sldi 4157; P8BE: lxvd2x 4158; P8BE: xxswapd v2 4159; P8BE-NEXT: blr 4160; P8LE: sldi 4161; P8LE: lxvd2x v2 4162; P8LE-NEXT: blr 4163} 4164 4165; Function Attrs: norecurse nounwind readonly 4166define <2 x i64> @fromRandMemConsull(i64* nocapture readonly %arr) { 4167entry: 4168 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4 4169 %0 = load i64, i64* %arrayidx, align 8 4170 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4171 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18 4172 %1 = load i64, i64* %arrayidx1, align 8 4173 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4174 ret <2 x i64> %vecinit2 4175; P9BE-LABEL: fromRandMemConsull 4176; P9LE-LABEL: fromRandMemConsull 4177; P8BE-LABEL: fromRandMemConsull 4178; P8LE-LABEL: fromRandMemConsull 4179; P9BE: ld 4180; P9BE: ld 4181; P9BE: mtvsrdd v2 4182; P9BE-NEXT: blr 4183; P9LE: ld 4184; P9LE: ld 4185; P9LE: mtvsrdd v2 4186; P9LE-NEXT: blr 4187; P8BE: ld 4188; P8BE: ld 4189; P8BE-DAG: mtvsrd 4190; P8BE-DAG: mtvsrd 4191; P8BE: xxmrghd v2 4192; P8BE-NEXT: blr 4193; P8LE: ld 4194; P8LE: ld 4195; P8LE-DAG: mtvsrd 4196; P8LE-DAG: mtvsrd 4197; P8LE: xxmrghd v2 4198; P8LE-NEXT: blr 4199} 4200 4201; Function Attrs: norecurse nounwind readonly 4202define <2 x i64> @fromRandMemVarull(i64* nocapture readonly %arr, i32 signext %elem) { 4203entry: 4204 %add = add nsw i32 %elem, 4 4205 %idxprom = sext i32 %add to i64 4206 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4207 %0 = load i64, i64* %arrayidx, align 8 4208 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4209 %add1 = add nsw i32 %elem, 1 4210 %idxprom2 = sext i32 %add1 to i64 4211 %arrayidx3 = getelementptr inbounds i64, i64* %arr, i64 %idxprom2 4212 %1 = load i64, i64* %arrayidx3, align 8 4213 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4214 ret <2 x i64> %vecinit4 4215; P9BE-LABEL: fromRandMemVarull 4216; P9LE-LABEL: fromRandMemVarull 4217; P8BE-LABEL: fromRandMemVarull 4218; P8LE-LABEL: fromRandMemVarull 4219; P9BE: sldi 4220; P9BE: ld 4221; P9BE: ld 4222; P9BE: mtvsrdd v2 4223; P9BE-NEXT: blr 4224; P9LE: sldi 4225; P9LE: ld 4226; P9LE: ld 4227; P9LE: mtvsrdd v2 4228; P9LE-NEXT: blr 4229; P8BE: sldi 4230; P8BE: ld 4231; P8BE: ld 4232; P8BE: mtvsrd 4233; P8BE: mtvsrd 4234; P8BE: xxmrghd v2 4235; P8BE-NEXT: blr 4236; P8LE: sldi 4237; P8LE: ld 4238; P8LE: ld 4239; P8LE: mtvsrd 4240; P8LE: mtvsrd 4241; P8LE: xxmrghd v2 4242; P8LE-NEXT: blr 4243} 4244 4245; Function Attrs: norecurse nounwind readnone 4246define <2 x i64> @spltRegValull(i64 %val) { 4247entry: 4248 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0 4249 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4250 ret <2 x i64> %splat.splat 4251; P9BE-LABEL: spltRegValull 4252; P9LE-LABEL: spltRegValull 4253; P8BE-LABEL: spltRegValull 4254; P8LE-LABEL: spltRegValull 4255; P9BE: mtvsrdd v2, r3, r3 4256; P9BE-NEXT: blr 4257; P9LE: mtvsrdd v2, r3, r3 4258; P9LE-NEXT: blr 4259; P8BE: mtvsrd {{[vsf]+}}[[REG1:[0-9]+]], r3 4260; P8BE: xxspltd v2, {{[vsf]+}}[[REG1]], 0 4261; P8BE-NEXT: blr 4262; P8LE: mtvsrd {{[vsf]+}}[[REG1:[0-9]+]], r3 4263; P8LE: xxspltd v2, {{[vsf]+}}[[REG1]], 0 4264; P8LE-NEXT: blr 4265} 4266 4267; Function Attrs: norecurse nounwind readonly 4268define <2 x i64> @spltMemValull(i64* nocapture readonly %ptr) { 4269entry: 4270 %0 = load i64, i64* %ptr, align 8 4271 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 4272 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4273 ret <2 x i64> %splat.splat 4274; P9BE-LABEL: spltMemValull 4275; P9LE-LABEL: spltMemValull 4276; P8BE-LABEL: spltMemValull 4277; P8LE-LABEL: spltMemValull 4278; P9BE: lxvdsx v2 4279; P9BE-NEXT: blr 4280; P9LE: lxvdsx v2 4281; P9LE-NEXT: blr 4282; P8BE: lxvdsx v2 4283; P8BE-NEXT: blr 4284; P8LE: lxvdsx v2 4285; P8LE-NEXT: blr 4286} 4287 4288; Function Attrs: norecurse nounwind readnone 4289define <2 x i64> @spltCnstConvftoull() { 4290entry: 4291 ret <2 x i64> <i64 4, i64 4> 4292; P9BE-LABEL: spltCnstConvftoull 4293; P9LE-LABEL: spltCnstConvftoull 4294; P8BE-LABEL: spltCnstConvftoull 4295; P8LE-LABEL: spltCnstConvftoull 4296; P9BE: lxv 4297; P9BE: blr 4298; P9LE: lxv 4299; P9LE: blr 4300; P8BE: lxvd2x 4301; P8BE: blr 4302; P8LE: lxvd2x 4303; P8LE: blr 4304} 4305 4306; Function Attrs: norecurse nounwind readnone 4307define <2 x i64> @fromRegsConvftoull(float %a, float %b) { 4308entry: 4309 %conv = fptoui float %a to i64 4310 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4311 %conv1 = fptoui float %b to i64 4312 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 4313 ret <2 x i64> %vecinit2 4314; P9BE-LABEL: fromRegsConvftoull 4315; P9LE-LABEL: fromRegsConvftoull 4316; P8BE-LABEL: fromRegsConvftoull 4317; P8LE-LABEL: fromRegsConvftoull 4318; P9BE: xxmrghd 4319; P9BE: xvcvdpuxds v2 4320; P9BE-NEXT: blr 4321; P9LE: xxmrghd 4322; P9LE: xvcvdpuxds v2 4323; P9LE-NEXT: blr 4324; P8BE: xxmrghd 4325; P8BE: xvcvdpuxds v2 4326; P8BE-NEXT: blr 4327; P8LE: xxmrghd 4328; P8LE: xvcvdpuxds v2 4329; P8LE-NEXT: blr 4330} 4331 4332; Function Attrs: norecurse nounwind readnone 4333define <2 x i64> @fromDiffConstsConvftoull() { 4334entry: 4335 ret <2 x i64> <i64 24, i64 234> 4336; P9BE-LABEL: fromDiffConstsConvftoull 4337; P9LE-LABEL: fromDiffConstsConvftoull 4338; P8BE-LABEL: fromDiffConstsConvftoull 4339; P8LE-LABEL: fromDiffConstsConvftoull 4340; P9BE: lxvx v2 4341; P9BE: blr 4342; P9LE: lxvx v2 4343; P9LE: blr 4344; P8BE: lxvd2x v2 4345; P8BE: blr 4346; P8LE: lxvd2x 4347; P8LE: xxswapd v2 4348; P8LE: blr 4349} 4350 4351; Function Attrs: norecurse nounwind readonly 4352define <2 x i64> @fromDiffMemConsAConvftoull(float* nocapture readonly %ptr) { 4353entry: 4354 %0 = load float, float* %ptr, align 4 4355 %conv = fptoui float %0 to i64 4356 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4357 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1 4358 %1 = load float, float* %arrayidx1, align 4 4359 %conv2 = fptoui float %1 to i64 4360 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4361 ret <2 x i64> %vecinit3 4362; P9BE-LABEL: fromDiffMemConsAConvftoull 4363; P9LE-LABEL: fromDiffMemConsAConvftoull 4364; P8BE-LABEL: fromDiffMemConsAConvftoull 4365; P8LE-LABEL: fromDiffMemConsAConvftoull 4366; P9BE: lfs 4367; P9BE: lfs 4368; P9BE: xxmrghd 4369; P9BE-NEXT: xvcvdpuxds v2 4370; P9BE-NEXT: blr 4371; P9LE: lfs 4372; P9LE: lfs 4373; P9LE: xxmrghd 4374; P9LE-NEXT: xvcvdpuxds v2 4375; P9LE-NEXT: blr 4376; P8BE: lfs 4377; P8BE: lfs 4378; P8BE: xxmrghd 4379; P8BE-NEXT: xvcvdpuxds v2 4380; P8BE-NEXT: blr 4381; P8LE: lfs 4382; P8LE: lfs 4383; P8LE: xxmrghd 4384; P8LE-NEXT: xvcvdpuxds v2 4385; P8LE-NEXT: blr 4386} 4387 4388; Function Attrs: norecurse nounwind readonly 4389define <2 x i64> @fromDiffMemConsDConvftoull(float* nocapture readonly %ptr) { 4390entry: 4391 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 4392 %0 = load float, float* %arrayidx, align 4 4393 %conv = fptoui float %0 to i64 4394 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4395 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 4396 %1 = load float, float* %arrayidx1, align 4 4397 %conv2 = fptoui float %1 to i64 4398 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4399 ret <2 x i64> %vecinit3 4400; P9BE-LABEL: fromDiffMemConsDConvftoull 4401; P9LE-LABEL: fromDiffMemConsDConvftoull 4402; P8BE-LABEL: fromDiffMemConsDConvftoull 4403; P8LE-LABEL: fromDiffMemConsDConvftoull 4404; P9BE: lfs 4405; P9BE: lfs 4406; P9BE: xxmrghd 4407; P9BE-NEXT: xvcvdpuxds v2 4408; P9BE-NEXT: blr 4409; P9LE: lfs 4410; P9LE: lfs 4411; P9LE: xxmrghd 4412; P9LE-NEXT: xvcvdpuxds v2 4413; P9LE-NEXT: blr 4414; P8BE: lfs 4415; P8BE: lfs 4416; P8BE: xxmrghd 4417; P8BE-NEXT: xvcvdpuxds v2 4418; P8BE-NEXT: blr 4419; P8LE: lfs 4420; P8LE: lfs 4421; P8LE: xxmrghd 4422; P8LE-NEXT: xvcvdpuxds v2 4423; P8LE-NEXT: blr 4424} 4425 4426; Function Attrs: norecurse nounwind readonly 4427define <2 x i64> @fromDiffMemVarAConvftoull(float* nocapture readonly %arr, i32 signext %elem) { 4428entry: 4429 %idxprom = sext i32 %elem to i64 4430 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 4431 %0 = load float, float* %arrayidx, align 4 4432 %conv = fptoui float %0 to i64 4433 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4434 %add = add nsw i32 %elem, 1 4435 %idxprom1 = sext i32 %add to i64 4436 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 4437 %1 = load float, float* %arrayidx2, align 4 4438 %conv3 = fptoui float %1 to i64 4439 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4440 ret <2 x i64> %vecinit4 4441; P9BE-LABEL: fromDiffMemVarAConvftoull 4442; P9LE-LABEL: fromDiffMemVarAConvftoull 4443; P8BE-LABEL: fromDiffMemVarAConvftoull 4444; P8LE-LABEL: fromDiffMemVarAConvftoull 4445; P9BE: sldi 4446; P9BE: lfsux 4447; P9BE: lfs 4448; P9BE: xxmrghd 4449; P9BE-NEXT: xvcvdpuxds v2 4450; P9BE-NEXT: blr 4451; P9LE: sldi 4452; P9LE: lfsux 4453; P9LE: lfs 4454; P9LE: xxmrghd 4455; P9LE-NEXT: xvcvdpuxds v2 4456; P9LE-NEXT: blr 4457; P8BE: sldi 4458; P8BE: lfsux 4459; P8BE: lfs 4460; P8BE: xxmrghd 4461; P8BE-NEXT: xvcvdpuxds v2 4462; P8BE-NEXT: blr 4463; P8LE: sldi 4464; P8LE: lfsux 4465; P8LE: lfs 4466; P8LE: xxmrghd 4467; P8LE-NEXT: xvcvdpuxds v2 4468; P8LE-NEXT: blr 4469} 4470 4471; Function Attrs: norecurse nounwind readonly 4472define <2 x i64> @fromDiffMemVarDConvftoull(float* nocapture readonly %arr, i32 signext %elem) { 4473entry: 4474 %idxprom = sext i32 %elem to i64 4475 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 4476 %0 = load float, float* %arrayidx, align 4 4477 %conv = fptoui float %0 to i64 4478 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4479 %sub = add nsw i32 %elem, -1 4480 %idxprom1 = sext i32 %sub to i64 4481 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 4482 %1 = load float, float* %arrayidx2, align 4 4483 %conv3 = fptoui float %1 to i64 4484 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4485 ret <2 x i64> %vecinit4 4486; P9BE-LABEL: fromDiffMemVarDConvftoull 4487; P9LE-LABEL: fromDiffMemVarDConvftoull 4488; P8BE-LABEL: fromDiffMemVarDConvftoull 4489; P8LE-LABEL: fromDiffMemVarDConvftoull 4490; P9BE: sldi 4491; P9BE: lfsux 4492; P9BE: lfs 4493; P9BE: xxmrghd 4494; P9BE-NEXT: xvcvdpuxds v2 4495; P9BE-NEXT: blr 4496; P9LE: sldi 4497; P9LE: lfsux 4498; P9LE: lfs 4499; P9LE: xxmrghd 4500; P9LE-NEXT: xvcvdpuxds v2 4501; P9LE-NEXT: blr 4502; P8BE: sldi 4503; P8BE: lfsux 4504; P8BE: lfs 4505; P8BE: xxmrghd 4506; P8BE-NEXT: xvcvdpuxds v2 4507; P8BE-NEXT: blr 4508; P8LE: sldi 4509; P8LE: lfsux 4510; P8LE: lfs 4511; P8LE: xxmrghd 4512; P8LE-NEXT: xvcvdpuxds v2 4513; P8LE-NEXT: blr 4514} 4515 4516; Function Attrs: norecurse nounwind readnone 4517define <2 x i64> @spltRegValConvftoull(float %val) { 4518entry: 4519 %conv = fptoui float %val to i64 4520 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4521 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4522 ret <2 x i64> %splat.splat 4523; P9BE-LABEL: spltRegValConvftoull 4524; P9LE-LABEL: spltRegValConvftoull 4525; P8BE-LABEL: spltRegValConvftoull 4526; P8LE-LABEL: spltRegValConvftoull 4527; P9BE: xscvdpuxds 4528; P9BE-NEXT: xxspltd v2 4529; P9BE-NEXT: blr 4530; P9LE: xscvdpuxds 4531; P9LE-NEXT: xxspltd v2 4532; P9LE-NEXT: blr 4533; P8BE: xscvdpuxds 4534; P8BE-NEXT: xxspltd v2 4535; P8BE-NEXT: blr 4536; P8LE: xscvdpuxds 4537; P8LE-NEXT: xxspltd v2 4538; P8LE-NEXT: blr 4539} 4540 4541; Function Attrs: norecurse nounwind readonly 4542define <2 x i64> @spltMemValConvftoull(float* nocapture readonly %ptr) { 4543entry: 4544 %0 = load float, float* %ptr, align 4 4545 %conv = fptoui float %0 to i64 4546 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4547 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4548 ret <2 x i64> %splat.splat 4549; P9BE-LABEL: spltMemValConvftoull 4550; P9LE-LABEL: spltMemValConvftoull 4551; P8BE-LABEL: spltMemValConvftoull 4552; P8LE-LABEL: spltMemValConvftoull 4553; P9BE: lfs 4554; P9BE-NEXT: xscvdpuxds 4555; P9BE-NEXT: xxspltd v2 4556; P9BE-NEXT: blr 4557; P9LE: lfs 4558; P9LE-NEXT: xscvdpuxds 4559; P9LE-NEXT: xxspltd v2 4560; P9LE-NEXT: blr 4561; P8BE: lfs 4562; P8BE-NEXT: xscvdpuxds 4563; P8BE-NEXT: xxspltd v2 4564; P8BE-NEXT: blr 4565; P8LE: lfs 4566; P8LE-NEXT: xscvdpuxds 4567; P8LE-NEXT: xxspltd v2 4568; P8LE-NEXT: blr 4569} 4570 4571; Function Attrs: norecurse nounwind readnone 4572define <2 x i64> @spltCnstConvdtoull() { 4573entry: 4574 ret <2 x i64> <i64 4, i64 4> 4575; P9BE-LABEL: spltCnstConvdtoull 4576; P9LE-LABEL: spltCnstConvdtoull 4577; P8BE-LABEL: spltCnstConvdtoull 4578; P8LE-LABEL: spltCnstConvdtoull 4579; P9BE: lxv 4580; P9BE: blr 4581; P9LE: lxv 4582; P9LE: blr 4583; P8BE: lxvd2x 4584; P8BE: blr 4585; P8LE: lxvd2x 4586; P8LE: blr 4587} 4588 4589; Function Attrs: norecurse nounwind readnone 4590define <2 x i64> @fromRegsConvdtoull(double %a, double %b) { 4591entry: 4592 %conv = fptoui double %a to i64 4593 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4594 %conv1 = fptoui double %b to i64 4595 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 4596 ret <2 x i64> %vecinit2 4597; P9BE-LABEL: fromRegsConvdtoull 4598; P9LE-LABEL: fromRegsConvdtoull 4599; P8BE-LABEL: fromRegsConvdtoull 4600; P8LE-LABEL: fromRegsConvdtoull 4601; P9BE: xxmrghd 4602; P9BE-NEXT: xvcvdpuxds 4603; P9BE-NEXT: blr 4604; P9LE: xxmrghd 4605; P9LE-NEXT: xvcvdpuxds 4606; P9LE-NEXT: blr 4607; P8BE: xxmrghd 4608; P8BE-NEXT: xvcvdpuxds 4609; P8BE-NEXT: blr 4610; P8LE: xxmrghd 4611; P8LE-NEXT: xvcvdpuxds 4612; P8LE-NEXT: blr 4613} 4614 4615; Function Attrs: norecurse nounwind readnone 4616define <2 x i64> @fromDiffConstsConvdtoull() { 4617entry: 4618 ret <2 x i64> <i64 24, i64 234> 4619; P9BE-LABEL: fromDiffConstsConvdtoull 4620; P9LE-LABEL: fromDiffConstsConvdtoull 4621; P8BE-LABEL: fromDiffConstsConvdtoull 4622; P8LE-LABEL: fromDiffConstsConvdtoull 4623; P9BE: lxv 4624; P9BE: blr 4625; P9LE: lxv 4626; P9LE: blr 4627; P8BE: lxvd2x 4628; P8BE: blr 4629; P8LE: lxvd2x 4630; P8LE: blr 4631} 4632 4633; Function Attrs: norecurse nounwind readonly 4634define <2 x i64> @fromDiffMemConsAConvdtoull(double* nocapture readonly %ptr) { 4635entry: 4636 %0 = bitcast double* %ptr to <2 x double>* 4637 %1 = load <2 x double>, <2 x double>* %0, align 8 4638 %2 = fptoui <2 x double> %1 to <2 x i64> 4639 ret <2 x i64> %2 4640; P9BE-LABEL: fromDiffMemConsAConvdtoull 4641; P9LE-LABEL: fromDiffMemConsAConvdtoull 4642; P8BE-LABEL: fromDiffMemConsAConvdtoull 4643; P8LE-LABEL: fromDiffMemConsAConvdtoull 4644; P9BE: lxv 4645; P9BE-NEXT: xvcvdpuxds v2 4646; P9BE-NEXT: blr 4647; P9LE: lxv 4648; P9LE-NEXT: xvcvdpuxds v2 4649; P9LE-NEXT: blr 4650; P8BE: lxvd2x 4651; P8BE-NEXT: xvcvdpuxds v2 4652; P8BE-NEXT: blr 4653; P8LE: lxvd2x 4654; P8LE: xxswapd 4655; P8LE-NEXT: xvcvdpuxds v2 4656; P8LE-NEXT: blr 4657} 4658 4659; Function Attrs: norecurse nounwind readonly 4660define <2 x i64> @fromDiffMemConsDConvdtoull(double* nocapture readonly %ptr) { 4661entry: 4662 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 4663 %0 = load double, double* %arrayidx, align 8 4664 %conv = fptoui double %0 to i64 4665 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4666 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 4667 %1 = load double, double* %arrayidx1, align 8 4668 %conv2 = fptoui double %1 to i64 4669 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4670 ret <2 x i64> %vecinit3 4671; P9BE-LABEL: fromDiffMemConsDConvdtoull 4672; P9LE-LABEL: fromDiffMemConsDConvdtoull 4673; P8BE-LABEL: fromDiffMemConsDConvdtoull 4674; P8LE-LABEL: fromDiffMemConsDConvdtoull 4675; P9BE: lxv 4676; P9BE-NEXT: xxswapd 4677; P9BE-NEXT: xvcvdpuxds v2 4678; P9BE-NEXT: blr 4679; P9LE: lxv 4680; P9LE-NEXT: xxswapd 4681; P9LE-NEXT: xvcvdpuxds v2 4682; P9LE-NEXT: blr 4683; P8BE: lxvd2x 4684; P8BE-NEXT: xxswapd 4685; P8BE-NEXT: xvcvdpuxds v2 4686; P8BE-NEXT: blr 4687; P8LE: lxvd2x 4688; P8LE-NEXT: xvcvdpuxds v2 4689; P8LE-NEXT: blr 4690} 4691 4692; Function Attrs: norecurse nounwind readonly 4693define <2 x i64> @fromDiffMemVarAConvdtoull(double* nocapture readonly %arr, i32 signext %elem) { 4694entry: 4695 %idxprom = sext i32 %elem to i64 4696 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 4697 %0 = load double, double* %arrayidx, align 8 4698 %conv = fptoui double %0 to i64 4699 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4700 %add = add nsw i32 %elem, 1 4701 %idxprom1 = sext i32 %add to i64 4702 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 4703 %1 = load double, double* %arrayidx2, align 8 4704 %conv3 = fptoui double %1 to i64 4705 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4706 ret <2 x i64> %vecinit4 4707; P9BE-LABEL: fromDiffMemVarAConvdtoull 4708; P9LE-LABEL: fromDiffMemVarAConvdtoull 4709; P8BE-LABEL: fromDiffMemVarAConvdtoull 4710; P8LE-LABEL: fromDiffMemVarAConvdtoull 4711; P9BE: sldi 4712; P9BE: lxvx 4713; P9BE-NEXT: xvcvdpuxds v2 4714; P9BE-NEXT: blr 4715; P9LE: sldi 4716; P9LE: lxvx 4717; P9LE-NEXT: xvcvdpuxds v2 4718; P9LE-NEXT: blr 4719; P8BE: sldi 4720; P8BE: lxvd2x 4721; P8BE-NEXT: xvcvdpuxds v2 4722; P8BE-NEXT: blr 4723; P8LE: sldi 4724; P8LE: lxvd2x 4725; P8LE-NEXT: xxswapd 4726; P8LE-NEXT: xvcvdpuxds v2 4727; P8LE-NEXT: blr 4728} 4729 4730; Function Attrs: norecurse nounwind readonly 4731define <2 x i64> @fromDiffMemVarDConvdtoull(double* nocapture readonly %arr, i32 signext %elem) { 4732entry: 4733 %idxprom = sext i32 %elem to i64 4734 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 4735 %0 = load double, double* %arrayidx, align 8 4736 %conv = fptoui double %0 to i64 4737 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4738 %sub = add nsw i32 %elem, -1 4739 %idxprom1 = sext i32 %sub to i64 4740 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 4741 %1 = load double, double* %arrayidx2, align 8 4742 %conv3 = fptoui double %1 to i64 4743 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4744 ret <2 x i64> %vecinit4 4745; P9BE-LABEL: fromDiffMemVarDConvdtoull 4746; P9LE-LABEL: fromDiffMemVarDConvdtoull 4747; P8BE-LABEL: fromDiffMemVarDConvdtoull 4748; P8LE-LABEL: fromDiffMemVarDConvdtoull 4749; P9BE: sldi 4750; P9BE: lxv 4751; P9BE-NEXT: xxswapd 4752; P9BE-NEXT: xvcvdpuxds v2 4753; P9BE-NEXT: blr 4754; P9LE: sldi 4755; P9LE: lxv 4756; P9LE-NEXT: xxswapd 4757; P9LE-NEXT: xvcvdpuxds v2 4758; P9LE-NEXT: blr 4759; P8BE: sldi 4760; P8BE: lxvd2x 4761; P8BE-NEXT: xxswapd 4762; P8BE-NEXT: xvcvdpuxds v2 4763; P8BE-NEXT: blr 4764; P8LE: sldi 4765; P8LE: lxvd2x 4766; P8LE-NEXT: xvcvdpuxds v2 4767; P8LE-NEXT: blr 4768} 4769 4770; Function Attrs: norecurse nounwind readnone 4771define <2 x i64> @spltRegValConvdtoull(double %val) { 4772entry: 4773 %conv = fptoui double %val to i64 4774 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4775 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4776 ret <2 x i64> %splat.splat 4777; P9BE-LABEL: spltRegValConvdtoull 4778; P9LE-LABEL: spltRegValConvdtoull 4779; P8BE-LABEL: spltRegValConvdtoull 4780; P8LE-LABEL: spltRegValConvdtoull 4781; P9BE: xscvdpuxds 4782; P9BE-NEXT: xxspltd v2 4783; P9BE-NEXT: blr 4784; P9LE: xscvdpuxds 4785; P9LE-NEXT: xxspltd v2 4786; P9LE-NEXT: blr 4787; P8BE: xscvdpuxds 4788; P8BE-NEXT: xxspltd v2 4789; P8BE-NEXT: blr 4790; P8LE: xscvdpuxds 4791; P8LE-NEXT: xxspltd v2 4792; P8LE-NEXT: blr 4793} 4794 4795; Function Attrs: norecurse nounwind readonly 4796define <2 x i64> @spltMemValConvdtoull(double* nocapture readonly %ptr) { 4797entry: 4798 %0 = load double, double* %ptr, align 8 4799 %conv = fptoui double %0 to i64 4800 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4801 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4802 ret <2 x i64> %splat.splat 4803; P9BE-LABEL: spltMemValConvdtoull 4804; P9LE-LABEL: spltMemValConvdtoull 4805; P8BE-LABEL: spltMemValConvdtoull 4806; P8LE-LABEL: spltMemValConvdtoull 4807; P9BE: lxvdsx 4808; P9BE-NEXT: xvcvdpuxds 4809; P9BE-NEXT: blr 4810; P9LE: lxvdsx 4811; P9LE-NEXT: xvcvdpuxds 4812; P9LE-NEXT: blr 4813; P8BE: lxvdsx 4814; P8BE-NEXT: xvcvdpuxds 4815; P8BE-NEXT: blr 4816; P8LE: lxvdsx 4817; P8LE-NEXT: xvcvdpuxds 4818; P8LE-NEXT: blr 4819} 4820