1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 3; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \ 4; RUN: -check-prefix=P9BE -implicit-check-not frsp 5; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 6; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \ 7; RUN: -check-prefix=P9LE -implicit-check-not frsp 8; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 9; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \ 10; RUN: -check-prefix=P8BE -implicit-check-not frsp 11; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 12; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \ 13; RUN: -check-prefix=P8LE -implicit-check-not frsp 14 15; This test case comes from the following C test case (included as it may be 16; slightly more readable than the LLVM IR. 17 18;/* This test case provides various ways of building vectors to ensure we 19; produce optimal code for all cases. The cases are (for each type): 20; - All zeros 21; - All ones 22; - Splat of a constant 23; - From different values already in registers 24; - From different constants 25; - From different values in memory 26; - Splat of a value in register 27; - Splat of a value in memory 28; - Inserting element into existing vector 29; - Inserting element from existing vector into existing vector 30; 31; With conversions (float <-> int) 32; - Splat of a constant 33; - From different values already in registers 34; - From different constants 35; - From different values in memory 36; - Splat of a value in register 37; - Splat of a value in memory 38; - Inserting element into existing vector 39; - Inserting element from existing vector into existing vector 40;*/ 41; 42;/*=================================== int ===================================*/ 43;// P8: xxlxor // 44;// P9: xxlxor // 45;vector int allZeroi() { // 46; return (vector int)0; // 47;} // 48;// P8: vspltisb -1 // 49;// P9: xxspltisb 255 // 50;vector int allOnei() { // 51; return (vector int)-1; // 52;} // 53;// P8: vspltisw 1 // 54;// P9: vspltisw 1 // 55;vector int spltConst1i() { // 56; return (vector int)1; // 57;} // 58;// P8: vspltisw -15; vsrw // 59;// P9: vspltisw -15; vsrw // 60;vector int spltConst16ki() { // 61; return (vector int)((1<<15) - 1); // 62;} // 63;// P8: vspltisw -16; vsrw // 64;// P9: vspltisw -16; vsrw // 65;vector int spltConst32ki() { // 66; return (vector int)((1<<16) - 1); // 67;} // 68;// P8: 4 x mtvsrwz, 2 x xxmrgh, vmrgow // 69;// P9: 2 x mtvsrdd, vmrgow // 70;vector int fromRegsi(int a, int b, int c, int d) { // 71; return (vector int){ a, b, c, d }; // 72;} // 73;// P8: lxvd2x, xxswapd // 74;// P9: lxvx (or even lxv) // 75;vector int fromDiffConstsi() { // 76; return (vector int) { 242, -113, 889, 19 }; // 77;} // 78;// P8: lxvd2x, xxswapd // 79;// P9: lxvx // 80;vector int fromDiffMemConsAi(int *arr) { // 81; return (vector int) { arr[0], arr[1], arr[2], arr[3] }; // 82;} // 83;// P8: 2 x lxvd2x, 2 x xxswapd, vperm // 84;// P9: 2 x lxvx, vperm // 85;vector int fromDiffMemConsDi(int *arr) { // 86; return (vector int) { arr[3], arr[2], arr[1], arr[0] }; // 87;} // 88;// P8: sldi 2, lxvd2x, xxswapd // 89;// P9: sldi 2, lxvx // 90;vector int fromDiffMemVarAi(int *arr, int elem) { // 91; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 92;} // 93;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm // 94;// P9: sldi 2, 2 x lxvx, vperm // 95;vector int fromDiffMemVarDi(int *arr, int elem) { // 96; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 97;} // 98;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 99;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow // 100;vector int fromRandMemConsi(int *arr) { // 101; return (vector int) { arr[4], arr[18], arr[2], arr[88] }; // 102;} // 103;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 104;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow // 105;vector int fromRandMemVari(int *arr, int elem) { // 106; return (vector int) { arr[elem+4], arr[elem+1], arr[elem+2], arr[elem+8] };// 107;} // 108;// P8: mtvsrwz, xxspltw // 109;// P9: mtvsrws // 110;vector int spltRegVali(int val) { // 111; return (vector int) val; // 112;} // 113;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 114;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 115;vector int spltMemVali(int *ptr) { // 116; return (vector int)*ptr; // 117;} // 118;// P8: vspltisw // 119;// P9: vspltisw // 120;vector int spltCnstConvftoi() { // 121; return (vector int) 4.74f; // 122;} // 123;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 124;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 125;vector int fromRegsConvftoi(float a, float b, float c, float d) { // 126; return (vector int) { a, b, c, d }; // 127;} // 128;// P8: lxvd2x, xxswapd // 129;// P9: lxvx (even lxv) // 130;vector int fromDiffConstsConvftoi() { // 131; return (vector int) { 24.46f, 234.f, 988.19f, 422.39f }; // 132;} // 133;// P8: lxvd2x, xxswapd, xvcvspsxws // 134;// P9: lxvx, xvcvspsxws // 135;vector int fromDiffMemConsAConvftoi(float *ptr) { // 136; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 137;} // 138;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspsxws // 139;// P9: 2 x lxvx, vperm, xvcvspsxws // 140;vector int fromDiffMemConsDConvftoi(float *ptr) { // 141; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 142;} // 143;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 144;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 145;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 146;// sldi 2, load, xvcvspuxws // 147;vector int fromDiffMemVarAConvftoi(float *arr, int elem) { // 148; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 149;} // 150;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 151;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 152;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 153;// sldi 2, 2 x load, vperm, xvcvspuxws // 154;vector int fromDiffMemVarDConvftoi(float *arr, int elem) { // 155; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 156;} // 157;// P8: xscvdpsxws, xxspltw // 158;// P9: xscvdpsxws, xxspltw // 159;vector int spltRegValConvftoi(float val) { // 160; return (vector int) val; // 161;} // 162;// P8: lxsspx, xscvdpsxws, xxspltw // 163;// P9: lxvwsx, xvcvspsxws // 164;vector int spltMemValConvftoi(float *ptr) { // 165; return (vector int)*ptr; // 166;} // 167;// P8: vspltisw // 168;// P9: vspltisw // 169;vector int spltCnstConvdtoi() { // 170; return (vector int) 4.74; // 171;} // 172;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 173;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 174;vector int fromRegsConvdtoi(double a, double b, double c, double d) { // 175; return (vector int) { a, b, c, d }; // 176;} // 177;// P8: lxvd2x, xxswapd // 178;// P9: lxvx (even lxv) // 179;vector int fromDiffConstsConvdtoi() { // 180; return (vector int) { 24.46, 234., 988.19, 422.39 }; // 181;} // 182;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew // 183;// P9: 2 x lxvx, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew // 184;vector int fromDiffMemConsAConvdtoi(double *ptr) { // 185; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 186;} // 187;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 188;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 189;vector int fromDiffMemConsDConvdtoi(double *ptr) { // 190; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 191;} // 192;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 193;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 194;vector int fromDiffMemVarAConvdtoi(double *arr, int elem) { // 195; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 196;} // 197;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 198;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 199;vector int fromDiffMemVarDConvdtoi(double *arr, int elem) { // 200; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 201;} // 202;// P8: xscvdpsxws, xxspltw // 203;// P9: xscvdpsxws, xxspltw // 204;vector int spltRegValConvdtoi(double val) { // 205; return (vector int) val; // 206;} // 207;// P8: lxsdx, xscvdpsxws, xxspltw // 208;// P9: lxssp, xscvdpsxws, xxspltw // 209;vector int spltMemValConvdtoi(double *ptr) { // 210; return (vector int)*ptr; // 211;} // 212;/*=================================== int ===================================*/ 213;/*=============================== unsigned int ==============================*/ 214;// P8: xxlxor // 215;// P9: xxlxor // 216;vector unsigned int allZeroui() { // 217; return (vector unsigned int)0; // 218;} // 219;// P8: vspltisb -1 // 220;// P9: xxspltisb 255 // 221;vector unsigned int allOneui() { // 222; return (vector unsigned int)-1; // 223;} // 224;// P8: vspltisw 1 // 225;// P9: vspltisw 1 // 226;vector unsigned int spltConst1ui() { // 227; return (vector unsigned int)1; // 228;} // 229;// P8: vspltisw -15; vsrw // 230;// P9: vspltisw -15; vsrw // 231;vector unsigned int spltConst16kui() { // 232; return (vector unsigned int)((1<<15) - 1); // 233;} // 234;// P8: vspltisw -16; vsrw // 235;// P9: vspltisw -16; vsrw // 236;vector unsigned int spltConst32kui() { // 237; return (vector unsigned int)((1<<16) - 1); // 238;} // 239;// P8: 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 240;// P9: 2 x mtvsrdd, vmrgow // 241;vector unsigned int fromRegsui(unsigned int a, unsigned int b, // 242; unsigned int c, unsigned int d) { // 243; return (vector unsigned int){ a, b, c, d }; // 244;} // 245;// P8: lxvd2x, xxswapd // 246;// P9: lxvx (or even lxv) // 247;vector unsigned int fromDiffConstsui() { // 248; return (vector unsigned int) { 242, -113, 889, 19 }; // 249;} // 250;// P8: lxvd2x, xxswapd // 251;// P9: lxvx // 252;vector unsigned int fromDiffMemConsAui(unsigned int *arr) { // 253; return (vector unsigned int) { arr[0], arr[1], arr[2], arr[3] }; // 254;} // 255;// P8: 2 x lxvd2x, 2 x xxswapd, vperm // 256;// P9: 2 x lxvx, vperm // 257;vector unsigned int fromDiffMemConsDui(unsigned int *arr) { // 258; return (vector unsigned int) { arr[3], arr[2], arr[1], arr[0] }; // 259;} // 260;// P8: sldi 2, lxvd2x, xxswapd // 261;// P9: sldi 2, lxvx // 262;vector unsigned int fromDiffMemVarAui(unsigned int *arr, int elem) { // 263; return (vector unsigned int) { arr[elem], arr[elem+1], // 264; arr[elem+2], arr[elem+3] }; // 265;} // 266;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm // 267;// P9: sldi 2, 2 x lxvx, vperm // 268;vector unsigned int fromDiffMemVarDui(unsigned int *arr, int elem) { // 269; return (vector unsigned int) { arr[elem], arr[elem-1], // 270; arr[elem-2], arr[elem-3] }; // 271;} // 272;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 273;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow // 274;vector unsigned int fromRandMemConsui(unsigned int *arr) { // 275; return (vector unsigned int) { arr[4], arr[18], arr[2], arr[88] }; // 276;} // 277;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 278;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow // 279;vector unsigned int fromRandMemVarui(unsigned int *arr, int elem) { // 280; return (vector unsigned int) { arr[elem+4], arr[elem+1], // 281; arr[elem+2], arr[elem+8] }; // 282;} // 283;// P8: mtvsrwz, xxspltw // 284;// P9: mtvsrws // 285;vector unsigned int spltRegValui(unsigned int val) { // 286; return (vector unsigned int) val; // 287;} // 288;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 289;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 290;vector unsigned int spltMemValui(unsigned int *ptr) { // 291; return (vector unsigned int)*ptr; // 292;} // 293;// P8: vspltisw // 294;// P9: vspltisw // 295;vector unsigned int spltCnstConvftoui() { // 296; return (vector unsigned int) 4.74f; // 297;} // 298;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 299;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 300;vector unsigned int fromRegsConvftoui(float a, float b, float c, float d) { // 301; return (vector unsigned int) { a, b, c, d }; // 302;} // 303;// P8: lxvd2x, xxswapd // 304;// P9: lxvx (even lxv) // 305;vector unsigned int fromDiffConstsConvftoui() { // 306; return (vector unsigned int) { 24.46f, 234.f, 988.19f, 422.39f }; // 307;} // 308;// P8: lxvd2x, xxswapd, xvcvspuxws // 309;// P9: lxvx, xvcvspuxws // 310;vector unsigned int fromDiffMemConsAConvftoui(float *ptr) { // 311; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 312;} // 313;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspuxws // 314;// P9: 2 x lxvx, vperm, xvcvspuxws // 315;vector unsigned int fromDiffMemConsDConvftoui(float *ptr) { // 316; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 317;} // 318;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 319;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 320;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 321;// sldi 2, load, xvcvspuxws // 322;vector unsigned int fromDiffMemVarAConvftoui(float *arr, int elem) { // 323; return (vector unsigned int) { arr[elem], arr[elem+1], // 324; arr[elem+2], arr[elem+3] }; // 325;} // 326;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 327;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 328;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 329;// sldi 2, 2 x load, vperm, xvcvspuxws // 330;vector unsigned int fromDiffMemVarDConvftoui(float *arr, int elem) { // 331; return (vector unsigned int) { arr[elem], arr[elem-1], // 332; arr[elem-2], arr[elem-3] }; // 333;} // 334;// P8: xscvdpuxws, xxspltw // 335;// P9: xscvdpuxws, xxspltw // 336;vector unsigned int spltRegValConvftoui(float val) { // 337; return (vector unsigned int) val; // 338;} // 339;// P8: lxsspx, xscvdpuxws, xxspltw // 340;// P9: lxvwsx, xvcvspuxws // 341;vector unsigned int spltMemValConvftoui(float *ptr) { // 342; return (vector unsigned int)*ptr; // 343;} // 344;// P8: vspltisw // 345;// P9: vspltisw // 346;vector unsigned int spltCnstConvdtoui() { // 347; return (vector unsigned int) 4.74; // 348;} // 349;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 350;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 351;vector unsigned int fromRegsConvdtoui(double a, double b, // 352; double c, double d) { // 353; return (vector unsigned int) { a, b, c, d }; // 354;} // 355;// P8: lxvd2x, xxswapd // 356;// P9: lxvx (even lxv) // 357;vector unsigned int fromDiffConstsConvdtoui() { // 358; return (vector unsigned int) { 24.46, 234., 988.19, 422.39 }; // 359;} // 360;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew // 361;// P9: 2 x lxvx, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew // 362;vector unsigned int fromDiffMemConsAConvdtoui(double *ptr) { // 363; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 364;} // 365;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 366;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 367;vector unsigned int fromDiffMemConsDConvdtoui(double *ptr) { // 368; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 369;} // 370;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 371;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 372;vector unsigned int fromDiffMemVarAConvdtoui(double *arr, int elem) { // 373; return (vector unsigned int) { arr[elem], arr[elem+1], // 374; arr[elem+2], arr[elem+3] }; // 375;} // 376;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 377;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 378;vector unsigned int fromDiffMemVarDConvdtoui(double *arr, int elem) { // 379; return (vector unsigned int) { arr[elem], arr[elem-1], // 380; arr[elem-2], arr[elem-3] }; // 381;} // 382;// P8: xscvdpuxws, xxspltw // 383;// P9: xscvdpuxws, xxspltw // 384;vector unsigned int spltRegValConvdtoui(double val) { // 385; return (vector unsigned int) val; // 386;} // 387;// P8: lxsspx, xscvdpuxws, xxspltw // 388;// P9: lfd, xscvdpuxws, xxspltw // 389;vector unsigned int spltMemValConvdtoui(double *ptr) { // 390; return (vector unsigned int)*ptr; // 391;} // 392;/*=============================== unsigned int ==============================*/ 393;/*=============================== long long =================================*/ 394;// P8: xxlxor // 395;// P9: xxlxor // 396;vector long long allZeroll() { // 397; return (vector long long)0; // 398;} // 399;// P8: vspltisb -1 // 400;// P9: xxspltisb 255 // 401;vector long long allOnell() { // 402; return (vector long long)-1; // 403;} // 404;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 405;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 406;vector long long spltConst1ll() { // 407; return (vector long long)1; // 408;} // 409;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 410;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 411;vector long long spltConst16kll() { // 412; return (vector long long)((1<<15) - 1); // 413;} // 414;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 415;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 416;vector long long spltConst32kll() { // 417; return (vector long long)((1<<16) - 1); // 418;} // 419;// P8: 2 x mtvsrd, xxmrghd // 420;// P9: mtvsrdd // 421;vector long long fromRegsll(long long a, long long b) { // 422; return (vector long long){ a, b }; // 423;} // 424;// P8: lxvd2x, xxswapd // 425;// P9: lxvx (or even lxv) // 426;vector long long fromDiffConstsll() { // 427; return (vector long long) { 242, -113 }; // 428;} // 429;// P8: lxvd2x, xxswapd // 430;// P9: lxvx // 431;vector long long fromDiffMemConsAll(long long *arr) { // 432; return (vector long long) { arr[0], arr[1] }; // 433;} // 434;// P8: lxvd2x // 435;// P9: lxvx, xxswapd (maybe just use lxvd2x) // 436;vector long long fromDiffMemConsDll(long long *arr) { // 437; return (vector long long) { arr[3], arr[2] }; // 438;} // 439;// P8: sldi 3, lxvd2x, xxswapd // 440;// P9: sldi 3, lxvx // 441;vector long long fromDiffMemVarAll(long long *arr, int elem) { // 442; return (vector long long) { arr[elem], arr[elem+1] }; // 443;} // 444;// P8: sldi 3, lxvd2x // 445;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) // 446;vector long long fromDiffMemVarDll(long long *arr, int elem) { // 447; return (vector long long) { arr[elem], arr[elem-1] }; // 448;} // 449;// P8: 2 x ld, 2 x mtvsrd, xxmrghd // 450;// P9: 2 x ld, mtvsrdd // 451;vector long long fromRandMemConsll(long long *arr) { // 452; return (vector long long) { arr[4], arr[18] }; // 453;} // 454;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd // 455;// P9: sldi 3, add, 2 x ld, mtvsrdd // 456;vector long long fromRandMemVarll(long long *arr, int elem) { // 457; return (vector long long) { arr[elem+4], arr[elem+1] }; // 458;} // 459;// P8: mtvsrd, xxspltd // 460;// P9: mtvsrdd // 461;vector long long spltRegValll(long long val) { // 462; return (vector long long) val; // 463;} // 464;// P8: lxvdsx // 465;// P9: lxvdsx // 466;vector long long spltMemValll(long long *ptr) { // 467; return (vector long long)*ptr; // 468;} // 469;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 470;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 471;vector long long spltCnstConvftoll() { // 472; return (vector long long) 4.74f; // 473;} // 474;// P8: xxmrghd, xvcvdpsxds // 475;// P9: xxmrghd, xvcvdpsxds // 476;vector long long fromRegsConvftoll(float a, float b) { // 477; return (vector long long) { a, b }; // 478;} // 479;// P8: lxvd2x, xxswapd // 480;// P9: lxvx (even lxv) // 481;vector long long fromDiffConstsConvftoll() { // 482; return (vector long long) { 24.46f, 234.f }; // 483;} // 484;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds // 485;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds // 486;vector long long fromDiffMemConsAConvftoll(float *ptr) { // 487; return (vector long long) { ptr[0], ptr[1] }; // 488;} // 489;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds // 490;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds // 491;vector long long fromDiffMemConsDConvftoll(float *ptr) { // 492; return (vector long long) { ptr[3], ptr[2] }; // 493;} // 494;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds // 495;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds // 496;vector long long fromDiffMemVarAConvftoll(float *arr, int elem) { // 497; return (vector long long) { arr[elem], arr[elem+1] }; // 498;} // 499;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds // 500;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds // 501;vector long long fromDiffMemVarDConvftoll(float *arr, int elem) { // 502; return (vector long long) { arr[elem], arr[elem-1] }; // 503;} // 504;// P8: xscvdpsxds, xxspltd // 505;// P9: xscvdpsxds, xxspltd // 506;vector long long spltRegValConvftoll(float val) { // 507; return (vector long long) val; // 508;} // 509;// P8: lxsspx, xscvdpsxds, xxspltd // 510;// P9: lfs, xscvdpsxds, xxspltd // 511;vector long long spltMemValConvftoll(float *ptr) { // 512; return (vector long long)*ptr; // 513;} // 514;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 515;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 516;vector long long spltCnstConvdtoll() { // 517; return (vector long long) 4.74; // 518;} // 519;// P8: xxmrghd, xvcvdpsxds // 520;// P9: xxmrghd, xvcvdpsxds // 521;vector long long fromRegsConvdtoll(double a, double b) { // 522; return (vector long long) { a, b }; // 523;} // 524;// P8: lxvd2x, xxswapd // 525;// P9: lxvx (even lxv) // 526;vector long long fromDiffConstsConvdtoll() { // 527; return (vector long long) { 24.46, 234. }; // 528;} // 529;// P8: lxvd2x, xxswapd, xvcvdpsxds // 530;// P9: lxvx, xvcvdpsxds // 531;vector long long fromDiffMemConsAConvdtoll(double *ptr) { // 532; return (vector long long) { ptr[0], ptr[1] }; // 533;} // 534;// P8: lxvd2x, xvcvdpsxds // 535;// P9: lxvx, xxswapd, xvcvdpsxds // 536;vector long long fromDiffMemConsDConvdtoll(double *ptr) { // 537; return (vector long long) { ptr[3], ptr[2] }; // 538;} // 539;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpsxds // 540;// P9: sldi 3, lxvx, xvcvdpsxds // 541;vector long long fromDiffMemVarAConvdtoll(double *arr, int elem) { // 542; return (vector long long) { arr[elem], arr[elem+1] }; // 543;} // 544;// P8: sldi 3, lxvd2x, xvcvdpsxds // 545;// P9: sldi 3, lxvx, xxswapd, xvcvdpsxds // 546;vector long long fromDiffMemVarDConvdtoll(double *arr, int elem) { // 547; return (vector long long) { arr[elem], arr[elem-1] }; // 548;} // 549;// P8: xscvdpsxds, xxspltd // 550;// P9: xscvdpsxds, xxspltd // 551;vector long long spltRegValConvdtoll(double val) { // 552; return (vector long long) val; // 553;} // 554;// P8: lxvdsx, xvcvdpsxds // 555;// P9: lxvdsx, xvcvdpsxds // 556;vector long long spltMemValConvdtoll(double *ptr) { // 557; return (vector long long)*ptr; // 558;} // 559;/*=============================== long long =================================*/ 560;/*========================== unsigned long long =============================*/ 561;// P8: xxlxor // 562;// P9: xxlxor // 563;vector unsigned long long allZeroull() { // 564; return (vector unsigned long long)0; // 565;} // 566;// P8: vspltisb -1 // 567;// P9: xxspltisb 255 // 568;vector unsigned long long allOneull() { // 569; return (vector unsigned long long)-1; // 570;} // 571;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 572;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 573;vector unsigned long long spltConst1ull() { // 574; return (vector unsigned long long)1; // 575;} // 576;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 577;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 578;vector unsigned long long spltConst16kull() { // 579; return (vector unsigned long long)((1<<15) - 1); // 580;} // 581;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 582;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 583;vector unsigned long long spltConst32kull() { // 584; return (vector unsigned long long)((1<<16) - 1); // 585;} // 586;// P8: 2 x mtvsrd, xxmrghd // 587;// P9: mtvsrdd // 588;vector unsigned long long fromRegsull(unsigned long long a, // 589; unsigned long long b) { // 590; return (vector unsigned long long){ a, b }; // 591;} // 592;// P8: lxvd2x, xxswapd // 593;// P9: lxvx (or even lxv) // 594;vector unsigned long long fromDiffConstsull() { // 595; return (vector unsigned long long) { 242, -113 }; // 596;} // 597;// P8: lxvd2x, xxswapd // 598;// P9: lxvx // 599;vector unsigned long long fromDiffMemConsAull(unsigned long long *arr) { // 600; return (vector unsigned long long) { arr[0], arr[1] }; // 601;} // 602;// P8: lxvd2x // 603;// P9: lxvx, xxswapd (maybe just use lxvd2x) // 604;vector unsigned long long fromDiffMemConsDull(unsigned long long *arr) { // 605; return (vector unsigned long long) { arr[3], arr[2] }; // 606;} // 607;// P8: sldi 3, lxvd2x, xxswapd // 608;// P9: sldi 3, lxvx // 609;vector unsigned long long fromDiffMemVarAull(unsigned long long *arr, // 610; int elem) { // 611; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 612;} // 613;// P8: sldi 3, lxvd2x // 614;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) // 615;vector unsigned long long fromDiffMemVarDull(unsigned long long *arr, // 616; int elem) { // 617; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 618;} // 619;// P8: 2 x ld, 2 x mtvsrd, xxmrghd // 620;// P9: 2 x ld, mtvsrdd // 621;vector unsigned long long fromRandMemConsull(unsigned long long *arr) { // 622; return (vector unsigned long long) { arr[4], arr[18] }; // 623;} // 624;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd // 625;// P9: sldi 3, add, 2 x ld, mtvsrdd // 626;vector unsigned long long fromRandMemVarull(unsigned long long *arr, // 627; int elem) { // 628; return (vector unsigned long long) { arr[elem+4], arr[elem+1] }; // 629;} // 630;// P8: mtvsrd, xxspltd // 631;// P9: mtvsrdd // 632;vector unsigned long long spltRegValull(unsigned long long val) { // 633; return (vector unsigned long long) val; // 634;} // 635;// P8: lxvdsx // 636;// P9: lxvdsx // 637;vector unsigned long long spltMemValull(unsigned long long *ptr) { // 638; return (vector unsigned long long)*ptr; // 639;} // 640;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 641;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 642;vector unsigned long long spltCnstConvftoull() { // 643; return (vector unsigned long long) 4.74f; // 644;} // 645;// P8: xxmrghd, xvcvdpuxds // 646;// P9: xxmrghd, xvcvdpuxds // 647;vector unsigned long long fromRegsConvftoull(float a, float b) { // 648; return (vector unsigned long long) { a, b }; // 649;} // 650;// P8: lxvd2x, xxswapd // 651;// P9: lxvx (even lxv) // 652;vector unsigned long long fromDiffConstsConvftoull() { // 653; return (vector unsigned long long) { 24.46f, 234.f }; // 654;} // 655;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds // 656;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds // 657;vector unsigned long long fromDiffMemConsAConvftoull(float *ptr) { // 658; return (vector unsigned long long) { ptr[0], ptr[1] }; // 659;} // 660;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds // 661;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds // 662;vector unsigned long long fromDiffMemConsDConvftoull(float *ptr) { // 663; return (vector unsigned long long) { ptr[3], ptr[2] }; // 664;} // 665;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds // 666;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds // 667;vector unsigned long long fromDiffMemVarAConvftoull(float *arr, int elem) { // 668; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 669;} // 670;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds // 671;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds // 672;vector unsigned long long fromDiffMemVarDConvftoull(float *arr, int elem) { // 673; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 674;} // 675;// P8: xscvdpuxds, xxspltd // 676;// P9: xscvdpuxds, xxspltd // 677;vector unsigned long long spltRegValConvftoull(float val) { // 678; return (vector unsigned long long) val; // 679;} // 680;// P8: lxsspx, xscvdpuxds, xxspltd // 681;// P9: lfs, xscvdpuxds, xxspltd // 682;vector unsigned long long spltMemValConvftoull(float *ptr) { // 683; return (vector unsigned long long)*ptr; // 684;} // 685;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 686;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 687;vector unsigned long long spltCnstConvdtoull() { // 688; return (vector unsigned long long) 4.74; // 689;} // 690;// P8: xxmrghd, xvcvdpuxds // 691;// P9: xxmrghd, xvcvdpuxds // 692;vector unsigned long long fromRegsConvdtoull(double a, double b) { // 693; return (vector unsigned long long) { a, b }; // 694;} // 695;// P8: lxvd2x, xxswapd // 696;// P9: lxvx (even lxv) // 697;vector unsigned long long fromDiffConstsConvdtoull() { // 698; return (vector unsigned long long) { 24.46, 234. }; // 699;} // 700;// P8: lxvd2x, xxswapd, xvcvdpuxds // 701;// P9: lxvx, xvcvdpuxds // 702;vector unsigned long long fromDiffMemConsAConvdtoull(double *ptr) { // 703; return (vector unsigned long long) { ptr[0], ptr[1] }; // 704;} // 705;// P8: lxvd2x, xvcvdpuxds // 706;// P9: lxvx, xxswapd, xvcvdpuxds // 707;vector unsigned long long fromDiffMemConsDConvdtoull(double *ptr) { // 708; return (vector unsigned long long) { ptr[3], ptr[2] }; // 709;} // 710;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpuxds // 711;// P9: sldi 3, lxvx, xvcvdpuxds // 712;vector unsigned long long fromDiffMemVarAConvdtoull(double *arr, int elem) { // 713; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 714;} // 715;// P8: sldi 3, lxvd2x, xvcvdpuxds // 716;// P9: sldi 3, lxvx, xxswapd, xvcvdpuxds // 717;vector unsigned long long fromDiffMemVarDConvdtoull(double *arr, int elem) { // 718; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 719;} // 720;// P8: xscvdpuxds, xxspltd // 721;// P9: xscvdpuxds, xxspltd // 722;vector unsigned long long spltRegValConvdtoull(double val) { // 723; return (vector unsigned long long) val; // 724;} // 725;// P8: lxvdsx, xvcvdpuxds // 726;// P9: lxvdsx, xvcvdpuxds // 727;vector unsigned long long spltMemValConvdtoull(double *ptr) { // 728; return (vector unsigned long long)*ptr; // 729;} // 730;/*========================== unsigned long long ==============================*/ 731 732; Function Attrs: norecurse nounwind readnone 733define <4 x i32> @allZeroi() { 734; P9BE-LABEL: allZeroi: 735; P9BE: # %bb.0: # %entry 736; P9BE-NEXT: xxlxor v2, v2, v2 737; P9BE-NEXT: blr 738; 739; P9LE-LABEL: allZeroi: 740; P9LE: # %bb.0: # %entry 741; P9LE-NEXT: xxlxor v2, v2, v2 742; P9LE-NEXT: blr 743; 744; P8BE-LABEL: allZeroi: 745; P8BE: # %bb.0: # %entry 746; P8BE-NEXT: xxlxor v2, v2, v2 747; P8BE-NEXT: blr 748; 749; P8LE-LABEL: allZeroi: 750; P8LE: # %bb.0: # %entry 751; P8LE-NEXT: xxlxor v2, v2, v2 752; P8LE-NEXT: blr 753entry: 754 ret <4 x i32> zeroinitializer 755} 756 757; Function Attrs: norecurse nounwind readnone 758define <4 x i32> @allOnei() { 759; P9BE-LABEL: allOnei: 760; P9BE: # %bb.0: # %entry 761; P9BE-NEXT: xxspltib v2, 255 762; P9BE-NEXT: blr 763; 764; P9LE-LABEL: allOnei: 765; P9LE: # %bb.0: # %entry 766; P9LE-NEXT: xxspltib v2, 255 767; P9LE-NEXT: blr 768; 769; P8BE-LABEL: allOnei: 770; P8BE: # %bb.0: # %entry 771; P8BE-NEXT: vspltisb v2, -1 772; P8BE-NEXT: blr 773; 774; P8LE-LABEL: allOnei: 775; P8LE: # %bb.0: # %entry 776; P8LE-NEXT: vspltisb v2, -1 777; P8LE-NEXT: blr 778entry: 779 ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> 780} 781 782; Function Attrs: norecurse nounwind readnone 783define <4 x i32> @spltConst1i() { 784; P9BE-LABEL: spltConst1i: 785; P9BE: # %bb.0: # %entry 786; P9BE-NEXT: vspltisw v2, 1 787; P9BE-NEXT: blr 788; 789; P9LE-LABEL: spltConst1i: 790; P9LE: # %bb.0: # %entry 791; P9LE-NEXT: vspltisw v2, 1 792; P9LE-NEXT: blr 793; 794; P8BE-LABEL: spltConst1i: 795; P8BE: # %bb.0: # %entry 796; P8BE-NEXT: vspltisw v2, 1 797; P8BE-NEXT: blr 798; 799; P8LE-LABEL: spltConst1i: 800; P8LE: # %bb.0: # %entry 801; P8LE-NEXT: vspltisw v2, 1 802; P8LE-NEXT: blr 803entry: 804 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1> 805} 806 807; Function Attrs: norecurse nounwind readnone 808define <4 x i32> @spltConst16ki() { 809; P9BE-LABEL: spltConst16ki: 810; P9BE: # %bb.0: # %entry 811; P9BE-NEXT: vspltisw v2, -15 812; P9BE-NEXT: vsrw v2, v2, v2 813; P9BE-NEXT: blr 814; 815; P9LE-LABEL: spltConst16ki: 816; P9LE: # %bb.0: # %entry 817; P9LE-NEXT: vspltisw v2, -15 818; P9LE-NEXT: vsrw v2, v2, v2 819; P9LE-NEXT: blr 820; 821; P8BE-LABEL: spltConst16ki: 822; P8BE: # %bb.0: # %entry 823; P8BE-NEXT: vspltisw v2, -15 824; P8BE-NEXT: vsrw v2, v2, v2 825; P8BE-NEXT: blr 826; 827; P8LE-LABEL: spltConst16ki: 828; P8LE: # %bb.0: # %entry 829; P8LE-NEXT: vspltisw v2, -15 830; P8LE-NEXT: vsrw v2, v2, v2 831; P8LE-NEXT: blr 832entry: 833 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 834} 835 836; Function Attrs: norecurse nounwind readnone 837define <4 x i32> @spltConst32ki() { 838; P9BE-LABEL: spltConst32ki: 839; P9BE: # %bb.0: # %entry 840; P9BE-NEXT: vspltisw v2, -16 841; P9BE-NEXT: vsrw v2, v2, v2 842; P9BE-NEXT: blr 843; 844; P9LE-LABEL: spltConst32ki: 845; P9LE: # %bb.0: # %entry 846; P9LE-NEXT: vspltisw v2, -16 847; P9LE-NEXT: vsrw v2, v2, v2 848; P9LE-NEXT: blr 849; 850; P8BE-LABEL: spltConst32ki: 851; P8BE: # %bb.0: # %entry 852; P8BE-NEXT: vspltisw v2, -16 853; P8BE-NEXT: vsrw v2, v2, v2 854; P8BE-NEXT: blr 855; 856; P8LE-LABEL: spltConst32ki: 857; P8LE: # %bb.0: # %entry 858; P8LE-NEXT: vspltisw v2, -16 859; P8LE-NEXT: vsrw v2, v2, v2 860; P8LE-NEXT: blr 861entry: 862 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 863} 864 865; Function Attrs: norecurse nounwind readnone 866define <4 x i32> @fromRegsi(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) { 867; P9BE-LABEL: fromRegsi: 868; P9BE: # %bb.0: # %entry 869; P9BE-NEXT: rldimi r6, r5, 32, 0 870; P9BE-NEXT: rldimi r4, r3, 32, 0 871; P9BE-NEXT: mtvsrdd v2, r4, r6 872; P9BE-NEXT: blr 873; 874; P9LE-LABEL: fromRegsi: 875; P9LE: # %bb.0: # %entry 876; P9LE-NEXT: rldimi r3, r4, 32, 0 877; P9LE-NEXT: rldimi r5, r6, 32, 0 878; P9LE-NEXT: mtvsrdd v2, r5, r3 879; P9LE-NEXT: blr 880; 881; P8BE-LABEL: fromRegsi: 882; P8BE: # %bb.0: # %entry 883; P8BE-NEXT: rldimi r6, r5, 32, 0 884; P8BE-NEXT: rldimi r4, r3, 32, 0 885; P8BE-NEXT: mtvsrd f0, r6 886; P8BE-NEXT: mtvsrd f1, r4 887; P8BE-NEXT: xxmrghd v2, vs1, vs0 888; P8BE-NEXT: blr 889; 890; P8LE-LABEL: fromRegsi: 891; P8LE: # %bb.0: # %entry 892; P8LE-NEXT: rldimi r3, r4, 32, 0 893; P8LE-NEXT: rldimi r5, r6, 32, 0 894; P8LE-NEXT: mtvsrd f0, r3 895; P8LE-NEXT: mtvsrd f1, r5 896; P8LE-NEXT: xxmrghd v2, vs1, vs0 897; P8LE-NEXT: blr 898entry: 899 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 900 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 901 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 902 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3 903 ret <4 x i32> %vecinit3 904} 905 906; Function Attrs: norecurse nounwind readnone 907define <4 x i32> @fromDiffConstsi() { 908; P9BE-LABEL: fromDiffConstsi: 909; P9BE: # %bb.0: # %entry 910; P9BE-NEXT: addis r3, r2, .LCPI6_0@toc@ha 911; P9BE-NEXT: addi r3, r3, .LCPI6_0@toc@l 912; P9BE-NEXT: lxvx v2, 0, r3 913; P9BE-NEXT: blr 914; 915; P9LE-LABEL: fromDiffConstsi: 916; P9LE: # %bb.0: # %entry 917; P9LE-NEXT: addis r3, r2, .LCPI6_0@toc@ha 918; P9LE-NEXT: addi r3, r3, .LCPI6_0@toc@l 919; P9LE-NEXT: lxvx v2, 0, r3 920; P9LE-NEXT: blr 921; 922; P8BE-LABEL: fromDiffConstsi: 923; P8BE: # %bb.0: # %entry 924; P8BE-NEXT: addis r3, r2, .LCPI6_0@toc@ha 925; P8BE-NEXT: addi r3, r3, .LCPI6_0@toc@l 926; P8BE-NEXT: lxvw4x v2, 0, r3 927; P8BE-NEXT: blr 928; 929; P8LE-LABEL: fromDiffConstsi: 930; P8LE: # %bb.0: # %entry 931; P8LE-NEXT: addis r3, r2, .LCPI6_0@toc@ha 932; P8LE-NEXT: addi r3, r3, .LCPI6_0@toc@l 933; P8LE-NEXT: lvx v2, 0, r3 934; P8LE-NEXT: blr 935entry: 936 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19> 937} 938 939; Function Attrs: norecurse nounwind readonly 940define <4 x i32> @fromDiffMemConsAi(i32* nocapture readonly %arr) { 941; P9BE-LABEL: fromDiffMemConsAi: 942; P9BE: # %bb.0: # %entry 943; P9BE-NEXT: lxv v2, 0(r3) 944; P9BE-NEXT: blr 945; 946; P9LE-LABEL: fromDiffMemConsAi: 947; P9LE: # %bb.0: # %entry 948; P9LE-NEXT: lxv v2, 0(r3) 949; P9LE-NEXT: blr 950; 951; P8BE-LABEL: fromDiffMemConsAi: 952; P8BE: # %bb.0: # %entry 953; P8BE-NEXT: lxvw4x v2, 0, r3 954; P8BE-NEXT: blr 955; 956; P8LE-LABEL: fromDiffMemConsAi: 957; P8LE: # %bb.0: # %entry 958; P8LE-NEXT: lxvd2x vs0, 0, r3 959; P8LE-NEXT: xxswapd v2, vs0 960; P8LE-NEXT: blr 961entry: 962 %0 = load i32, i32* %arr, align 4 963 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 964 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 1 965 %1 = load i32, i32* %arrayidx1, align 4 966 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 967 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 968 %2 = load i32, i32* %arrayidx3, align 4 969 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 970 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 3 971 %3 = load i32, i32* %arrayidx5, align 4 972 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 973 ret <4 x i32> %vecinit6 974} 975 976; Function Attrs: norecurse nounwind readonly 977define <4 x i32> @fromDiffMemConsDi(i32* nocapture readonly %arr) { 978; P9BE-LABEL: fromDiffMemConsDi: 979; P9BE: # %bb.0: # %entry 980; P9BE-NEXT: lxv v2, 0(r3) 981; P9BE-NEXT: addis r3, r2, .LCPI8_0@toc@ha 982; P9BE-NEXT: addi r3, r3, .LCPI8_0@toc@l 983; P9BE-NEXT: lxvx v3, 0, r3 984; P9BE-NEXT: vperm v2, v2, v2, v3 985; P9BE-NEXT: blr 986; 987; P9LE-LABEL: fromDiffMemConsDi: 988; P9LE: # %bb.0: # %entry 989; P9LE-NEXT: lxvw4x v2, 0, r3 990; P9LE-NEXT: blr 991; 992; P8BE-LABEL: fromDiffMemConsDi: 993; P8BE: # %bb.0: # %entry 994; P8BE-NEXT: addis r4, r2, .LCPI8_0@toc@ha 995; P8BE-NEXT: lxvw4x v2, 0, r3 996; P8BE-NEXT: addi r4, r4, .LCPI8_0@toc@l 997; P8BE-NEXT: lxvw4x v3, 0, r4 998; P8BE-NEXT: vperm v2, v2, v2, v3 999; P8BE-NEXT: blr 1000; 1001; P8LE-LABEL: fromDiffMemConsDi: 1002; P8LE: # %bb.0: # %entry 1003; P8LE-NEXT: lxvd2x vs0, 0, r3 1004; P8LE-NEXT: addis r4, r2, .LCPI8_0@toc@ha 1005; P8LE-NEXT: addi r3, r4, .LCPI8_0@toc@l 1006; P8LE-NEXT: lvx v2, 0, r3 1007; P8LE-NEXT: xxswapd v3, vs0 1008; P8LE-NEXT: vperm v2, v3, v3, v2 1009; P8LE-NEXT: blr 1010entry: 1011 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3 1012 %0 = load i32, i32* %arrayidx, align 4 1013 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1014 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 1015 %1 = load i32, i32* %arrayidx1, align 4 1016 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1017 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 1 1018 %2 = load i32, i32* %arrayidx3, align 4 1019 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 1020 %3 = load i32, i32* %arr, align 4 1021 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 1022 ret <4 x i32> %vecinit6 1023} 1024 1025; Function Attrs: norecurse nounwind readonly 1026define <4 x i32> @fromDiffMemVarAi(i32* nocapture readonly %arr, i32 signext %elem) { 1027; P9BE-LABEL: fromDiffMemVarAi: 1028; P9BE: # %bb.0: # %entry 1029; P9BE-NEXT: sldi r4, r4, 2 1030; P9BE-NEXT: lxvx v2, r3, r4 1031; P9BE-NEXT: blr 1032; 1033; P9LE-LABEL: fromDiffMemVarAi: 1034; P9LE: # %bb.0: # %entry 1035; P9LE-NEXT: sldi r4, r4, 2 1036; P9LE-NEXT: lxvx v2, r3, r4 1037; P9LE-NEXT: blr 1038; 1039; P8BE-LABEL: fromDiffMemVarAi: 1040; P8BE: # %bb.0: # %entry 1041; P8BE-NEXT: sldi r4, r4, 2 1042; P8BE-NEXT: lxvw4x v2, r3, r4 1043; P8BE-NEXT: blr 1044; 1045; P8LE-LABEL: fromDiffMemVarAi: 1046; P8LE: # %bb.0: # %entry 1047; P8LE-NEXT: sldi r4, r4, 2 1048; P8LE-NEXT: lxvd2x vs0, r3, r4 1049; P8LE-NEXT: xxswapd v2, vs0 1050; P8LE-NEXT: blr 1051entry: 1052 %idxprom = sext i32 %elem to i64 1053 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 1054 %0 = load i32, i32* %arrayidx, align 4 1055 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1056 %add = add nsw i32 %elem, 1 1057 %idxprom1 = sext i32 %add to i64 1058 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 1059 %1 = load i32, i32* %arrayidx2, align 4 1060 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1061 %add4 = add nsw i32 %elem, 2 1062 %idxprom5 = sext i32 %add4 to i64 1063 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 1064 %2 = load i32, i32* %arrayidx6, align 4 1065 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 1066 %add8 = add nsw i32 %elem, 3 1067 %idxprom9 = sext i32 %add8 to i64 1068 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 1069 %3 = load i32, i32* %arrayidx10, align 4 1070 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 1071 ret <4 x i32> %vecinit11 1072} 1073 1074; Function Attrs: norecurse nounwind readonly 1075define <4 x i32> @fromDiffMemVarDi(i32* nocapture readonly %arr, i32 signext %elem) { 1076; P9BE-LABEL: fromDiffMemVarDi: 1077; P9BE: # %bb.0: # %entry 1078; P9BE-NEXT: sldi r4, r4, 2 1079; P9BE-NEXT: add r3, r3, r4 1080; P9BE-NEXT: addi r3, r3, -12 1081; P9BE-NEXT: lxvx v2, 0, r3 1082; P9BE-NEXT: addis r3, r2, .LCPI10_0@toc@ha 1083; P9BE-NEXT: addi r3, r3, .LCPI10_0@toc@l 1084; P9BE-NEXT: lxvx v3, 0, r3 1085; P9BE-NEXT: vperm v2, v2, v2, v3 1086; P9BE-NEXT: blr 1087; 1088; P9LE-LABEL: fromDiffMemVarDi: 1089; P9LE: # %bb.0: # %entry 1090; P9LE-NEXT: sldi r4, r4, 2 1091; P9LE-NEXT: add r3, r3, r4 1092; P9LE-NEXT: addi r3, r3, -12 1093; P9LE-NEXT: lxvx v2, 0, r3 1094; P9LE-NEXT: addis r3, r2, .LCPI10_0@toc@ha 1095; P9LE-NEXT: addi r3, r3, .LCPI10_0@toc@l 1096; P9LE-NEXT: lxvx v3, 0, r3 1097; P9LE-NEXT: vperm v2, v2, v2, v3 1098; P9LE-NEXT: blr 1099; 1100; P8BE-LABEL: fromDiffMemVarDi: 1101; P8BE: # %bb.0: # %entry 1102; P8BE-NEXT: sldi r4, r4, 2 1103; P8BE-NEXT: addis r5, r2, .LCPI10_0@toc@ha 1104; P8BE-NEXT: add r3, r3, r4 1105; P8BE-NEXT: addi r4, r5, .LCPI10_0@toc@l 1106; P8BE-NEXT: addi r3, r3, -12 1107; P8BE-NEXT: lxvw4x v3, 0, r4 1108; P8BE-NEXT: lxvw4x v2, 0, r3 1109; P8BE-NEXT: vperm v2, v2, v2, v3 1110; P8BE-NEXT: blr 1111; 1112; P8LE-LABEL: fromDiffMemVarDi: 1113; P8LE: # %bb.0: # %entry 1114; P8LE-NEXT: sldi r4, r4, 2 1115; P8LE-NEXT: addis r5, r2, .LCPI10_0@toc@ha 1116; P8LE-NEXT: add r3, r3, r4 1117; P8LE-NEXT: addi r3, r3, -12 1118; P8LE-NEXT: lxvd2x vs0, 0, r3 1119; P8LE-NEXT: addi r3, r5, .LCPI10_0@toc@l 1120; P8LE-NEXT: lvx v3, 0, r3 1121; P8LE-NEXT: xxswapd v2, vs0 1122; P8LE-NEXT: vperm v2, v2, v2, v3 1123; P8LE-NEXT: blr 1124entry: 1125 %idxprom = sext i32 %elem to i64 1126 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 1127 %0 = load i32, i32* %arrayidx, align 4 1128 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1129 %sub = add nsw i32 %elem, -1 1130 %idxprom1 = sext i32 %sub to i64 1131 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 1132 %1 = load i32, i32* %arrayidx2, align 4 1133 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1134 %sub4 = add nsw i32 %elem, -2 1135 %idxprom5 = sext i32 %sub4 to i64 1136 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 1137 %2 = load i32, i32* %arrayidx6, align 4 1138 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 1139 %sub8 = add nsw i32 %elem, -3 1140 %idxprom9 = sext i32 %sub8 to i64 1141 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 1142 %3 = load i32, i32* %arrayidx10, align 4 1143 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 1144 ret <4 x i32> %vecinit11 1145} 1146 1147; Function Attrs: norecurse nounwind readonly 1148define <4 x i32> @fromRandMemConsi(i32* nocapture readonly %arr) { 1149; P9BE-LABEL: fromRandMemConsi: 1150; P9BE: # %bb.0: # %entry 1151; P9BE-NEXT: lwz r4, 16(r3) 1152; P9BE-NEXT: lwz r5, 72(r3) 1153; P9BE-NEXT: lwz r6, 8(r3) 1154; P9BE-NEXT: lwz r3, 352(r3) 1155; P9BE-NEXT: rldimi r3, r6, 32, 0 1156; P9BE-NEXT: rldimi r5, r4, 32, 0 1157; P9BE-NEXT: mtvsrdd v2, r5, r3 1158; P9BE-NEXT: blr 1159; 1160; P9LE-LABEL: fromRandMemConsi: 1161; P9LE: # %bb.0: # %entry 1162; P9LE-NEXT: lwz r4, 16(r3) 1163; P9LE-NEXT: lwz r5, 72(r3) 1164; P9LE-NEXT: lwz r6, 8(r3) 1165; P9LE-NEXT: lwz r3, 352(r3) 1166; P9LE-NEXT: rldimi r4, r5, 32, 0 1167; P9LE-NEXT: rldimi r6, r3, 32, 0 1168; P9LE-NEXT: mtvsrdd v2, r6, r4 1169; P9LE-NEXT: blr 1170; 1171; P8BE-LABEL: fromRandMemConsi: 1172; P8BE: # %bb.0: # %entry 1173; P8BE-NEXT: lwz r4, 8(r3) 1174; P8BE-NEXT: lwz r5, 352(r3) 1175; P8BE-NEXT: lwz r6, 16(r3) 1176; P8BE-NEXT: lwz r3, 72(r3) 1177; P8BE-NEXT: rldimi r5, r4, 32, 0 1178; P8BE-NEXT: rldimi r3, r6, 32, 0 1179; P8BE-NEXT: mtvsrd f0, r5 1180; P8BE-NEXT: mtvsrd f1, r3 1181; P8BE-NEXT: xxmrghd v2, vs1, vs0 1182; P8BE-NEXT: blr 1183; 1184; P8LE-LABEL: fromRandMemConsi: 1185; P8LE: # %bb.0: # %entry 1186; P8LE-NEXT: lwz r4, 16(r3) 1187; P8LE-NEXT: lwz r5, 72(r3) 1188; P8LE-NEXT: lwz r6, 8(r3) 1189; P8LE-NEXT: lwz r3, 352(r3) 1190; P8LE-NEXT: rldimi r4, r5, 32, 0 1191; P8LE-NEXT: rldimi r6, r3, 32, 0 1192; P8LE-NEXT: mtvsrd f0, r4 1193; P8LE-NEXT: mtvsrd f1, r6 1194; P8LE-NEXT: xxmrghd v2, vs1, vs0 1195; P8LE-NEXT: blr 1196entry: 1197 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4 1198 %0 = load i32, i32* %arrayidx, align 4 1199 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1200 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18 1201 %1 = load i32, i32* %arrayidx1, align 4 1202 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1203 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 1204 %2 = load i32, i32* %arrayidx3, align 4 1205 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 1206 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 88 1207 %3 = load i32, i32* %arrayidx5, align 4 1208 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 1209 ret <4 x i32> %vecinit6 1210} 1211 1212; Function Attrs: norecurse nounwind readonly 1213define <4 x i32> @fromRandMemVari(i32* nocapture readonly %arr, i32 signext %elem) { 1214; P9BE-LABEL: fromRandMemVari: 1215; P9BE: # %bb.0: # %entry 1216; P9BE-NEXT: sldi r4, r4, 2 1217; P9BE-NEXT: add r3, r3, r4 1218; P9BE-NEXT: lwz r4, 16(r3) 1219; P9BE-NEXT: lwz r5, 4(r3) 1220; P9BE-NEXT: lwz r6, 8(r3) 1221; P9BE-NEXT: lwz r3, 32(r3) 1222; P9BE-NEXT: rldimi r3, r6, 32, 0 1223; P9BE-NEXT: rldimi r5, r4, 32, 0 1224; P9BE-NEXT: mtvsrdd v2, r5, r3 1225; P9BE-NEXT: blr 1226; 1227; P9LE-LABEL: fromRandMemVari: 1228; P9LE: # %bb.0: # %entry 1229; P9LE-NEXT: sldi r4, r4, 2 1230; P9LE-NEXT: add r3, r3, r4 1231; P9LE-NEXT: lwz r4, 16(r3) 1232; P9LE-NEXT: lwz r5, 4(r3) 1233; P9LE-NEXT: lwz r6, 8(r3) 1234; P9LE-NEXT: lwz r3, 32(r3) 1235; P9LE-NEXT: rldimi r4, r5, 32, 0 1236; P9LE-NEXT: rldimi r6, r3, 32, 0 1237; P9LE-NEXT: mtvsrdd v2, r6, r4 1238; P9LE-NEXT: blr 1239; 1240; P8BE-LABEL: fromRandMemVari: 1241; P8BE: # %bb.0: # %entry 1242; P8BE-NEXT: sldi r4, r4, 2 1243; P8BE-NEXT: add r3, r3, r4 1244; P8BE-NEXT: lwz r4, 8(r3) 1245; P8BE-NEXT: lwz r5, 32(r3) 1246; P8BE-NEXT: lwz r6, 16(r3) 1247; P8BE-NEXT: lwz r3, 4(r3) 1248; P8BE-NEXT: rldimi r5, r4, 32, 0 1249; P8BE-NEXT: rldimi r3, r6, 32, 0 1250; P8BE-NEXT: mtvsrd f0, r5 1251; P8BE-NEXT: mtvsrd f1, r3 1252; P8BE-NEXT: xxmrghd v2, vs1, vs0 1253; P8BE-NEXT: blr 1254; 1255; P8LE-LABEL: fromRandMemVari: 1256; P8LE: # %bb.0: # %entry 1257; P8LE-NEXT: sldi r4, r4, 2 1258; P8LE-NEXT: add r3, r3, r4 1259; P8LE-NEXT: lwz r4, 16(r3) 1260; P8LE-NEXT: lwz r5, 4(r3) 1261; P8LE-NEXT: lwz r6, 8(r3) 1262; P8LE-NEXT: lwz r3, 32(r3) 1263; P8LE-NEXT: rldimi r4, r5, 32, 0 1264; P8LE-NEXT: rldimi r6, r3, 32, 0 1265; P8LE-NEXT: mtvsrd f0, r4 1266; P8LE-NEXT: mtvsrd f1, r6 1267; P8LE-NEXT: xxmrghd v2, vs1, vs0 1268; P8LE-NEXT: blr 1269entry: 1270 %add = add nsw i32 %elem, 4 1271 %idxprom = sext i32 %add to i64 1272 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 1273 %0 = load i32, i32* %arrayidx, align 4 1274 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1275 %add1 = add nsw i32 %elem, 1 1276 %idxprom2 = sext i32 %add1 to i64 1277 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 %idxprom2 1278 %1 = load i32, i32* %arrayidx3, align 4 1279 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1280 %add5 = add nsw i32 %elem, 2 1281 %idxprom6 = sext i32 %add5 to i64 1282 %arrayidx7 = getelementptr inbounds i32, i32* %arr, i64 %idxprom6 1283 %2 = load i32, i32* %arrayidx7, align 4 1284 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2 1285 %add9 = add nsw i32 %elem, 8 1286 %idxprom10 = sext i32 %add9 to i64 1287 %arrayidx11 = getelementptr inbounds i32, i32* %arr, i64 %idxprom10 1288 %3 = load i32, i32* %arrayidx11, align 4 1289 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3 1290 ret <4 x i32> %vecinit12 1291} 1292 1293; Function Attrs: norecurse nounwind readnone 1294define <4 x i32> @spltRegVali(i32 signext %val) { 1295; P9BE-LABEL: spltRegVali: 1296; P9BE: # %bb.0: # %entry 1297; P9BE-NEXT: mtvsrws v2, r3 1298; P9BE-NEXT: blr 1299; 1300; P9LE-LABEL: spltRegVali: 1301; P9LE: # %bb.0: # %entry 1302; P9LE-NEXT: mtvsrws v2, r3 1303; P9LE-NEXT: blr 1304; 1305; P8BE-LABEL: spltRegVali: 1306; P8BE: # %bb.0: # %entry 1307; P8BE-NEXT: mtvsrwz f0, r3 1308; P8BE-NEXT: xxspltw v2, vs0, 1 1309; P8BE-NEXT: blr 1310; 1311; P8LE-LABEL: spltRegVali: 1312; P8LE: # %bb.0: # %entry 1313; P8LE-NEXT: mtvsrwz f0, r3 1314; P8LE-NEXT: xxspltw v2, vs0, 1 1315; P8LE-NEXT: blr 1316entry: 1317 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0 1318 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1319 ret <4 x i32> %splat.splat 1320} 1321 1322; Function Attrs: norecurse nounwind readonly 1323define <4 x i32> @spltMemVali(i32* nocapture readonly %ptr) { 1324; P9BE-LABEL: spltMemVali: 1325; P9BE: # %bb.0: # %entry 1326; P9BE-NEXT: lfiwzx f0, 0, r3 1327; P9BE-NEXT: xxsldwi vs0, f0, f0, 1 1328; P9BE-NEXT: xxspltw v2, vs0, 0 1329; P9BE-NEXT: blr 1330; 1331; P9LE-LABEL: spltMemVali: 1332; P9LE: # %bb.0: # %entry 1333; P9LE-NEXT: lfiwzx f0, 0, r3 1334; P9LE-NEXT: xxpermdi vs0, f0, f0, 2 1335; P9LE-NEXT: xxspltw v2, vs0, 3 1336; P9LE-NEXT: blr 1337; 1338; P8BE-LABEL: spltMemVali: 1339; P8BE: # %bb.0: # %entry 1340; P8BE-NEXT: lfiwzx f0, 0, r3 1341; P8BE-NEXT: xxsldwi vs0, f0, f0, 1 1342; P8BE-NEXT: xxspltw v2, vs0, 0 1343; P8BE-NEXT: blr 1344; 1345; P8LE-LABEL: spltMemVali: 1346; P8LE: # %bb.0: # %entry 1347; P8LE-NEXT: lfiwzx f0, 0, r3 1348; P8LE-NEXT: xxpermdi vs0, f0, f0, 2 1349; P8LE-NEXT: xxspltw v2, vs0, 3 1350; P8LE-NEXT: blr 1351entry: 1352 %0 = load i32, i32* %ptr, align 4 1353 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 1354 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1355 ret <4 x i32> %splat.splat 1356} 1357 1358; Function Attrs: norecurse nounwind readnone 1359define <4 x i32> @spltCnstConvftoi() { 1360; P9BE-LABEL: spltCnstConvftoi: 1361; P9BE: # %bb.0: # %entry 1362; P9BE-NEXT: vspltisw v2, 4 1363; P9BE-NEXT: blr 1364; 1365; P9LE-LABEL: spltCnstConvftoi: 1366; P9LE: # %bb.0: # %entry 1367; P9LE-NEXT: vspltisw v2, 4 1368; P9LE-NEXT: blr 1369; 1370; P8BE-LABEL: spltCnstConvftoi: 1371; P8BE: # %bb.0: # %entry 1372; P8BE-NEXT: vspltisw v2, 4 1373; P8BE-NEXT: blr 1374; 1375; P8LE-LABEL: spltCnstConvftoi: 1376; P8LE: # %bb.0: # %entry 1377; P8LE-NEXT: vspltisw v2, 4 1378; P8LE-NEXT: blr 1379entry: 1380 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 1381} 1382 1383; Function Attrs: norecurse nounwind readnone 1384define <4 x i32> @fromRegsConvftoi(float %a, float %b, float %c, float %d) { 1385; P9BE-LABEL: fromRegsConvftoi: 1386; P9BE: # %bb.0: # %entry 1387; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1388; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1389; P9BE-NEXT: xxmrghd vs0, vs2, vs4 1390; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1391; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1392; P9BE-NEXT: xvcvdpsxws v2, vs0 1393; P9BE-NEXT: xxmrghd vs0, vs1, vs3 1394; P9BE-NEXT: xvcvdpsxws v3, vs0 1395; P9BE-NEXT: vmrgew v2, v3, v2 1396; P9BE-NEXT: blr 1397; 1398; P9LE-LABEL: fromRegsConvftoi: 1399; P9LE: # %bb.0: # %entry 1400; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1401; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1402; P9LE-NEXT: xxmrghd vs0, vs3, vs1 1403; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1404; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1405; P9LE-NEXT: xvcvdpsxws v2, vs0 1406; P9LE-NEXT: xxmrghd vs0, vs4, vs2 1407; P9LE-NEXT: xvcvdpsxws v3, vs0 1408; P9LE-NEXT: vmrgew v2, v3, v2 1409; P9LE-NEXT: blr 1410; 1411; P8BE-LABEL: fromRegsConvftoi: 1412; P8BE: # %bb.0: # %entry 1413; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1414; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1415; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1416; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1417; P8BE-NEXT: xxmrghd vs0, vs2, vs4 1418; P8BE-NEXT: xxmrghd vs1, vs1, vs3 1419; P8BE-NEXT: xvcvdpsxws v2, vs0 1420; P8BE-NEXT: xvcvdpsxws v3, vs1 1421; P8BE-NEXT: vmrgew v2, v3, v2 1422; P8BE-NEXT: blr 1423; 1424; P8LE-LABEL: fromRegsConvftoi: 1425; P8LE: # %bb.0: # %entry 1426; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1427; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1428; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1429; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1430; P8LE-NEXT: xxmrghd vs0, vs3, vs1 1431; P8LE-NEXT: xxmrghd vs1, vs4, vs2 1432; P8LE-NEXT: xvcvdpsxws v2, vs0 1433; P8LE-NEXT: xvcvdpsxws v3, vs1 1434; P8LE-NEXT: vmrgew v2, v3, v2 1435; P8LE-NEXT: blr 1436entry: 1437 %conv = fptosi float %a to i32 1438 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1439 %conv1 = fptosi float %b to i32 1440 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 1441 %conv3 = fptosi float %c to i32 1442 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 1443 %conv5 = fptosi float %d to i32 1444 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 1445 ret <4 x i32> %vecinit6 1446} 1447 1448; Function Attrs: norecurse nounwind readnone 1449define <4 x i32> @fromDiffConstsConvftoi() { 1450; P9BE-LABEL: fromDiffConstsConvftoi: 1451; P9BE: # %bb.0: # %entry 1452; P9BE-NEXT: addis r3, r2, .LCPI17_0@toc@ha 1453; P9BE-NEXT: addi r3, r3, .LCPI17_0@toc@l 1454; P9BE-NEXT: lxvx v2, 0, r3 1455; P9BE-NEXT: blr 1456; 1457; P9LE-LABEL: fromDiffConstsConvftoi: 1458; P9LE: # %bb.0: # %entry 1459; P9LE-NEXT: addis r3, r2, .LCPI17_0@toc@ha 1460; P9LE-NEXT: addi r3, r3, .LCPI17_0@toc@l 1461; P9LE-NEXT: lxvx v2, 0, r3 1462; P9LE-NEXT: blr 1463; 1464; P8BE-LABEL: fromDiffConstsConvftoi: 1465; P8BE: # %bb.0: # %entry 1466; P8BE-NEXT: addis r3, r2, .LCPI17_0@toc@ha 1467; P8BE-NEXT: addi r3, r3, .LCPI17_0@toc@l 1468; P8BE-NEXT: lxvw4x v2, 0, r3 1469; P8BE-NEXT: blr 1470; 1471; P8LE-LABEL: fromDiffConstsConvftoi: 1472; P8LE: # %bb.0: # %entry 1473; P8LE-NEXT: addis r3, r2, .LCPI17_0@toc@ha 1474; P8LE-NEXT: addi r3, r3, .LCPI17_0@toc@l 1475; P8LE-NEXT: lvx v2, 0, r3 1476; P8LE-NEXT: blr 1477entry: 1478 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 1479} 1480 1481; Function Attrs: norecurse nounwind readonly 1482define <4 x i32> @fromDiffMemConsAConvftoi(float* nocapture readonly %ptr) { 1483; P9BE-LABEL: fromDiffMemConsAConvftoi: 1484; P9BE: # %bb.0: # %entry 1485; P9BE-NEXT: lxv vs0, 0(r3) 1486; P9BE-NEXT: xvcvspsxws v2, vs0 1487; P9BE-NEXT: blr 1488; 1489; P9LE-LABEL: fromDiffMemConsAConvftoi: 1490; P9LE: # %bb.0: # %entry 1491; P9LE-NEXT: lxv vs0, 0(r3) 1492; P9LE-NEXT: xvcvspsxws v2, vs0 1493; P9LE-NEXT: blr 1494; 1495; P8BE-LABEL: fromDiffMemConsAConvftoi: 1496; P8BE: # %bb.0: # %entry 1497; P8BE-NEXT: lxvw4x vs0, 0, r3 1498; P8BE-NEXT: xvcvspsxws v2, vs0 1499; P8BE-NEXT: blr 1500; 1501; P8LE-LABEL: fromDiffMemConsAConvftoi: 1502; P8LE: # %bb.0: # %entry 1503; P8LE-NEXT: lxvd2x vs0, 0, r3 1504; P8LE-NEXT: xxswapd v2, vs0 1505; P8LE-NEXT: xvcvspsxws v2, v2 1506; P8LE-NEXT: blr 1507entry: 1508 %0 = bitcast float* %ptr to <4 x float>* 1509 %1 = load <4 x float>, <4 x float>* %0, align 4 1510 %2 = fptosi <4 x float> %1 to <4 x i32> 1511 ret <4 x i32> %2 1512} 1513 1514; Function Attrs: norecurse nounwind readonly 1515define <4 x i32> @fromDiffMemConsDConvftoi(float* nocapture readonly %ptr) { 1516; P9BE-LABEL: fromDiffMemConsDConvftoi: 1517; P9BE: # %bb.0: # %entry 1518; P9BE-NEXT: lxv v2, 0(r3) 1519; P9BE-NEXT: addis r3, r2, .LCPI19_0@toc@ha 1520; P9BE-NEXT: addi r3, r3, .LCPI19_0@toc@l 1521; P9BE-NEXT: lxvx v3, 0, r3 1522; P9BE-NEXT: vperm v2, v2, v2, v3 1523; P9BE-NEXT: xvcvspsxws v2, v2 1524; P9BE-NEXT: blr 1525; 1526; P9LE-LABEL: fromDiffMemConsDConvftoi: 1527; P9LE: # %bb.0: # %entry 1528; P9LE-NEXT: lxv v2, 0(r3) 1529; P9LE-NEXT: addis r3, r2, .LCPI19_0@toc@ha 1530; P9LE-NEXT: addi r3, r3, .LCPI19_0@toc@l 1531; P9LE-NEXT: lxvx v3, 0, r3 1532; P9LE-NEXT: vperm v2, v2, v2, v3 1533; P9LE-NEXT: xvcvspsxws v2, v2 1534; P9LE-NEXT: blr 1535; 1536; P8BE-LABEL: fromDiffMemConsDConvftoi: 1537; P8BE: # %bb.0: # %entry 1538; P8BE-NEXT: addis r4, r2, .LCPI19_0@toc@ha 1539; P8BE-NEXT: lxvw4x v2, 0, r3 1540; P8BE-NEXT: addi r4, r4, .LCPI19_0@toc@l 1541; P8BE-NEXT: lxvw4x v3, 0, r4 1542; P8BE-NEXT: vperm v2, v2, v2, v3 1543; P8BE-NEXT: xvcvspsxws v2, v2 1544; P8BE-NEXT: blr 1545; 1546; P8LE-LABEL: fromDiffMemConsDConvftoi: 1547; P8LE: # %bb.0: # %entry 1548; P8LE-NEXT: lxvd2x vs0, 0, r3 1549; P8LE-NEXT: addis r4, r2, .LCPI19_0@toc@ha 1550; P8LE-NEXT: addi r3, r4, .LCPI19_0@toc@l 1551; P8LE-NEXT: lvx v2, 0, r3 1552; P8LE-NEXT: xxswapd v3, vs0 1553; P8LE-NEXT: vperm v2, v3, v3, v2 1554; P8LE-NEXT: xvcvspsxws v2, v2 1555; P8LE-NEXT: blr 1556entry: 1557 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 1558 %0 = load float, float* %arrayidx, align 4 1559 %conv = fptosi float %0 to i32 1560 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1561 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 1562 %1 = load float, float* %arrayidx1, align 4 1563 %conv2 = fptosi float %1 to i32 1564 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 1565 %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1 1566 %2 = load float, float* %arrayidx4, align 4 1567 %conv5 = fptosi float %2 to i32 1568 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 1569 %3 = load float, float* %ptr, align 4 1570 %conv8 = fptosi float %3 to i32 1571 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 1572 ret <4 x i32> %vecinit9 1573} 1574 1575; Function Attrs: norecurse nounwind readonly 1576define <4 x i32> @fromDiffMemVarAConvftoi(float* nocapture readonly %arr, i32 signext %elem) { 1577; P9BE-LABEL: fromDiffMemVarAConvftoi: 1578; P9BE: # %bb.0: # %entry 1579; P9BE-NEXT: sldi r4, r4, 2 1580; P9BE-NEXT: lfsux f0, r3, r4 1581; P9BE-NEXT: lfs f1, 12(r3) 1582; P9BE-NEXT: lfs f2, 4(r3) 1583; P9BE-NEXT: xxmrghd vs1, vs2, vs1 1584; P9BE-NEXT: xvcvdpsp v2, vs1 1585; P9BE-NEXT: lfs f1, 8(r3) 1586; P9BE-NEXT: xxmrghd vs0, vs0, vs1 1587; P9BE-NEXT: xvcvdpsp v3, vs0 1588; P9BE-NEXT: vmrgew v2, v3, v2 1589; P9BE-NEXT: xvcvspsxws v2, v2 1590; P9BE-NEXT: blr 1591; 1592; P9LE-LABEL: fromDiffMemVarAConvftoi: 1593; P9LE: # %bb.0: # %entry 1594; P9LE-NEXT: sldi r4, r4, 2 1595; P9LE-NEXT: lfsux f0, r3, r4 1596; P9LE-NEXT: lfs f1, 8(r3) 1597; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1598; P9LE-NEXT: lfs f1, 12(r3) 1599; P9LE-NEXT: xvcvdpsp v2, vs0 1600; P9LE-NEXT: lfs f0, 4(r3) 1601; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1602; P9LE-NEXT: xvcvdpsp v3, vs0 1603; P9LE-NEXT: vmrgew v2, v3, v2 1604; P9LE-NEXT: xvcvspsxws v2, v2 1605; P9LE-NEXT: blr 1606; 1607; P8BE-LABEL: fromDiffMemVarAConvftoi: 1608; P8BE: # %bb.0: # %entry 1609; P8BE-NEXT: sldi r4, r4, 2 1610; P8BE-NEXT: lfsux f0, r3, r4 1611; P8BE-NEXT: lfs f1, 12(r3) 1612; P8BE-NEXT: lfs f2, 4(r3) 1613; P8BE-NEXT: lfs f3, 8(r3) 1614; P8BE-NEXT: xxmrghd vs1, vs2, vs1 1615; P8BE-NEXT: xxmrghd vs0, vs0, vs3 1616; P8BE-NEXT: xvcvdpsp v2, vs1 1617; P8BE-NEXT: xvcvdpsp v3, vs0 1618; P8BE-NEXT: vmrgew v2, v3, v2 1619; P8BE-NEXT: xvcvspsxws v2, v2 1620; P8BE-NEXT: blr 1621; 1622; P8LE-LABEL: fromDiffMemVarAConvftoi: 1623; P8LE: # %bb.0: # %entry 1624; P8LE-NEXT: sldi r4, r4, 2 1625; P8LE-NEXT: lfsux f0, r3, r4 1626; P8LE-NEXT: lfs f1, 8(r3) 1627; P8LE-NEXT: lfs f2, 4(r3) 1628; P8LE-NEXT: lfs f3, 12(r3) 1629; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1630; P8LE-NEXT: xxmrghd vs1, vs3, vs2 1631; P8LE-NEXT: xvcvdpsp v2, vs0 1632; P8LE-NEXT: xvcvdpsp v3, vs1 1633; P8LE-NEXT: vmrgew v2, v3, v2 1634; P8LE-NEXT: xvcvspsxws v2, v2 1635; P8LE-NEXT: blr 1636entry: 1637 %idxprom = sext i32 %elem to i64 1638 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 1639 %0 = load float, float* %arrayidx, align 4 1640 %conv = fptosi float %0 to i32 1641 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1642 %add = add nsw i32 %elem, 1 1643 %idxprom1 = sext i32 %add to i64 1644 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 1645 %1 = load float, float* %arrayidx2, align 4 1646 %conv3 = fptosi float %1 to i32 1647 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1648 %add5 = add nsw i32 %elem, 2 1649 %idxprom6 = sext i32 %add5 to i64 1650 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 1651 %2 = load float, float* %arrayidx7, align 4 1652 %conv8 = fptosi float %2 to i32 1653 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1654 %add10 = add nsw i32 %elem, 3 1655 %idxprom11 = sext i32 %add10 to i64 1656 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 1657 %3 = load float, float* %arrayidx12, align 4 1658 %conv13 = fptosi float %3 to i32 1659 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1660 ret <4 x i32> %vecinit14 1661; FIXME: implement finding consecutive loads with pre-inc 1662} 1663 1664; Function Attrs: norecurse nounwind readonly 1665define <4 x i32> @fromDiffMemVarDConvftoi(float* nocapture readonly %arr, i32 signext %elem) { 1666; P9BE-LABEL: fromDiffMemVarDConvftoi: 1667; P9BE: # %bb.0: # %entry 1668; P9BE-NEXT: sldi r4, r4, 2 1669; P9BE-NEXT: lfsux f0, r3, r4 1670; P9BE-NEXT: lfs f1, -12(r3) 1671; P9BE-NEXT: lfs f2, -4(r3) 1672; P9BE-NEXT: xxmrghd vs1, vs2, vs1 1673; P9BE-NEXT: xvcvdpsp v2, vs1 1674; P9BE-NEXT: lfs f1, -8(r3) 1675; P9BE-NEXT: xxmrghd vs0, vs0, vs1 1676; P9BE-NEXT: xvcvdpsp v3, vs0 1677; P9BE-NEXT: vmrgew v2, v3, v2 1678; P9BE-NEXT: xvcvspsxws v2, v2 1679; P9BE-NEXT: blr 1680; 1681; P9LE-LABEL: fromDiffMemVarDConvftoi: 1682; P9LE: # %bb.0: # %entry 1683; P9LE-NEXT: sldi r4, r4, 2 1684; P9LE-NEXT: lfsux f0, r3, r4 1685; P9LE-NEXT: lfs f1, -8(r3) 1686; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1687; P9LE-NEXT: lfs f1, -12(r3) 1688; P9LE-NEXT: xvcvdpsp v2, vs0 1689; P9LE-NEXT: lfs f0, -4(r3) 1690; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1691; P9LE-NEXT: xvcvdpsp v3, vs0 1692; P9LE-NEXT: vmrgew v2, v3, v2 1693; P9LE-NEXT: xvcvspsxws v2, v2 1694; P9LE-NEXT: blr 1695; 1696; P8BE-LABEL: fromDiffMemVarDConvftoi: 1697; P8BE: # %bb.0: # %entry 1698; P8BE-NEXT: sldi r4, r4, 2 1699; P8BE-NEXT: lfsux f0, r3, r4 1700; P8BE-NEXT: lfs f1, -12(r3) 1701; P8BE-NEXT: lfs f2, -4(r3) 1702; P8BE-NEXT: lfs f3, -8(r3) 1703; P8BE-NEXT: xxmrghd vs1, vs2, vs1 1704; P8BE-NEXT: xxmrghd vs0, vs0, vs3 1705; P8BE-NEXT: xvcvdpsp v2, vs1 1706; P8BE-NEXT: xvcvdpsp v3, vs0 1707; P8BE-NEXT: vmrgew v2, v3, v2 1708; P8BE-NEXT: xvcvspsxws v2, v2 1709; P8BE-NEXT: blr 1710; 1711; P8LE-LABEL: fromDiffMemVarDConvftoi: 1712; P8LE: # %bb.0: # %entry 1713; P8LE-NEXT: sldi r4, r4, 2 1714; P8LE-NEXT: lfsux f0, r3, r4 1715; P8LE-NEXT: lfs f1, -8(r3) 1716; P8LE-NEXT: lfs f2, -4(r3) 1717; P8LE-NEXT: lfs f3, -12(r3) 1718; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1719; P8LE-NEXT: xxmrghd vs1, vs3, vs2 1720; P8LE-NEXT: xvcvdpsp v2, vs0 1721; P8LE-NEXT: xvcvdpsp v3, vs1 1722; P8LE-NEXT: vmrgew v2, v3, v2 1723; P8LE-NEXT: xvcvspsxws v2, v2 1724; P8LE-NEXT: blr 1725entry: 1726 %idxprom = sext i32 %elem to i64 1727 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 1728 %0 = load float, float* %arrayidx, align 4 1729 %conv = fptosi float %0 to i32 1730 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1731 %sub = add nsw i32 %elem, -1 1732 %idxprom1 = sext i32 %sub to i64 1733 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 1734 %1 = load float, float* %arrayidx2, align 4 1735 %conv3 = fptosi float %1 to i32 1736 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1737 %sub5 = add nsw i32 %elem, -2 1738 %idxprom6 = sext i32 %sub5 to i64 1739 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 1740 %2 = load float, float* %arrayidx7, align 4 1741 %conv8 = fptosi float %2 to i32 1742 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1743 %sub10 = add nsw i32 %elem, -3 1744 %idxprom11 = sext i32 %sub10 to i64 1745 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 1746 %3 = load float, float* %arrayidx12, align 4 1747 %conv13 = fptosi float %3 to i32 1748 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1749 ret <4 x i32> %vecinit14 1750; FIXME: implement finding consecutive loads with pre-inc 1751} 1752 1753; Function Attrs: norecurse nounwind readnone 1754define <4 x i32> @spltRegValConvftoi(float %val) { 1755; P9BE-LABEL: spltRegValConvftoi: 1756; P9BE: # %bb.0: # %entry 1757; P9BE-NEXT: xscvdpsxws f0, f1 1758; P9BE-NEXT: xxspltw v2, vs0, 1 1759; P9BE-NEXT: blr 1760; 1761; P9LE-LABEL: spltRegValConvftoi: 1762; P9LE: # %bb.0: # %entry 1763; P9LE-NEXT: xscvdpsxws f0, f1 1764; P9LE-NEXT: xxspltw v2, vs0, 1 1765; P9LE-NEXT: blr 1766; 1767; P8BE-LABEL: spltRegValConvftoi: 1768; P8BE: # %bb.0: # %entry 1769; P8BE-NEXT: xscvdpsxws f0, f1 1770; P8BE-NEXT: xxspltw v2, vs0, 1 1771; P8BE-NEXT: blr 1772; 1773; P8LE-LABEL: spltRegValConvftoi: 1774; P8LE: # %bb.0: # %entry 1775; P8LE-NEXT: xscvdpsxws f0, f1 1776; P8LE-NEXT: xxspltw v2, vs0, 1 1777; P8LE-NEXT: blr 1778entry: 1779 %conv = fptosi float %val to i32 1780 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1781 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1782 ret <4 x i32> %splat.splat 1783} 1784 1785; Function Attrs: norecurse nounwind readonly 1786define <4 x i32> @spltMemValConvftoi(float* nocapture readonly %ptr) { 1787; P9BE-LABEL: spltMemValConvftoi: 1788; P9BE: # %bb.0: # %entry 1789; P9BE-NEXT: lxvwsx vs0, 0, r3 1790; P9BE-NEXT: xvcvspsxws v2, vs0 1791; P9BE-NEXT: blr 1792; 1793; P9LE-LABEL: spltMemValConvftoi: 1794; P9LE: # %bb.0: # %entry 1795; P9LE-NEXT: lxvwsx vs0, 0, r3 1796; P9LE-NEXT: xvcvspsxws v2, vs0 1797; P9LE-NEXT: blr 1798; 1799; P8BE-LABEL: spltMemValConvftoi: 1800; P8BE: # %bb.0: # %entry 1801; P8BE-NEXT: lfsx f0, 0, r3 1802; P8BE-NEXT: xscvdpsxws f0, f0 1803; P8BE-NEXT: xxspltw v2, vs0, 1 1804; P8BE-NEXT: blr 1805; 1806; P8LE-LABEL: spltMemValConvftoi: 1807; P8LE: # %bb.0: # %entry 1808; P8LE-NEXT: lfsx f0, 0, r3 1809; P8LE-NEXT: xscvdpsxws f0, f0 1810; P8LE-NEXT: xxspltw v2, vs0, 1 1811; P8LE-NEXT: blr 1812entry: 1813 %0 = load float, float* %ptr, align 4 1814 %conv = fptosi float %0 to i32 1815 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1816 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1817 ret <4 x i32> %splat.splat 1818} 1819 1820; Function Attrs: norecurse nounwind readnone 1821define <4 x i32> @spltCnstConvdtoi() { 1822; P9BE-LABEL: spltCnstConvdtoi: 1823; P9BE: # %bb.0: # %entry 1824; P9BE-NEXT: vspltisw v2, 4 1825; P9BE-NEXT: blr 1826; 1827; P9LE-LABEL: spltCnstConvdtoi: 1828; P9LE: # %bb.0: # %entry 1829; P9LE-NEXT: vspltisw v2, 4 1830; P9LE-NEXT: blr 1831; 1832; P8BE-LABEL: spltCnstConvdtoi: 1833; P8BE: # %bb.0: # %entry 1834; P8BE-NEXT: vspltisw v2, 4 1835; P8BE-NEXT: blr 1836; 1837; P8LE-LABEL: spltCnstConvdtoi: 1838; P8LE: # %bb.0: # %entry 1839; P8LE-NEXT: vspltisw v2, 4 1840; P8LE-NEXT: blr 1841entry: 1842 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 1843} 1844 1845; Function Attrs: norecurse nounwind readnone 1846define <4 x i32> @fromRegsConvdtoi(double %a, double %b, double %c, double %d) { 1847; P9BE-LABEL: fromRegsConvdtoi: 1848; P9BE: # %bb.0: # %entry 1849; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1850; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1851; P9BE-NEXT: xxmrghd vs0, vs2, vs4 1852; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1853; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1854; P9BE-NEXT: xvcvdpsxws v2, vs0 1855; P9BE-NEXT: xxmrghd vs0, vs1, vs3 1856; P9BE-NEXT: xvcvdpsxws v3, vs0 1857; P9BE-NEXT: vmrgew v2, v3, v2 1858; P9BE-NEXT: blr 1859; 1860; P9LE-LABEL: fromRegsConvdtoi: 1861; P9LE: # %bb.0: # %entry 1862; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1863; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1864; P9LE-NEXT: xxmrghd vs0, vs3, vs1 1865; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1866; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1867; P9LE-NEXT: xvcvdpsxws v2, vs0 1868; P9LE-NEXT: xxmrghd vs0, vs4, vs2 1869; P9LE-NEXT: xvcvdpsxws v3, vs0 1870; P9LE-NEXT: vmrgew v2, v3, v2 1871; P9LE-NEXT: blr 1872; 1873; P8BE-LABEL: fromRegsConvdtoi: 1874; P8BE: # %bb.0: # %entry 1875; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1876; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1877; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1878; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1879; P8BE-NEXT: xxmrghd vs0, vs2, vs4 1880; P8BE-NEXT: xxmrghd vs1, vs1, vs3 1881; P8BE-NEXT: xvcvdpsxws v2, vs0 1882; P8BE-NEXT: xvcvdpsxws v3, vs1 1883; P8BE-NEXT: vmrgew v2, v3, v2 1884; P8BE-NEXT: blr 1885; 1886; P8LE-LABEL: fromRegsConvdtoi: 1887; P8LE: # %bb.0: # %entry 1888; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1889; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1890; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1891; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1892; P8LE-NEXT: xxmrghd vs0, vs3, vs1 1893; P8LE-NEXT: xxmrghd vs1, vs4, vs2 1894; P8LE-NEXT: xvcvdpsxws v2, vs0 1895; P8LE-NEXT: xvcvdpsxws v3, vs1 1896; P8LE-NEXT: vmrgew v2, v3, v2 1897; P8LE-NEXT: blr 1898entry: 1899 %conv = fptosi double %a to i32 1900 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1901 %conv1 = fptosi double %b to i32 1902 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 1903 %conv3 = fptosi double %c to i32 1904 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 1905 %conv5 = fptosi double %d to i32 1906 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 1907 ret <4 x i32> %vecinit6 1908} 1909 1910; Function Attrs: norecurse nounwind readnone 1911define <4 x i32> @fromDiffConstsConvdtoi() { 1912; P9BE-LABEL: fromDiffConstsConvdtoi: 1913; P9BE: # %bb.0: # %entry 1914; P9BE-NEXT: addis r3, r2, .LCPI26_0@toc@ha 1915; P9BE-NEXT: addi r3, r3, .LCPI26_0@toc@l 1916; P9BE-NEXT: lxvx v2, 0, r3 1917; P9BE-NEXT: blr 1918; 1919; P9LE-LABEL: fromDiffConstsConvdtoi: 1920; P9LE: # %bb.0: # %entry 1921; P9LE-NEXT: addis r3, r2, .LCPI26_0@toc@ha 1922; P9LE-NEXT: addi r3, r3, .LCPI26_0@toc@l 1923; P9LE-NEXT: lxvx v2, 0, r3 1924; P9LE-NEXT: blr 1925; 1926; P8BE-LABEL: fromDiffConstsConvdtoi: 1927; P8BE: # %bb.0: # %entry 1928; P8BE-NEXT: addis r3, r2, .LCPI26_0@toc@ha 1929; P8BE-NEXT: addi r3, r3, .LCPI26_0@toc@l 1930; P8BE-NEXT: lxvw4x v2, 0, r3 1931; P8BE-NEXT: blr 1932; 1933; P8LE-LABEL: fromDiffConstsConvdtoi: 1934; P8LE: # %bb.0: # %entry 1935; P8LE-NEXT: addis r3, r2, .LCPI26_0@toc@ha 1936; P8LE-NEXT: addi r3, r3, .LCPI26_0@toc@l 1937; P8LE-NEXT: lvx v2, 0, r3 1938; P8LE-NEXT: blr 1939entry: 1940 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 1941} 1942 1943; Function Attrs: norecurse nounwind readonly 1944define <4 x i32> @fromDiffMemConsAConvdtoi(double* nocapture readonly %ptr) { 1945; P9BE-LABEL: fromDiffMemConsAConvdtoi: 1946; P9BE: # %bb.0: # %entry 1947; P9BE-NEXT: lxv vs0, 0(r3) 1948; P9BE-NEXT: lxv vs1, 16(r3) 1949; P9BE-NEXT: xxmrgld vs2, vs0, vs1 1950; P9BE-NEXT: xxmrghd vs0, vs0, vs1 1951; P9BE-NEXT: xvcvdpsxws v2, vs2 1952; P9BE-NEXT: xvcvdpsxws v3, vs0 1953; P9BE-NEXT: vmrgew v2, v3, v2 1954; P9BE-NEXT: blr 1955; 1956; P9LE-LABEL: fromDiffMemConsAConvdtoi: 1957; P9LE: # %bb.0: # %entry 1958; P9LE-NEXT: lxv vs0, 0(r3) 1959; P9LE-NEXT: lxv vs1, 16(r3) 1960; P9LE-NEXT: xxmrgld vs2, vs1, vs0 1961; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1962; P9LE-NEXT: xvcvdpsxws v2, vs2 1963; P9LE-NEXT: xvcvdpsxws v3, vs0 1964; P9LE-NEXT: vmrgew v2, v3, v2 1965; P9LE-NEXT: blr 1966; 1967; P8BE-LABEL: fromDiffMemConsAConvdtoi: 1968; P8BE: # %bb.0: # %entry 1969; P8BE-NEXT: li r4, 16 1970; P8BE-NEXT: lxvd2x vs0, 0, r3 1971; P8BE-NEXT: lxvd2x vs1, r3, r4 1972; P8BE-NEXT: xxmrgld vs2, vs0, vs1 1973; P8BE-NEXT: xxmrghd vs0, vs0, vs1 1974; P8BE-NEXT: xvcvdpsxws v2, vs2 1975; P8BE-NEXT: xvcvdpsxws v3, vs0 1976; P8BE-NEXT: vmrgew v2, v3, v2 1977; P8BE-NEXT: blr 1978; 1979; P8LE-LABEL: fromDiffMemConsAConvdtoi: 1980; P8LE: # %bb.0: # %entry 1981; P8LE-NEXT: li r4, 16 1982; P8LE-NEXT: lxvd2x vs0, 0, r3 1983; P8LE-NEXT: lxvd2x vs1, r3, r4 1984; P8LE-NEXT: xxswapd vs0, vs0 1985; P8LE-NEXT: xxswapd vs1, vs1 1986; P8LE-NEXT: xxmrgld vs2, vs1, vs0 1987; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1988; P8LE-NEXT: xvcvdpsxws v2, vs2 1989; P8LE-NEXT: xvcvdpsxws v3, vs0 1990; P8LE-NEXT: vmrgew v2, v3, v2 1991; P8LE-NEXT: blr 1992entry: 1993 %0 = bitcast double* %ptr to <2 x double>* 1994 %1 = load <2 x double>, <2 x double>* %0, align 8 1995 %2 = fptosi <2 x double> %1 to <2 x i32> 1996 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 2 1997 %3 = bitcast double* %arrayidx4 to <2 x double>* 1998 %4 = load <2 x double>, <2 x double>* %3, align 8 1999 %5 = fptosi <2 x double> %4 to <2 x i32> 2000 %vecinit9 = shufflevector <2 x i32> %2, <2 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 2001 ret <4 x i32> %vecinit9 2002} 2003 2004; Function Attrs: norecurse nounwind readonly 2005define <4 x i32> @fromDiffMemConsDConvdtoi(double* nocapture readonly %ptr) { 2006; P9BE-LABEL: fromDiffMemConsDConvdtoi: 2007; P9BE: # %bb.0: # %entry 2008; P9BE-NEXT: lfd f0, 24(r3) 2009; P9BE-NEXT: lfd f1, 16(r3) 2010; P9BE-NEXT: lfd f2, 8(r3) 2011; P9BE-NEXT: xxmrghd vs0, vs0, vs2 2012; P9BE-NEXT: lfd f3, 0(r3) 2013; P9BE-NEXT: xxmrghd vs1, vs1, vs3 2014; P9BE-NEXT: xvcvdpsxws v2, vs1 2015; P9BE-NEXT: xvcvdpsxws v3, vs0 2016; P9BE-NEXT: vmrgew v2, v3, v2 2017; P9BE-NEXT: blr 2018; 2019; P9LE-LABEL: fromDiffMemConsDConvdtoi: 2020; P9LE: # %bb.0: # %entry 2021; P9LE-NEXT: lfd f0, 24(r3) 2022; P9LE-NEXT: lfd f2, 8(r3) 2023; P9LE-NEXT: xxmrghd vs0, vs2, vs0 2024; P9LE-NEXT: lfd f1, 16(r3) 2025; P9LE-NEXT: lfd f3, 0(r3) 2026; P9LE-NEXT: xvcvdpsxws v2, vs0 2027; P9LE-NEXT: xxmrghd vs0, vs3, vs1 2028; P9LE-NEXT: xvcvdpsxws v3, vs0 2029; P9LE-NEXT: vmrgew v2, v3, v2 2030; P9LE-NEXT: blr 2031; 2032; P8BE-LABEL: fromDiffMemConsDConvdtoi: 2033; P8BE: # %bb.0: # %entry 2034; P8BE-NEXT: lfdx f3, 0, r3 2035; P8BE-NEXT: lfd f0, 24(r3) 2036; P8BE-NEXT: lfd f1, 8(r3) 2037; P8BE-NEXT: lfd f2, 16(r3) 2038; P8BE-NEXT: xxmrghd vs0, vs0, vs1 2039; P8BE-NEXT: xxmrghd vs1, vs2, vs3 2040; P8BE-NEXT: xvcvdpsxws v2, vs0 2041; P8BE-NEXT: xvcvdpsxws v3, vs1 2042; P8BE-NEXT: vmrgew v2, v2, v3 2043; P8BE-NEXT: blr 2044; 2045; P8LE-LABEL: fromDiffMemConsDConvdtoi: 2046; P8LE: # %bb.0: # %entry 2047; P8LE-NEXT: lfdx f3, 0, r3 2048; P8LE-NEXT: lfd f0, 24(r3) 2049; P8LE-NEXT: lfd f1, 8(r3) 2050; P8LE-NEXT: lfd f2, 16(r3) 2051; P8LE-NEXT: xxmrghd vs0, vs1, vs0 2052; P8LE-NEXT: xxmrghd vs1, vs3, vs2 2053; P8LE-NEXT: xvcvdpsxws v2, vs0 2054; P8LE-NEXT: xvcvdpsxws v3, vs1 2055; P8LE-NEXT: vmrgew v2, v3, v2 2056; P8LE-NEXT: blr 2057entry: 2058 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 2059 %0 = load double, double* %arrayidx, align 8 2060 %conv = fptosi double %0 to i32 2061 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2062 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 2063 %1 = load double, double* %arrayidx1, align 8 2064 %conv2 = fptosi double %1 to i32 2065 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 2066 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 1 2067 %2 = load double, double* %arrayidx4, align 8 2068 %conv5 = fptosi double %2 to i32 2069 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 2070 %3 = load double, double* %ptr, align 8 2071 %conv8 = fptosi double %3 to i32 2072 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 2073 ret <4 x i32> %vecinit9 2074} 2075 2076; Function Attrs: norecurse nounwind readonly 2077define <4 x i32> @fromDiffMemVarAConvdtoi(double* nocapture readonly %arr, i32 signext %elem) { 2078; P9BE-LABEL: fromDiffMemVarAConvdtoi: 2079; P9BE: # %bb.0: # %entry 2080; P9BE-NEXT: sldi r4, r4, 3 2081; P9BE-NEXT: lfdux f0, r3, r4 2082; P9BE-NEXT: lfd f1, 8(r3) 2083; P9BE-NEXT: lfd f2, 16(r3) 2084; P9BE-NEXT: lfd f3, 24(r3) 2085; P9BE-NEXT: xxmrghd vs1, vs1, vs3 2086; P9BE-NEXT: xxmrghd vs0, vs0, vs2 2087; P9BE-NEXT: xvcvdpsxws v2, vs1 2088; P9BE-NEXT: xvcvdpsxws v3, vs0 2089; P9BE-NEXT: vmrgew v2, v3, v2 2090; P9BE-NEXT: blr 2091; 2092; P9LE-LABEL: fromDiffMemVarAConvdtoi: 2093; P9LE: # %bb.0: # %entry 2094; P9LE-NEXT: sldi r4, r4, 3 2095; P9LE-NEXT: lfdux f0, r3, r4 2096; P9LE-NEXT: lfd f2, 16(r3) 2097; P9LE-NEXT: lfd f1, 8(r3) 2098; P9LE-NEXT: lfd f3, 24(r3) 2099; P9LE-NEXT: xxmrghd vs0, vs2, vs0 2100; P9LE-NEXT: xvcvdpsxws v2, vs0 2101; P9LE-NEXT: xxmrghd vs0, vs3, vs1 2102; P9LE-NEXT: xvcvdpsxws v3, vs0 2103; P9LE-NEXT: vmrgew v2, v3, v2 2104; P9LE-NEXT: blr 2105; 2106; P8BE-LABEL: fromDiffMemVarAConvdtoi: 2107; P8BE: # %bb.0: # %entry 2108; P8BE-NEXT: sldi r4, r4, 3 2109; P8BE-NEXT: lfdux f0, r3, r4 2110; P8BE-NEXT: lfd f1, 8(r3) 2111; P8BE-NEXT: lfd f2, 24(r3) 2112; P8BE-NEXT: lfd f3, 16(r3) 2113; P8BE-NEXT: xxmrghd vs1, vs1, vs2 2114; P8BE-NEXT: xxmrghd vs0, vs0, vs3 2115; P8BE-NEXT: xvcvdpsxws v2, vs1 2116; P8BE-NEXT: xvcvdpsxws v3, vs0 2117; P8BE-NEXT: vmrgew v2, v3, v2 2118; P8BE-NEXT: blr 2119; 2120; P8LE-LABEL: fromDiffMemVarAConvdtoi: 2121; P8LE: # %bb.0: # %entry 2122; P8LE-NEXT: sldi r4, r4, 3 2123; P8LE-NEXT: lfdux f0, r3, r4 2124; P8LE-NEXT: lfd f1, 16(r3) 2125; P8LE-NEXT: lfd f2, 8(r3) 2126; P8LE-NEXT: lfd f3, 24(r3) 2127; P8LE-NEXT: xxmrghd vs0, vs1, vs0 2128; P8LE-NEXT: xxmrghd vs1, vs3, vs2 2129; P8LE-NEXT: xvcvdpsxws v2, vs0 2130; P8LE-NEXT: xvcvdpsxws v3, vs1 2131; P8LE-NEXT: vmrgew v2, v3, v2 2132; P8LE-NEXT: blr 2133entry: 2134 %idxprom = sext i32 %elem to i64 2135 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 2136 %0 = load double, double* %arrayidx, align 8 2137 %conv = fptosi double %0 to i32 2138 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2139 %add = add nsw i32 %elem, 1 2140 %idxprom1 = sext i32 %add to i64 2141 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 2142 %1 = load double, double* %arrayidx2, align 8 2143 %conv3 = fptosi double %1 to i32 2144 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2145 %add5 = add nsw i32 %elem, 2 2146 %idxprom6 = sext i32 %add5 to i64 2147 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 2148 %2 = load double, double* %arrayidx7, align 8 2149 %conv8 = fptosi double %2 to i32 2150 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2151 %add10 = add nsw i32 %elem, 3 2152 %idxprom11 = sext i32 %add10 to i64 2153 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 2154 %3 = load double, double* %arrayidx12, align 8 2155 %conv13 = fptosi double %3 to i32 2156 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2157 ret <4 x i32> %vecinit14 2158} 2159 2160; Function Attrs: norecurse nounwind readonly 2161define <4 x i32> @fromDiffMemVarDConvdtoi(double* nocapture readonly %arr, i32 signext %elem) { 2162; P9BE-LABEL: fromDiffMemVarDConvdtoi: 2163; P9BE: # %bb.0: # %entry 2164; P9BE-NEXT: sldi r4, r4, 3 2165; P9BE-NEXT: lfdux f0, r3, r4 2166; P9BE-NEXT: lfd f1, -8(r3) 2167; P9BE-NEXT: lfd f2, -16(r3) 2168; P9BE-NEXT: lfd f3, -24(r3) 2169; P9BE-NEXT: xxmrghd vs1, vs1, vs3 2170; P9BE-NEXT: xxmrghd vs0, vs0, vs2 2171; P9BE-NEXT: xvcvdpsxws v2, vs1 2172; P9BE-NEXT: xvcvdpsxws v3, vs0 2173; P9BE-NEXT: vmrgew v2, v3, v2 2174; P9BE-NEXT: blr 2175; 2176; P9LE-LABEL: fromDiffMemVarDConvdtoi: 2177; P9LE: # %bb.0: # %entry 2178; P9LE-NEXT: sldi r4, r4, 3 2179; P9LE-NEXT: lfdux f0, r3, r4 2180; P9LE-NEXT: lfd f2, -16(r3) 2181; P9LE-NEXT: lfd f1, -8(r3) 2182; P9LE-NEXT: lfd f3, -24(r3) 2183; P9LE-NEXT: xxmrghd vs0, vs2, vs0 2184; P9LE-NEXT: xvcvdpsxws v2, vs0 2185; P9LE-NEXT: xxmrghd vs0, vs3, vs1 2186; P9LE-NEXT: xvcvdpsxws v3, vs0 2187; P9LE-NEXT: vmrgew v2, v3, v2 2188; P9LE-NEXT: blr 2189; 2190; P8BE-LABEL: fromDiffMemVarDConvdtoi: 2191; P8BE: # %bb.0: # %entry 2192; P8BE-NEXT: sldi r4, r4, 3 2193; P8BE-NEXT: lfdux f0, r3, r4 2194; P8BE-NEXT: lfd f1, -8(r3) 2195; P8BE-NEXT: lfd f2, -24(r3) 2196; P8BE-NEXT: lfd f3, -16(r3) 2197; P8BE-NEXT: xxmrghd vs1, vs1, vs2 2198; P8BE-NEXT: xxmrghd vs0, vs0, vs3 2199; P8BE-NEXT: xvcvdpsxws v2, vs1 2200; P8BE-NEXT: xvcvdpsxws v3, vs0 2201; P8BE-NEXT: vmrgew v2, v3, v2 2202; P8BE-NEXT: blr 2203; 2204; P8LE-LABEL: fromDiffMemVarDConvdtoi: 2205; P8LE: # %bb.0: # %entry 2206; P8LE-NEXT: sldi r4, r4, 3 2207; P8LE-NEXT: lfdux f0, r3, r4 2208; P8LE-NEXT: lfd f1, -16(r3) 2209; P8LE-NEXT: lfd f2, -8(r3) 2210; P8LE-NEXT: lfd f3, -24(r3) 2211; P8LE-NEXT: xxmrghd vs0, vs1, vs0 2212; P8LE-NEXT: xxmrghd vs1, vs3, vs2 2213; P8LE-NEXT: xvcvdpsxws v2, vs0 2214; P8LE-NEXT: xvcvdpsxws v3, vs1 2215; P8LE-NEXT: vmrgew v2, v3, v2 2216; P8LE-NEXT: blr 2217entry: 2218 %idxprom = sext i32 %elem to i64 2219 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 2220 %0 = load double, double* %arrayidx, align 8 2221 %conv = fptosi double %0 to i32 2222 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2223 %sub = add nsw i32 %elem, -1 2224 %idxprom1 = sext i32 %sub to i64 2225 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 2226 %1 = load double, double* %arrayidx2, align 8 2227 %conv3 = fptosi double %1 to i32 2228 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2229 %sub5 = add nsw i32 %elem, -2 2230 %idxprom6 = sext i32 %sub5 to i64 2231 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 2232 %2 = load double, double* %arrayidx7, align 8 2233 %conv8 = fptosi double %2 to i32 2234 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2235 %sub10 = add nsw i32 %elem, -3 2236 %idxprom11 = sext i32 %sub10 to i64 2237 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 2238 %3 = load double, double* %arrayidx12, align 8 2239 %conv13 = fptosi double %3 to i32 2240 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2241 ret <4 x i32> %vecinit14 2242} 2243 2244; Function Attrs: norecurse nounwind readnone 2245define <4 x i32> @spltRegValConvdtoi(double %val) { 2246; P9BE-LABEL: spltRegValConvdtoi: 2247; P9BE: # %bb.0: # %entry 2248; P9BE-NEXT: xscvdpsxws f0, f1 2249; P9BE-NEXT: xxspltw v2, vs0, 1 2250; P9BE-NEXT: blr 2251; 2252; P9LE-LABEL: spltRegValConvdtoi: 2253; P9LE: # %bb.0: # %entry 2254; P9LE-NEXT: xscvdpsxws f0, f1 2255; P9LE-NEXT: xxspltw v2, vs0, 1 2256; P9LE-NEXT: blr 2257; 2258; P8BE-LABEL: spltRegValConvdtoi: 2259; P8BE: # %bb.0: # %entry 2260; P8BE-NEXT: xscvdpsxws f0, f1 2261; P8BE-NEXT: xxspltw v2, vs0, 1 2262; P8BE-NEXT: blr 2263; 2264; P8LE-LABEL: spltRegValConvdtoi: 2265; P8LE: # %bb.0: # %entry 2266; P8LE-NEXT: xscvdpsxws f0, f1 2267; P8LE-NEXT: xxspltw v2, vs0, 1 2268; P8LE-NEXT: blr 2269entry: 2270 %conv = fptosi double %val to i32 2271 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2272 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2273 ret <4 x i32> %splat.splat 2274} 2275 2276; Function Attrs: norecurse nounwind readonly 2277define <4 x i32> @spltMemValConvdtoi(double* nocapture readonly %ptr) { 2278; P9BE-LABEL: spltMemValConvdtoi: 2279; P9BE: # %bb.0: # %entry 2280; P9BE-NEXT: lfd f0, 0(r3) 2281; P9BE-NEXT: xscvdpsxws f0, f0 2282; P9BE-NEXT: xxspltw v2, vs0, 1 2283; P9BE-NEXT: blr 2284; 2285; P9LE-LABEL: spltMemValConvdtoi: 2286; P9LE: # %bb.0: # %entry 2287; P9LE-NEXT: lfd f0, 0(r3) 2288; P9LE-NEXT: xscvdpsxws f0, f0 2289; P9LE-NEXT: xxspltw v2, vs0, 1 2290; P9LE-NEXT: blr 2291; 2292; P8BE-LABEL: spltMemValConvdtoi: 2293; P8BE: # %bb.0: # %entry 2294; P8BE-NEXT: lfdx f0, 0, r3 2295; P8BE-NEXT: xscvdpsxws f0, f0 2296; P8BE-NEXT: xxspltw v2, vs0, 1 2297; P8BE-NEXT: blr 2298; 2299; P8LE-LABEL: spltMemValConvdtoi: 2300; P8LE: # %bb.0: # %entry 2301; P8LE-NEXT: lfdx f0, 0, r3 2302; P8LE-NEXT: xscvdpsxws f0, f0 2303; P8LE-NEXT: xxspltw v2, vs0, 1 2304; P8LE-NEXT: blr 2305entry: 2306 %0 = load double, double* %ptr, align 8 2307 %conv = fptosi double %0 to i32 2308 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2309 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2310 ret <4 x i32> %splat.splat 2311} 2312; Function Attrs: norecurse nounwind readnone 2313define <4 x i32> @allZeroui() { 2314; P9BE-LABEL: allZeroui: 2315; P9BE: # %bb.0: # %entry 2316; P9BE-NEXT: xxlxor v2, v2, v2 2317; P9BE-NEXT: blr 2318; 2319; P9LE-LABEL: allZeroui: 2320; P9LE: # %bb.0: # %entry 2321; P9LE-NEXT: xxlxor v2, v2, v2 2322; P9LE-NEXT: blr 2323; 2324; P8BE-LABEL: allZeroui: 2325; P8BE: # %bb.0: # %entry 2326; P8BE-NEXT: xxlxor v2, v2, v2 2327; P8BE-NEXT: blr 2328; 2329; P8LE-LABEL: allZeroui: 2330; P8LE: # %bb.0: # %entry 2331; P8LE-NEXT: xxlxor v2, v2, v2 2332; P8LE-NEXT: blr 2333entry: 2334 ret <4 x i32> zeroinitializer 2335} 2336 2337; Function Attrs: norecurse nounwind readnone 2338define <4 x i32> @allOneui() { 2339; P9BE-LABEL: allOneui: 2340; P9BE: # %bb.0: # %entry 2341; P9BE-NEXT: xxspltib v2, 255 2342; P9BE-NEXT: blr 2343; 2344; P9LE-LABEL: allOneui: 2345; P9LE: # %bb.0: # %entry 2346; P9LE-NEXT: xxspltib v2, 255 2347; P9LE-NEXT: blr 2348; 2349; P8BE-LABEL: allOneui: 2350; P8BE: # %bb.0: # %entry 2351; P8BE-NEXT: vspltisb v2, -1 2352; P8BE-NEXT: blr 2353; 2354; P8LE-LABEL: allOneui: 2355; P8LE: # %bb.0: # %entry 2356; P8LE-NEXT: vspltisb v2, -1 2357; P8LE-NEXT: blr 2358entry: 2359 ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> 2360} 2361 2362; Function Attrs: norecurse nounwind readnone 2363define <4 x i32> @spltConst1ui() { 2364; P9BE-LABEL: spltConst1ui: 2365; P9BE: # %bb.0: # %entry 2366; P9BE-NEXT: vspltisw v2, 1 2367; P9BE-NEXT: blr 2368; 2369; P9LE-LABEL: spltConst1ui: 2370; P9LE: # %bb.0: # %entry 2371; P9LE-NEXT: vspltisw v2, 1 2372; P9LE-NEXT: blr 2373; 2374; P8BE-LABEL: spltConst1ui: 2375; P8BE: # %bb.0: # %entry 2376; P8BE-NEXT: vspltisw v2, 1 2377; P8BE-NEXT: blr 2378; 2379; P8LE-LABEL: spltConst1ui: 2380; P8LE: # %bb.0: # %entry 2381; P8LE-NEXT: vspltisw v2, 1 2382; P8LE-NEXT: blr 2383entry: 2384 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1> 2385} 2386 2387; Function Attrs: norecurse nounwind readnone 2388define <4 x i32> @spltConst16kui() { 2389; P9BE-LABEL: spltConst16kui: 2390; P9BE: # %bb.0: # %entry 2391; P9BE-NEXT: vspltisw v2, -15 2392; P9BE-NEXT: vsrw v2, v2, v2 2393; P9BE-NEXT: blr 2394; 2395; P9LE-LABEL: spltConst16kui: 2396; P9LE: # %bb.0: # %entry 2397; P9LE-NEXT: vspltisw v2, -15 2398; P9LE-NEXT: vsrw v2, v2, v2 2399; P9LE-NEXT: blr 2400; 2401; P8BE-LABEL: spltConst16kui: 2402; P8BE: # %bb.0: # %entry 2403; P8BE-NEXT: vspltisw v2, -15 2404; P8BE-NEXT: vsrw v2, v2, v2 2405; P8BE-NEXT: blr 2406; 2407; P8LE-LABEL: spltConst16kui: 2408; P8LE: # %bb.0: # %entry 2409; P8LE-NEXT: vspltisw v2, -15 2410; P8LE-NEXT: vsrw v2, v2, v2 2411; P8LE-NEXT: blr 2412entry: 2413 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 2414} 2415 2416; Function Attrs: norecurse nounwind readnone 2417define <4 x i32> @spltConst32kui() { 2418; P9BE-LABEL: spltConst32kui: 2419; P9BE: # %bb.0: # %entry 2420; P9BE-NEXT: vspltisw v2, -16 2421; P9BE-NEXT: vsrw v2, v2, v2 2422; P9BE-NEXT: blr 2423; 2424; P9LE-LABEL: spltConst32kui: 2425; P9LE: # %bb.0: # %entry 2426; P9LE-NEXT: vspltisw v2, -16 2427; P9LE-NEXT: vsrw v2, v2, v2 2428; P9LE-NEXT: blr 2429; 2430; P8BE-LABEL: spltConst32kui: 2431; P8BE: # %bb.0: # %entry 2432; P8BE-NEXT: vspltisw v2, -16 2433; P8BE-NEXT: vsrw v2, v2, v2 2434; P8BE-NEXT: blr 2435; 2436; P8LE-LABEL: spltConst32kui: 2437; P8LE: # %bb.0: # %entry 2438; P8LE-NEXT: vspltisw v2, -16 2439; P8LE-NEXT: vsrw v2, v2, v2 2440; P8LE-NEXT: blr 2441entry: 2442 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 2443} 2444 2445; Function Attrs: norecurse nounwind readnone 2446define <4 x i32> @fromRegsui(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c, i32 zeroext %d) { 2447; P9BE-LABEL: fromRegsui: 2448; P9BE: # %bb.0: # %entry 2449; P9BE-NEXT: rldimi r6, r5, 32, 0 2450; P9BE-NEXT: rldimi r4, r3, 32, 0 2451; P9BE-NEXT: mtvsrdd v2, r4, r6 2452; P9BE-NEXT: blr 2453; 2454; P9LE-LABEL: fromRegsui: 2455; P9LE: # %bb.0: # %entry 2456; P9LE-NEXT: rldimi r3, r4, 32, 0 2457; P9LE-NEXT: rldimi r5, r6, 32, 0 2458; P9LE-NEXT: mtvsrdd v2, r5, r3 2459; P9LE-NEXT: blr 2460; 2461; P8BE-LABEL: fromRegsui: 2462; P8BE: # %bb.0: # %entry 2463; P8BE-NEXT: rldimi r6, r5, 32, 0 2464; P8BE-NEXT: rldimi r4, r3, 32, 0 2465; P8BE-NEXT: mtvsrd f0, r6 2466; P8BE-NEXT: mtvsrd f1, r4 2467; P8BE-NEXT: xxmrghd v2, vs1, vs0 2468; P8BE-NEXT: blr 2469; 2470; P8LE-LABEL: fromRegsui: 2471; P8LE: # %bb.0: # %entry 2472; P8LE-NEXT: rldimi r3, r4, 32, 0 2473; P8LE-NEXT: rldimi r5, r6, 32, 0 2474; P8LE-NEXT: mtvsrd f0, r3 2475; P8LE-NEXT: mtvsrd f1, r5 2476; P8LE-NEXT: xxmrghd v2, vs1, vs0 2477; P8LE-NEXT: blr 2478entry: 2479 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 2480 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 2481 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 2482 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3 2483 ret <4 x i32> %vecinit3 2484} 2485 2486; Function Attrs: norecurse nounwind readnone 2487define <4 x i32> @fromDiffConstsui() { 2488; P9BE-LABEL: fromDiffConstsui: 2489; P9BE: # %bb.0: # %entry 2490; P9BE-NEXT: addis r3, r2, .LCPI39_0@toc@ha 2491; P9BE-NEXT: addi r3, r3, .LCPI39_0@toc@l 2492; P9BE-NEXT: lxvx v2, 0, r3 2493; P9BE-NEXT: blr 2494; 2495; P9LE-LABEL: fromDiffConstsui: 2496; P9LE: # %bb.0: # %entry 2497; P9LE-NEXT: addis r3, r2, .LCPI39_0@toc@ha 2498; P9LE-NEXT: addi r3, r3, .LCPI39_0@toc@l 2499; P9LE-NEXT: lxvx v2, 0, r3 2500; P9LE-NEXT: blr 2501; 2502; P8BE-LABEL: fromDiffConstsui: 2503; P8BE: # %bb.0: # %entry 2504; P8BE-NEXT: addis r3, r2, .LCPI39_0@toc@ha 2505; P8BE-NEXT: addi r3, r3, .LCPI39_0@toc@l 2506; P8BE-NEXT: lxvw4x v2, 0, r3 2507; P8BE-NEXT: blr 2508; 2509; P8LE-LABEL: fromDiffConstsui: 2510; P8LE: # %bb.0: # %entry 2511; P8LE-NEXT: addis r3, r2, .LCPI39_0@toc@ha 2512; P8LE-NEXT: addi r3, r3, .LCPI39_0@toc@l 2513; P8LE-NEXT: lvx v2, 0, r3 2514; P8LE-NEXT: blr 2515entry: 2516 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19> 2517} 2518 2519; Function Attrs: norecurse nounwind readonly 2520define <4 x i32> @fromDiffMemConsAui(i32* nocapture readonly %arr) { 2521; P9BE-LABEL: fromDiffMemConsAui: 2522; P9BE: # %bb.0: # %entry 2523; P9BE-NEXT: lxv v2, 0(r3) 2524; P9BE-NEXT: blr 2525; 2526; P9LE-LABEL: fromDiffMemConsAui: 2527; P9LE: # %bb.0: # %entry 2528; P9LE-NEXT: lxv v2, 0(r3) 2529; P9LE-NEXT: blr 2530; 2531; P8BE-LABEL: fromDiffMemConsAui: 2532; P8BE: # %bb.0: # %entry 2533; P8BE-NEXT: lxvw4x v2, 0, r3 2534; P8BE-NEXT: blr 2535; 2536; P8LE-LABEL: fromDiffMemConsAui: 2537; P8LE: # %bb.0: # %entry 2538; P8LE-NEXT: lxvd2x vs0, 0, r3 2539; P8LE-NEXT: xxswapd v2, vs0 2540; P8LE-NEXT: blr 2541entry: 2542 %0 = load i32, i32* %arr, align 4 2543 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2544 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 1 2545 %1 = load i32, i32* %arrayidx1, align 4 2546 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2547 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 2548 %2 = load i32, i32* %arrayidx3, align 4 2549 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2550 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 3 2551 %3 = load i32, i32* %arrayidx5, align 4 2552 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2553 ret <4 x i32> %vecinit6 2554} 2555 2556; Function Attrs: norecurse nounwind readonly 2557define <4 x i32> @fromDiffMemConsDui(i32* nocapture readonly %arr) { 2558; P9BE-LABEL: fromDiffMemConsDui: 2559; P9BE: # %bb.0: # %entry 2560; P9BE-NEXT: lxv v2, 0(r3) 2561; P9BE-NEXT: addis r3, r2, .LCPI41_0@toc@ha 2562; P9BE-NEXT: addi r3, r3, .LCPI41_0@toc@l 2563; P9BE-NEXT: lxvx v3, 0, r3 2564; P9BE-NEXT: vperm v2, v2, v2, v3 2565; P9BE-NEXT: blr 2566; 2567; P9LE-LABEL: fromDiffMemConsDui: 2568; P9LE: # %bb.0: # %entry 2569; P9LE-NEXT: lxvw4x v2, 0, r3 2570; P9LE-NEXT: blr 2571; 2572; P8BE-LABEL: fromDiffMemConsDui: 2573; P8BE: # %bb.0: # %entry 2574; P8BE-NEXT: addis r4, r2, .LCPI41_0@toc@ha 2575; P8BE-NEXT: lxvw4x v2, 0, r3 2576; P8BE-NEXT: addi r4, r4, .LCPI41_0@toc@l 2577; P8BE-NEXT: lxvw4x v3, 0, r4 2578; P8BE-NEXT: vperm v2, v2, v2, v3 2579; P8BE-NEXT: blr 2580; 2581; P8LE-LABEL: fromDiffMemConsDui: 2582; P8LE: # %bb.0: # %entry 2583; P8LE-NEXT: lxvd2x vs0, 0, r3 2584; P8LE-NEXT: addis r4, r2, .LCPI41_0@toc@ha 2585; P8LE-NEXT: addi r3, r4, .LCPI41_0@toc@l 2586; P8LE-NEXT: lvx v2, 0, r3 2587; P8LE-NEXT: xxswapd v3, vs0 2588; P8LE-NEXT: vperm v2, v3, v3, v2 2589; P8LE-NEXT: blr 2590entry: 2591 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3 2592 %0 = load i32, i32* %arrayidx, align 4 2593 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2594 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 2595 %1 = load i32, i32* %arrayidx1, align 4 2596 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2597 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 1 2598 %2 = load i32, i32* %arrayidx3, align 4 2599 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2600 %3 = load i32, i32* %arr, align 4 2601 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2602 ret <4 x i32> %vecinit6 2603} 2604 2605; Function Attrs: norecurse nounwind readonly 2606define <4 x i32> @fromDiffMemVarAui(i32* nocapture readonly %arr, i32 signext %elem) { 2607; P9BE-LABEL: fromDiffMemVarAui: 2608; P9BE: # %bb.0: # %entry 2609; P9BE-NEXT: sldi r4, r4, 2 2610; P9BE-NEXT: lxvx v2, r3, r4 2611; P9BE-NEXT: blr 2612; 2613; P9LE-LABEL: fromDiffMemVarAui: 2614; P9LE: # %bb.0: # %entry 2615; P9LE-NEXT: sldi r4, r4, 2 2616; P9LE-NEXT: lxvx v2, r3, r4 2617; P9LE-NEXT: blr 2618; 2619; P8BE-LABEL: fromDiffMemVarAui: 2620; P8BE: # %bb.0: # %entry 2621; P8BE-NEXT: sldi r4, r4, 2 2622; P8BE-NEXT: lxvw4x v2, r3, r4 2623; P8BE-NEXT: blr 2624; 2625; P8LE-LABEL: fromDiffMemVarAui: 2626; P8LE: # %bb.0: # %entry 2627; P8LE-NEXT: sldi r4, r4, 2 2628; P8LE-NEXT: lxvd2x vs0, r3, r4 2629; P8LE-NEXT: xxswapd v2, vs0 2630; P8LE-NEXT: blr 2631entry: 2632 %idxprom = sext i32 %elem to i64 2633 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2634 %0 = load i32, i32* %arrayidx, align 4 2635 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2636 %add = add nsw i32 %elem, 1 2637 %idxprom1 = sext i32 %add to i64 2638 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 2639 %1 = load i32, i32* %arrayidx2, align 4 2640 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2641 %add4 = add nsw i32 %elem, 2 2642 %idxprom5 = sext i32 %add4 to i64 2643 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 2644 %2 = load i32, i32* %arrayidx6, align 4 2645 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 2646 %add8 = add nsw i32 %elem, 3 2647 %idxprom9 = sext i32 %add8 to i64 2648 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 2649 %3 = load i32, i32* %arrayidx10, align 4 2650 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 2651 ret <4 x i32> %vecinit11 2652} 2653 2654; Function Attrs: norecurse nounwind readonly 2655define <4 x i32> @fromDiffMemVarDui(i32* nocapture readonly %arr, i32 signext %elem) { 2656; P9BE-LABEL: fromDiffMemVarDui: 2657; P9BE: # %bb.0: # %entry 2658; P9BE-NEXT: sldi r4, r4, 2 2659; P9BE-NEXT: add r3, r3, r4 2660; P9BE-NEXT: addi r3, r3, -12 2661; P9BE-NEXT: lxvx v2, 0, r3 2662; P9BE-NEXT: addis r3, r2, .LCPI43_0@toc@ha 2663; P9BE-NEXT: addi r3, r3, .LCPI43_0@toc@l 2664; P9BE-NEXT: lxvx v3, 0, r3 2665; P9BE-NEXT: vperm v2, v2, v2, v3 2666; P9BE-NEXT: blr 2667; 2668; P9LE-LABEL: fromDiffMemVarDui: 2669; P9LE: # %bb.0: # %entry 2670; P9LE-NEXT: sldi r4, r4, 2 2671; P9LE-NEXT: add r3, r3, r4 2672; P9LE-NEXT: addi r3, r3, -12 2673; P9LE-NEXT: lxvx v2, 0, r3 2674; P9LE-NEXT: addis r3, r2, .LCPI43_0@toc@ha 2675; P9LE-NEXT: addi r3, r3, .LCPI43_0@toc@l 2676; P9LE-NEXT: lxvx v3, 0, r3 2677; P9LE-NEXT: vperm v2, v2, v2, v3 2678; P9LE-NEXT: blr 2679; 2680; P8BE-LABEL: fromDiffMemVarDui: 2681; P8BE: # %bb.0: # %entry 2682; P8BE-NEXT: sldi r4, r4, 2 2683; P8BE-NEXT: addis r5, r2, .LCPI43_0@toc@ha 2684; P8BE-NEXT: add r3, r3, r4 2685; P8BE-NEXT: addi r4, r5, .LCPI43_0@toc@l 2686; P8BE-NEXT: addi r3, r3, -12 2687; P8BE-NEXT: lxvw4x v3, 0, r4 2688; P8BE-NEXT: lxvw4x v2, 0, r3 2689; P8BE-NEXT: vperm v2, v2, v2, v3 2690; P8BE-NEXT: blr 2691; 2692; P8LE-LABEL: fromDiffMemVarDui: 2693; P8LE: # %bb.0: # %entry 2694; P8LE-NEXT: sldi r4, r4, 2 2695; P8LE-NEXT: addis r5, r2, .LCPI43_0@toc@ha 2696; P8LE-NEXT: add r3, r3, r4 2697; P8LE-NEXT: addi r3, r3, -12 2698; P8LE-NEXT: lxvd2x vs0, 0, r3 2699; P8LE-NEXT: addi r3, r5, .LCPI43_0@toc@l 2700; P8LE-NEXT: lvx v3, 0, r3 2701; P8LE-NEXT: xxswapd v2, vs0 2702; P8LE-NEXT: vperm v2, v2, v2, v3 2703; P8LE-NEXT: blr 2704entry: 2705 %idxprom = sext i32 %elem to i64 2706 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2707 %0 = load i32, i32* %arrayidx, align 4 2708 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2709 %sub = add nsw i32 %elem, -1 2710 %idxprom1 = sext i32 %sub to i64 2711 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 2712 %1 = load i32, i32* %arrayidx2, align 4 2713 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2714 %sub4 = add nsw i32 %elem, -2 2715 %idxprom5 = sext i32 %sub4 to i64 2716 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 2717 %2 = load i32, i32* %arrayidx6, align 4 2718 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 2719 %sub8 = add nsw i32 %elem, -3 2720 %idxprom9 = sext i32 %sub8 to i64 2721 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 2722 %3 = load i32, i32* %arrayidx10, align 4 2723 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 2724 ret <4 x i32> %vecinit11 2725} 2726 2727; Function Attrs: norecurse nounwind readonly 2728define <4 x i32> @fromRandMemConsui(i32* nocapture readonly %arr) { 2729; P9BE-LABEL: fromRandMemConsui: 2730; P9BE: # %bb.0: # %entry 2731; P9BE-NEXT: lwz r4, 16(r3) 2732; P9BE-NEXT: lwz r5, 72(r3) 2733; P9BE-NEXT: lwz r6, 8(r3) 2734; P9BE-NEXT: lwz r3, 352(r3) 2735; P9BE-NEXT: rldimi r3, r6, 32, 0 2736; P9BE-NEXT: rldimi r5, r4, 32, 0 2737; P9BE-NEXT: mtvsrdd v2, r5, r3 2738; P9BE-NEXT: blr 2739; 2740; P9LE-LABEL: fromRandMemConsui: 2741; P9LE: # %bb.0: # %entry 2742; P9LE-NEXT: lwz r4, 16(r3) 2743; P9LE-NEXT: lwz r5, 72(r3) 2744; P9LE-NEXT: lwz r6, 8(r3) 2745; P9LE-NEXT: lwz r3, 352(r3) 2746; P9LE-NEXT: rldimi r4, r5, 32, 0 2747; P9LE-NEXT: rldimi r6, r3, 32, 0 2748; P9LE-NEXT: mtvsrdd v2, r6, r4 2749; P9LE-NEXT: blr 2750; 2751; P8BE-LABEL: fromRandMemConsui: 2752; P8BE: # %bb.0: # %entry 2753; P8BE-NEXT: lwz r4, 8(r3) 2754; P8BE-NEXT: lwz r5, 352(r3) 2755; P8BE-NEXT: lwz r6, 16(r3) 2756; P8BE-NEXT: lwz r3, 72(r3) 2757; P8BE-NEXT: rldimi r5, r4, 32, 0 2758; P8BE-NEXT: rldimi r3, r6, 32, 0 2759; P8BE-NEXT: mtvsrd f0, r5 2760; P8BE-NEXT: mtvsrd f1, r3 2761; P8BE-NEXT: xxmrghd v2, vs1, vs0 2762; P8BE-NEXT: blr 2763; 2764; P8LE-LABEL: fromRandMemConsui: 2765; P8LE: # %bb.0: # %entry 2766; P8LE-NEXT: lwz r4, 16(r3) 2767; P8LE-NEXT: lwz r5, 72(r3) 2768; P8LE-NEXT: lwz r6, 8(r3) 2769; P8LE-NEXT: lwz r3, 352(r3) 2770; P8LE-NEXT: rldimi r4, r5, 32, 0 2771; P8LE-NEXT: rldimi r6, r3, 32, 0 2772; P8LE-NEXT: mtvsrd f0, r4 2773; P8LE-NEXT: mtvsrd f1, r6 2774; P8LE-NEXT: xxmrghd v2, vs1, vs0 2775; P8LE-NEXT: blr 2776entry: 2777 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4 2778 %0 = load i32, i32* %arrayidx, align 4 2779 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2780 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18 2781 %1 = load i32, i32* %arrayidx1, align 4 2782 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2783 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 2784 %2 = load i32, i32* %arrayidx3, align 4 2785 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2786 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 88 2787 %3 = load i32, i32* %arrayidx5, align 4 2788 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2789 ret <4 x i32> %vecinit6 2790} 2791 2792; Function Attrs: norecurse nounwind readonly 2793define <4 x i32> @fromRandMemVarui(i32* nocapture readonly %arr, i32 signext %elem) { 2794; P9BE-LABEL: fromRandMemVarui: 2795; P9BE: # %bb.0: # %entry 2796; P9BE-NEXT: sldi r4, r4, 2 2797; P9BE-NEXT: add r3, r3, r4 2798; P9BE-NEXT: lwz r4, 16(r3) 2799; P9BE-NEXT: lwz r5, 4(r3) 2800; P9BE-NEXT: lwz r6, 8(r3) 2801; P9BE-NEXT: lwz r3, 32(r3) 2802; P9BE-NEXT: rldimi r3, r6, 32, 0 2803; P9BE-NEXT: rldimi r5, r4, 32, 0 2804; P9BE-NEXT: mtvsrdd v2, r5, r3 2805; P9BE-NEXT: blr 2806; 2807; P9LE-LABEL: fromRandMemVarui: 2808; P9LE: # %bb.0: # %entry 2809; P9LE-NEXT: sldi r4, r4, 2 2810; P9LE-NEXT: add r3, r3, r4 2811; P9LE-NEXT: lwz r4, 16(r3) 2812; P9LE-NEXT: lwz r5, 4(r3) 2813; P9LE-NEXT: lwz r6, 8(r3) 2814; P9LE-NEXT: lwz r3, 32(r3) 2815; P9LE-NEXT: rldimi r4, r5, 32, 0 2816; P9LE-NEXT: rldimi r6, r3, 32, 0 2817; P9LE-NEXT: mtvsrdd v2, r6, r4 2818; P9LE-NEXT: blr 2819; 2820; P8BE-LABEL: fromRandMemVarui: 2821; P8BE: # %bb.0: # %entry 2822; P8BE-NEXT: sldi r4, r4, 2 2823; P8BE-NEXT: add r3, r3, r4 2824; P8BE-NEXT: lwz r4, 8(r3) 2825; P8BE-NEXT: lwz r5, 32(r3) 2826; P8BE-NEXT: lwz r6, 16(r3) 2827; P8BE-NEXT: lwz r3, 4(r3) 2828; P8BE-NEXT: rldimi r5, r4, 32, 0 2829; P8BE-NEXT: rldimi r3, r6, 32, 0 2830; P8BE-NEXT: mtvsrd f0, r5 2831; P8BE-NEXT: mtvsrd f1, r3 2832; P8BE-NEXT: xxmrghd v2, vs1, vs0 2833; P8BE-NEXT: blr 2834; 2835; P8LE-LABEL: fromRandMemVarui: 2836; P8LE: # %bb.0: # %entry 2837; P8LE-NEXT: sldi r4, r4, 2 2838; P8LE-NEXT: add r3, r3, r4 2839; P8LE-NEXT: lwz r4, 16(r3) 2840; P8LE-NEXT: lwz r5, 4(r3) 2841; P8LE-NEXT: lwz r6, 8(r3) 2842; P8LE-NEXT: lwz r3, 32(r3) 2843; P8LE-NEXT: rldimi r4, r5, 32, 0 2844; P8LE-NEXT: rldimi r6, r3, 32, 0 2845; P8LE-NEXT: mtvsrd f0, r4 2846; P8LE-NEXT: mtvsrd f1, r6 2847; P8LE-NEXT: xxmrghd v2, vs1, vs0 2848; P8LE-NEXT: blr 2849entry: 2850 %add = add nsw i32 %elem, 4 2851 %idxprom = sext i32 %add to i64 2852 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2853 %0 = load i32, i32* %arrayidx, align 4 2854 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2855 %add1 = add nsw i32 %elem, 1 2856 %idxprom2 = sext i32 %add1 to i64 2857 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 %idxprom2 2858 %1 = load i32, i32* %arrayidx3, align 4 2859 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2860 %add5 = add nsw i32 %elem, 2 2861 %idxprom6 = sext i32 %add5 to i64 2862 %arrayidx7 = getelementptr inbounds i32, i32* %arr, i64 %idxprom6 2863 %2 = load i32, i32* %arrayidx7, align 4 2864 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2 2865 %add9 = add nsw i32 %elem, 8 2866 %idxprom10 = sext i32 %add9 to i64 2867 %arrayidx11 = getelementptr inbounds i32, i32* %arr, i64 %idxprom10 2868 %3 = load i32, i32* %arrayidx11, align 4 2869 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3 2870 ret <4 x i32> %vecinit12 2871} 2872 2873; Function Attrs: norecurse nounwind readnone 2874define <4 x i32> @spltRegValui(i32 zeroext %val) { 2875; P9BE-LABEL: spltRegValui: 2876; P9BE: # %bb.0: # %entry 2877; P9BE-NEXT: mtvsrws v2, r3 2878; P9BE-NEXT: blr 2879; 2880; P9LE-LABEL: spltRegValui: 2881; P9LE: # %bb.0: # %entry 2882; P9LE-NEXT: mtvsrws v2, r3 2883; P9LE-NEXT: blr 2884; 2885; P8BE-LABEL: spltRegValui: 2886; P8BE: # %bb.0: # %entry 2887; P8BE-NEXT: mtvsrwz f0, r3 2888; P8BE-NEXT: xxspltw v2, vs0, 1 2889; P8BE-NEXT: blr 2890; 2891; P8LE-LABEL: spltRegValui: 2892; P8LE: # %bb.0: # %entry 2893; P8LE-NEXT: mtvsrwz f0, r3 2894; P8LE-NEXT: xxspltw v2, vs0, 1 2895; P8LE-NEXT: blr 2896entry: 2897 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0 2898 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2899 ret <4 x i32> %splat.splat 2900} 2901 2902; Function Attrs: norecurse nounwind readonly 2903define <4 x i32> @spltMemValui(i32* nocapture readonly %ptr) { 2904; P9BE-LABEL: spltMemValui: 2905; P9BE: # %bb.0: # %entry 2906; P9BE-NEXT: lfiwzx f0, 0, r3 2907; P9BE-NEXT: xxsldwi vs0, f0, f0, 1 2908; P9BE-NEXT: xxspltw v2, vs0, 0 2909; P9BE-NEXT: blr 2910; 2911; P9LE-LABEL: spltMemValui: 2912; P9LE: # %bb.0: # %entry 2913; P9LE-NEXT: lfiwzx f0, 0, r3 2914; P9LE-NEXT: xxpermdi vs0, f0, f0, 2 2915; P9LE-NEXT: xxspltw v2, vs0, 3 2916; P9LE-NEXT: blr 2917; 2918; P8BE-LABEL: spltMemValui: 2919; P8BE: # %bb.0: # %entry 2920; P8BE-NEXT: lfiwzx f0, 0, r3 2921; P8BE-NEXT: xxsldwi vs0, f0, f0, 1 2922; P8BE-NEXT: xxspltw v2, vs0, 0 2923; P8BE-NEXT: blr 2924; 2925; P8LE-LABEL: spltMemValui: 2926; P8LE: # %bb.0: # %entry 2927; P8LE-NEXT: lfiwzx f0, 0, r3 2928; P8LE-NEXT: xxpermdi vs0, f0, f0, 2 2929; P8LE-NEXT: xxspltw v2, vs0, 3 2930; P8LE-NEXT: blr 2931entry: 2932 %0 = load i32, i32* %ptr, align 4 2933 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 2934 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2935 ret <4 x i32> %splat.splat 2936} 2937 2938; Function Attrs: norecurse nounwind readnone 2939define <4 x i32> @spltCnstConvftoui() { 2940; P9BE-LABEL: spltCnstConvftoui: 2941; P9BE: # %bb.0: # %entry 2942; P9BE-NEXT: vspltisw v2, 4 2943; P9BE-NEXT: blr 2944; 2945; P9LE-LABEL: spltCnstConvftoui: 2946; P9LE: # %bb.0: # %entry 2947; P9LE-NEXT: vspltisw v2, 4 2948; P9LE-NEXT: blr 2949; 2950; P8BE-LABEL: spltCnstConvftoui: 2951; P8BE: # %bb.0: # %entry 2952; P8BE-NEXT: vspltisw v2, 4 2953; P8BE-NEXT: blr 2954; 2955; P8LE-LABEL: spltCnstConvftoui: 2956; P8LE: # %bb.0: # %entry 2957; P8LE-NEXT: vspltisw v2, 4 2958; P8LE-NEXT: blr 2959entry: 2960 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 2961} 2962 2963; Function Attrs: norecurse nounwind readnone 2964define <4 x i32> @fromRegsConvftoui(float %a, float %b, float %c, float %d) { 2965; P9BE-LABEL: fromRegsConvftoui: 2966; P9BE: # %bb.0: # %entry 2967; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2968; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 2969; P9BE-NEXT: xxmrghd vs0, vs2, vs4 2970; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2971; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2972; P9BE-NEXT: xvcvdpuxws v2, vs0 2973; P9BE-NEXT: xxmrghd vs0, vs1, vs3 2974; P9BE-NEXT: xvcvdpuxws v3, vs0 2975; P9BE-NEXT: vmrgew v2, v3, v2 2976; P9BE-NEXT: blr 2977; 2978; P9LE-LABEL: fromRegsConvftoui: 2979; P9LE: # %bb.0: # %entry 2980; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2981; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2982; P9LE-NEXT: xxmrghd vs0, vs3, vs1 2983; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2984; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 2985; P9LE-NEXT: xvcvdpuxws v2, vs0 2986; P9LE-NEXT: xxmrghd vs0, vs4, vs2 2987; P9LE-NEXT: xvcvdpuxws v3, vs0 2988; P9LE-NEXT: vmrgew v2, v3, v2 2989; P9LE-NEXT: blr 2990; 2991; P8BE-LABEL: fromRegsConvftoui: 2992; P8BE: # %bb.0: # %entry 2993; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2994; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2995; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2996; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 2997; P8BE-NEXT: xxmrghd vs0, vs2, vs4 2998; P8BE-NEXT: xxmrghd vs1, vs1, vs3 2999; P8BE-NEXT: xvcvdpuxws v2, vs0 3000; P8BE-NEXT: xvcvdpuxws v3, vs1 3001; P8BE-NEXT: vmrgew v2, v3, v2 3002; P8BE-NEXT: blr 3003; 3004; P8LE-LABEL: fromRegsConvftoui: 3005; P8LE: # %bb.0: # %entry 3006; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3007; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3008; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3009; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3010; P8LE-NEXT: xxmrghd vs0, vs3, vs1 3011; P8LE-NEXT: xxmrghd vs1, vs4, vs2 3012; P8LE-NEXT: xvcvdpuxws v2, vs0 3013; P8LE-NEXT: xvcvdpuxws v3, vs1 3014; P8LE-NEXT: vmrgew v2, v3, v2 3015; P8LE-NEXT: blr 3016entry: 3017 %conv = fptoui float %a to i32 3018 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3019 %conv1 = fptoui float %b to i32 3020 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 3021 %conv3 = fptoui float %c to i32 3022 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 3023 %conv5 = fptoui float %d to i32 3024 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 3025 ret <4 x i32> %vecinit6 3026} 3027 3028; Function Attrs: norecurse nounwind readnone 3029define <4 x i32> @fromDiffConstsConvftoui() { 3030; P9BE-LABEL: fromDiffConstsConvftoui: 3031; P9BE: # %bb.0: # %entry 3032; P9BE-NEXT: addis r3, r2, .LCPI50_0@toc@ha 3033; P9BE-NEXT: addi r3, r3, .LCPI50_0@toc@l 3034; P9BE-NEXT: lxvx v2, 0, r3 3035; P9BE-NEXT: blr 3036; 3037; P9LE-LABEL: fromDiffConstsConvftoui: 3038; P9LE: # %bb.0: # %entry 3039; P9LE-NEXT: addis r3, r2, .LCPI50_0@toc@ha 3040; P9LE-NEXT: addi r3, r3, .LCPI50_0@toc@l 3041; P9LE-NEXT: lxvx v2, 0, r3 3042; P9LE-NEXT: blr 3043; 3044; P8BE-LABEL: fromDiffConstsConvftoui: 3045; P8BE: # %bb.0: # %entry 3046; P8BE-NEXT: addis r3, r2, .LCPI50_0@toc@ha 3047; P8BE-NEXT: addi r3, r3, .LCPI50_0@toc@l 3048; P8BE-NEXT: lxvw4x v2, 0, r3 3049; P8BE-NEXT: blr 3050; 3051; P8LE-LABEL: fromDiffConstsConvftoui: 3052; P8LE: # %bb.0: # %entry 3053; P8LE-NEXT: addis r3, r2, .LCPI50_0@toc@ha 3054; P8LE-NEXT: addi r3, r3, .LCPI50_0@toc@l 3055; P8LE-NEXT: lvx v2, 0, r3 3056; P8LE-NEXT: blr 3057entry: 3058 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 3059} 3060 3061; Function Attrs: norecurse nounwind readonly 3062define <4 x i32> @fromDiffMemConsAConvftoui(float* nocapture readonly %ptr) { 3063; P9BE-LABEL: fromDiffMemConsAConvftoui: 3064; P9BE: # %bb.0: # %entry 3065; P9BE-NEXT: lxv vs0, 0(r3) 3066; P9BE-NEXT: xvcvspuxws v2, vs0 3067; P9BE-NEXT: blr 3068; 3069; P9LE-LABEL: fromDiffMemConsAConvftoui: 3070; P9LE: # %bb.0: # %entry 3071; P9LE-NEXT: lxv vs0, 0(r3) 3072; P9LE-NEXT: xvcvspuxws v2, vs0 3073; P9LE-NEXT: blr 3074; 3075; P8BE-LABEL: fromDiffMemConsAConvftoui: 3076; P8BE: # %bb.0: # %entry 3077; P8BE-NEXT: lxvw4x vs0, 0, r3 3078; P8BE-NEXT: xvcvspuxws v2, vs0 3079; P8BE-NEXT: blr 3080; 3081; P8LE-LABEL: fromDiffMemConsAConvftoui: 3082; P8LE: # %bb.0: # %entry 3083; P8LE-NEXT: lxvd2x vs0, 0, r3 3084; P8LE-NEXT: xxswapd v2, vs0 3085; P8LE-NEXT: xvcvspuxws v2, v2 3086; P8LE-NEXT: blr 3087entry: 3088 %0 = bitcast float* %ptr to <4 x float>* 3089 %1 = load <4 x float>, <4 x float>* %0, align 4 3090 %2 = fptoui <4 x float> %1 to <4 x i32> 3091 ret <4 x i32> %2 3092} 3093 3094; Function Attrs: norecurse nounwind readonly 3095define <4 x i32> @fromDiffMemConsDConvftoui(float* nocapture readonly %ptr) { 3096; P9BE-LABEL: fromDiffMemConsDConvftoui: 3097; P9BE: # %bb.0: # %entry 3098; P9BE-NEXT: lxv v2, 0(r3) 3099; P9BE-NEXT: addis r3, r2, .LCPI52_0@toc@ha 3100; P9BE-NEXT: addi r3, r3, .LCPI52_0@toc@l 3101; P9BE-NEXT: lxvx v3, 0, r3 3102; P9BE-NEXT: vperm v2, v2, v2, v3 3103; P9BE-NEXT: xvcvspuxws v2, v2 3104; P9BE-NEXT: blr 3105; 3106; P9LE-LABEL: fromDiffMemConsDConvftoui: 3107; P9LE: # %bb.0: # %entry 3108; P9LE-NEXT: lxv v2, 0(r3) 3109; P9LE-NEXT: addis r3, r2, .LCPI52_0@toc@ha 3110; P9LE-NEXT: addi r3, r3, .LCPI52_0@toc@l 3111; P9LE-NEXT: lxvx v3, 0, r3 3112; P9LE-NEXT: vperm v2, v2, v2, v3 3113; P9LE-NEXT: xvcvspuxws v2, v2 3114; P9LE-NEXT: blr 3115; 3116; P8BE-LABEL: fromDiffMemConsDConvftoui: 3117; P8BE: # %bb.0: # %entry 3118; P8BE-NEXT: addis r4, r2, .LCPI52_0@toc@ha 3119; P8BE-NEXT: lxvw4x v2, 0, r3 3120; P8BE-NEXT: addi r4, r4, .LCPI52_0@toc@l 3121; P8BE-NEXT: lxvw4x v3, 0, r4 3122; P8BE-NEXT: vperm v2, v2, v2, v3 3123; P8BE-NEXT: xvcvspuxws v2, v2 3124; P8BE-NEXT: blr 3125; 3126; P8LE-LABEL: fromDiffMemConsDConvftoui: 3127; P8LE: # %bb.0: # %entry 3128; P8LE-NEXT: lxvd2x vs0, 0, r3 3129; P8LE-NEXT: addis r4, r2, .LCPI52_0@toc@ha 3130; P8LE-NEXT: addi r3, r4, .LCPI52_0@toc@l 3131; P8LE-NEXT: lvx v2, 0, r3 3132; P8LE-NEXT: xxswapd v3, vs0 3133; P8LE-NEXT: vperm v2, v3, v3, v2 3134; P8LE-NEXT: xvcvspuxws v2, v2 3135; P8LE-NEXT: blr 3136entry: 3137 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 3138 %0 = load float, float* %arrayidx, align 4 3139 %conv = fptoui float %0 to i32 3140 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3141 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 3142 %1 = load float, float* %arrayidx1, align 4 3143 %conv2 = fptoui float %1 to i32 3144 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 3145 %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1 3146 %2 = load float, float* %arrayidx4, align 4 3147 %conv5 = fptoui float %2 to i32 3148 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 3149 %3 = load float, float* %ptr, align 4 3150 %conv8 = fptoui float %3 to i32 3151 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 3152 ret <4 x i32> %vecinit9 3153} 3154 3155; Function Attrs: norecurse nounwind readonly 3156define <4 x i32> @fromDiffMemVarAConvftoui(float* nocapture readonly %arr, i32 signext %elem) { 3157; P9BE-LABEL: fromDiffMemVarAConvftoui: 3158; P9BE: # %bb.0: # %entry 3159; P9BE-NEXT: sldi r4, r4, 2 3160; P9BE-NEXT: lfsux f0, r3, r4 3161; P9BE-NEXT: lfs f1, 12(r3) 3162; P9BE-NEXT: lfs f2, 4(r3) 3163; P9BE-NEXT: xxmrghd vs1, vs2, vs1 3164; P9BE-NEXT: xvcvdpsp v2, vs1 3165; P9BE-NEXT: lfs f1, 8(r3) 3166; P9BE-NEXT: xxmrghd vs0, vs0, vs1 3167; P9BE-NEXT: xvcvdpsp v3, vs0 3168; P9BE-NEXT: vmrgew v2, v3, v2 3169; P9BE-NEXT: xvcvspuxws v2, v2 3170; P9BE-NEXT: blr 3171; 3172; P9LE-LABEL: fromDiffMemVarAConvftoui: 3173; P9LE: # %bb.0: # %entry 3174; P9LE-NEXT: sldi r4, r4, 2 3175; P9LE-NEXT: lfsux f0, r3, r4 3176; P9LE-NEXT: lfs f1, 8(r3) 3177; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3178; P9LE-NEXT: lfs f1, 12(r3) 3179; P9LE-NEXT: xvcvdpsp v2, vs0 3180; P9LE-NEXT: lfs f0, 4(r3) 3181; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3182; P9LE-NEXT: xvcvdpsp v3, vs0 3183; P9LE-NEXT: vmrgew v2, v3, v2 3184; P9LE-NEXT: xvcvspuxws v2, v2 3185; P9LE-NEXT: blr 3186; 3187; P8BE-LABEL: fromDiffMemVarAConvftoui: 3188; P8BE: # %bb.0: # %entry 3189; P8BE-NEXT: sldi r4, r4, 2 3190; P8BE-NEXT: lfsux f0, r3, r4 3191; P8BE-NEXT: lfs f1, 12(r3) 3192; P8BE-NEXT: lfs f2, 4(r3) 3193; P8BE-NEXT: lfs f3, 8(r3) 3194; P8BE-NEXT: xxmrghd vs1, vs2, vs1 3195; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3196; P8BE-NEXT: xvcvdpsp v2, vs1 3197; P8BE-NEXT: xvcvdpsp v3, vs0 3198; P8BE-NEXT: vmrgew v2, v3, v2 3199; P8BE-NEXT: xvcvspuxws v2, v2 3200; P8BE-NEXT: blr 3201; 3202; P8LE-LABEL: fromDiffMemVarAConvftoui: 3203; P8LE: # %bb.0: # %entry 3204; P8LE-NEXT: sldi r4, r4, 2 3205; P8LE-NEXT: lfsux f0, r3, r4 3206; P8LE-NEXT: lfs f1, 8(r3) 3207; P8LE-NEXT: lfs f2, 4(r3) 3208; P8LE-NEXT: lfs f3, 12(r3) 3209; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3210; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3211; P8LE-NEXT: xvcvdpsp v2, vs0 3212; P8LE-NEXT: xvcvdpsp v3, vs1 3213; P8LE-NEXT: vmrgew v2, v3, v2 3214; P8LE-NEXT: xvcvspuxws v2, v2 3215; P8LE-NEXT: blr 3216entry: 3217 %idxprom = sext i32 %elem to i64 3218 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 3219 %0 = load float, float* %arrayidx, align 4 3220 %conv = fptoui float %0 to i32 3221 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3222 %add = add nsw i32 %elem, 1 3223 %idxprom1 = sext i32 %add to i64 3224 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 3225 %1 = load float, float* %arrayidx2, align 4 3226 %conv3 = fptoui float %1 to i32 3227 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3228 %add5 = add nsw i32 %elem, 2 3229 %idxprom6 = sext i32 %add5 to i64 3230 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 3231 %2 = load float, float* %arrayidx7, align 4 3232 %conv8 = fptoui float %2 to i32 3233 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3234 %add10 = add nsw i32 %elem, 3 3235 %idxprom11 = sext i32 %add10 to i64 3236 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 3237 %3 = load float, float* %arrayidx12, align 4 3238 %conv13 = fptoui float %3 to i32 3239 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3240 ret <4 x i32> %vecinit14 3241; FIXME: implement finding consecutive loads with pre-inc 3242} 3243 3244; Function Attrs: norecurse nounwind readonly 3245define <4 x i32> @fromDiffMemVarDConvftoui(float* nocapture readonly %arr, i32 signext %elem) { 3246; P9BE-LABEL: fromDiffMemVarDConvftoui: 3247; P9BE: # %bb.0: # %entry 3248; P9BE-NEXT: sldi r4, r4, 2 3249; P9BE-NEXT: lfsux f0, r3, r4 3250; P9BE-NEXT: lfs f1, -12(r3) 3251; P9BE-NEXT: lfs f2, -4(r3) 3252; P9BE-NEXT: xxmrghd vs1, vs2, vs1 3253; P9BE-NEXT: xvcvdpsp v2, vs1 3254; P9BE-NEXT: lfs f1, -8(r3) 3255; P9BE-NEXT: xxmrghd vs0, vs0, vs1 3256; P9BE-NEXT: xvcvdpsp v3, vs0 3257; P9BE-NEXT: vmrgew v2, v3, v2 3258; P9BE-NEXT: xvcvspuxws v2, v2 3259; P9BE-NEXT: blr 3260; 3261; P9LE-LABEL: fromDiffMemVarDConvftoui: 3262; P9LE: # %bb.0: # %entry 3263; P9LE-NEXT: sldi r4, r4, 2 3264; P9LE-NEXT: lfsux f0, r3, r4 3265; P9LE-NEXT: lfs f1, -8(r3) 3266; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3267; P9LE-NEXT: lfs f1, -12(r3) 3268; P9LE-NEXT: xvcvdpsp v2, vs0 3269; P9LE-NEXT: lfs f0, -4(r3) 3270; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3271; P9LE-NEXT: xvcvdpsp v3, vs0 3272; P9LE-NEXT: vmrgew v2, v3, v2 3273; P9LE-NEXT: xvcvspuxws v2, v2 3274; P9LE-NEXT: blr 3275; 3276; P8BE-LABEL: fromDiffMemVarDConvftoui: 3277; P8BE: # %bb.0: # %entry 3278; P8BE-NEXT: sldi r4, r4, 2 3279; P8BE-NEXT: lfsux f0, r3, r4 3280; P8BE-NEXT: lfs f1, -12(r3) 3281; P8BE-NEXT: lfs f2, -4(r3) 3282; P8BE-NEXT: lfs f3, -8(r3) 3283; P8BE-NEXT: xxmrghd vs1, vs2, vs1 3284; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3285; P8BE-NEXT: xvcvdpsp v2, vs1 3286; P8BE-NEXT: xvcvdpsp v3, vs0 3287; P8BE-NEXT: vmrgew v2, v3, v2 3288; P8BE-NEXT: xvcvspuxws v2, v2 3289; P8BE-NEXT: blr 3290; 3291; P8LE-LABEL: fromDiffMemVarDConvftoui: 3292; P8LE: # %bb.0: # %entry 3293; P8LE-NEXT: sldi r4, r4, 2 3294; P8LE-NEXT: lfsux f0, r3, r4 3295; P8LE-NEXT: lfs f1, -8(r3) 3296; P8LE-NEXT: lfs f2, -4(r3) 3297; P8LE-NEXT: lfs f3, -12(r3) 3298; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3299; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3300; P8LE-NEXT: xvcvdpsp v2, vs0 3301; P8LE-NEXT: xvcvdpsp v3, vs1 3302; P8LE-NEXT: vmrgew v2, v3, v2 3303; P8LE-NEXT: xvcvspuxws v2, v2 3304; P8LE-NEXT: blr 3305entry: 3306 %idxprom = sext i32 %elem to i64 3307 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 3308 %0 = load float, float* %arrayidx, align 4 3309 %conv = fptoui float %0 to i32 3310 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3311 %sub = add nsw i32 %elem, -1 3312 %idxprom1 = sext i32 %sub to i64 3313 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 3314 %1 = load float, float* %arrayidx2, align 4 3315 %conv3 = fptoui float %1 to i32 3316 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3317 %sub5 = add nsw i32 %elem, -2 3318 %idxprom6 = sext i32 %sub5 to i64 3319 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 3320 %2 = load float, float* %arrayidx7, align 4 3321 %conv8 = fptoui float %2 to i32 3322 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3323 %sub10 = add nsw i32 %elem, -3 3324 %idxprom11 = sext i32 %sub10 to i64 3325 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 3326 %3 = load float, float* %arrayidx12, align 4 3327 %conv13 = fptoui float %3 to i32 3328 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3329 ret <4 x i32> %vecinit14 3330; FIXME: implement finding consecutive loads with pre-inc 3331} 3332 3333; Function Attrs: norecurse nounwind readnone 3334define <4 x i32> @spltRegValConvftoui(float %val) { 3335; P9BE-LABEL: spltRegValConvftoui: 3336; P9BE: # %bb.0: # %entry 3337; P9BE-NEXT: xscvdpuxws f0, f1 3338; P9BE-NEXT: xxspltw v2, vs0, 1 3339; P9BE-NEXT: blr 3340; 3341; P9LE-LABEL: spltRegValConvftoui: 3342; P9LE: # %bb.0: # %entry 3343; P9LE-NEXT: xscvdpuxws f0, f1 3344; P9LE-NEXT: xxspltw v2, vs0, 1 3345; P9LE-NEXT: blr 3346; 3347; P8BE-LABEL: spltRegValConvftoui: 3348; P8BE: # %bb.0: # %entry 3349; P8BE-NEXT: xscvdpuxws f0, f1 3350; P8BE-NEXT: xxspltw v2, vs0, 1 3351; P8BE-NEXT: blr 3352; 3353; P8LE-LABEL: spltRegValConvftoui: 3354; P8LE: # %bb.0: # %entry 3355; P8LE-NEXT: xscvdpuxws f0, f1 3356; P8LE-NEXT: xxspltw v2, vs0, 1 3357; P8LE-NEXT: blr 3358entry: 3359 %conv = fptoui float %val to i32 3360 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3361 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3362 ret <4 x i32> %splat.splat 3363} 3364 3365; Function Attrs: norecurse nounwind readonly 3366define <4 x i32> @spltMemValConvftoui(float* nocapture readonly %ptr) { 3367; P9BE-LABEL: spltMemValConvftoui: 3368; P9BE: # %bb.0: # %entry 3369; P9BE-NEXT: lxvwsx vs0, 0, r3 3370; P9BE-NEXT: xvcvspuxws v2, vs0 3371; P9BE-NEXT: blr 3372; 3373; P9LE-LABEL: spltMemValConvftoui: 3374; P9LE: # %bb.0: # %entry 3375; P9LE-NEXT: lxvwsx vs0, 0, r3 3376; P9LE-NEXT: xvcvspuxws v2, vs0 3377; P9LE-NEXT: blr 3378; 3379; P8BE-LABEL: spltMemValConvftoui: 3380; P8BE: # %bb.0: # %entry 3381; P8BE-NEXT: lfsx f0, 0, r3 3382; P8BE-NEXT: xscvdpuxws f0, f0 3383; P8BE-NEXT: xxspltw v2, vs0, 1 3384; P8BE-NEXT: blr 3385; 3386; P8LE-LABEL: spltMemValConvftoui: 3387; P8LE: # %bb.0: # %entry 3388; P8LE-NEXT: lfsx f0, 0, r3 3389; P8LE-NEXT: xscvdpuxws f0, f0 3390; P8LE-NEXT: xxspltw v2, vs0, 1 3391; P8LE-NEXT: blr 3392entry: 3393 %0 = load float, float* %ptr, align 4 3394 %conv = fptoui float %0 to i32 3395 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3396 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3397 ret <4 x i32> %splat.splat 3398} 3399 3400; Function Attrs: norecurse nounwind readnone 3401define <4 x i32> @spltCnstConvdtoui() { 3402; P9BE-LABEL: spltCnstConvdtoui: 3403; P9BE: # %bb.0: # %entry 3404; P9BE-NEXT: vspltisw v2, 4 3405; P9BE-NEXT: blr 3406; 3407; P9LE-LABEL: spltCnstConvdtoui: 3408; P9LE: # %bb.0: # %entry 3409; P9LE-NEXT: vspltisw v2, 4 3410; P9LE-NEXT: blr 3411; 3412; P8BE-LABEL: spltCnstConvdtoui: 3413; P8BE: # %bb.0: # %entry 3414; P8BE-NEXT: vspltisw v2, 4 3415; P8BE-NEXT: blr 3416; 3417; P8LE-LABEL: spltCnstConvdtoui: 3418; P8LE: # %bb.0: # %entry 3419; P8LE-NEXT: vspltisw v2, 4 3420; P8LE-NEXT: blr 3421entry: 3422 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 3423} 3424 3425; Function Attrs: norecurse nounwind readnone 3426define <4 x i32> @fromRegsConvdtoui(double %a, double %b, double %c, double %d) { 3427; P9BE-LABEL: fromRegsConvdtoui: 3428; P9BE: # %bb.0: # %entry 3429; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3430; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3431; P9BE-NEXT: xxmrghd vs0, vs2, vs4 3432; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3433; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3434; P9BE-NEXT: xvcvdpuxws v2, vs0 3435; P9BE-NEXT: xxmrghd vs0, vs1, vs3 3436; P9BE-NEXT: xvcvdpuxws v3, vs0 3437; P9BE-NEXT: vmrgew v2, v3, v2 3438; P9BE-NEXT: blr 3439; 3440; P9LE-LABEL: fromRegsConvdtoui: 3441; P9LE: # %bb.0: # %entry 3442; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3443; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3444; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3445; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3446; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3447; P9LE-NEXT: xvcvdpuxws v2, vs0 3448; P9LE-NEXT: xxmrghd vs0, vs4, vs2 3449; P9LE-NEXT: xvcvdpuxws v3, vs0 3450; P9LE-NEXT: vmrgew v2, v3, v2 3451; P9LE-NEXT: blr 3452; 3453; P8BE-LABEL: fromRegsConvdtoui: 3454; P8BE: # %bb.0: # %entry 3455; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3456; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3457; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3458; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3459; P8BE-NEXT: xxmrghd vs0, vs2, vs4 3460; P8BE-NEXT: xxmrghd vs1, vs1, vs3 3461; P8BE-NEXT: xvcvdpuxws v2, vs0 3462; P8BE-NEXT: xvcvdpuxws v3, vs1 3463; P8BE-NEXT: vmrgew v2, v3, v2 3464; P8BE-NEXT: blr 3465; 3466; P8LE-LABEL: fromRegsConvdtoui: 3467; P8LE: # %bb.0: # %entry 3468; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3469; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3470; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3471; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3472; P8LE-NEXT: xxmrghd vs0, vs3, vs1 3473; P8LE-NEXT: xxmrghd vs1, vs4, vs2 3474; P8LE-NEXT: xvcvdpuxws v2, vs0 3475; P8LE-NEXT: xvcvdpuxws v3, vs1 3476; P8LE-NEXT: vmrgew v2, v3, v2 3477; P8LE-NEXT: blr 3478entry: 3479 %conv = fptoui double %a to i32 3480 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3481 %conv1 = fptoui double %b to i32 3482 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 3483 %conv3 = fptoui double %c to i32 3484 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 3485 %conv5 = fptoui double %d to i32 3486 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 3487 ret <4 x i32> %vecinit6 3488} 3489 3490; Function Attrs: norecurse nounwind readnone 3491define <4 x i32> @fromDiffConstsConvdtoui() { 3492; P9BE-LABEL: fromDiffConstsConvdtoui: 3493; P9BE: # %bb.0: # %entry 3494; P9BE-NEXT: addis r3, r2, .LCPI59_0@toc@ha 3495; P9BE-NEXT: addi r3, r3, .LCPI59_0@toc@l 3496; P9BE-NEXT: lxvx v2, 0, r3 3497; P9BE-NEXT: blr 3498; 3499; P9LE-LABEL: fromDiffConstsConvdtoui: 3500; P9LE: # %bb.0: # %entry 3501; P9LE-NEXT: addis r3, r2, .LCPI59_0@toc@ha 3502; P9LE-NEXT: addi r3, r3, .LCPI59_0@toc@l 3503; P9LE-NEXT: lxvx v2, 0, r3 3504; P9LE-NEXT: blr 3505; 3506; P8BE-LABEL: fromDiffConstsConvdtoui: 3507; P8BE: # %bb.0: # %entry 3508; P8BE-NEXT: addis r3, r2, .LCPI59_0@toc@ha 3509; P8BE-NEXT: addi r3, r3, .LCPI59_0@toc@l 3510; P8BE-NEXT: lxvw4x v2, 0, r3 3511; P8BE-NEXT: blr 3512; 3513; P8LE-LABEL: fromDiffConstsConvdtoui: 3514; P8LE: # %bb.0: # %entry 3515; P8LE-NEXT: addis r3, r2, .LCPI59_0@toc@ha 3516; P8LE-NEXT: addi r3, r3, .LCPI59_0@toc@l 3517; P8LE-NEXT: lvx v2, 0, r3 3518; P8LE-NEXT: blr 3519entry: 3520 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 3521} 3522 3523; Function Attrs: norecurse nounwind readonly 3524define <4 x i32> @fromDiffMemConsAConvdtoui(double* nocapture readonly %ptr) { 3525; P9BE-LABEL: fromDiffMemConsAConvdtoui: 3526; P9BE: # %bb.0: # %entry 3527; P9BE-NEXT: lxv vs0, 0(r3) 3528; P9BE-NEXT: lxv vs1, 16(r3) 3529; P9BE-NEXT: xxmrgld vs2, vs0, vs1 3530; P9BE-NEXT: xxmrghd vs0, vs0, vs1 3531; P9BE-NEXT: xvcvdpuxws v2, vs2 3532; P9BE-NEXT: xvcvdpuxws v3, vs0 3533; P9BE-NEXT: vmrgew v2, v3, v2 3534; P9BE-NEXT: blr 3535; 3536; P9LE-LABEL: fromDiffMemConsAConvdtoui: 3537; P9LE: # %bb.0: # %entry 3538; P9LE-NEXT: lxv vs0, 0(r3) 3539; P9LE-NEXT: lxv vs1, 16(r3) 3540; P9LE-NEXT: xxmrgld vs2, vs1, vs0 3541; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3542; P9LE-NEXT: xvcvdpuxws v2, vs2 3543; P9LE-NEXT: xvcvdpuxws v3, vs0 3544; P9LE-NEXT: vmrgew v2, v3, v2 3545; P9LE-NEXT: blr 3546; 3547; P8BE-LABEL: fromDiffMemConsAConvdtoui: 3548; P8BE: # %bb.0: # %entry 3549; P8BE-NEXT: li r4, 16 3550; P8BE-NEXT: lxvd2x vs0, 0, r3 3551; P8BE-NEXT: lxvd2x vs1, r3, r4 3552; P8BE-NEXT: xxmrgld vs2, vs0, vs1 3553; P8BE-NEXT: xxmrghd vs0, vs0, vs1 3554; P8BE-NEXT: xvcvdpuxws v2, vs2 3555; P8BE-NEXT: xvcvdpuxws v3, vs0 3556; P8BE-NEXT: vmrgew v2, v3, v2 3557; P8BE-NEXT: blr 3558; 3559; P8LE-LABEL: fromDiffMemConsAConvdtoui: 3560; P8LE: # %bb.0: # %entry 3561; P8LE-NEXT: li r4, 16 3562; P8LE-NEXT: lxvd2x vs0, 0, r3 3563; P8LE-NEXT: lxvd2x vs1, r3, r4 3564; P8LE-NEXT: xxswapd vs0, vs0 3565; P8LE-NEXT: xxswapd vs1, vs1 3566; P8LE-NEXT: xxmrgld vs2, vs1, vs0 3567; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3568; P8LE-NEXT: xvcvdpuxws v2, vs2 3569; P8LE-NEXT: xvcvdpuxws v3, vs0 3570; P8LE-NEXT: vmrgew v2, v3, v2 3571; P8LE-NEXT: blr 3572entry: 3573 %0 = bitcast double* %ptr to <2 x double>* 3574 %1 = load <2 x double>, <2 x double>* %0, align 8 3575 %2 = fptoui <2 x double> %1 to <2 x i32> 3576 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 2 3577 %3 = bitcast double* %arrayidx4 to <2 x double>* 3578 %4 = load <2 x double>, <2 x double>* %3, align 8 3579 %5 = fptoui <2 x double> %4 to <2 x i32> 3580 %vecinit9 = shufflevector <2 x i32> %2, <2 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 3581 ret <4 x i32> %vecinit9 3582} 3583 3584; Function Attrs: norecurse nounwind readonly 3585define <4 x i32> @fromDiffMemConsDConvdtoui(double* nocapture readonly %ptr) { 3586; P9BE-LABEL: fromDiffMemConsDConvdtoui: 3587; P9BE: # %bb.0: # %entry 3588; P9BE-NEXT: lfd f0, 24(r3) 3589; P9BE-NEXT: lfd f1, 16(r3) 3590; P9BE-NEXT: lfd f2, 8(r3) 3591; P9BE-NEXT: xxmrghd vs0, vs0, vs2 3592; P9BE-NEXT: lfd f3, 0(r3) 3593; P9BE-NEXT: xxmrghd vs1, vs1, vs3 3594; P9BE-NEXT: xvcvdpuxws v2, vs1 3595; P9BE-NEXT: xvcvdpuxws v3, vs0 3596; P9BE-NEXT: vmrgew v2, v3, v2 3597; P9BE-NEXT: blr 3598; 3599; P9LE-LABEL: fromDiffMemConsDConvdtoui: 3600; P9LE: # %bb.0: # %entry 3601; P9LE-NEXT: lfd f0, 24(r3) 3602; P9LE-NEXT: lfd f2, 8(r3) 3603; P9LE-NEXT: xxmrghd vs0, vs2, vs0 3604; P9LE-NEXT: lfd f1, 16(r3) 3605; P9LE-NEXT: lfd f3, 0(r3) 3606; P9LE-NEXT: xvcvdpuxws v2, vs0 3607; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3608; P9LE-NEXT: xvcvdpuxws v3, vs0 3609; P9LE-NEXT: vmrgew v2, v3, v2 3610; P9LE-NEXT: blr 3611; 3612; P8BE-LABEL: fromDiffMemConsDConvdtoui: 3613; P8BE: # %bb.0: # %entry 3614; P8BE-NEXT: lfdx f3, 0, r3 3615; P8BE-NEXT: lfd f0, 24(r3) 3616; P8BE-NEXT: lfd f1, 8(r3) 3617; P8BE-NEXT: lfd f2, 16(r3) 3618; P8BE-NEXT: xxmrghd vs0, vs0, vs1 3619; P8BE-NEXT: xxmrghd vs1, vs2, vs3 3620; P8BE-NEXT: xvcvdpuxws v2, vs0 3621; P8BE-NEXT: xvcvdpuxws v3, vs1 3622; P8BE-NEXT: vmrgew v2, v2, v3 3623; P8BE-NEXT: blr 3624; 3625; P8LE-LABEL: fromDiffMemConsDConvdtoui: 3626; P8LE: # %bb.0: # %entry 3627; P8LE-NEXT: lfdx f3, 0, r3 3628; P8LE-NEXT: lfd f0, 24(r3) 3629; P8LE-NEXT: lfd f1, 8(r3) 3630; P8LE-NEXT: lfd f2, 16(r3) 3631; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3632; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3633; P8LE-NEXT: xvcvdpuxws v2, vs0 3634; P8LE-NEXT: xvcvdpuxws v3, vs1 3635; P8LE-NEXT: vmrgew v2, v3, v2 3636; P8LE-NEXT: blr 3637entry: 3638 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 3639 %0 = load double, double* %arrayidx, align 8 3640 %conv = fptoui double %0 to i32 3641 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3642 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 3643 %1 = load double, double* %arrayidx1, align 8 3644 %conv2 = fptoui double %1 to i32 3645 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 3646 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 1 3647 %2 = load double, double* %arrayidx4, align 8 3648 %conv5 = fptoui double %2 to i32 3649 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 3650 %3 = load double, double* %ptr, align 8 3651 %conv8 = fptoui double %3 to i32 3652 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 3653 ret <4 x i32> %vecinit9 3654} 3655 3656; Function Attrs: norecurse nounwind readonly 3657define <4 x i32> @fromDiffMemVarAConvdtoui(double* nocapture readonly %arr, i32 signext %elem) { 3658; P9BE-LABEL: fromDiffMemVarAConvdtoui: 3659; P9BE: # %bb.0: # %entry 3660; P9BE-NEXT: sldi r4, r4, 3 3661; P9BE-NEXT: lfdux f0, r3, r4 3662; P9BE-NEXT: lfd f1, 8(r3) 3663; P9BE-NEXT: lfd f2, 16(r3) 3664; P9BE-NEXT: lfd f3, 24(r3) 3665; P9BE-NEXT: xxmrghd vs1, vs1, vs3 3666; P9BE-NEXT: xxmrghd vs0, vs0, vs2 3667; P9BE-NEXT: xvcvdpuxws v2, vs1 3668; P9BE-NEXT: xvcvdpuxws v3, vs0 3669; P9BE-NEXT: vmrgew v2, v3, v2 3670; P9BE-NEXT: blr 3671; 3672; P9LE-LABEL: fromDiffMemVarAConvdtoui: 3673; P9LE: # %bb.0: # %entry 3674; P9LE-NEXT: sldi r4, r4, 3 3675; P9LE-NEXT: lfdux f0, r3, r4 3676; P9LE-NEXT: lfd f2, 16(r3) 3677; P9LE-NEXT: lfd f1, 8(r3) 3678; P9LE-NEXT: lfd f3, 24(r3) 3679; P9LE-NEXT: xxmrghd vs0, vs2, vs0 3680; P9LE-NEXT: xvcvdpuxws v2, vs0 3681; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3682; P9LE-NEXT: xvcvdpuxws v3, vs0 3683; P9LE-NEXT: vmrgew v2, v3, v2 3684; P9LE-NEXT: blr 3685; 3686; P8BE-LABEL: fromDiffMemVarAConvdtoui: 3687; P8BE: # %bb.0: # %entry 3688; P8BE-NEXT: sldi r4, r4, 3 3689; P8BE-NEXT: lfdux f0, r3, r4 3690; P8BE-NEXT: lfd f1, 8(r3) 3691; P8BE-NEXT: lfd f2, 24(r3) 3692; P8BE-NEXT: lfd f3, 16(r3) 3693; P8BE-NEXT: xxmrghd vs1, vs1, vs2 3694; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3695; P8BE-NEXT: xvcvdpuxws v2, vs1 3696; P8BE-NEXT: xvcvdpuxws v3, vs0 3697; P8BE-NEXT: vmrgew v2, v3, v2 3698; P8BE-NEXT: blr 3699; 3700; P8LE-LABEL: fromDiffMemVarAConvdtoui: 3701; P8LE: # %bb.0: # %entry 3702; P8LE-NEXT: sldi r4, r4, 3 3703; P8LE-NEXT: lfdux f0, r3, r4 3704; P8LE-NEXT: lfd f1, 16(r3) 3705; P8LE-NEXT: lfd f2, 8(r3) 3706; P8LE-NEXT: lfd f3, 24(r3) 3707; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3708; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3709; P8LE-NEXT: xvcvdpuxws v2, vs0 3710; P8LE-NEXT: xvcvdpuxws v3, vs1 3711; P8LE-NEXT: vmrgew v2, v3, v2 3712; P8LE-NEXT: blr 3713entry: 3714 %idxprom = sext i32 %elem to i64 3715 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 3716 %0 = load double, double* %arrayidx, align 8 3717 %conv = fptoui double %0 to i32 3718 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3719 %add = add nsw i32 %elem, 1 3720 %idxprom1 = sext i32 %add to i64 3721 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 3722 %1 = load double, double* %arrayidx2, align 8 3723 %conv3 = fptoui double %1 to i32 3724 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3725 %add5 = add nsw i32 %elem, 2 3726 %idxprom6 = sext i32 %add5 to i64 3727 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 3728 %2 = load double, double* %arrayidx7, align 8 3729 %conv8 = fptoui double %2 to i32 3730 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3731 %add10 = add nsw i32 %elem, 3 3732 %idxprom11 = sext i32 %add10 to i64 3733 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 3734 %3 = load double, double* %arrayidx12, align 8 3735 %conv13 = fptoui double %3 to i32 3736 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3737 ret <4 x i32> %vecinit14 3738} 3739 3740; Function Attrs: norecurse nounwind readonly 3741define <4 x i32> @fromDiffMemVarDConvdtoui(double* nocapture readonly %arr, i32 signext %elem) { 3742; P9BE-LABEL: fromDiffMemVarDConvdtoui: 3743; P9BE: # %bb.0: # %entry 3744; P9BE-NEXT: sldi r4, r4, 3 3745; P9BE-NEXT: lfdux f0, r3, r4 3746; P9BE-NEXT: lfd f1, -8(r3) 3747; P9BE-NEXT: lfd f2, -16(r3) 3748; P9BE-NEXT: lfd f3, -24(r3) 3749; P9BE-NEXT: xxmrghd vs1, vs1, vs3 3750; P9BE-NEXT: xxmrghd vs0, vs0, vs2 3751; P9BE-NEXT: xvcvdpuxws v2, vs1 3752; P9BE-NEXT: xvcvdpuxws v3, vs0 3753; P9BE-NEXT: vmrgew v2, v3, v2 3754; P9BE-NEXT: blr 3755; 3756; P9LE-LABEL: fromDiffMemVarDConvdtoui: 3757; P9LE: # %bb.0: # %entry 3758; P9LE-NEXT: sldi r4, r4, 3 3759; P9LE-NEXT: lfdux f0, r3, r4 3760; P9LE-NEXT: lfd f2, -16(r3) 3761; P9LE-NEXT: lfd f1, -8(r3) 3762; P9LE-NEXT: lfd f3, -24(r3) 3763; P9LE-NEXT: xxmrghd vs0, vs2, vs0 3764; P9LE-NEXT: xvcvdpuxws v2, vs0 3765; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3766; P9LE-NEXT: xvcvdpuxws v3, vs0 3767; P9LE-NEXT: vmrgew v2, v3, v2 3768; P9LE-NEXT: blr 3769; 3770; P8BE-LABEL: fromDiffMemVarDConvdtoui: 3771; P8BE: # %bb.0: # %entry 3772; P8BE-NEXT: sldi r4, r4, 3 3773; P8BE-NEXT: lfdux f0, r3, r4 3774; P8BE-NEXT: lfd f1, -8(r3) 3775; P8BE-NEXT: lfd f2, -24(r3) 3776; P8BE-NEXT: lfd f3, -16(r3) 3777; P8BE-NEXT: xxmrghd vs1, vs1, vs2 3778; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3779; P8BE-NEXT: xvcvdpuxws v2, vs1 3780; P8BE-NEXT: xvcvdpuxws v3, vs0 3781; P8BE-NEXT: vmrgew v2, v3, v2 3782; P8BE-NEXT: blr 3783; 3784; P8LE-LABEL: fromDiffMemVarDConvdtoui: 3785; P8LE: # %bb.0: # %entry 3786; P8LE-NEXT: sldi r4, r4, 3 3787; P8LE-NEXT: lfdux f0, r3, r4 3788; P8LE-NEXT: lfd f1, -16(r3) 3789; P8LE-NEXT: lfd f2, -8(r3) 3790; P8LE-NEXT: lfd f3, -24(r3) 3791; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3792; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3793; P8LE-NEXT: xvcvdpuxws v2, vs0 3794; P8LE-NEXT: xvcvdpuxws v3, vs1 3795; P8LE-NEXT: vmrgew v2, v3, v2 3796; P8LE-NEXT: blr 3797entry: 3798 %idxprom = sext i32 %elem to i64 3799 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 3800 %0 = load double, double* %arrayidx, align 8 3801 %conv = fptoui double %0 to i32 3802 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3803 %sub = add nsw i32 %elem, -1 3804 %idxprom1 = sext i32 %sub to i64 3805 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 3806 %1 = load double, double* %arrayidx2, align 8 3807 %conv3 = fptoui double %1 to i32 3808 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3809 %sub5 = add nsw i32 %elem, -2 3810 %idxprom6 = sext i32 %sub5 to i64 3811 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 3812 %2 = load double, double* %arrayidx7, align 8 3813 %conv8 = fptoui double %2 to i32 3814 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3815 %sub10 = add nsw i32 %elem, -3 3816 %idxprom11 = sext i32 %sub10 to i64 3817 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 3818 %3 = load double, double* %arrayidx12, align 8 3819 %conv13 = fptoui double %3 to i32 3820 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3821 ret <4 x i32> %vecinit14 3822} 3823 3824; Function Attrs: norecurse nounwind readnone 3825define <4 x i32> @spltRegValConvdtoui(double %val) { 3826; P9BE-LABEL: spltRegValConvdtoui: 3827; P9BE: # %bb.0: # %entry 3828; P9BE-NEXT: xscvdpuxws f0, f1 3829; P9BE-NEXT: xxspltw v2, vs0, 1 3830; P9BE-NEXT: blr 3831; 3832; P9LE-LABEL: spltRegValConvdtoui: 3833; P9LE: # %bb.0: # %entry 3834; P9LE-NEXT: xscvdpuxws f0, f1 3835; P9LE-NEXT: xxspltw v2, vs0, 1 3836; P9LE-NEXT: blr 3837; 3838; P8BE-LABEL: spltRegValConvdtoui: 3839; P8BE: # %bb.0: # %entry 3840; P8BE-NEXT: xscvdpuxws f0, f1 3841; P8BE-NEXT: xxspltw v2, vs0, 1 3842; P8BE-NEXT: blr 3843; 3844; P8LE-LABEL: spltRegValConvdtoui: 3845; P8LE: # %bb.0: # %entry 3846; P8LE-NEXT: xscvdpuxws f0, f1 3847; P8LE-NEXT: xxspltw v2, vs0, 1 3848; P8LE-NEXT: blr 3849entry: 3850 %conv = fptoui double %val to i32 3851 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3852 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3853 ret <4 x i32> %splat.splat 3854} 3855 3856; Function Attrs: norecurse nounwind readonly 3857define <4 x i32> @spltMemValConvdtoui(double* nocapture readonly %ptr) { 3858; P9BE-LABEL: spltMemValConvdtoui: 3859; P9BE: # %bb.0: # %entry 3860; P9BE-NEXT: lfd f0, 0(r3) 3861; P9BE-NEXT: xscvdpuxws f0, f0 3862; P9BE-NEXT: xxspltw v2, vs0, 1 3863; P9BE-NEXT: blr 3864; 3865; P9LE-LABEL: spltMemValConvdtoui: 3866; P9LE: # %bb.0: # %entry 3867; P9LE-NEXT: lfd f0, 0(r3) 3868; P9LE-NEXT: xscvdpuxws f0, f0 3869; P9LE-NEXT: xxspltw v2, vs0, 1 3870; P9LE-NEXT: blr 3871; 3872; P8BE-LABEL: spltMemValConvdtoui: 3873; P8BE: # %bb.0: # %entry 3874; P8BE-NEXT: lfdx f0, 0, r3 3875; P8BE-NEXT: xscvdpuxws f0, f0 3876; P8BE-NEXT: xxspltw v2, vs0, 1 3877; P8BE-NEXT: blr 3878; 3879; P8LE-LABEL: spltMemValConvdtoui: 3880; P8LE: # %bb.0: # %entry 3881; P8LE-NEXT: lfdx f0, 0, r3 3882; P8LE-NEXT: xscvdpuxws f0, f0 3883; P8LE-NEXT: xxspltw v2, vs0, 1 3884; P8LE-NEXT: blr 3885entry: 3886 %0 = load double, double* %ptr, align 8 3887 %conv = fptoui double %0 to i32 3888 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3889 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3890 ret <4 x i32> %splat.splat 3891} 3892; Function Attrs: norecurse nounwind readnone 3893define <2 x i64> @allZeroll() { 3894; P9BE-LABEL: allZeroll: 3895; P9BE: # %bb.0: # %entry 3896; P9BE-NEXT: xxlxor v2, v2, v2 3897; P9BE-NEXT: blr 3898; 3899; P9LE-LABEL: allZeroll: 3900; P9LE: # %bb.0: # %entry 3901; P9LE-NEXT: xxlxor v2, v2, v2 3902; P9LE-NEXT: blr 3903; 3904; P8BE-LABEL: allZeroll: 3905; P8BE: # %bb.0: # %entry 3906; P8BE-NEXT: xxlxor v2, v2, v2 3907; P8BE-NEXT: blr 3908; 3909; P8LE-LABEL: allZeroll: 3910; P8LE: # %bb.0: # %entry 3911; P8LE-NEXT: xxlxor v2, v2, v2 3912; P8LE-NEXT: blr 3913entry: 3914 ret <2 x i64> zeroinitializer 3915} 3916 3917; Function Attrs: norecurse nounwind readnone 3918define <2 x i64> @allOnell() { 3919; P9BE-LABEL: allOnell: 3920; P9BE: # %bb.0: # %entry 3921; P9BE-NEXT: xxspltib v2, 255 3922; P9BE-NEXT: blr 3923; 3924; P9LE-LABEL: allOnell: 3925; P9LE: # %bb.0: # %entry 3926; P9LE-NEXT: xxspltib v2, 255 3927; P9LE-NEXT: blr 3928; 3929; P8BE-LABEL: allOnell: 3930; P8BE: # %bb.0: # %entry 3931; P8BE-NEXT: vspltisb v2, -1 3932; P8BE-NEXT: blr 3933; 3934; P8LE-LABEL: allOnell: 3935; P8LE: # %bb.0: # %entry 3936; P8LE-NEXT: vspltisb v2, -1 3937; P8LE-NEXT: blr 3938entry: 3939 ret <2 x i64> <i64 -1, i64 -1> 3940} 3941 3942; Function Attrs: norecurse nounwind readnone 3943define <2 x i64> @spltConst1ll() { 3944; P9BE-LABEL: spltConst1ll: 3945; P9BE: # %bb.0: # %entry 3946; P9BE-NEXT: addis r3, r2, .LCPI68_0@toc@ha 3947; P9BE-NEXT: addi r3, r3, .LCPI68_0@toc@l 3948; P9BE-NEXT: lxvx v2, 0, r3 3949; P9BE-NEXT: blr 3950; 3951; P9LE-LABEL: spltConst1ll: 3952; P9LE: # %bb.0: # %entry 3953; P9LE-NEXT: addis r3, r2, .LCPI68_0@toc@ha 3954; P9LE-NEXT: addi r3, r3, .LCPI68_0@toc@l 3955; P9LE-NEXT: lxvx v2, 0, r3 3956; P9LE-NEXT: blr 3957; 3958; P8BE-LABEL: spltConst1ll: 3959; P8BE: # %bb.0: # %entry 3960; P8BE-NEXT: addis r3, r2, .LCPI68_0@toc@ha 3961; P8BE-NEXT: addi r3, r3, .LCPI68_0@toc@l 3962; P8BE-NEXT: lxvd2x v2, 0, r3 3963; P8BE-NEXT: blr 3964; 3965; P8LE-LABEL: spltConst1ll: 3966; P8LE: # %bb.0: # %entry 3967; P8LE-NEXT: addis r3, r2, .LCPI68_0@toc@ha 3968; P8LE-NEXT: addi r3, r3, .LCPI68_0@toc@l 3969; P8LE-NEXT: lxvd2x vs0, 0, r3 3970; P8LE-NEXT: xxswapd v2, vs0 3971; P8LE-NEXT: blr 3972entry: 3973 ret <2 x i64> <i64 1, i64 1> 3974} 3975 3976; Function Attrs: norecurse nounwind readnone 3977define <2 x i64> @spltConst16kll() { 3978; P9BE-LABEL: spltConst16kll: 3979; P9BE: # %bb.0: # %entry 3980; P9BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3981; P9BE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3982; P9BE-NEXT: lxvx v2, 0, r3 3983; P9BE-NEXT: blr 3984; 3985; P9LE-LABEL: spltConst16kll: 3986; P9LE: # %bb.0: # %entry 3987; P9LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3988; P9LE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3989; P9LE-NEXT: lxvx v2, 0, r3 3990; P9LE-NEXT: blr 3991; 3992; P8BE-LABEL: spltConst16kll: 3993; P8BE: # %bb.0: # %entry 3994; P8BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3995; P8BE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3996; P8BE-NEXT: lxvd2x v2, 0, r3 3997; P8BE-NEXT: blr 3998; 3999; P8LE-LABEL: spltConst16kll: 4000; P8LE: # %bb.0: # %entry 4001; P8LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 4002; P8LE-NEXT: addi r3, r3, .LCPI69_0@toc@l 4003; P8LE-NEXT: lxvd2x vs0, 0, r3 4004; P8LE-NEXT: xxswapd v2, vs0 4005; P8LE-NEXT: blr 4006entry: 4007 ret <2 x i64> <i64 32767, i64 32767> 4008} 4009 4010; Function Attrs: norecurse nounwind readnone 4011define <2 x i64> @spltConst32kll() { 4012; P9BE-LABEL: spltConst32kll: 4013; P9BE: # %bb.0: # %entry 4014; P9BE-NEXT: addis r3, r2, .LCPI70_0@toc@ha 4015; P9BE-NEXT: addi r3, r3, .LCPI70_0@toc@l 4016; P9BE-NEXT: lxvx v2, 0, r3 4017; P9BE-NEXT: blr 4018; 4019; P9LE-LABEL: spltConst32kll: 4020; P9LE: # %bb.0: # %entry 4021; P9LE-NEXT: addis r3, r2, .LCPI70_0@toc@ha 4022; P9LE-NEXT: addi r3, r3, .LCPI70_0@toc@l 4023; P9LE-NEXT: lxvx v2, 0, r3 4024; P9LE-NEXT: blr 4025; 4026; P8BE-LABEL: spltConst32kll: 4027; P8BE: # %bb.0: # %entry 4028; P8BE-NEXT: addis r3, r2, .LCPI70_0@toc@ha 4029; P8BE-NEXT: addi r3, r3, .LCPI70_0@toc@l 4030; P8BE-NEXT: lxvd2x v2, 0, r3 4031; P8BE-NEXT: blr 4032; 4033; P8LE-LABEL: spltConst32kll: 4034; P8LE: # %bb.0: # %entry 4035; P8LE-NEXT: addis r3, r2, .LCPI70_0@toc@ha 4036; P8LE-NEXT: addi r3, r3, .LCPI70_0@toc@l 4037; P8LE-NEXT: lxvd2x vs0, 0, r3 4038; P8LE-NEXT: xxswapd v2, vs0 4039; P8LE-NEXT: blr 4040entry: 4041 ret <2 x i64> <i64 65535, i64 65535> 4042} 4043 4044; Function Attrs: norecurse nounwind readnone 4045define <2 x i64> @fromRegsll(i64 %a, i64 %b) { 4046; P9BE-LABEL: fromRegsll: 4047; P9BE: # %bb.0: # %entry 4048; P9BE-NEXT: mtvsrdd v2, r3, r4 4049; P9BE-NEXT: blr 4050; 4051; P9LE-LABEL: fromRegsll: 4052; P9LE: # %bb.0: # %entry 4053; P9LE-NEXT: mtvsrdd v2, r4, r3 4054; P9LE-NEXT: blr 4055; 4056; P8BE-LABEL: fromRegsll: 4057; P8BE: # %bb.0: # %entry 4058; P8BE-NEXT: mtvsrd f0, r4 4059; P8BE-NEXT: mtvsrd f1, r3 4060; P8BE-NEXT: xxmrghd v2, vs1, vs0 4061; P8BE-NEXT: blr 4062; 4063; P8LE-LABEL: fromRegsll: 4064; P8LE: # %bb.0: # %entry 4065; P8LE-NEXT: mtvsrd f0, r3 4066; P8LE-NEXT: mtvsrd f1, r4 4067; P8LE-NEXT: xxmrghd v2, vs1, vs0 4068; P8LE-NEXT: blr 4069entry: 4070 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 4071 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 4072 ret <2 x i64> %vecinit1 4073} 4074 4075; Function Attrs: norecurse nounwind readnone 4076define <2 x i64> @fromDiffConstsll() { 4077; P9BE-LABEL: fromDiffConstsll: 4078; P9BE: # %bb.0: # %entry 4079; P9BE-NEXT: addis r3, r2, .LCPI72_0@toc@ha 4080; P9BE-NEXT: addi r3, r3, .LCPI72_0@toc@l 4081; P9BE-NEXT: lxvx v2, 0, r3 4082; P9BE-NEXT: blr 4083; 4084; P9LE-LABEL: fromDiffConstsll: 4085; P9LE: # %bb.0: # %entry 4086; P9LE-NEXT: addis r3, r2, .LCPI72_0@toc@ha 4087; P9LE-NEXT: addi r3, r3, .LCPI72_0@toc@l 4088; P9LE-NEXT: lxvx v2, 0, r3 4089; P9LE-NEXT: blr 4090; 4091; P8BE-LABEL: fromDiffConstsll: 4092; P8BE: # %bb.0: # %entry 4093; P8BE-NEXT: addis r3, r2, .LCPI72_0@toc@ha 4094; P8BE-NEXT: addi r3, r3, .LCPI72_0@toc@l 4095; P8BE-NEXT: lxvd2x v2, 0, r3 4096; P8BE-NEXT: blr 4097; 4098; P8LE-LABEL: fromDiffConstsll: 4099; P8LE: # %bb.0: # %entry 4100; P8LE-NEXT: addis r3, r2, .LCPI72_0@toc@ha 4101; P8LE-NEXT: addi r3, r3, .LCPI72_0@toc@l 4102; P8LE-NEXT: lxvd2x vs0, 0, r3 4103; P8LE-NEXT: xxswapd v2, vs0 4104; P8LE-NEXT: blr 4105entry: 4106 ret <2 x i64> <i64 242, i64 -113> 4107} 4108 4109; Function Attrs: norecurse nounwind readonly 4110define <2 x i64> @fromDiffMemConsAll(i64* nocapture readonly %arr) { 4111; P9BE-LABEL: fromDiffMemConsAll: 4112; P9BE: # %bb.0: # %entry 4113; P9BE-NEXT: lxv v2, 0(r3) 4114; P9BE-NEXT: blr 4115; 4116; P9LE-LABEL: fromDiffMemConsAll: 4117; P9LE: # %bb.0: # %entry 4118; P9LE-NEXT: lxv v2, 0(r3) 4119; P9LE-NEXT: blr 4120; 4121; P8BE-LABEL: fromDiffMemConsAll: 4122; P8BE: # %bb.0: # %entry 4123; P8BE-NEXT: lxvd2x v2, 0, r3 4124; P8BE-NEXT: blr 4125; 4126; P8LE-LABEL: fromDiffMemConsAll: 4127; P8LE: # %bb.0: # %entry 4128; P8LE-NEXT: lxvd2x vs0, 0, r3 4129; P8LE-NEXT: xxswapd v2, vs0 4130; P8LE-NEXT: blr 4131entry: 4132 %0 = load i64, i64* %arr, align 8 4133 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4134 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 1 4135 %1 = load i64, i64* %arrayidx1, align 8 4136 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4137 ret <2 x i64> %vecinit2 4138} 4139 4140; Function Attrs: norecurse nounwind readonly 4141define <2 x i64> @fromDiffMemConsDll(i64* nocapture readonly %arr) { 4142; P9BE-LABEL: fromDiffMemConsDll: 4143; P9BE: # %bb.0: # %entry 4144; P9BE-NEXT: lxv v2, 16(r3) 4145; P9BE-NEXT: xxswapd v2, v2 4146; P9BE-NEXT: blr 4147; 4148; P9LE-LABEL: fromDiffMemConsDll: 4149; P9LE: # %bb.0: # %entry 4150; P9LE-NEXT: addi r3, r3, 16 4151; P9LE-NEXT: lxvd2x v2, 0, r3 4152; P9LE-NEXT: blr 4153; 4154; P8BE-LABEL: fromDiffMemConsDll: 4155; P8BE: # %bb.0: # %entry 4156; P8BE-NEXT: addi r3, r3, 16 4157; P8BE-NEXT: lxvd2x v2, 0, r3 4158; P8BE-NEXT: xxswapd v2, v2 4159; P8BE-NEXT: blr 4160; 4161; P8LE-LABEL: fromDiffMemConsDll: 4162; P8LE: # %bb.0: # %entry 4163; P8LE-NEXT: addi r3, r3, 16 4164; P8LE-NEXT: lxvd2x v2, 0, r3 4165; P8LE-NEXT: blr 4166entry: 4167 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 3 4168 %0 = load i64, i64* %arrayidx, align 8 4169 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4170 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 2 4171 %1 = load i64, i64* %arrayidx1, align 8 4172 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4173 ret <2 x i64> %vecinit2 4174} 4175 4176; Function Attrs: norecurse nounwind readonly 4177define <2 x i64> @fromDiffMemVarAll(i64* nocapture readonly %arr, i32 signext %elem) { 4178; P9BE-LABEL: fromDiffMemVarAll: 4179; P9BE: # %bb.0: # %entry 4180; P9BE-NEXT: sldi r4, r4, 3 4181; P9BE-NEXT: lxvx v2, r3, r4 4182; P9BE-NEXT: blr 4183; 4184; P9LE-LABEL: fromDiffMemVarAll: 4185; P9LE: # %bb.0: # %entry 4186; P9LE-NEXT: sldi r4, r4, 3 4187; P9LE-NEXT: lxvx v2, r3, r4 4188; P9LE-NEXT: blr 4189; 4190; P8BE-LABEL: fromDiffMemVarAll: 4191; P8BE: # %bb.0: # %entry 4192; P8BE-NEXT: sldi r4, r4, 3 4193; P8BE-NEXT: lxvd2x v2, r3, r4 4194; P8BE-NEXT: blr 4195; 4196; P8LE-LABEL: fromDiffMemVarAll: 4197; P8LE: # %bb.0: # %entry 4198; P8LE-NEXT: sldi r4, r4, 3 4199; P8LE-NEXT: lxvd2x vs0, r3, r4 4200; P8LE-NEXT: xxswapd v2, vs0 4201; P8LE-NEXT: blr 4202entry: 4203 %idxprom = sext i32 %elem to i64 4204 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4205 %0 = load i64, i64* %arrayidx, align 8 4206 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4207 %add = add nsw i32 %elem, 1 4208 %idxprom1 = sext i32 %add to i64 4209 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 4210 %1 = load i64, i64* %arrayidx2, align 8 4211 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4212 ret <2 x i64> %vecinit3 4213} 4214 4215; Function Attrs: norecurse nounwind readonly 4216define <2 x i64> @fromDiffMemVarDll(i64* nocapture readonly %arr, i32 signext %elem) { 4217; P9BE-LABEL: fromDiffMemVarDll: 4218; P9BE: # %bb.0: # %entry 4219; P9BE-NEXT: sldi r4, r4, 3 4220; P9BE-NEXT: add r3, r3, r4 4221; P9BE-NEXT: li r4, -8 4222; P9BE-NEXT: lxvx v2, r3, r4 4223; P9BE-NEXT: xxswapd v2, v2 4224; P9BE-NEXT: blr 4225; 4226; P9LE-LABEL: fromDiffMemVarDll: 4227; P9LE: # %bb.0: # %entry 4228; P9LE-NEXT: sldi r4, r4, 3 4229; P9LE-NEXT: add r3, r3, r4 4230; P9LE-NEXT: addi r3, r3, -8 4231; P9LE-NEXT: lxvd2x v2, 0, r3 4232; P9LE-NEXT: blr 4233; 4234; P8BE-LABEL: fromDiffMemVarDll: 4235; P8BE: # %bb.0: # %entry 4236; P8BE-NEXT: sldi r4, r4, 3 4237; P8BE-NEXT: add r3, r3, r4 4238; P8BE-NEXT: addi r3, r3, -8 4239; P8BE-NEXT: lxvd2x v2, 0, r3 4240; P8BE-NEXT: xxswapd v2, v2 4241; P8BE-NEXT: blr 4242; 4243; P8LE-LABEL: fromDiffMemVarDll: 4244; P8LE: # %bb.0: # %entry 4245; P8LE-NEXT: sldi r4, r4, 3 4246; P8LE-NEXT: add r3, r3, r4 4247; P8LE-NEXT: addi r3, r3, -8 4248; P8LE-NEXT: lxvd2x v2, 0, r3 4249; P8LE-NEXT: blr 4250entry: 4251 %idxprom = sext i32 %elem to i64 4252 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4253 %0 = load i64, i64* %arrayidx, align 8 4254 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4255 %sub = add nsw i32 %elem, -1 4256 %idxprom1 = sext i32 %sub to i64 4257 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 4258 %1 = load i64, i64* %arrayidx2, align 8 4259 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4260 ret <2 x i64> %vecinit3 4261} 4262 4263; Function Attrs: norecurse nounwind readonly 4264define <2 x i64> @fromRandMemConsll(i64* nocapture readonly %arr) { 4265; P9BE-LABEL: fromRandMemConsll: 4266; P9BE: # %bb.0: # %entry 4267; P9BE-NEXT: ld r4, 32(r3) 4268; P9BE-NEXT: ld r3, 144(r3) 4269; P9BE-NEXT: mtvsrdd v2, r4, r3 4270; P9BE-NEXT: blr 4271; 4272; P9LE-LABEL: fromRandMemConsll: 4273; P9LE: # %bb.0: # %entry 4274; P9LE-NEXT: ld r4, 32(r3) 4275; P9LE-NEXT: ld r3, 144(r3) 4276; P9LE-NEXT: mtvsrdd v2, r3, r4 4277; P9LE-NEXT: blr 4278; 4279; P8BE-LABEL: fromRandMemConsll: 4280; P8BE: # %bb.0: # %entry 4281; P8BE-NEXT: ld r4, 144(r3) 4282; P8BE-NEXT: ld r3, 32(r3) 4283; P8BE-NEXT: mtvsrd f0, r4 4284; P8BE-NEXT: mtvsrd f1, r3 4285; P8BE-NEXT: xxmrghd v2, vs1, vs0 4286; P8BE-NEXT: blr 4287; 4288; P8LE-LABEL: fromRandMemConsll: 4289; P8LE: # %bb.0: # %entry 4290; P8LE-NEXT: ld r4, 32(r3) 4291; P8LE-NEXT: ld r3, 144(r3) 4292; P8LE-NEXT: mtvsrd f0, r4 4293; P8LE-NEXT: mtvsrd f1, r3 4294; P8LE-NEXT: xxmrghd v2, vs1, vs0 4295; P8LE-NEXT: blr 4296entry: 4297 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4 4298 %0 = load i64, i64* %arrayidx, align 8 4299 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4300 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18 4301 %1 = load i64, i64* %arrayidx1, align 8 4302 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4303 ret <2 x i64> %vecinit2 4304} 4305 4306; Function Attrs: norecurse nounwind readonly 4307define <2 x i64> @fromRandMemVarll(i64* nocapture readonly %arr, i32 signext %elem) { 4308; P9BE-LABEL: fromRandMemVarll: 4309; P9BE: # %bb.0: # %entry 4310; P9BE-NEXT: sldi r4, r4, 3 4311; P9BE-NEXT: add r3, r3, r4 4312; P9BE-NEXT: ld r4, 32(r3) 4313; P9BE-NEXT: ld r3, 8(r3) 4314; P9BE-NEXT: mtvsrdd v2, r4, r3 4315; P9BE-NEXT: blr 4316; 4317; P9LE-LABEL: fromRandMemVarll: 4318; P9LE: # %bb.0: # %entry 4319; P9LE-NEXT: sldi r4, r4, 3 4320; P9LE-NEXT: add r3, r3, r4 4321; P9LE-NEXT: ld r4, 32(r3) 4322; P9LE-NEXT: ld r3, 8(r3) 4323; P9LE-NEXT: mtvsrdd v2, r3, r4 4324; P9LE-NEXT: blr 4325; 4326; P8BE-LABEL: fromRandMemVarll: 4327; P8BE: # %bb.0: # %entry 4328; P8BE-NEXT: sldi r4, r4, 3 4329; P8BE-NEXT: add r3, r3, r4 4330; P8BE-NEXT: ld r4, 8(r3) 4331; P8BE-NEXT: ld r3, 32(r3) 4332; P8BE-NEXT: mtvsrd f0, r4 4333; P8BE-NEXT: mtvsrd f1, r3 4334; P8BE-NEXT: xxmrghd v2, vs1, vs0 4335; P8BE-NEXT: blr 4336; 4337; P8LE-LABEL: fromRandMemVarll: 4338; P8LE: # %bb.0: # %entry 4339; P8LE-NEXT: sldi r4, r4, 3 4340; P8LE-NEXT: add r3, r3, r4 4341; P8LE-NEXT: ld r4, 32(r3) 4342; P8LE-NEXT: ld r3, 8(r3) 4343; P8LE-NEXT: mtvsrd f0, r4 4344; P8LE-NEXT: mtvsrd f1, r3 4345; P8LE-NEXT: xxmrghd v2, vs1, vs0 4346; P8LE-NEXT: blr 4347entry: 4348 %add = add nsw i32 %elem, 4 4349 %idxprom = sext i32 %add to i64 4350 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4351 %0 = load i64, i64* %arrayidx, align 8 4352 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4353 %add1 = add nsw i32 %elem, 1 4354 %idxprom2 = sext i32 %add1 to i64 4355 %arrayidx3 = getelementptr inbounds i64, i64* %arr, i64 %idxprom2 4356 %1 = load i64, i64* %arrayidx3, align 8 4357 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4358 ret <2 x i64> %vecinit4 4359} 4360 4361; Function Attrs: norecurse nounwind readnone 4362define <2 x i64> @spltRegValll(i64 %val) { 4363; P9BE-LABEL: spltRegValll: 4364; P9BE: # %bb.0: # %entry 4365; P9BE-NEXT: mtvsrdd v2, r3, r3 4366; P9BE-NEXT: blr 4367; 4368; P9LE-LABEL: spltRegValll: 4369; P9LE: # %bb.0: # %entry 4370; P9LE-NEXT: mtvsrdd v2, r3, r3 4371; P9LE-NEXT: blr 4372; 4373; P8BE-LABEL: spltRegValll: 4374; P8BE: # %bb.0: # %entry 4375; P8BE-NEXT: mtvsrd f0, r3 4376; P8BE-NEXT: xxspltd v2, vs0, 0 4377; P8BE-NEXT: blr 4378; 4379; P8LE-LABEL: spltRegValll: 4380; P8LE: # %bb.0: # %entry 4381; P8LE-NEXT: mtvsrd f0, r3 4382; P8LE-NEXT: xxspltd v2, vs0, 0 4383; P8LE-NEXT: blr 4384entry: 4385 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0 4386 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4387 ret <2 x i64> %splat.splat 4388} 4389 4390; Function Attrs: norecurse nounwind readonly 4391define <2 x i64> @spltMemValll(i64* nocapture readonly %ptr) { 4392; P9BE-LABEL: spltMemValll: 4393; P9BE: # %bb.0: # %entry 4394; P9BE-NEXT: lxvdsx v2, 0, r3 4395; P9BE-NEXT: blr 4396; 4397; P9LE-LABEL: spltMemValll: 4398; P9LE: # %bb.0: # %entry 4399; P9LE-NEXT: lxvdsx v2, 0, r3 4400; P9LE-NEXT: blr 4401; 4402; P8BE-LABEL: spltMemValll: 4403; P8BE: # %bb.0: # %entry 4404; P8BE-NEXT: lxvdsx v2, 0, r3 4405; P8BE-NEXT: blr 4406; 4407; P8LE-LABEL: spltMemValll: 4408; P8LE: # %bb.0: # %entry 4409; P8LE-NEXT: lxvdsx v2, 0, r3 4410; P8LE-NEXT: blr 4411entry: 4412 %0 = load i64, i64* %ptr, align 8 4413 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 4414 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4415 ret <2 x i64> %splat.splat 4416} 4417 4418; Function Attrs: norecurse nounwind readnone 4419define <2 x i64> @spltCnstConvftoll() { 4420; P9BE-LABEL: spltCnstConvftoll: 4421; P9BE: # %bb.0: # %entry 4422; P9BE-NEXT: addis r3, r2, .LCPI81_0@toc@ha 4423; P9BE-NEXT: addi r3, r3, .LCPI81_0@toc@l 4424; P9BE-NEXT: lxvx v2, 0, r3 4425; P9BE-NEXT: blr 4426; 4427; P9LE-LABEL: spltCnstConvftoll: 4428; P9LE: # %bb.0: # %entry 4429; P9LE-NEXT: addis r3, r2, .LCPI81_0@toc@ha 4430; P9LE-NEXT: addi r3, r3, .LCPI81_0@toc@l 4431; P9LE-NEXT: lxvx v2, 0, r3 4432; P9LE-NEXT: blr 4433; 4434; P8BE-LABEL: spltCnstConvftoll: 4435; P8BE: # %bb.0: # %entry 4436; P8BE-NEXT: addis r3, r2, .LCPI81_0@toc@ha 4437; P8BE-NEXT: addi r3, r3, .LCPI81_0@toc@l 4438; P8BE-NEXT: lxvd2x v2, 0, r3 4439; P8BE-NEXT: blr 4440; 4441; P8LE-LABEL: spltCnstConvftoll: 4442; P8LE: # %bb.0: # %entry 4443; P8LE-NEXT: addis r3, r2, .LCPI81_0@toc@ha 4444; P8LE-NEXT: addi r3, r3, .LCPI81_0@toc@l 4445; P8LE-NEXT: lxvd2x vs0, 0, r3 4446; P8LE-NEXT: xxswapd v2, vs0 4447; P8LE-NEXT: blr 4448entry: 4449 ret <2 x i64> <i64 4, i64 4> 4450} 4451 4452; Function Attrs: norecurse nounwind readnone 4453define <2 x i64> @fromRegsConvftoll(float %a, float %b) { 4454; P9BE-LABEL: fromRegsConvftoll: 4455; P9BE: # %bb.0: # %entry 4456; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4457; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4458; P9BE-NEXT: xxmrghd vs0, vs1, vs2 4459; P9BE-NEXT: xvcvdpsxds v2, vs0 4460; P9BE-NEXT: blr 4461; 4462; P9LE-LABEL: fromRegsConvftoll: 4463; P9LE: # %bb.0: # %entry 4464; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4465; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4466; P9LE-NEXT: xxmrghd vs0, vs2, vs1 4467; P9LE-NEXT: xvcvdpsxds v2, vs0 4468; P9LE-NEXT: blr 4469; 4470; P8BE-LABEL: fromRegsConvftoll: 4471; P8BE: # %bb.0: # %entry 4472; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4473; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4474; P8BE-NEXT: xxmrghd vs0, vs1, vs2 4475; P8BE-NEXT: xvcvdpsxds v2, vs0 4476; P8BE-NEXT: blr 4477; 4478; P8LE-LABEL: fromRegsConvftoll: 4479; P8LE: # %bb.0: # %entry 4480; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4481; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4482; P8LE-NEXT: xxmrghd vs0, vs2, vs1 4483; P8LE-NEXT: xvcvdpsxds v2, vs0 4484; P8LE-NEXT: blr 4485entry: 4486 %conv = fptosi float %a to i64 4487 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4488 %conv1 = fptosi float %b to i64 4489 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 4490 ret <2 x i64> %vecinit2 4491} 4492 4493; Function Attrs: norecurse nounwind readnone 4494define <2 x i64> @fromDiffConstsConvftoll() { 4495; P9BE-LABEL: fromDiffConstsConvftoll: 4496; P9BE: # %bb.0: # %entry 4497; P9BE-NEXT: addis r3, r2, .LCPI83_0@toc@ha 4498; P9BE-NEXT: addi r3, r3, .LCPI83_0@toc@l 4499; P9BE-NEXT: lxvx v2, 0, r3 4500; P9BE-NEXT: blr 4501; 4502; P9LE-LABEL: fromDiffConstsConvftoll: 4503; P9LE: # %bb.0: # %entry 4504; P9LE-NEXT: addis r3, r2, .LCPI83_0@toc@ha 4505; P9LE-NEXT: addi r3, r3, .LCPI83_0@toc@l 4506; P9LE-NEXT: lxvx v2, 0, r3 4507; P9LE-NEXT: blr 4508; 4509; P8BE-LABEL: fromDiffConstsConvftoll: 4510; P8BE: # %bb.0: # %entry 4511; P8BE-NEXT: addis r3, r2, .LCPI83_0@toc@ha 4512; P8BE-NEXT: addi r3, r3, .LCPI83_0@toc@l 4513; P8BE-NEXT: lxvd2x v2, 0, r3 4514; P8BE-NEXT: blr 4515; 4516; P8LE-LABEL: fromDiffConstsConvftoll: 4517; P8LE: # %bb.0: # %entry 4518; P8LE-NEXT: addis r3, r2, .LCPI83_0@toc@ha 4519; P8LE-NEXT: addi r3, r3, .LCPI83_0@toc@l 4520; P8LE-NEXT: lxvd2x vs0, 0, r3 4521; P8LE-NEXT: xxswapd v2, vs0 4522; P8LE-NEXT: blr 4523entry: 4524 ret <2 x i64> <i64 24, i64 234> 4525} 4526 4527; Function Attrs: norecurse nounwind readonly 4528define <2 x i64> @fromDiffMemConsAConvftoll(float* nocapture readonly %ptr) { 4529; P9BE-LABEL: fromDiffMemConsAConvftoll: 4530; P9BE: # %bb.0: # %entry 4531; P9BE-NEXT: lfs f0, 0(r3) 4532; P9BE-NEXT: lfs f1, 4(r3) 4533; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4534; P9BE-NEXT: xvcvdpsxds v2, vs0 4535; P9BE-NEXT: blr 4536; 4537; P9LE-LABEL: fromDiffMemConsAConvftoll: 4538; P9LE: # %bb.0: # %entry 4539; P9LE-NEXT: lfs f0, 0(r3) 4540; P9LE-NEXT: lfs f1, 4(r3) 4541; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4542; P9LE-NEXT: xvcvdpsxds v2, vs0 4543; P9LE-NEXT: blr 4544; 4545; P8BE-LABEL: fromDiffMemConsAConvftoll: 4546; P8BE: # %bb.0: # %entry 4547; P8BE-NEXT: lfsx f0, 0, r3 4548; P8BE-NEXT: lfs f1, 4(r3) 4549; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4550; P8BE-NEXT: xvcvdpsxds v2, vs0 4551; P8BE-NEXT: blr 4552; 4553; P8LE-LABEL: fromDiffMemConsAConvftoll: 4554; P8LE: # %bb.0: # %entry 4555; P8LE-NEXT: lfsx f0, 0, r3 4556; P8LE-NEXT: lfs f1, 4(r3) 4557; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4558; P8LE-NEXT: xvcvdpsxds v2, vs0 4559; P8LE-NEXT: blr 4560entry: 4561 %0 = load float, float* %ptr, align 4 4562 %conv = fptosi float %0 to i64 4563 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4564 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1 4565 %1 = load float, float* %arrayidx1, align 4 4566 %conv2 = fptosi float %1 to i64 4567 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4568 ret <2 x i64> %vecinit3 4569} 4570 4571; Function Attrs: norecurse nounwind readonly 4572define <2 x i64> @fromDiffMemConsDConvftoll(float* nocapture readonly %ptr) { 4573; P9BE-LABEL: fromDiffMemConsDConvftoll: 4574; P9BE: # %bb.0: # %entry 4575; P9BE-NEXT: lfs f0, 12(r3) 4576; P9BE-NEXT: lfs f1, 8(r3) 4577; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4578; P9BE-NEXT: xvcvdpsxds v2, vs0 4579; P9BE-NEXT: blr 4580; 4581; P9LE-LABEL: fromDiffMemConsDConvftoll: 4582; P9LE: # %bb.0: # %entry 4583; P9LE-NEXT: lfs f0, 12(r3) 4584; P9LE-NEXT: lfs f1, 8(r3) 4585; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4586; P9LE-NEXT: xvcvdpsxds v2, vs0 4587; P9LE-NEXT: blr 4588; 4589; P8BE-LABEL: fromDiffMemConsDConvftoll: 4590; P8BE: # %bb.0: # %entry 4591; P8BE-NEXT: lfs f0, 12(r3) 4592; P8BE-NEXT: lfs f1, 8(r3) 4593; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4594; P8BE-NEXT: xvcvdpsxds v2, vs0 4595; P8BE-NEXT: blr 4596; 4597; P8LE-LABEL: fromDiffMemConsDConvftoll: 4598; P8LE: # %bb.0: # %entry 4599; P8LE-NEXT: lfs f0, 12(r3) 4600; P8LE-NEXT: lfs f1, 8(r3) 4601; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4602; P8LE-NEXT: xvcvdpsxds v2, vs0 4603; P8LE-NEXT: blr 4604entry: 4605 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 4606 %0 = load float, float* %arrayidx, align 4 4607 %conv = fptosi float %0 to i64 4608 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4609 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 4610 %1 = load float, float* %arrayidx1, align 4 4611 %conv2 = fptosi float %1 to i64 4612 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4613 ret <2 x i64> %vecinit3 4614} 4615 4616; Function Attrs: norecurse nounwind readonly 4617define <2 x i64> @fromDiffMemVarAConvftoll(float* nocapture readonly %arr, i32 signext %elem) { 4618; P9BE-LABEL: fromDiffMemVarAConvftoll: 4619; P9BE: # %bb.0: # %entry 4620; P9BE-NEXT: sldi r4, r4, 2 4621; P9BE-NEXT: lfsux f0, r3, r4 4622; P9BE-NEXT: lfs f1, 4(r3) 4623; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4624; P9BE-NEXT: xvcvdpsxds v2, vs0 4625; P9BE-NEXT: blr 4626; 4627; P9LE-LABEL: fromDiffMemVarAConvftoll: 4628; P9LE: # %bb.0: # %entry 4629; P9LE-NEXT: sldi r4, r4, 2 4630; P9LE-NEXT: lfsux f0, r3, r4 4631; P9LE-NEXT: lfs f1, 4(r3) 4632; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4633; P9LE-NEXT: xvcvdpsxds v2, vs0 4634; P9LE-NEXT: blr 4635; 4636; P8BE-LABEL: fromDiffMemVarAConvftoll: 4637; P8BE: # %bb.0: # %entry 4638; P8BE-NEXT: sldi r4, r4, 2 4639; P8BE-NEXT: lfsux f0, r3, r4 4640; P8BE-NEXT: lfs f1, 4(r3) 4641; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4642; P8BE-NEXT: xvcvdpsxds v2, vs0 4643; P8BE-NEXT: blr 4644; 4645; P8LE-LABEL: fromDiffMemVarAConvftoll: 4646; P8LE: # %bb.0: # %entry 4647; P8LE-NEXT: sldi r4, r4, 2 4648; P8LE-NEXT: lfsux f0, r3, r4 4649; P8LE-NEXT: lfs f1, 4(r3) 4650; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4651; P8LE-NEXT: xvcvdpsxds v2, vs0 4652; P8LE-NEXT: blr 4653entry: 4654 %idxprom = sext i32 %elem to i64 4655 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 4656 %0 = load float, float* %arrayidx, align 4 4657 %conv = fptosi float %0 to i64 4658 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4659 %add = add nsw i32 %elem, 1 4660 %idxprom1 = sext i32 %add to i64 4661 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 4662 %1 = load float, float* %arrayidx2, align 4 4663 %conv3 = fptosi float %1 to i64 4664 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4665 ret <2 x i64> %vecinit4 4666} 4667 4668; Function Attrs: norecurse nounwind readonly 4669define <2 x i64> @fromDiffMemVarDConvftoll(float* nocapture readonly %arr, i32 signext %elem) { 4670; P9BE-LABEL: fromDiffMemVarDConvftoll: 4671; P9BE: # %bb.0: # %entry 4672; P9BE-NEXT: sldi r4, r4, 2 4673; P9BE-NEXT: lfsux f0, r3, r4 4674; P9BE-NEXT: lfs f1, -4(r3) 4675; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4676; P9BE-NEXT: xvcvdpsxds v2, vs0 4677; P9BE-NEXT: blr 4678; 4679; P9LE-LABEL: fromDiffMemVarDConvftoll: 4680; P9LE: # %bb.0: # %entry 4681; P9LE-NEXT: sldi r4, r4, 2 4682; P9LE-NEXT: lfsux f0, r3, r4 4683; P9LE-NEXT: lfs f1, -4(r3) 4684; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4685; P9LE-NEXT: xvcvdpsxds v2, vs0 4686; P9LE-NEXT: blr 4687; 4688; P8BE-LABEL: fromDiffMemVarDConvftoll: 4689; P8BE: # %bb.0: # %entry 4690; P8BE-NEXT: sldi r4, r4, 2 4691; P8BE-NEXT: lfsux f0, r3, r4 4692; P8BE-NEXT: lfs f1, -4(r3) 4693; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4694; P8BE-NEXT: xvcvdpsxds v2, vs0 4695; P8BE-NEXT: blr 4696; 4697; P8LE-LABEL: fromDiffMemVarDConvftoll: 4698; P8LE: # %bb.0: # %entry 4699; P8LE-NEXT: sldi r4, r4, 2 4700; P8LE-NEXT: lfsux f0, r3, r4 4701; P8LE-NEXT: lfs f1, -4(r3) 4702; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4703; P8LE-NEXT: xvcvdpsxds v2, vs0 4704; P8LE-NEXT: blr 4705entry: 4706 %idxprom = sext i32 %elem to i64 4707 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 4708 %0 = load float, float* %arrayidx, align 4 4709 %conv = fptosi float %0 to i64 4710 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4711 %sub = add nsw i32 %elem, -1 4712 %idxprom1 = sext i32 %sub to i64 4713 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 4714 %1 = load float, float* %arrayidx2, align 4 4715 %conv3 = fptosi float %1 to i64 4716 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4717 ret <2 x i64> %vecinit4 4718} 4719 4720; Function Attrs: norecurse nounwind readnone 4721define <2 x i64> @spltRegValConvftoll(float %val) { 4722; P9BE-LABEL: spltRegValConvftoll: 4723; P9BE: # %bb.0: # %entry 4724; P9BE-NEXT: xscvdpsxds f0, f1 4725; P9BE-NEXT: xxspltd v2, f0, 0 4726; P9BE-NEXT: blr 4727; 4728; P9LE-LABEL: spltRegValConvftoll: 4729; P9LE: # %bb.0: # %entry 4730; P9LE-NEXT: xscvdpsxds f0, f1 4731; P9LE-NEXT: xxspltd v2, f0, 0 4732; P9LE-NEXT: blr 4733; 4734; P8BE-LABEL: spltRegValConvftoll: 4735; P8BE: # %bb.0: # %entry 4736; P8BE-NEXT: xscvdpsxds f0, f1 4737; P8BE-NEXT: xxspltd v2, f0, 0 4738; P8BE-NEXT: blr 4739; 4740; P8LE-LABEL: spltRegValConvftoll: 4741; P8LE: # %bb.0: # %entry 4742; P8LE-NEXT: xscvdpsxds f0, f1 4743; P8LE-NEXT: xxspltd v2, f0, 0 4744; P8LE-NEXT: blr 4745entry: 4746 %conv = fptosi float %val to i64 4747 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4748 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4749 ret <2 x i64> %splat.splat 4750} 4751 4752; Function Attrs: norecurse nounwind readonly 4753define <2 x i64> @spltMemValConvftoll(float* nocapture readonly %ptr) { 4754; P9BE-LABEL: spltMemValConvftoll: 4755; P9BE: # %bb.0: # %entry 4756; P9BE-NEXT: lfs f0, 0(r3) 4757; P9BE-NEXT: xscvdpsxds f0, f0 4758; P9BE-NEXT: xxspltd v2, f0, 0 4759; P9BE-NEXT: blr 4760; 4761; P9LE-LABEL: spltMemValConvftoll: 4762; P9LE: # %bb.0: # %entry 4763; P9LE-NEXT: lfs f0, 0(r3) 4764; P9LE-NEXT: xscvdpsxds f0, f0 4765; P9LE-NEXT: xxspltd v2, f0, 0 4766; P9LE-NEXT: blr 4767; 4768; P8BE-LABEL: spltMemValConvftoll: 4769; P8BE: # %bb.0: # %entry 4770; P8BE-NEXT: lfsx f0, 0, r3 4771; P8BE-NEXT: xscvdpsxds f0, f0 4772; P8BE-NEXT: xxspltd v2, f0, 0 4773; P8BE-NEXT: blr 4774; 4775; P8LE-LABEL: spltMemValConvftoll: 4776; P8LE: # %bb.0: # %entry 4777; P8LE-NEXT: lfsx f0, 0, r3 4778; P8LE-NEXT: xscvdpsxds f0, f0 4779; P8LE-NEXT: xxspltd v2, f0, 0 4780; P8LE-NEXT: blr 4781entry: 4782 %0 = load float, float* %ptr, align 4 4783 %conv = fptosi float %0 to i64 4784 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4785 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4786 ret <2 x i64> %splat.splat 4787} 4788 4789; Function Attrs: norecurse nounwind readnone 4790define <2 x i64> @spltCnstConvdtoll() { 4791; P9BE-LABEL: spltCnstConvdtoll: 4792; P9BE: # %bb.0: # %entry 4793; P9BE-NEXT: addis r3, r2, .LCPI90_0@toc@ha 4794; P9BE-NEXT: addi r3, r3, .LCPI90_0@toc@l 4795; P9BE-NEXT: lxvx v2, 0, r3 4796; P9BE-NEXT: blr 4797; 4798; P9LE-LABEL: spltCnstConvdtoll: 4799; P9LE: # %bb.0: # %entry 4800; P9LE-NEXT: addis r3, r2, .LCPI90_0@toc@ha 4801; P9LE-NEXT: addi r3, r3, .LCPI90_0@toc@l 4802; P9LE-NEXT: lxvx v2, 0, r3 4803; P9LE-NEXT: blr 4804; 4805; P8BE-LABEL: spltCnstConvdtoll: 4806; P8BE: # %bb.0: # %entry 4807; P8BE-NEXT: addis r3, r2, .LCPI90_0@toc@ha 4808; P8BE-NEXT: addi r3, r3, .LCPI90_0@toc@l 4809; P8BE-NEXT: lxvd2x v2, 0, r3 4810; P8BE-NEXT: blr 4811; 4812; P8LE-LABEL: spltCnstConvdtoll: 4813; P8LE: # %bb.0: # %entry 4814; P8LE-NEXT: addis r3, r2, .LCPI90_0@toc@ha 4815; P8LE-NEXT: addi r3, r3, .LCPI90_0@toc@l 4816; P8LE-NEXT: lxvd2x vs0, 0, r3 4817; P8LE-NEXT: xxswapd v2, vs0 4818; P8LE-NEXT: blr 4819entry: 4820 ret <2 x i64> <i64 4, i64 4> 4821} 4822 4823; Function Attrs: norecurse nounwind readnone 4824define <2 x i64> @fromRegsConvdtoll(double %a, double %b) { 4825; P9BE-LABEL: fromRegsConvdtoll: 4826; P9BE: # %bb.0: # %entry 4827; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4828; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4829; P9BE-NEXT: xxmrghd vs0, vs1, vs2 4830; P9BE-NEXT: xvcvdpsxds v2, vs0 4831; P9BE-NEXT: blr 4832; 4833; P9LE-LABEL: fromRegsConvdtoll: 4834; P9LE: # %bb.0: # %entry 4835; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4836; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4837; P9LE-NEXT: xxmrghd vs0, vs2, vs1 4838; P9LE-NEXT: xvcvdpsxds v2, vs0 4839; P9LE-NEXT: blr 4840; 4841; P8BE-LABEL: fromRegsConvdtoll: 4842; P8BE: # %bb.0: # %entry 4843; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4844; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4845; P8BE-NEXT: xxmrghd vs0, vs1, vs2 4846; P8BE-NEXT: xvcvdpsxds v2, vs0 4847; P8BE-NEXT: blr 4848; 4849; P8LE-LABEL: fromRegsConvdtoll: 4850; P8LE: # %bb.0: # %entry 4851; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4852; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4853; P8LE-NEXT: xxmrghd vs0, vs2, vs1 4854; P8LE-NEXT: xvcvdpsxds v2, vs0 4855; P8LE-NEXT: blr 4856entry: 4857 %conv = fptosi double %a to i64 4858 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4859 %conv1 = fptosi double %b to i64 4860 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 4861 ret <2 x i64> %vecinit2 4862} 4863 4864; Function Attrs: norecurse nounwind readnone 4865define <2 x i64> @fromDiffConstsConvdtoll() { 4866; P9BE-LABEL: fromDiffConstsConvdtoll: 4867; P9BE: # %bb.0: # %entry 4868; P9BE-NEXT: addis r3, r2, .LCPI92_0@toc@ha 4869; P9BE-NEXT: addi r3, r3, .LCPI92_0@toc@l 4870; P9BE-NEXT: lxvx v2, 0, r3 4871; P9BE-NEXT: blr 4872; 4873; P9LE-LABEL: fromDiffConstsConvdtoll: 4874; P9LE: # %bb.0: # %entry 4875; P9LE-NEXT: addis r3, r2, .LCPI92_0@toc@ha 4876; P9LE-NEXT: addi r3, r3, .LCPI92_0@toc@l 4877; P9LE-NEXT: lxvx v2, 0, r3 4878; P9LE-NEXT: blr 4879; 4880; P8BE-LABEL: fromDiffConstsConvdtoll: 4881; P8BE: # %bb.0: # %entry 4882; P8BE-NEXT: addis r3, r2, .LCPI92_0@toc@ha 4883; P8BE-NEXT: addi r3, r3, .LCPI92_0@toc@l 4884; P8BE-NEXT: lxvd2x v2, 0, r3 4885; P8BE-NEXT: blr 4886; 4887; P8LE-LABEL: fromDiffConstsConvdtoll: 4888; P8LE: # %bb.0: # %entry 4889; P8LE-NEXT: addis r3, r2, .LCPI92_0@toc@ha 4890; P8LE-NEXT: addi r3, r3, .LCPI92_0@toc@l 4891; P8LE-NEXT: lxvd2x vs0, 0, r3 4892; P8LE-NEXT: xxswapd v2, vs0 4893; P8LE-NEXT: blr 4894entry: 4895 ret <2 x i64> <i64 24, i64 234> 4896} 4897 4898; Function Attrs: norecurse nounwind readonly 4899define <2 x i64> @fromDiffMemConsAConvdtoll(double* nocapture readonly %ptr) { 4900; P9BE-LABEL: fromDiffMemConsAConvdtoll: 4901; P9BE: # %bb.0: # %entry 4902; P9BE-NEXT: lxv vs0, 0(r3) 4903; P9BE-NEXT: xvcvdpsxds v2, vs0 4904; P9BE-NEXT: blr 4905; 4906; P9LE-LABEL: fromDiffMemConsAConvdtoll: 4907; P9LE: # %bb.0: # %entry 4908; P9LE-NEXT: lxv vs0, 0(r3) 4909; P9LE-NEXT: xvcvdpsxds v2, vs0 4910; P9LE-NEXT: blr 4911; 4912; P8BE-LABEL: fromDiffMemConsAConvdtoll: 4913; P8BE: # %bb.0: # %entry 4914; P8BE-NEXT: lxvd2x vs0, 0, r3 4915; P8BE-NEXT: xvcvdpsxds v2, vs0 4916; P8BE-NEXT: blr 4917; 4918; P8LE-LABEL: fromDiffMemConsAConvdtoll: 4919; P8LE: # %bb.0: # %entry 4920; P8LE-NEXT: lxvd2x vs0, 0, r3 4921; P8LE-NEXT: xxswapd vs0, vs0 4922; P8LE-NEXT: xvcvdpsxds v2, vs0 4923; P8LE-NEXT: blr 4924entry: 4925 %0 = bitcast double* %ptr to <2 x double>* 4926 %1 = load <2 x double>, <2 x double>* %0, align 8 4927 %2 = fptosi <2 x double> %1 to <2 x i64> 4928 ret <2 x i64> %2 4929} 4930 4931; Function Attrs: norecurse nounwind readonly 4932define <2 x i64> @fromDiffMemConsDConvdtoll(double* nocapture readonly %ptr) { 4933; P9BE-LABEL: fromDiffMemConsDConvdtoll: 4934; P9BE: # %bb.0: # %entry 4935; P9BE-NEXT: lxv vs0, 16(r3) 4936; P9BE-NEXT: xxswapd vs0, vs0 4937; P9BE-NEXT: xvcvdpsxds v2, vs0 4938; P9BE-NEXT: blr 4939; 4940; P9LE-LABEL: fromDiffMemConsDConvdtoll: 4941; P9LE: # %bb.0: # %entry 4942; P9LE-NEXT: addi r3, r3, 16 4943; P9LE-NEXT: lxvd2x vs0, 0, r3 4944; P9LE-NEXT: xvcvdpsxds v2, vs0 4945; P9LE-NEXT: blr 4946; 4947; P8BE-LABEL: fromDiffMemConsDConvdtoll: 4948; P8BE: # %bb.0: # %entry 4949; P8BE-NEXT: addi r3, r3, 16 4950; P8BE-NEXT: lxvd2x vs0, 0, r3 4951; P8BE-NEXT: xxswapd vs0, vs0 4952; P8BE-NEXT: xvcvdpsxds v2, vs0 4953; P8BE-NEXT: blr 4954; 4955; P8LE-LABEL: fromDiffMemConsDConvdtoll: 4956; P8LE: # %bb.0: # %entry 4957; P8LE-NEXT: addi r3, r3, 16 4958; P8LE-NEXT: lxvd2x vs0, 0, r3 4959; P8LE-NEXT: xvcvdpsxds v2, vs0 4960; P8LE-NEXT: blr 4961entry: 4962 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 4963 %0 = load double, double* %arrayidx, align 8 4964 %conv = fptosi double %0 to i64 4965 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4966 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 4967 %1 = load double, double* %arrayidx1, align 8 4968 %conv2 = fptosi double %1 to i64 4969 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4970 ret <2 x i64> %vecinit3 4971} 4972 4973; Function Attrs: norecurse nounwind readonly 4974define <2 x i64> @fromDiffMemVarAConvdtoll(double* nocapture readonly %arr, i32 signext %elem) { 4975; P9BE-LABEL: fromDiffMemVarAConvdtoll: 4976; P9BE: # %bb.0: # %entry 4977; P9BE-NEXT: sldi r4, r4, 3 4978; P9BE-NEXT: lxvx vs0, r3, r4 4979; P9BE-NEXT: xvcvdpsxds v2, vs0 4980; P9BE-NEXT: blr 4981; 4982; P9LE-LABEL: fromDiffMemVarAConvdtoll: 4983; P9LE: # %bb.0: # %entry 4984; P9LE-NEXT: sldi r4, r4, 3 4985; P9LE-NEXT: lxvx vs0, r3, r4 4986; P9LE-NEXT: xvcvdpsxds v2, vs0 4987; P9LE-NEXT: blr 4988; 4989; P8BE-LABEL: fromDiffMemVarAConvdtoll: 4990; P8BE: # %bb.0: # %entry 4991; P8BE-NEXT: sldi r4, r4, 3 4992; P8BE-NEXT: lxvd2x vs0, r3, r4 4993; P8BE-NEXT: xvcvdpsxds v2, vs0 4994; P8BE-NEXT: blr 4995; 4996; P8LE-LABEL: fromDiffMemVarAConvdtoll: 4997; P8LE: # %bb.0: # %entry 4998; P8LE-NEXT: sldi r4, r4, 3 4999; P8LE-NEXT: lxvd2x vs0, r3, r4 5000; P8LE-NEXT: xxswapd vs0, vs0 5001; P8LE-NEXT: xvcvdpsxds v2, vs0 5002; P8LE-NEXT: blr 5003entry: 5004 %idxprom = sext i32 %elem to i64 5005 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 5006 %0 = load double, double* %arrayidx, align 8 5007 %conv = fptosi double %0 to i64 5008 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5009 %add = add nsw i32 %elem, 1 5010 %idxprom1 = sext i32 %add to i64 5011 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 5012 %1 = load double, double* %arrayidx2, align 8 5013 %conv3 = fptosi double %1 to i64 5014 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 5015 ret <2 x i64> %vecinit4 5016} 5017 5018; Function Attrs: norecurse nounwind readonly 5019define <2 x i64> @fromDiffMemVarDConvdtoll(double* nocapture readonly %arr, i32 signext %elem) { 5020; P9BE-LABEL: fromDiffMemVarDConvdtoll: 5021; P9BE: # %bb.0: # %entry 5022; P9BE-NEXT: sldi r4, r4, 3 5023; P9BE-NEXT: add r3, r3, r4 5024; P9BE-NEXT: li r4, -8 5025; P9BE-NEXT: lxvx vs0, r3, r4 5026; P9BE-NEXT: xxswapd vs0, vs0 5027; P9BE-NEXT: xvcvdpsxds v2, vs0 5028; P9BE-NEXT: blr 5029; 5030; P9LE-LABEL: fromDiffMemVarDConvdtoll: 5031; P9LE: # %bb.0: # %entry 5032; P9LE-NEXT: sldi r4, r4, 3 5033; P9LE-NEXT: add r3, r3, r4 5034; P9LE-NEXT: addi r3, r3, -8 5035; P9LE-NEXT: lxvd2x vs0, 0, r3 5036; P9LE-NEXT: xvcvdpsxds v2, vs0 5037; P9LE-NEXT: blr 5038; 5039; P8BE-LABEL: fromDiffMemVarDConvdtoll: 5040; P8BE: # %bb.0: # %entry 5041; P8BE-NEXT: sldi r4, r4, 3 5042; P8BE-NEXT: add r3, r3, r4 5043; P8BE-NEXT: addi r3, r3, -8 5044; P8BE-NEXT: lxvd2x vs0, 0, r3 5045; P8BE-NEXT: xxswapd vs0, vs0 5046; P8BE-NEXT: xvcvdpsxds v2, vs0 5047; P8BE-NEXT: blr 5048; 5049; P8LE-LABEL: fromDiffMemVarDConvdtoll: 5050; P8LE: # %bb.0: # %entry 5051; P8LE-NEXT: sldi r4, r4, 3 5052; P8LE-NEXT: add r3, r3, r4 5053; P8LE-NEXT: addi r3, r3, -8 5054; P8LE-NEXT: lxvd2x vs0, 0, r3 5055; P8LE-NEXT: xvcvdpsxds v2, vs0 5056; P8LE-NEXT: blr 5057entry: 5058 %idxprom = sext i32 %elem to i64 5059 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 5060 %0 = load double, double* %arrayidx, align 8 5061 %conv = fptosi double %0 to i64 5062 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5063 %sub = add nsw i32 %elem, -1 5064 %idxprom1 = sext i32 %sub to i64 5065 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 5066 %1 = load double, double* %arrayidx2, align 8 5067 %conv3 = fptosi double %1 to i64 5068 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 5069 ret <2 x i64> %vecinit4 5070} 5071 5072; Function Attrs: norecurse nounwind readnone 5073define <2 x i64> @spltRegValConvdtoll(double %val) { 5074; P9BE-LABEL: spltRegValConvdtoll: 5075; P9BE: # %bb.0: # %entry 5076; P9BE-NEXT: xscvdpsxds f0, f1 5077; P9BE-NEXT: xxspltd v2, vs0, 0 5078; P9BE-NEXT: blr 5079; 5080; P9LE-LABEL: spltRegValConvdtoll: 5081; P9LE: # %bb.0: # %entry 5082; P9LE-NEXT: xscvdpsxds f0, f1 5083; P9LE-NEXT: xxspltd v2, vs0, 0 5084; P9LE-NEXT: blr 5085; 5086; P8BE-LABEL: spltRegValConvdtoll: 5087; P8BE: # %bb.0: # %entry 5088; P8BE-NEXT: xscvdpsxds f0, f1 5089; P8BE-NEXT: xxspltd v2, vs0, 0 5090; P8BE-NEXT: blr 5091; 5092; P8LE-LABEL: spltRegValConvdtoll: 5093; P8LE: # %bb.0: # %entry 5094; P8LE-NEXT: xscvdpsxds f0, f1 5095; P8LE-NEXT: xxspltd v2, vs0, 0 5096; P8LE-NEXT: blr 5097entry: 5098 %conv = fptosi double %val to i64 5099 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 5100 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5101 ret <2 x i64> %splat.splat 5102} 5103 5104; Function Attrs: norecurse nounwind readonly 5105define <2 x i64> @spltMemValConvdtoll(double* nocapture readonly %ptr) { 5106; P9BE-LABEL: spltMemValConvdtoll: 5107; P9BE: # %bb.0: # %entry 5108; P9BE-NEXT: lxvdsx vs0, 0, r3 5109; P9BE-NEXT: xvcvdpsxds v2, vs0 5110; P9BE-NEXT: blr 5111; 5112; P9LE-LABEL: spltMemValConvdtoll: 5113; P9LE: # %bb.0: # %entry 5114; P9LE-NEXT: lxvdsx vs0, 0, r3 5115; P9LE-NEXT: xvcvdpsxds v2, vs0 5116; P9LE-NEXT: blr 5117; 5118; P8BE-LABEL: spltMemValConvdtoll: 5119; P8BE: # %bb.0: # %entry 5120; P8BE-NEXT: lxvdsx vs0, 0, r3 5121; P8BE-NEXT: xvcvdpsxds v2, vs0 5122; P8BE-NEXT: blr 5123; 5124; P8LE-LABEL: spltMemValConvdtoll: 5125; P8LE: # %bb.0: # %entry 5126; P8LE-NEXT: lxvdsx vs0, 0, r3 5127; P8LE-NEXT: xvcvdpsxds v2, vs0 5128; P8LE-NEXT: blr 5129entry: 5130 %0 = load double, double* %ptr, align 8 5131 %conv = fptosi double %0 to i64 5132 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 5133 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5134 ret <2 x i64> %splat.splat 5135} 5136 5137; Function Attrs: norecurse nounwind readnone 5138define <2 x i64> @allZeroull() { 5139; P9BE-LABEL: allZeroull: 5140; P9BE: # %bb.0: # %entry 5141; P9BE-NEXT: xxlxor v2, v2, v2 5142; P9BE-NEXT: blr 5143; 5144; P9LE-LABEL: allZeroull: 5145; P9LE: # %bb.0: # %entry 5146; P9LE-NEXT: xxlxor v2, v2, v2 5147; P9LE-NEXT: blr 5148; 5149; P8BE-LABEL: allZeroull: 5150; P8BE: # %bb.0: # %entry 5151; P8BE-NEXT: xxlxor v2, v2, v2 5152; P8BE-NEXT: blr 5153; 5154; P8LE-LABEL: allZeroull: 5155; P8LE: # %bb.0: # %entry 5156; P8LE-NEXT: xxlxor v2, v2, v2 5157; P8LE-NEXT: blr 5158entry: 5159 ret <2 x i64> zeroinitializer 5160} 5161 5162; Function Attrs: norecurse nounwind readnone 5163define <2 x i64> @allOneull() { 5164; P9BE-LABEL: allOneull: 5165; P9BE: # %bb.0: # %entry 5166; P9BE-NEXT: xxspltib v2, 255 5167; P9BE-NEXT: blr 5168; 5169; P9LE-LABEL: allOneull: 5170; P9LE: # %bb.0: # %entry 5171; P9LE-NEXT: xxspltib v2, 255 5172; P9LE-NEXT: blr 5173; 5174; P8BE-LABEL: allOneull: 5175; P8BE: # %bb.0: # %entry 5176; P8BE-NEXT: vspltisb v2, -1 5177; P8BE-NEXT: blr 5178; 5179; P8LE-LABEL: allOneull: 5180; P8LE: # %bb.0: # %entry 5181; P8LE-NEXT: vspltisb v2, -1 5182; P8LE-NEXT: blr 5183entry: 5184 ret <2 x i64> <i64 -1, i64 -1> 5185} 5186 5187; Function Attrs: norecurse nounwind readnone 5188define <2 x i64> @spltConst1ull() { 5189; P9BE-LABEL: spltConst1ull: 5190; P9BE: # %bb.0: # %entry 5191; P9BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5192; P9BE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5193; P9BE-NEXT: lxvx v2, 0, r3 5194; P9BE-NEXT: blr 5195; 5196; P9LE-LABEL: spltConst1ull: 5197; P9LE: # %bb.0: # %entry 5198; P9LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5199; P9LE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5200; P9LE-NEXT: lxvx v2, 0, r3 5201; P9LE-NEXT: blr 5202; 5203; P8BE-LABEL: spltConst1ull: 5204; P8BE: # %bb.0: # %entry 5205; P8BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5206; P8BE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5207; P8BE-NEXT: lxvd2x v2, 0, r3 5208; P8BE-NEXT: blr 5209; 5210; P8LE-LABEL: spltConst1ull: 5211; P8LE: # %bb.0: # %entry 5212; P8LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5213; P8LE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5214; P8LE-NEXT: lxvd2x vs0, 0, r3 5215; P8LE-NEXT: xxswapd v2, vs0 5216; P8LE-NEXT: blr 5217entry: 5218 ret <2 x i64> <i64 1, i64 1> 5219} 5220 5221; Function Attrs: norecurse nounwind readnone 5222define <2 x i64> @spltConst16kull() { 5223; P9BE-LABEL: spltConst16kull: 5224; P9BE: # %bb.0: # %entry 5225; P9BE-NEXT: addis r3, r2, .LCPI102_0@toc@ha 5226; P9BE-NEXT: addi r3, r3, .LCPI102_0@toc@l 5227; P9BE-NEXT: lxvx v2, 0, r3 5228; P9BE-NEXT: blr 5229; 5230; P9LE-LABEL: spltConst16kull: 5231; P9LE: # %bb.0: # %entry 5232; P9LE-NEXT: addis r3, r2, .LCPI102_0@toc@ha 5233; P9LE-NEXT: addi r3, r3, .LCPI102_0@toc@l 5234; P9LE-NEXT: lxvx v2, 0, r3 5235; P9LE-NEXT: blr 5236; 5237; P8BE-LABEL: spltConst16kull: 5238; P8BE: # %bb.0: # %entry 5239; P8BE-NEXT: addis r3, r2, .LCPI102_0@toc@ha 5240; P8BE-NEXT: addi r3, r3, .LCPI102_0@toc@l 5241; P8BE-NEXT: lxvd2x v2, 0, r3 5242; P8BE-NEXT: blr 5243; 5244; P8LE-LABEL: spltConst16kull: 5245; P8LE: # %bb.0: # %entry 5246; P8LE-NEXT: addis r3, r2, .LCPI102_0@toc@ha 5247; P8LE-NEXT: addi r3, r3, .LCPI102_0@toc@l 5248; P8LE-NEXT: lxvd2x vs0, 0, r3 5249; P8LE-NEXT: xxswapd v2, vs0 5250; P8LE-NEXT: blr 5251entry: 5252 ret <2 x i64> <i64 32767, i64 32767> 5253} 5254 5255; Function Attrs: norecurse nounwind readnone 5256define <2 x i64> @spltConst32kull() { 5257; P9BE-LABEL: spltConst32kull: 5258; P9BE: # %bb.0: # %entry 5259; P9BE-NEXT: addis r3, r2, .LCPI103_0@toc@ha 5260; P9BE-NEXT: addi r3, r3, .LCPI103_0@toc@l 5261; P9BE-NEXT: lxvx v2, 0, r3 5262; P9BE-NEXT: blr 5263; 5264; P9LE-LABEL: spltConst32kull: 5265; P9LE: # %bb.0: # %entry 5266; P9LE-NEXT: addis r3, r2, .LCPI103_0@toc@ha 5267; P9LE-NEXT: addi r3, r3, .LCPI103_0@toc@l 5268; P9LE-NEXT: lxvx v2, 0, r3 5269; P9LE-NEXT: blr 5270; 5271; P8BE-LABEL: spltConst32kull: 5272; P8BE: # %bb.0: # %entry 5273; P8BE-NEXT: addis r3, r2, .LCPI103_0@toc@ha 5274; P8BE-NEXT: addi r3, r3, .LCPI103_0@toc@l 5275; P8BE-NEXT: lxvd2x v2, 0, r3 5276; P8BE-NEXT: blr 5277; 5278; P8LE-LABEL: spltConst32kull: 5279; P8LE: # %bb.0: # %entry 5280; P8LE-NEXT: addis r3, r2, .LCPI103_0@toc@ha 5281; P8LE-NEXT: addi r3, r3, .LCPI103_0@toc@l 5282; P8LE-NEXT: lxvd2x vs0, 0, r3 5283; P8LE-NEXT: xxswapd v2, vs0 5284; P8LE-NEXT: blr 5285entry: 5286 ret <2 x i64> <i64 65535, i64 65535> 5287} 5288 5289; Function Attrs: norecurse nounwind readnone 5290define <2 x i64> @fromRegsull(i64 %a, i64 %b) { 5291; P9BE-LABEL: fromRegsull: 5292; P9BE: # %bb.0: # %entry 5293; P9BE-NEXT: mtvsrdd v2, r3, r4 5294; P9BE-NEXT: blr 5295; 5296; P9LE-LABEL: fromRegsull: 5297; P9LE: # %bb.0: # %entry 5298; P9LE-NEXT: mtvsrdd v2, r4, r3 5299; P9LE-NEXT: blr 5300; 5301; P8BE-LABEL: fromRegsull: 5302; P8BE: # %bb.0: # %entry 5303; P8BE-NEXT: mtvsrd f0, r4 5304; P8BE-NEXT: mtvsrd f1, r3 5305; P8BE-NEXT: xxmrghd v2, vs1, vs0 5306; P8BE-NEXT: blr 5307; 5308; P8LE-LABEL: fromRegsull: 5309; P8LE: # %bb.0: # %entry 5310; P8LE-NEXT: mtvsrd f0, r3 5311; P8LE-NEXT: mtvsrd f1, r4 5312; P8LE-NEXT: xxmrghd v2, vs1, vs0 5313; P8LE-NEXT: blr 5314entry: 5315 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 5316 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 5317 ret <2 x i64> %vecinit1 5318} 5319 5320; Function Attrs: norecurse nounwind readnone 5321define <2 x i64> @fromDiffConstsull() { 5322; P9BE-LABEL: fromDiffConstsull: 5323; P9BE: # %bb.0: # %entry 5324; P9BE-NEXT: addis r3, r2, .LCPI105_0@toc@ha 5325; P9BE-NEXT: addi r3, r3, .LCPI105_0@toc@l 5326; P9BE-NEXT: lxvx v2, 0, r3 5327; P9BE-NEXT: blr 5328; 5329; P9LE-LABEL: fromDiffConstsull: 5330; P9LE: # %bb.0: # %entry 5331; P9LE-NEXT: addis r3, r2, .LCPI105_0@toc@ha 5332; P9LE-NEXT: addi r3, r3, .LCPI105_0@toc@l 5333; P9LE-NEXT: lxvx v2, 0, r3 5334; P9LE-NEXT: blr 5335; 5336; P8BE-LABEL: fromDiffConstsull: 5337; P8BE: # %bb.0: # %entry 5338; P8BE-NEXT: addis r3, r2, .LCPI105_0@toc@ha 5339; P8BE-NEXT: addi r3, r3, .LCPI105_0@toc@l 5340; P8BE-NEXT: lxvd2x v2, 0, r3 5341; P8BE-NEXT: blr 5342; 5343; P8LE-LABEL: fromDiffConstsull: 5344; P8LE: # %bb.0: # %entry 5345; P8LE-NEXT: addis r3, r2, .LCPI105_0@toc@ha 5346; P8LE-NEXT: addi r3, r3, .LCPI105_0@toc@l 5347; P8LE-NEXT: lxvd2x vs0, 0, r3 5348; P8LE-NEXT: xxswapd v2, vs0 5349; P8LE-NEXT: blr 5350entry: 5351 ret <2 x i64> <i64 242, i64 -113> 5352} 5353 5354; Function Attrs: norecurse nounwind readonly 5355define <2 x i64> @fromDiffMemConsAull(i64* nocapture readonly %arr) { 5356; P9BE-LABEL: fromDiffMemConsAull: 5357; P9BE: # %bb.0: # %entry 5358; P9BE-NEXT: lxv v2, 0(r3) 5359; P9BE-NEXT: blr 5360; 5361; P9LE-LABEL: fromDiffMemConsAull: 5362; P9LE: # %bb.0: # %entry 5363; P9LE-NEXT: lxv v2, 0(r3) 5364; P9LE-NEXT: blr 5365; 5366; P8BE-LABEL: fromDiffMemConsAull: 5367; P8BE: # %bb.0: # %entry 5368; P8BE-NEXT: lxvd2x v2, 0, r3 5369; P8BE-NEXT: blr 5370; 5371; P8LE-LABEL: fromDiffMemConsAull: 5372; P8LE: # %bb.0: # %entry 5373; P8LE-NEXT: lxvd2x vs0, 0, r3 5374; P8LE-NEXT: xxswapd v2, vs0 5375; P8LE-NEXT: blr 5376entry: 5377 %0 = load i64, i64* %arr, align 8 5378 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5379 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 1 5380 %1 = load i64, i64* %arrayidx1, align 8 5381 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5382 ret <2 x i64> %vecinit2 5383} 5384 5385; Function Attrs: norecurse nounwind readonly 5386define <2 x i64> @fromDiffMemConsDull(i64* nocapture readonly %arr) { 5387; P9BE-LABEL: fromDiffMemConsDull: 5388; P9BE: # %bb.0: # %entry 5389; P9BE-NEXT: lxv v2, 16(r3) 5390; P9BE-NEXT: xxswapd v2, v2 5391; P9BE-NEXT: blr 5392; 5393; P9LE-LABEL: fromDiffMemConsDull: 5394; P9LE: # %bb.0: # %entry 5395; P9LE-NEXT: addi r3, r3, 16 5396; P9LE-NEXT: lxvd2x v2, 0, r3 5397; P9LE-NEXT: blr 5398; 5399; P8BE-LABEL: fromDiffMemConsDull: 5400; P8BE: # %bb.0: # %entry 5401; P8BE-NEXT: addi r3, r3, 16 5402; P8BE-NEXT: lxvd2x v2, 0, r3 5403; P8BE-NEXT: xxswapd v2, v2 5404; P8BE-NEXT: blr 5405; 5406; P8LE-LABEL: fromDiffMemConsDull: 5407; P8LE: # %bb.0: # %entry 5408; P8LE-NEXT: addi r3, r3, 16 5409; P8LE-NEXT: lxvd2x v2, 0, r3 5410; P8LE-NEXT: blr 5411entry: 5412 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 3 5413 %0 = load i64, i64* %arrayidx, align 8 5414 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5415 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 2 5416 %1 = load i64, i64* %arrayidx1, align 8 5417 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5418 ret <2 x i64> %vecinit2 5419} 5420 5421; Function Attrs: norecurse nounwind readonly 5422define <2 x i64> @fromDiffMemVarAull(i64* nocapture readonly %arr, i32 signext %elem) { 5423; P9BE-LABEL: fromDiffMemVarAull: 5424; P9BE: # %bb.0: # %entry 5425; P9BE-NEXT: sldi r4, r4, 3 5426; P9BE-NEXT: lxvx v2, r3, r4 5427; P9BE-NEXT: blr 5428; 5429; P9LE-LABEL: fromDiffMemVarAull: 5430; P9LE: # %bb.0: # %entry 5431; P9LE-NEXT: sldi r4, r4, 3 5432; P9LE-NEXT: lxvx v2, r3, r4 5433; P9LE-NEXT: blr 5434; 5435; P8BE-LABEL: fromDiffMemVarAull: 5436; P8BE: # %bb.0: # %entry 5437; P8BE-NEXT: sldi r4, r4, 3 5438; P8BE-NEXT: lxvd2x v2, r3, r4 5439; P8BE-NEXT: blr 5440; 5441; P8LE-LABEL: fromDiffMemVarAull: 5442; P8LE: # %bb.0: # %entry 5443; P8LE-NEXT: sldi r4, r4, 3 5444; P8LE-NEXT: lxvd2x vs0, r3, r4 5445; P8LE-NEXT: xxswapd v2, vs0 5446; P8LE-NEXT: blr 5447entry: 5448 %idxprom = sext i32 %elem to i64 5449 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 5450 %0 = load i64, i64* %arrayidx, align 8 5451 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5452 %add = add nsw i32 %elem, 1 5453 %idxprom1 = sext i32 %add to i64 5454 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 5455 %1 = load i64, i64* %arrayidx2, align 8 5456 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5457 ret <2 x i64> %vecinit3 5458} 5459 5460; Function Attrs: norecurse nounwind readonly 5461define <2 x i64> @fromDiffMemVarDull(i64* nocapture readonly %arr, i32 signext %elem) { 5462; P9BE-LABEL: fromDiffMemVarDull: 5463; P9BE: # %bb.0: # %entry 5464; P9BE-NEXT: sldi r4, r4, 3 5465; P9BE-NEXT: add r3, r3, r4 5466; P9BE-NEXT: li r4, -8 5467; P9BE-NEXT: lxvx v2, r3, r4 5468; P9BE-NEXT: xxswapd v2, v2 5469; P9BE-NEXT: blr 5470; 5471; P9LE-LABEL: fromDiffMemVarDull: 5472; P9LE: # %bb.0: # %entry 5473; P9LE-NEXT: sldi r4, r4, 3 5474; P9LE-NEXT: add r3, r3, r4 5475; P9LE-NEXT: addi r3, r3, -8 5476; P9LE-NEXT: lxvd2x v2, 0, r3 5477; P9LE-NEXT: blr 5478; 5479; P8BE-LABEL: fromDiffMemVarDull: 5480; P8BE: # %bb.0: # %entry 5481; P8BE-NEXT: sldi r4, r4, 3 5482; P8BE-NEXT: add r3, r3, r4 5483; P8BE-NEXT: addi r3, r3, -8 5484; P8BE-NEXT: lxvd2x v2, 0, r3 5485; P8BE-NEXT: xxswapd v2, v2 5486; P8BE-NEXT: blr 5487; 5488; P8LE-LABEL: fromDiffMemVarDull: 5489; P8LE: # %bb.0: # %entry 5490; P8LE-NEXT: sldi r4, r4, 3 5491; P8LE-NEXT: add r3, r3, r4 5492; P8LE-NEXT: addi r3, r3, -8 5493; P8LE-NEXT: lxvd2x v2, 0, r3 5494; P8LE-NEXT: blr 5495entry: 5496 %idxprom = sext i32 %elem to i64 5497 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 5498 %0 = load i64, i64* %arrayidx, align 8 5499 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5500 %sub = add nsw i32 %elem, -1 5501 %idxprom1 = sext i32 %sub to i64 5502 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 5503 %1 = load i64, i64* %arrayidx2, align 8 5504 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5505 ret <2 x i64> %vecinit3 5506} 5507 5508; Function Attrs: norecurse nounwind readonly 5509define <2 x i64> @fromRandMemConsull(i64* nocapture readonly %arr) { 5510; P9BE-LABEL: fromRandMemConsull: 5511; P9BE: # %bb.0: # %entry 5512; P9BE-NEXT: ld r4, 32(r3) 5513; P9BE-NEXT: ld r3, 144(r3) 5514; P9BE-NEXT: mtvsrdd v2, r4, r3 5515; P9BE-NEXT: blr 5516; 5517; P9LE-LABEL: fromRandMemConsull: 5518; P9LE: # %bb.0: # %entry 5519; P9LE-NEXT: ld r4, 32(r3) 5520; P9LE-NEXT: ld r3, 144(r3) 5521; P9LE-NEXT: mtvsrdd v2, r3, r4 5522; P9LE-NEXT: blr 5523; 5524; P8BE-LABEL: fromRandMemConsull: 5525; P8BE: # %bb.0: # %entry 5526; P8BE-NEXT: ld r4, 144(r3) 5527; P8BE-NEXT: ld r3, 32(r3) 5528; P8BE-NEXT: mtvsrd f0, r4 5529; P8BE-NEXT: mtvsrd f1, r3 5530; P8BE-NEXT: xxmrghd v2, vs1, vs0 5531; P8BE-NEXT: blr 5532; 5533; P8LE-LABEL: fromRandMemConsull: 5534; P8LE: # %bb.0: # %entry 5535; P8LE-NEXT: ld r4, 32(r3) 5536; P8LE-NEXT: ld r3, 144(r3) 5537; P8LE-NEXT: mtvsrd f0, r4 5538; P8LE-NEXT: mtvsrd f1, r3 5539; P8LE-NEXT: xxmrghd v2, vs1, vs0 5540; P8LE-NEXT: blr 5541entry: 5542 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4 5543 %0 = load i64, i64* %arrayidx, align 8 5544 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5545 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18 5546 %1 = load i64, i64* %arrayidx1, align 8 5547 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5548 ret <2 x i64> %vecinit2 5549} 5550 5551; Function Attrs: norecurse nounwind readonly 5552define <2 x i64> @fromRandMemVarull(i64* nocapture readonly %arr, i32 signext %elem) { 5553; P9BE-LABEL: fromRandMemVarull: 5554; P9BE: # %bb.0: # %entry 5555; P9BE-NEXT: sldi r4, r4, 3 5556; P9BE-NEXT: add r3, r3, r4 5557; P9BE-NEXT: ld r4, 32(r3) 5558; P9BE-NEXT: ld r3, 8(r3) 5559; P9BE-NEXT: mtvsrdd v2, r4, r3 5560; P9BE-NEXT: blr 5561; 5562; P9LE-LABEL: fromRandMemVarull: 5563; P9LE: # %bb.0: # %entry 5564; P9LE-NEXT: sldi r4, r4, 3 5565; P9LE-NEXT: add r3, r3, r4 5566; P9LE-NEXT: ld r4, 32(r3) 5567; P9LE-NEXT: ld r3, 8(r3) 5568; P9LE-NEXT: mtvsrdd v2, r3, r4 5569; P9LE-NEXT: blr 5570; 5571; P8BE-LABEL: fromRandMemVarull: 5572; P8BE: # %bb.0: # %entry 5573; P8BE-NEXT: sldi r4, r4, 3 5574; P8BE-NEXT: add r3, r3, r4 5575; P8BE-NEXT: ld r4, 8(r3) 5576; P8BE-NEXT: ld r3, 32(r3) 5577; P8BE-NEXT: mtvsrd f0, r4 5578; P8BE-NEXT: mtvsrd f1, r3 5579; P8BE-NEXT: xxmrghd v2, vs1, vs0 5580; P8BE-NEXT: blr 5581; 5582; P8LE-LABEL: fromRandMemVarull: 5583; P8LE: # %bb.0: # %entry 5584; P8LE-NEXT: sldi r4, r4, 3 5585; P8LE-NEXT: add r3, r3, r4 5586; P8LE-NEXT: ld r4, 32(r3) 5587; P8LE-NEXT: ld r3, 8(r3) 5588; P8LE-NEXT: mtvsrd f0, r4 5589; P8LE-NEXT: mtvsrd f1, r3 5590; P8LE-NEXT: xxmrghd v2, vs1, vs0 5591; P8LE-NEXT: blr 5592entry: 5593 %add = add nsw i32 %elem, 4 5594 %idxprom = sext i32 %add to i64 5595 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 5596 %0 = load i64, i64* %arrayidx, align 8 5597 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5598 %add1 = add nsw i32 %elem, 1 5599 %idxprom2 = sext i32 %add1 to i64 5600 %arrayidx3 = getelementptr inbounds i64, i64* %arr, i64 %idxprom2 5601 %1 = load i64, i64* %arrayidx3, align 8 5602 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5603 ret <2 x i64> %vecinit4 5604} 5605 5606; Function Attrs: norecurse nounwind readnone 5607define <2 x i64> @spltRegValull(i64 %val) { 5608; P9BE-LABEL: spltRegValull: 5609; P9BE: # %bb.0: # %entry 5610; P9BE-NEXT: mtvsrdd v2, r3, r3 5611; P9BE-NEXT: blr 5612; 5613; P9LE-LABEL: spltRegValull: 5614; P9LE: # %bb.0: # %entry 5615; P9LE-NEXT: mtvsrdd v2, r3, r3 5616; P9LE-NEXT: blr 5617; 5618; P8BE-LABEL: spltRegValull: 5619; P8BE: # %bb.0: # %entry 5620; P8BE-NEXT: mtvsrd f0, r3 5621; P8BE-NEXT: xxspltd v2, vs0, 0 5622; P8BE-NEXT: blr 5623; 5624; P8LE-LABEL: spltRegValull: 5625; P8LE: # %bb.0: # %entry 5626; P8LE-NEXT: mtvsrd f0, r3 5627; P8LE-NEXT: xxspltd v2, vs0, 0 5628; P8LE-NEXT: blr 5629entry: 5630 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0 5631 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5632 ret <2 x i64> %splat.splat 5633} 5634 5635; Function Attrs: norecurse nounwind readonly 5636define <2 x i64> @spltMemValull(i64* nocapture readonly %ptr) { 5637; P9BE-LABEL: spltMemValull: 5638; P9BE: # %bb.0: # %entry 5639; P9BE-NEXT: lxvdsx v2, 0, r3 5640; P9BE-NEXT: blr 5641; 5642; P9LE-LABEL: spltMemValull: 5643; P9LE: # %bb.0: # %entry 5644; P9LE-NEXT: lxvdsx v2, 0, r3 5645; P9LE-NEXT: blr 5646; 5647; P8BE-LABEL: spltMemValull: 5648; P8BE: # %bb.0: # %entry 5649; P8BE-NEXT: lxvdsx v2, 0, r3 5650; P8BE-NEXT: blr 5651; 5652; P8LE-LABEL: spltMemValull: 5653; P8LE: # %bb.0: # %entry 5654; P8LE-NEXT: lxvdsx v2, 0, r3 5655; P8LE-NEXT: blr 5656entry: 5657 %0 = load i64, i64* %ptr, align 8 5658 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 5659 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5660 ret <2 x i64> %splat.splat 5661} 5662 5663; Function Attrs: norecurse nounwind readnone 5664define <2 x i64> @spltCnstConvftoull() { 5665; P9BE-LABEL: spltCnstConvftoull: 5666; P9BE: # %bb.0: # %entry 5667; P9BE-NEXT: addis r3, r2, .LCPI114_0@toc@ha 5668; P9BE-NEXT: addi r3, r3, .LCPI114_0@toc@l 5669; P9BE-NEXT: lxvx v2, 0, r3 5670; P9BE-NEXT: blr 5671; 5672; P9LE-LABEL: spltCnstConvftoull: 5673; P9LE: # %bb.0: # %entry 5674; P9LE-NEXT: addis r3, r2, .LCPI114_0@toc@ha 5675; P9LE-NEXT: addi r3, r3, .LCPI114_0@toc@l 5676; P9LE-NEXT: lxvx v2, 0, r3 5677; P9LE-NEXT: blr 5678; 5679; P8BE-LABEL: spltCnstConvftoull: 5680; P8BE: # %bb.0: # %entry 5681; P8BE-NEXT: addis r3, r2, .LCPI114_0@toc@ha 5682; P8BE-NEXT: addi r3, r3, .LCPI114_0@toc@l 5683; P8BE-NEXT: lxvd2x v2, 0, r3 5684; P8BE-NEXT: blr 5685; 5686; P8LE-LABEL: spltCnstConvftoull: 5687; P8LE: # %bb.0: # %entry 5688; P8LE-NEXT: addis r3, r2, .LCPI114_0@toc@ha 5689; P8LE-NEXT: addi r3, r3, .LCPI114_0@toc@l 5690; P8LE-NEXT: lxvd2x vs0, 0, r3 5691; P8LE-NEXT: xxswapd v2, vs0 5692; P8LE-NEXT: blr 5693entry: 5694 ret <2 x i64> <i64 4, i64 4> 5695} 5696 5697; Function Attrs: norecurse nounwind readnone 5698define <2 x i64> @fromRegsConvftoull(float %a, float %b) { 5699; P9BE-LABEL: fromRegsConvftoull: 5700; P9BE: # %bb.0: # %entry 5701; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5702; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5703; P9BE-NEXT: xxmrghd vs0, vs1, vs2 5704; P9BE-NEXT: xvcvdpuxds v2, vs0 5705; P9BE-NEXT: blr 5706; 5707; P9LE-LABEL: fromRegsConvftoull: 5708; P9LE: # %bb.0: # %entry 5709; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5710; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5711; P9LE-NEXT: xxmrghd vs0, vs2, vs1 5712; P9LE-NEXT: xvcvdpuxds v2, vs0 5713; P9LE-NEXT: blr 5714; 5715; P8BE-LABEL: fromRegsConvftoull: 5716; P8BE: # %bb.0: # %entry 5717; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5718; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5719; P8BE-NEXT: xxmrghd vs0, vs1, vs2 5720; P8BE-NEXT: xvcvdpuxds v2, vs0 5721; P8BE-NEXT: blr 5722; 5723; P8LE-LABEL: fromRegsConvftoull: 5724; P8LE: # %bb.0: # %entry 5725; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5726; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5727; P8LE-NEXT: xxmrghd vs0, vs2, vs1 5728; P8LE-NEXT: xvcvdpuxds v2, vs0 5729; P8LE-NEXT: blr 5730entry: 5731 %conv = fptoui float %a to i64 5732 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5733 %conv1 = fptoui float %b to i64 5734 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 5735 ret <2 x i64> %vecinit2 5736} 5737 5738; Function Attrs: norecurse nounwind readnone 5739define <2 x i64> @fromDiffConstsConvftoull() { 5740; P9BE-LABEL: fromDiffConstsConvftoull: 5741; P9BE: # %bb.0: # %entry 5742; P9BE-NEXT: addis r3, r2, .LCPI116_0@toc@ha 5743; P9BE-NEXT: addi r3, r3, .LCPI116_0@toc@l 5744; P9BE-NEXT: lxvx v2, 0, r3 5745; P9BE-NEXT: blr 5746; 5747; P9LE-LABEL: fromDiffConstsConvftoull: 5748; P9LE: # %bb.0: # %entry 5749; P9LE-NEXT: addis r3, r2, .LCPI116_0@toc@ha 5750; P9LE-NEXT: addi r3, r3, .LCPI116_0@toc@l 5751; P9LE-NEXT: lxvx v2, 0, r3 5752; P9LE-NEXT: blr 5753; 5754; P8BE-LABEL: fromDiffConstsConvftoull: 5755; P8BE: # %bb.0: # %entry 5756; P8BE-NEXT: addis r3, r2, .LCPI116_0@toc@ha 5757; P8BE-NEXT: addi r3, r3, .LCPI116_0@toc@l 5758; P8BE-NEXT: lxvd2x v2, 0, r3 5759; P8BE-NEXT: blr 5760; 5761; P8LE-LABEL: fromDiffConstsConvftoull: 5762; P8LE: # %bb.0: # %entry 5763; P8LE-NEXT: addis r3, r2, .LCPI116_0@toc@ha 5764; P8LE-NEXT: addi r3, r3, .LCPI116_0@toc@l 5765; P8LE-NEXT: lxvd2x vs0, 0, r3 5766; P8LE-NEXT: xxswapd v2, vs0 5767; P8LE-NEXT: blr 5768entry: 5769 ret <2 x i64> <i64 24, i64 234> 5770} 5771 5772; Function Attrs: norecurse nounwind readonly 5773define <2 x i64> @fromDiffMemConsAConvftoull(float* nocapture readonly %ptr) { 5774; P9BE-LABEL: fromDiffMemConsAConvftoull: 5775; P9BE: # %bb.0: # %entry 5776; P9BE-NEXT: lfs f0, 0(r3) 5777; P9BE-NEXT: lfs f1, 4(r3) 5778; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5779; P9BE-NEXT: xvcvdpuxds v2, vs0 5780; P9BE-NEXT: blr 5781; 5782; P9LE-LABEL: fromDiffMemConsAConvftoull: 5783; P9LE: # %bb.0: # %entry 5784; P9LE-NEXT: lfs f0, 0(r3) 5785; P9LE-NEXT: lfs f1, 4(r3) 5786; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5787; P9LE-NEXT: xvcvdpuxds v2, vs0 5788; P9LE-NEXT: blr 5789; 5790; P8BE-LABEL: fromDiffMemConsAConvftoull: 5791; P8BE: # %bb.0: # %entry 5792; P8BE-NEXT: lfsx f0, 0, r3 5793; P8BE-NEXT: lfs f1, 4(r3) 5794; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5795; P8BE-NEXT: xvcvdpuxds v2, vs0 5796; P8BE-NEXT: blr 5797; 5798; P8LE-LABEL: fromDiffMemConsAConvftoull: 5799; P8LE: # %bb.0: # %entry 5800; P8LE-NEXT: lfsx f0, 0, r3 5801; P8LE-NEXT: lfs f1, 4(r3) 5802; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5803; P8LE-NEXT: xvcvdpuxds v2, vs0 5804; P8LE-NEXT: blr 5805entry: 5806 %0 = load float, float* %ptr, align 4 5807 %conv = fptoui float %0 to i64 5808 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5809 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1 5810 %1 = load float, float* %arrayidx1, align 4 5811 %conv2 = fptoui float %1 to i64 5812 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 5813 ret <2 x i64> %vecinit3 5814} 5815 5816; Function Attrs: norecurse nounwind readonly 5817define <2 x i64> @fromDiffMemConsDConvftoull(float* nocapture readonly %ptr) { 5818; P9BE-LABEL: fromDiffMemConsDConvftoull: 5819; P9BE: # %bb.0: # %entry 5820; P9BE-NEXT: lfs f0, 12(r3) 5821; P9BE-NEXT: lfs f1, 8(r3) 5822; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5823; P9BE-NEXT: xvcvdpuxds v2, vs0 5824; P9BE-NEXT: blr 5825; 5826; P9LE-LABEL: fromDiffMemConsDConvftoull: 5827; P9LE: # %bb.0: # %entry 5828; P9LE-NEXT: lfs f0, 12(r3) 5829; P9LE-NEXT: lfs f1, 8(r3) 5830; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5831; P9LE-NEXT: xvcvdpuxds v2, vs0 5832; P9LE-NEXT: blr 5833; 5834; P8BE-LABEL: fromDiffMemConsDConvftoull: 5835; P8BE: # %bb.0: # %entry 5836; P8BE-NEXT: lfs f0, 12(r3) 5837; P8BE-NEXT: lfs f1, 8(r3) 5838; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5839; P8BE-NEXT: xvcvdpuxds v2, vs0 5840; P8BE-NEXT: blr 5841; 5842; P8LE-LABEL: fromDiffMemConsDConvftoull: 5843; P8LE: # %bb.0: # %entry 5844; P8LE-NEXT: lfs f0, 12(r3) 5845; P8LE-NEXT: lfs f1, 8(r3) 5846; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5847; P8LE-NEXT: xvcvdpuxds v2, vs0 5848; P8LE-NEXT: blr 5849entry: 5850 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 5851 %0 = load float, float* %arrayidx, align 4 5852 %conv = fptoui float %0 to i64 5853 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5854 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 5855 %1 = load float, float* %arrayidx1, align 4 5856 %conv2 = fptoui float %1 to i64 5857 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 5858 ret <2 x i64> %vecinit3 5859} 5860 5861; Function Attrs: norecurse nounwind readonly 5862define <2 x i64> @fromDiffMemVarAConvftoull(float* nocapture readonly %arr, i32 signext %elem) { 5863; P9BE-LABEL: fromDiffMemVarAConvftoull: 5864; P9BE: # %bb.0: # %entry 5865; P9BE-NEXT: sldi r4, r4, 2 5866; P9BE-NEXT: lfsux f0, r3, r4 5867; P9BE-NEXT: lfs f1, 4(r3) 5868; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5869; P9BE-NEXT: xvcvdpuxds v2, vs0 5870; P9BE-NEXT: blr 5871; 5872; P9LE-LABEL: fromDiffMemVarAConvftoull: 5873; P9LE: # %bb.0: # %entry 5874; P9LE-NEXT: sldi r4, r4, 2 5875; P9LE-NEXT: lfsux f0, r3, r4 5876; P9LE-NEXT: lfs f1, 4(r3) 5877; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5878; P9LE-NEXT: xvcvdpuxds v2, vs0 5879; P9LE-NEXT: blr 5880; 5881; P8BE-LABEL: fromDiffMemVarAConvftoull: 5882; P8BE: # %bb.0: # %entry 5883; P8BE-NEXT: sldi r4, r4, 2 5884; P8BE-NEXT: lfsux f0, r3, r4 5885; P8BE-NEXT: lfs f1, 4(r3) 5886; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5887; P8BE-NEXT: xvcvdpuxds v2, vs0 5888; P8BE-NEXT: blr 5889; 5890; P8LE-LABEL: fromDiffMemVarAConvftoull: 5891; P8LE: # %bb.0: # %entry 5892; P8LE-NEXT: sldi r4, r4, 2 5893; P8LE-NEXT: lfsux f0, r3, r4 5894; P8LE-NEXT: lfs f1, 4(r3) 5895; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5896; P8LE-NEXT: xvcvdpuxds v2, vs0 5897; P8LE-NEXT: blr 5898entry: 5899 %idxprom = sext i32 %elem to i64 5900 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 5901 %0 = load float, float* %arrayidx, align 4 5902 %conv = fptoui float %0 to i64 5903 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5904 %add = add nsw i32 %elem, 1 5905 %idxprom1 = sext i32 %add to i64 5906 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 5907 %1 = load float, float* %arrayidx2, align 4 5908 %conv3 = fptoui float %1 to i64 5909 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 5910 ret <2 x i64> %vecinit4 5911} 5912 5913; Function Attrs: norecurse nounwind readonly 5914define <2 x i64> @fromDiffMemVarDConvftoull(float* nocapture readonly %arr, i32 signext %elem) { 5915; P9BE-LABEL: fromDiffMemVarDConvftoull: 5916; P9BE: # %bb.0: # %entry 5917; P9BE-NEXT: sldi r4, r4, 2 5918; P9BE-NEXT: lfsux f0, r3, r4 5919; P9BE-NEXT: lfs f1, -4(r3) 5920; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5921; P9BE-NEXT: xvcvdpuxds v2, vs0 5922; P9BE-NEXT: blr 5923; 5924; P9LE-LABEL: fromDiffMemVarDConvftoull: 5925; P9LE: # %bb.0: # %entry 5926; P9LE-NEXT: sldi r4, r4, 2 5927; P9LE-NEXT: lfsux f0, r3, r4 5928; P9LE-NEXT: lfs f1, -4(r3) 5929; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5930; P9LE-NEXT: xvcvdpuxds v2, vs0 5931; P9LE-NEXT: blr 5932; 5933; P8BE-LABEL: fromDiffMemVarDConvftoull: 5934; P8BE: # %bb.0: # %entry 5935; P8BE-NEXT: sldi r4, r4, 2 5936; P8BE-NEXT: lfsux f0, r3, r4 5937; P8BE-NEXT: lfs f1, -4(r3) 5938; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5939; P8BE-NEXT: xvcvdpuxds v2, vs0 5940; P8BE-NEXT: blr 5941; 5942; P8LE-LABEL: fromDiffMemVarDConvftoull: 5943; P8LE: # %bb.0: # %entry 5944; P8LE-NEXT: sldi r4, r4, 2 5945; P8LE-NEXT: lfsux f0, r3, r4 5946; P8LE-NEXT: lfs f1, -4(r3) 5947; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5948; P8LE-NEXT: xvcvdpuxds v2, vs0 5949; P8LE-NEXT: blr 5950entry: 5951 %idxprom = sext i32 %elem to i64 5952 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 5953 %0 = load float, float* %arrayidx, align 4 5954 %conv = fptoui float %0 to i64 5955 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5956 %sub = add nsw i32 %elem, -1 5957 %idxprom1 = sext i32 %sub to i64 5958 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 5959 %1 = load float, float* %arrayidx2, align 4 5960 %conv3 = fptoui float %1 to i64 5961 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 5962 ret <2 x i64> %vecinit4 5963} 5964 5965; Function Attrs: norecurse nounwind readnone 5966define <2 x i64> @spltRegValConvftoull(float %val) { 5967; P9BE-LABEL: spltRegValConvftoull: 5968; P9BE: # %bb.0: # %entry 5969; P9BE-NEXT: xscvdpuxds f0, f1 5970; P9BE-NEXT: xxspltd v2, f0, 0 5971; P9BE-NEXT: blr 5972; 5973; P9LE-LABEL: spltRegValConvftoull: 5974; P9LE: # %bb.0: # %entry 5975; P9LE-NEXT: xscvdpuxds f0, f1 5976; P9LE-NEXT: xxspltd v2, f0, 0 5977; P9LE-NEXT: blr 5978; 5979; P8BE-LABEL: spltRegValConvftoull: 5980; P8BE: # %bb.0: # %entry 5981; P8BE-NEXT: xscvdpuxds f0, f1 5982; P8BE-NEXT: xxspltd v2, f0, 0 5983; P8BE-NEXT: blr 5984; 5985; P8LE-LABEL: spltRegValConvftoull: 5986; P8LE: # %bb.0: # %entry 5987; P8LE-NEXT: xscvdpuxds f0, f1 5988; P8LE-NEXT: xxspltd v2, f0, 0 5989; P8LE-NEXT: blr 5990entry: 5991 %conv = fptoui float %val to i64 5992 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 5993 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5994 ret <2 x i64> %splat.splat 5995} 5996 5997; Function Attrs: norecurse nounwind readonly 5998define <2 x i64> @spltMemValConvftoull(float* nocapture readonly %ptr) { 5999; P9BE-LABEL: spltMemValConvftoull: 6000; P9BE: # %bb.0: # %entry 6001; P9BE-NEXT: lfs f0, 0(r3) 6002; P9BE-NEXT: xscvdpuxds f0, f0 6003; P9BE-NEXT: xxspltd v2, f0, 0 6004; P9BE-NEXT: blr 6005; 6006; P9LE-LABEL: spltMemValConvftoull: 6007; P9LE: # %bb.0: # %entry 6008; P9LE-NEXT: lfs f0, 0(r3) 6009; P9LE-NEXT: xscvdpuxds f0, f0 6010; P9LE-NEXT: xxspltd v2, f0, 0 6011; P9LE-NEXT: blr 6012; 6013; P8BE-LABEL: spltMemValConvftoull: 6014; P8BE: # %bb.0: # %entry 6015; P8BE-NEXT: lfsx f0, 0, r3 6016; P8BE-NEXT: xscvdpuxds f0, f0 6017; P8BE-NEXT: xxspltd v2, f0, 0 6018; P8BE-NEXT: blr 6019; 6020; P8LE-LABEL: spltMemValConvftoull: 6021; P8LE: # %bb.0: # %entry 6022; P8LE-NEXT: lfsx f0, 0, r3 6023; P8LE-NEXT: xscvdpuxds f0, f0 6024; P8LE-NEXT: xxspltd v2, f0, 0 6025; P8LE-NEXT: blr 6026entry: 6027 %0 = load float, float* %ptr, align 4 6028 %conv = fptoui float %0 to i64 6029 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 6030 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 6031 ret <2 x i64> %splat.splat 6032} 6033 6034; Function Attrs: norecurse nounwind readnone 6035define <2 x i64> @spltCnstConvdtoull() { 6036; P9BE-LABEL: spltCnstConvdtoull: 6037; P9BE: # %bb.0: # %entry 6038; P9BE-NEXT: addis r3, r2, .LCPI123_0@toc@ha 6039; P9BE-NEXT: addi r3, r3, .LCPI123_0@toc@l 6040; P9BE-NEXT: lxvx v2, 0, r3 6041; P9BE-NEXT: blr 6042; 6043; P9LE-LABEL: spltCnstConvdtoull: 6044; P9LE: # %bb.0: # %entry 6045; P9LE-NEXT: addis r3, r2, .LCPI123_0@toc@ha 6046; P9LE-NEXT: addi r3, r3, .LCPI123_0@toc@l 6047; P9LE-NEXT: lxvx v2, 0, r3 6048; P9LE-NEXT: blr 6049; 6050; P8BE-LABEL: spltCnstConvdtoull: 6051; P8BE: # %bb.0: # %entry 6052; P8BE-NEXT: addis r3, r2, .LCPI123_0@toc@ha 6053; P8BE-NEXT: addi r3, r3, .LCPI123_0@toc@l 6054; P8BE-NEXT: lxvd2x v2, 0, r3 6055; P8BE-NEXT: blr 6056; 6057; P8LE-LABEL: spltCnstConvdtoull: 6058; P8LE: # %bb.0: # %entry 6059; P8LE-NEXT: addis r3, r2, .LCPI123_0@toc@ha 6060; P8LE-NEXT: addi r3, r3, .LCPI123_0@toc@l 6061; P8LE-NEXT: lxvd2x vs0, 0, r3 6062; P8LE-NEXT: xxswapd v2, vs0 6063; P8LE-NEXT: blr 6064entry: 6065 ret <2 x i64> <i64 4, i64 4> 6066} 6067 6068; Function Attrs: norecurse nounwind readnone 6069define <2 x i64> @fromRegsConvdtoull(double %a, double %b) { 6070; P9BE-LABEL: fromRegsConvdtoull: 6071; P9BE: # %bb.0: # %entry 6072; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 6073; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 6074; P9BE-NEXT: xxmrghd vs0, vs1, vs2 6075; P9BE-NEXT: xvcvdpuxds v2, vs0 6076; P9BE-NEXT: blr 6077; 6078; P9LE-LABEL: fromRegsConvdtoull: 6079; P9LE: # %bb.0: # %entry 6080; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 6081; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 6082; P9LE-NEXT: xxmrghd vs0, vs2, vs1 6083; P9LE-NEXT: xvcvdpuxds v2, vs0 6084; P9LE-NEXT: blr 6085; 6086; P8BE-LABEL: fromRegsConvdtoull: 6087; P8BE: # %bb.0: # %entry 6088; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 6089; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 6090; P8BE-NEXT: xxmrghd vs0, vs1, vs2 6091; P8BE-NEXT: xvcvdpuxds v2, vs0 6092; P8BE-NEXT: blr 6093; 6094; P8LE-LABEL: fromRegsConvdtoull: 6095; P8LE: # %bb.0: # %entry 6096; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 6097; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 6098; P8LE-NEXT: xxmrghd vs0, vs2, vs1 6099; P8LE-NEXT: xvcvdpuxds v2, vs0 6100; P8LE-NEXT: blr 6101entry: 6102 %conv = fptoui double %a to i64 6103 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6104 %conv1 = fptoui double %b to i64 6105 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 6106 ret <2 x i64> %vecinit2 6107} 6108 6109; Function Attrs: norecurse nounwind readnone 6110define <2 x i64> @fromDiffConstsConvdtoull() { 6111; P9BE-LABEL: fromDiffConstsConvdtoull: 6112; P9BE: # %bb.0: # %entry 6113; P9BE-NEXT: addis r3, r2, .LCPI125_0@toc@ha 6114; P9BE-NEXT: addi r3, r3, .LCPI125_0@toc@l 6115; P9BE-NEXT: lxvx v2, 0, r3 6116; P9BE-NEXT: blr 6117; 6118; P9LE-LABEL: fromDiffConstsConvdtoull: 6119; P9LE: # %bb.0: # %entry 6120; P9LE-NEXT: addis r3, r2, .LCPI125_0@toc@ha 6121; P9LE-NEXT: addi r3, r3, .LCPI125_0@toc@l 6122; P9LE-NEXT: lxvx v2, 0, r3 6123; P9LE-NEXT: blr 6124; 6125; P8BE-LABEL: fromDiffConstsConvdtoull: 6126; P8BE: # %bb.0: # %entry 6127; P8BE-NEXT: addis r3, r2, .LCPI125_0@toc@ha 6128; P8BE-NEXT: addi r3, r3, .LCPI125_0@toc@l 6129; P8BE-NEXT: lxvd2x v2, 0, r3 6130; P8BE-NEXT: blr 6131; 6132; P8LE-LABEL: fromDiffConstsConvdtoull: 6133; P8LE: # %bb.0: # %entry 6134; P8LE-NEXT: addis r3, r2, .LCPI125_0@toc@ha 6135; P8LE-NEXT: addi r3, r3, .LCPI125_0@toc@l 6136; P8LE-NEXT: lxvd2x vs0, 0, r3 6137; P8LE-NEXT: xxswapd v2, vs0 6138; P8LE-NEXT: blr 6139entry: 6140 ret <2 x i64> <i64 24, i64 234> 6141} 6142 6143; Function Attrs: norecurse nounwind readonly 6144define <2 x i64> @fromDiffMemConsAConvdtoull(double* nocapture readonly %ptr) { 6145; P9BE-LABEL: fromDiffMemConsAConvdtoull: 6146; P9BE: # %bb.0: # %entry 6147; P9BE-NEXT: lxv vs0, 0(r3) 6148; P9BE-NEXT: xvcvdpuxds v2, vs0 6149; P9BE-NEXT: blr 6150; 6151; P9LE-LABEL: fromDiffMemConsAConvdtoull: 6152; P9LE: # %bb.0: # %entry 6153; P9LE-NEXT: lxv vs0, 0(r3) 6154; P9LE-NEXT: xvcvdpuxds v2, vs0 6155; P9LE-NEXT: blr 6156; 6157; P8BE-LABEL: fromDiffMemConsAConvdtoull: 6158; P8BE: # %bb.0: # %entry 6159; P8BE-NEXT: lxvd2x vs0, 0, r3 6160; P8BE-NEXT: xvcvdpuxds v2, vs0 6161; P8BE-NEXT: blr 6162; 6163; P8LE-LABEL: fromDiffMemConsAConvdtoull: 6164; P8LE: # %bb.0: # %entry 6165; P8LE-NEXT: lxvd2x vs0, 0, r3 6166; P8LE-NEXT: xxswapd vs0, vs0 6167; P8LE-NEXT: xvcvdpuxds v2, vs0 6168; P8LE-NEXT: blr 6169entry: 6170 %0 = bitcast double* %ptr to <2 x double>* 6171 %1 = load <2 x double>, <2 x double>* %0, align 8 6172 %2 = fptoui <2 x double> %1 to <2 x i64> 6173 ret <2 x i64> %2 6174} 6175 6176; Function Attrs: norecurse nounwind readonly 6177define <2 x i64> @fromDiffMemConsDConvdtoull(double* nocapture readonly %ptr) { 6178; P9BE-LABEL: fromDiffMemConsDConvdtoull: 6179; P9BE: # %bb.0: # %entry 6180; P9BE-NEXT: lxv vs0, 16(r3) 6181; P9BE-NEXT: xxswapd vs0, vs0 6182; P9BE-NEXT: xvcvdpuxds v2, vs0 6183; P9BE-NEXT: blr 6184; 6185; P9LE-LABEL: fromDiffMemConsDConvdtoull: 6186; P9LE: # %bb.0: # %entry 6187; P9LE-NEXT: addi r3, r3, 16 6188; P9LE-NEXT: lxvd2x vs0, 0, r3 6189; P9LE-NEXT: xvcvdpuxds v2, vs0 6190; P9LE-NEXT: blr 6191; 6192; P8BE-LABEL: fromDiffMemConsDConvdtoull: 6193; P8BE: # %bb.0: # %entry 6194; P8BE-NEXT: addi r3, r3, 16 6195; P8BE-NEXT: lxvd2x vs0, 0, r3 6196; P8BE-NEXT: xxswapd vs0, vs0 6197; P8BE-NEXT: xvcvdpuxds v2, vs0 6198; P8BE-NEXT: blr 6199; 6200; P8LE-LABEL: fromDiffMemConsDConvdtoull: 6201; P8LE: # %bb.0: # %entry 6202; P8LE-NEXT: addi r3, r3, 16 6203; P8LE-NEXT: lxvd2x vs0, 0, r3 6204; P8LE-NEXT: xvcvdpuxds v2, vs0 6205; P8LE-NEXT: blr 6206entry: 6207 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 6208 %0 = load double, double* %arrayidx, align 8 6209 %conv = fptoui double %0 to i64 6210 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6211 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 6212 %1 = load double, double* %arrayidx1, align 8 6213 %conv2 = fptoui double %1 to i64 6214 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 6215 ret <2 x i64> %vecinit3 6216} 6217 6218; Function Attrs: norecurse nounwind readonly 6219define <2 x i64> @fromDiffMemVarAConvdtoull(double* nocapture readonly %arr, i32 signext %elem) { 6220; P9BE-LABEL: fromDiffMemVarAConvdtoull: 6221; P9BE: # %bb.0: # %entry 6222; P9BE-NEXT: sldi r4, r4, 3 6223; P9BE-NEXT: lxvx vs0, r3, r4 6224; P9BE-NEXT: xvcvdpuxds v2, vs0 6225; P9BE-NEXT: blr 6226; 6227; P9LE-LABEL: fromDiffMemVarAConvdtoull: 6228; P9LE: # %bb.0: # %entry 6229; P9LE-NEXT: sldi r4, r4, 3 6230; P9LE-NEXT: lxvx vs0, r3, r4 6231; P9LE-NEXT: xvcvdpuxds v2, vs0 6232; P9LE-NEXT: blr 6233; 6234; P8BE-LABEL: fromDiffMemVarAConvdtoull: 6235; P8BE: # %bb.0: # %entry 6236; P8BE-NEXT: sldi r4, r4, 3 6237; P8BE-NEXT: lxvd2x vs0, r3, r4 6238; P8BE-NEXT: xvcvdpuxds v2, vs0 6239; P8BE-NEXT: blr 6240; 6241; P8LE-LABEL: fromDiffMemVarAConvdtoull: 6242; P8LE: # %bb.0: # %entry 6243; P8LE-NEXT: sldi r4, r4, 3 6244; P8LE-NEXT: lxvd2x vs0, r3, r4 6245; P8LE-NEXT: xxswapd vs0, vs0 6246; P8LE-NEXT: xvcvdpuxds v2, vs0 6247; P8LE-NEXT: blr 6248entry: 6249 %idxprom = sext i32 %elem to i64 6250 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 6251 %0 = load double, double* %arrayidx, align 8 6252 %conv = fptoui double %0 to i64 6253 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6254 %add = add nsw i32 %elem, 1 6255 %idxprom1 = sext i32 %add to i64 6256 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 6257 %1 = load double, double* %arrayidx2, align 8 6258 %conv3 = fptoui double %1 to i64 6259 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 6260 ret <2 x i64> %vecinit4 6261} 6262 6263; Function Attrs: norecurse nounwind readonly 6264define <2 x i64> @fromDiffMemVarDConvdtoull(double* nocapture readonly %arr, i32 signext %elem) { 6265; P9BE-LABEL: fromDiffMemVarDConvdtoull: 6266; P9BE: # %bb.0: # %entry 6267; P9BE-NEXT: sldi r4, r4, 3 6268; P9BE-NEXT: add r3, r3, r4 6269; P9BE-NEXT: li r4, -8 6270; P9BE-NEXT: lxvx vs0, r3, r4 6271; P9BE-NEXT: xxswapd vs0, vs0 6272; P9BE-NEXT: xvcvdpuxds v2, vs0 6273; P9BE-NEXT: blr 6274; 6275; P9LE-LABEL: fromDiffMemVarDConvdtoull: 6276; P9LE: # %bb.0: # %entry 6277; P9LE-NEXT: sldi r4, r4, 3 6278; P9LE-NEXT: add r3, r3, r4 6279; P9LE-NEXT: addi r3, r3, -8 6280; P9LE-NEXT: lxvd2x vs0, 0, r3 6281; P9LE-NEXT: xvcvdpuxds v2, vs0 6282; P9LE-NEXT: blr 6283; 6284; P8BE-LABEL: fromDiffMemVarDConvdtoull: 6285; P8BE: # %bb.0: # %entry 6286; P8BE-NEXT: sldi r4, r4, 3 6287; P8BE-NEXT: add r3, r3, r4 6288; P8BE-NEXT: addi r3, r3, -8 6289; P8BE-NEXT: lxvd2x vs0, 0, r3 6290; P8BE-NEXT: xxswapd vs0, vs0 6291; P8BE-NEXT: xvcvdpuxds v2, vs0 6292; P8BE-NEXT: blr 6293; 6294; P8LE-LABEL: fromDiffMemVarDConvdtoull: 6295; P8LE: # %bb.0: # %entry 6296; P8LE-NEXT: sldi r4, r4, 3 6297; P8LE-NEXT: add r3, r3, r4 6298; P8LE-NEXT: addi r3, r3, -8 6299; P8LE-NEXT: lxvd2x vs0, 0, r3 6300; P8LE-NEXT: xvcvdpuxds v2, vs0 6301; P8LE-NEXT: blr 6302entry: 6303 %idxprom = sext i32 %elem to i64 6304 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 6305 %0 = load double, double* %arrayidx, align 8 6306 %conv = fptoui double %0 to i64 6307 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6308 %sub = add nsw i32 %elem, -1 6309 %idxprom1 = sext i32 %sub to i64 6310 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 6311 %1 = load double, double* %arrayidx2, align 8 6312 %conv3 = fptoui double %1 to i64 6313 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 6314 ret <2 x i64> %vecinit4 6315} 6316 6317; Function Attrs: norecurse nounwind readnone 6318define <2 x i64> @spltRegValConvdtoull(double %val) { 6319; P9BE-LABEL: spltRegValConvdtoull: 6320; P9BE: # %bb.0: # %entry 6321; P9BE-NEXT: xscvdpuxds f0, f1 6322; P9BE-NEXT: xxspltd v2, vs0, 0 6323; P9BE-NEXT: blr 6324; 6325; P9LE-LABEL: spltRegValConvdtoull: 6326; P9LE: # %bb.0: # %entry 6327; P9LE-NEXT: xscvdpuxds f0, f1 6328; P9LE-NEXT: xxspltd v2, vs0, 0 6329; P9LE-NEXT: blr 6330; 6331; P8BE-LABEL: spltRegValConvdtoull: 6332; P8BE: # %bb.0: # %entry 6333; P8BE-NEXT: xscvdpuxds f0, f1 6334; P8BE-NEXT: xxspltd v2, vs0, 0 6335; P8BE-NEXT: blr 6336; 6337; P8LE-LABEL: spltRegValConvdtoull: 6338; P8LE: # %bb.0: # %entry 6339; P8LE-NEXT: xscvdpuxds f0, f1 6340; P8LE-NEXT: xxspltd v2, vs0, 0 6341; P8LE-NEXT: blr 6342entry: 6343 %conv = fptoui double %val to i64 6344 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 6345 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 6346 ret <2 x i64> %splat.splat 6347} 6348 6349; Function Attrs: norecurse nounwind readonly 6350define <2 x i64> @spltMemValConvdtoull(double* nocapture readonly %ptr) { 6351; P9BE-LABEL: spltMemValConvdtoull: 6352; P9BE: # %bb.0: # %entry 6353; P9BE-NEXT: lxvdsx vs0, 0, r3 6354; P9BE-NEXT: xvcvdpuxds v2, vs0 6355; P9BE-NEXT: blr 6356; 6357; P9LE-LABEL: spltMemValConvdtoull: 6358; P9LE: # %bb.0: # %entry 6359; P9LE-NEXT: lxvdsx vs0, 0, r3 6360; P9LE-NEXT: xvcvdpuxds v2, vs0 6361; P9LE-NEXT: blr 6362; 6363; P8BE-LABEL: spltMemValConvdtoull: 6364; P8BE: # %bb.0: # %entry 6365; P8BE-NEXT: lxvdsx vs0, 0, r3 6366; P8BE-NEXT: xvcvdpuxds v2, vs0 6367; P8BE-NEXT: blr 6368; 6369; P8LE-LABEL: spltMemValConvdtoull: 6370; P8LE: # %bb.0: # %entry 6371; P8LE-NEXT: lxvdsx vs0, 0, r3 6372; P8LE-NEXT: xvcvdpuxds v2, vs0 6373; P8LE-NEXT: blr 6374entry: 6375 %0 = load double, double* %ptr, align 8 6376 %conv = fptoui double %0 to i64 6377 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 6378 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 6379 ret <2 x i64> %splat.splat 6380} 6381