1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 3; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \ 4; RUN: -check-prefix=P9BE -implicit-check-not frsp 5; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 6; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \ 7; RUN: -check-prefix=P9LE -implicit-check-not frsp 8; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 9; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \ 10; RUN: -check-prefix=P8BE -implicit-check-not frsp 11; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 12; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \ 13; RUN: -check-prefix=P8LE -implicit-check-not frsp 14 15; This test case comes from the following C test case (included as it may be 16; slightly more readable than the LLVM IR. 17 18;/* This test case provides various ways of building vectors to ensure we 19; produce optimal code for all cases. The cases are (for each type): 20; - All zeros 21; - All ones - split to build-vector-allones.ll 22; - Splat of a constant 23; - From different values already in registers 24; - From different constants 25; - From different values in memory 26; - Splat of a value in register 27; - Splat of a value in memory 28; - Inserting element into existing vector 29; - Inserting element from existing vector into existing vector 30; 31; With conversions (float <-> int) 32; - Splat of a constant 33; - From different values already in registers 34; - From different constants 35; - From different values in memory 36; - Splat of a value in register 37; - Splat of a value in memory 38; - Inserting element into existing vector 39; - Inserting element from existing vector into existing vector 40;*/ 41; 42;/*=================================== int ===================================*/ 43;// P8: xxlxor // 44;// P9: xxlxor // 45;vector int allZeroi() { // 46; return (vector int)0; // 47;} // 48;// P8: vspltisb -1 // 49;// P9: xxspltisb 255 // 50;vector int spltConst1i() { // 51; return (vector int)1; // 52;} // 53;// P8: vspltisw -15; vsrw // 54;// P9: vspltisw -15; vsrw // 55;vector int spltConst16ki() { // 56; return (vector int)((1<<15) - 1); // 57;} // 58;// P8: vspltisw -16; vsrw // 59;// P9: vspltisw -16; vsrw // 60;vector int spltConst32ki() { // 61; return (vector int)((1<<16) - 1); // 62;} // 63;// P8: 4 x mtvsrwz, 2 x xxmrgh, vmrgow // 64;// P9: 2 x mtvsrdd, vmrgow // 65;vector int fromRegsi(int a, int b, int c, int d) { // 66; return (vector int){ a, b, c, d }; // 67;} // 68;// P8: lxvd2x, xxswapd // 69;// P9: lxvx (or even lxv) // 70;vector int fromDiffConstsi() { // 71; return (vector int) { 242, -113, 889, 19 }; // 72;} // 73;// P8: lxvd2x, xxswapd // 74;// P9: lxvx // 75;vector int fromDiffMemConsAi(int *arr) { // 76; return (vector int) { arr[0], arr[1], arr[2], arr[3] }; // 77;} // 78;// P8: 2 x lxvd2x, 2 x xxswapd, vperm // 79;// P9: 2 x lxvx, vperm // 80;vector int fromDiffMemConsDi(int *arr) { // 81; return (vector int) { arr[3], arr[2], arr[1], arr[0] }; // 82;} // 83;// P8: sldi 2, lxvd2x, xxswapd // 84;// P9: sldi 2, lxvx // 85;vector int fromDiffMemVarAi(int *arr, int elem) { // 86; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 87;} // 88;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm // 89;// P9: sldi 2, 2 x lxvx, vperm // 90;vector int fromDiffMemVarDi(int *arr, int elem) { // 91; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 92;} // 93;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 94;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow // 95;vector int fromRandMemConsi(int *arr) { // 96; return (vector int) { arr[4], arr[18], arr[2], arr[88] }; // 97;} // 98;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 99;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow // 100;vector int fromRandMemVari(int *arr, int elem) { // 101; return (vector int) { arr[elem+4], arr[elem+1], arr[elem+2], arr[elem+8] };// 102;} // 103;// P8: mtvsrwz, xxspltw // 104;// P9: mtvsrws // 105;vector int spltRegVali(int val) { // 106; return (vector int) val; // 107;} // 108;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 109;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 110;vector int spltMemVali(int *ptr) { // 111; return (vector int)*ptr; // 112;} // 113;// P8: vspltisw // 114;// P9: vspltisw // 115;vector int spltCnstConvftoi() { // 116; return (vector int) 4.74f; // 117;} // 118;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 119;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 120;vector int fromRegsConvftoi(float a, float b, float c, float d) { // 121; return (vector int) { a, b, c, d }; // 122;} // 123;// P8: lxvd2x, xxswapd // 124;// P9: lxvx (even lxv) // 125;vector int fromDiffConstsConvftoi() { // 126; return (vector int) { 24.46f, 234.f, 988.19f, 422.39f }; // 127;} // 128;// P8: lxvd2x, xxswapd, xvcvspsxws // 129;// P9: lxvx, xvcvspsxws // 130;vector int fromDiffMemConsAConvftoi(float *ptr) { // 131; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 132;} // 133;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspsxws // 134;// P9: 2 x lxvx, vperm, xvcvspsxws // 135;vector int fromDiffMemConsDConvftoi(float *ptr) { // 136; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 137;} // 138;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 139;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 140;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 141;// sldi 2, load, xvcvspuxws // 142;vector int fromDiffMemVarAConvftoi(float *arr, int elem) { // 143; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 144;} // 145;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 146;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 147;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 148;// sldi 2, 2 x load, vperm, xvcvspuxws // 149;vector int fromDiffMemVarDConvftoi(float *arr, int elem) { // 150; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 151;} // 152;// P8: xscvdpsxws, xxspltw // 153;// P9: xscvdpsxws, xxspltw // 154;vector int spltRegValConvftoi(float val) { // 155; return (vector int) val; // 156;} // 157;// P8: lxsspx, xscvdpsxws, xxspltw // 158;// P9: lxvwsx, xvcvspsxws // 159;vector int spltMemValConvftoi(float *ptr) { // 160; return (vector int)*ptr; // 161;} // 162;// P8: vspltisw // 163;// P9: vspltisw // 164;vector int spltCnstConvdtoi() { // 165; return (vector int) 4.74; // 166;} // 167;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 168;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 169;vector int fromRegsConvdtoi(double a, double b, double c, double d) { // 170; return (vector int) { a, b, c, d }; // 171;} // 172;// P8: lxvd2x, xxswapd // 173;// P9: lxvx (even lxv) // 174;vector int fromDiffConstsConvdtoi() { // 175; return (vector int) { 24.46, 234., 988.19, 422.39 }; // 176;} // 177;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew // 178;// P9: 2 x lxvx, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew // 179;vector int fromDiffMemConsAConvdtoi(double *ptr) { // 180; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 181;} // 182;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 183;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 184;vector int fromDiffMemConsDConvdtoi(double *ptr) { // 185; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 186;} // 187;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 188;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 189;vector int fromDiffMemVarAConvdtoi(double *arr, int elem) { // 190; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 191;} // 192;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 193;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 194;vector int fromDiffMemVarDConvdtoi(double *arr, int elem) { // 195; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 196;} // 197;// P8: xscvdpsxws, xxspltw // 198;// P9: xscvdpsxws, xxspltw // 199;vector int spltRegValConvdtoi(double val) { // 200; return (vector int) val; // 201;} // 202;// P8: lxsdx, xscvdpsxws, xxspltw // 203;// P9: lxssp, xscvdpsxws, xxspltw // 204;vector int spltMemValConvdtoi(double *ptr) { // 205; return (vector int)*ptr; // 206;} // 207;/*=================================== int ===================================*/ 208;/*=============================== unsigned int ==============================*/ 209;// P8: xxlxor // 210;// P9: xxlxor // 211;vector unsigned int allZeroui() { // 212; return (vector unsigned int)0; // 213;} // 214;// P8: vspltisb -1 // 215;// P9: xxspltisb 255 // 216;vector unsigned int spltConst1ui() { // 217; return (vector unsigned int)1; // 218;} // 219;// P8: vspltisw -15; vsrw // 220;// P9: vspltisw -15; vsrw // 221;vector unsigned int spltConst16kui() { // 222; return (vector unsigned int)((1<<15) - 1); // 223;} // 224;// P8: vspltisw -16; vsrw // 225;// P9: vspltisw -16; vsrw // 226;vector unsigned int spltConst32kui() { // 227; return (vector unsigned int)((1<<16) - 1); // 228;} // 229;// P8: 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 230;// P9: 2 x mtvsrdd, vmrgow // 231;vector unsigned int fromRegsui(unsigned int a, unsigned int b, // 232; unsigned int c, unsigned int d) { // 233; return (vector unsigned int){ a, b, c, d }; // 234;} // 235;// P8: lxvd2x, xxswapd // 236;// P9: lxvx (or even lxv) // 237;vector unsigned int fromDiffConstsui() { // 238; return (vector unsigned int) { 242, -113, 889, 19 }; // 239;} // 240;// P8: lxvd2x, xxswapd // 241;// P9: lxvx // 242;vector unsigned int fromDiffMemConsAui(unsigned int *arr) { // 243; return (vector unsigned int) { arr[0], arr[1], arr[2], arr[3] }; // 244;} // 245;// P8: 2 x lxvd2x, 2 x xxswapd, vperm // 246;// P9: 2 x lxvx, vperm // 247;vector unsigned int fromDiffMemConsDui(unsigned int *arr) { // 248; return (vector unsigned int) { arr[3], arr[2], arr[1], arr[0] }; // 249;} // 250;// P8: sldi 2, lxvd2x, xxswapd // 251;// P9: sldi 2, lxvx // 252;vector unsigned int fromDiffMemVarAui(unsigned int *arr, int elem) { // 253; return (vector unsigned int) { arr[elem], arr[elem+1], // 254; arr[elem+2], arr[elem+3] }; // 255;} // 256;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm // 257;// P9: sldi 2, 2 x lxvx, vperm // 258;vector unsigned int fromDiffMemVarDui(unsigned int *arr, int elem) { // 259; return (vector unsigned int) { arr[elem], arr[elem-1], // 260; arr[elem-2], arr[elem-3] }; // 261;} // 262;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 263;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow // 264;vector unsigned int fromRandMemConsui(unsigned int *arr) { // 265; return (vector unsigned int) { arr[4], arr[18], arr[2], arr[88] }; // 266;} // 267;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 268;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow // 269;vector unsigned int fromRandMemVarui(unsigned int *arr, int elem) { // 270; return (vector unsigned int) { arr[elem+4], arr[elem+1], // 271; arr[elem+2], arr[elem+8] }; // 272;} // 273;// P8: mtvsrwz, xxspltw // 274;// P9: mtvsrws // 275;vector unsigned int spltRegValui(unsigned int val) { // 276; return (vector unsigned int) val; // 277;} // 278;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 279;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 280;vector unsigned int spltMemValui(unsigned int *ptr) { // 281; return (vector unsigned int)*ptr; // 282;} // 283;// P8: vspltisw // 284;// P9: vspltisw // 285;vector unsigned int spltCnstConvftoui() { // 286; return (vector unsigned int) 4.74f; // 287;} // 288;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 289;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 290;vector unsigned int fromRegsConvftoui(float a, float b, float c, float d) { // 291; return (vector unsigned int) { a, b, c, d }; // 292;} // 293;// P8: lxvd2x, xxswapd // 294;// P9: lxvx (even lxv) // 295;vector unsigned int fromDiffConstsConvftoui() { // 296; return (vector unsigned int) { 24.46f, 234.f, 988.19f, 422.39f }; // 297;} // 298;// P8: lxvd2x, xxswapd, xvcvspuxws // 299;// P9: lxvx, xvcvspuxws // 300;vector unsigned int fromDiffMemConsAConvftoui(float *ptr) { // 301; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 302;} // 303;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspuxws // 304;// P9: 2 x lxvx, vperm, xvcvspuxws // 305;vector unsigned int fromDiffMemConsDConvftoui(float *ptr) { // 306; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 307;} // 308;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 309;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 310;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 311;// sldi 2, load, xvcvspuxws // 312;vector unsigned int fromDiffMemVarAConvftoui(float *arr, int elem) { // 313; return (vector unsigned int) { arr[elem], arr[elem+1], // 314; arr[elem+2], arr[elem+3] }; // 315;} // 316;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 317;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 318;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 319;// sldi 2, 2 x load, vperm, xvcvspuxws // 320;vector unsigned int fromDiffMemVarDConvftoui(float *arr, int elem) { // 321; return (vector unsigned int) { arr[elem], arr[elem-1], // 322; arr[elem-2], arr[elem-3] }; // 323;} // 324;// P8: xscvdpuxws, xxspltw // 325;// P9: xscvdpuxws, xxspltw // 326;vector unsigned int spltRegValConvftoui(float val) { // 327; return (vector unsigned int) val; // 328;} // 329;// P8: lxsspx, xscvdpuxws, xxspltw // 330;// P9: lxvwsx, xvcvspuxws // 331;vector unsigned int spltMemValConvftoui(float *ptr) { // 332; return (vector unsigned int)*ptr; // 333;} // 334;// P8: vspltisw // 335;// P9: vspltisw // 336;vector unsigned int spltCnstConvdtoui() { // 337; return (vector unsigned int) 4.74; // 338;} // 339;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 340;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 341;vector unsigned int fromRegsConvdtoui(double a, double b, // 342; double c, double d) { // 343; return (vector unsigned int) { a, b, c, d }; // 344;} // 345;// P8: lxvd2x, xxswapd // 346;// P9: lxvx (even lxv) // 347;vector unsigned int fromDiffConstsConvdtoui() { // 348; return (vector unsigned int) { 24.46, 234., 988.19, 422.39 }; // 349;} // 350;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew // 351;// P9: 2 x lxvx, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew // 352;vector unsigned int fromDiffMemConsAConvdtoui(double *ptr) { // 353; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 354;} // 355;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 356;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 357;vector unsigned int fromDiffMemConsDConvdtoui(double *ptr) { // 358; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 359;} // 360;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 361;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 362;vector unsigned int fromDiffMemVarAConvdtoui(double *arr, int elem) { // 363; return (vector unsigned int) { arr[elem], arr[elem+1], // 364; arr[elem+2], arr[elem+3] }; // 365;} // 366;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 367;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 368;vector unsigned int fromDiffMemVarDConvdtoui(double *arr, int elem) { // 369; return (vector unsigned int) { arr[elem], arr[elem-1], // 370; arr[elem-2], arr[elem-3] }; // 371;} // 372;// P8: xscvdpuxws, xxspltw // 373;// P9: xscvdpuxws, xxspltw // 374;vector unsigned int spltRegValConvdtoui(double val) { // 375; return (vector unsigned int) val; // 376;} // 377;// P8: lxsspx, xscvdpuxws, xxspltw // 378;// P9: lfd, xscvdpuxws, xxspltw // 379;vector unsigned int spltMemValConvdtoui(double *ptr) { // 380; return (vector unsigned int)*ptr; // 381;} // 382;/*=============================== unsigned int ==============================*/ 383;/*=============================== long long =================================*/ 384;// P8: xxlxor // 385;// P9: xxlxor // 386;vector long long allZeroll() { // 387; return (vector long long)0; // 388;} // 389;// P8: vspltisb -1 // 390;// P9: xxspltisb 255 // 391;vector long long spltConst1ll() { // 392; return (vector long long)1; // 393;} // 394;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 395;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 396;vector long long spltConst16kll() { // 397; return (vector long long)((1<<15) - 1); // 398;} // 399;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 400;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 401;vector long long spltConst32kll() { // 402; return (vector long long)((1<<16) - 1); // 403;} // 404;// P8: 2 x mtvsrd, xxmrghd // 405;// P9: mtvsrdd // 406;vector long long fromRegsll(long long a, long long b) { // 407; return (vector long long){ a, b }; // 408;} // 409;// P8: lxvd2x, xxswapd // 410;// P9: lxvx (or even lxv) // 411;vector long long fromDiffConstsll() { // 412; return (vector long long) { 242, -113 }; // 413;} // 414;// P8: lxvd2x, xxswapd // 415;// P9: lxvx // 416;vector long long fromDiffMemConsAll(long long *arr) { // 417; return (vector long long) { arr[0], arr[1] }; // 418;} // 419;// P8: lxvd2x // 420;// P9: lxvx, xxswapd (maybe just use lxvd2x) // 421;vector long long fromDiffMemConsDll(long long *arr) { // 422; return (vector long long) { arr[3], arr[2] }; // 423;} // 424;// P8: sldi 3, lxvd2x, xxswapd // 425;// P9: sldi 3, lxvx // 426;vector long long fromDiffMemVarAll(long long *arr, int elem) { // 427; return (vector long long) { arr[elem], arr[elem+1] }; // 428;} // 429;// P8: sldi 3, lxvd2x // 430;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) // 431;vector long long fromDiffMemVarDll(long long *arr, int elem) { // 432; return (vector long long) { arr[elem], arr[elem-1] }; // 433;} // 434;// P8: 2 x ld, 2 x mtvsrd, xxmrghd // 435;// P9: 2 x ld, mtvsrdd // 436;vector long long fromRandMemConsll(long long *arr) { // 437; return (vector long long) { arr[4], arr[18] }; // 438;} // 439;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd // 440;// P9: sldi 3, add, 2 x ld, mtvsrdd // 441;vector long long fromRandMemVarll(long long *arr, int elem) { // 442; return (vector long long) { arr[elem+4], arr[elem+1] }; // 443;} // 444;// P8: mtvsrd, xxspltd // 445;// P9: mtvsrdd // 446;vector long long spltRegValll(long long val) { // 447; return (vector long long) val; // 448;} // 449;// P8: lxvdsx // 450;// P9: lxvdsx // 451;vector long long spltMemValll(long long *ptr) { // 452; return (vector long long)*ptr; // 453;} // 454;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 455;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 456;vector long long spltCnstConvftoll() { // 457; return (vector long long) 4.74f; // 458;} // 459;// P8: xxmrghd, xvcvdpsxds // 460;// P9: xxmrghd, xvcvdpsxds // 461;vector long long fromRegsConvftoll(float a, float b) { // 462; return (vector long long) { a, b }; // 463;} // 464;// P8: lxvd2x, xxswapd // 465;// P9: lxvx (even lxv) // 466;vector long long fromDiffConstsConvftoll() { // 467; return (vector long long) { 24.46f, 234.f }; // 468;} // 469;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds // 470;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds // 471;vector long long fromDiffMemConsAConvftoll(float *ptr) { // 472; return (vector long long) { ptr[0], ptr[1] }; // 473;} // 474;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds // 475;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds // 476;vector long long fromDiffMemConsDConvftoll(float *ptr) { // 477; return (vector long long) { ptr[3], ptr[2] }; // 478;} // 479;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds // 480;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds // 481;vector long long fromDiffMemVarAConvftoll(float *arr, int elem) { // 482; return (vector long long) { arr[elem], arr[elem+1] }; // 483;} // 484;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds // 485;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds // 486;vector long long fromDiffMemVarDConvftoll(float *arr, int elem) { // 487; return (vector long long) { arr[elem], arr[elem-1] }; // 488;} // 489;// P8: xscvdpsxds, xxspltd // 490;// P9: xscvdpsxds, xxspltd // 491;vector long long spltRegValConvftoll(float val) { // 492; return (vector long long) val; // 493;} // 494;// P8: lxsspx, xscvdpsxds, xxspltd // 495;// P9: lfs, xscvdpsxds, xxspltd // 496;vector long long spltMemValConvftoll(float *ptr) { // 497; return (vector long long)*ptr; // 498;} // 499;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 500;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 501;vector long long spltCnstConvdtoll() { // 502; return (vector long long) 4.74; // 503;} // 504;// P8: xxmrghd, xvcvdpsxds // 505;// P9: xxmrghd, xvcvdpsxds // 506;vector long long fromRegsConvdtoll(double a, double b) { // 507; return (vector long long) { a, b }; // 508;} // 509;// P8: lxvd2x, xxswapd // 510;// P9: lxvx (even lxv) // 511;vector long long fromDiffConstsConvdtoll() { // 512; return (vector long long) { 24.46, 234. }; // 513;} // 514;// P8: lxvd2x, xxswapd, xvcvdpsxds // 515;// P9: lxvx, xvcvdpsxds // 516;vector long long fromDiffMemConsAConvdtoll(double *ptr) { // 517; return (vector long long) { ptr[0], ptr[1] }; // 518;} // 519;// P8: lxvd2x, xvcvdpsxds // 520;// P9: lxvx, xxswapd, xvcvdpsxds // 521;vector long long fromDiffMemConsDConvdtoll(double *ptr) { // 522; return (vector long long) { ptr[3], ptr[2] }; // 523;} // 524;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpsxds // 525;// P9: sldi 3, lxvx, xvcvdpsxds // 526;vector long long fromDiffMemVarAConvdtoll(double *arr, int elem) { // 527; return (vector long long) { arr[elem], arr[elem+1] }; // 528;} // 529;// P8: sldi 3, lxvd2x, xvcvdpsxds // 530;// P9: sldi 3, lxvx, xxswapd, xvcvdpsxds // 531;vector long long fromDiffMemVarDConvdtoll(double *arr, int elem) { // 532; return (vector long long) { arr[elem], arr[elem-1] }; // 533;} // 534;// P8: xscvdpsxds, xxspltd // 535;// P9: xscvdpsxds, xxspltd // 536;vector long long spltRegValConvdtoll(double val) { // 537; return (vector long long) val; // 538;} // 539;// P8: lxvdsx, xvcvdpsxds // 540;// P9: lxvdsx, xvcvdpsxds // 541;vector long long spltMemValConvdtoll(double *ptr) { // 542; return (vector long long)*ptr; // 543;} // 544;/*=============================== long long =================================*/ 545;/*========================== unsigned long long =============================*/ 546;// P8: xxlxor // 547;// P9: xxlxor // 548;vector unsigned long long allZeroull() { // 549; return (vector unsigned long long)0; // 550;} // 551;// P8: vspltisb -1 // 552;// P9: xxspltisb 255 // 553;vector unsigned long long spltConst1ull() { // 554; return (vector unsigned long long)1; // 555;} // 556;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 557;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 558;vector unsigned long long spltConst16kull() { // 559; return (vector unsigned long long)((1<<15) - 1); // 560;} // 561;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 562;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 563;vector unsigned long long spltConst32kull() { // 564; return (vector unsigned long long)((1<<16) - 1); // 565;} // 566;// P8: 2 x mtvsrd, xxmrghd // 567;// P9: mtvsrdd // 568;vector unsigned long long fromRegsull(unsigned long long a, // 569; unsigned long long b) { // 570; return (vector unsigned long long){ a, b }; // 571;} // 572;// P8: lxvd2x, xxswapd // 573;// P9: lxvx (or even lxv) // 574;vector unsigned long long fromDiffConstsull() { // 575; return (vector unsigned long long) { 242, -113 }; // 576;} // 577;// P8: lxvd2x, xxswapd // 578;// P9: lxvx // 579;vector unsigned long long fromDiffMemConsAull(unsigned long long *arr) { // 580; return (vector unsigned long long) { arr[0], arr[1] }; // 581;} // 582;// P8: lxvd2x // 583;// P9: lxvx, xxswapd (maybe just use lxvd2x) // 584;vector unsigned long long fromDiffMemConsDull(unsigned long long *arr) { // 585; return (vector unsigned long long) { arr[3], arr[2] }; // 586;} // 587;// P8: sldi 3, lxvd2x, xxswapd // 588;// P9: sldi 3, lxvx // 589;vector unsigned long long fromDiffMemVarAull(unsigned long long *arr, // 590; int elem) { // 591; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 592;} // 593;// P8: sldi 3, lxvd2x // 594;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) // 595;vector unsigned long long fromDiffMemVarDull(unsigned long long *arr, // 596; int elem) { // 597; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 598;} // 599;// P8: 2 x ld, 2 x mtvsrd, xxmrghd // 600;// P9: 2 x ld, mtvsrdd // 601;vector unsigned long long fromRandMemConsull(unsigned long long *arr) { // 602; return (vector unsigned long long) { arr[4], arr[18] }; // 603;} // 604;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd // 605;// P9: sldi 3, add, 2 x ld, mtvsrdd // 606;vector unsigned long long fromRandMemVarull(unsigned long long *arr, // 607; int elem) { // 608; return (vector unsigned long long) { arr[elem+4], arr[elem+1] }; // 609;} // 610;// P8: mtvsrd, xxspltd // 611;// P9: mtvsrdd // 612;vector unsigned long long spltRegValull(unsigned long long val) { // 613; return (vector unsigned long long) val; // 614;} // 615;// P8: lxvdsx // 616;// P9: lxvdsx // 617;vector unsigned long long spltMemValull(unsigned long long *ptr) { // 618; return (vector unsigned long long)*ptr; // 619;} // 620;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 621;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 622;vector unsigned long long spltCnstConvftoull() { // 623; return (vector unsigned long long) 4.74f; // 624;} // 625;// P8: xxmrghd, xvcvdpuxds // 626;// P9: xxmrghd, xvcvdpuxds // 627;vector unsigned long long fromRegsConvftoull(float a, float b) { // 628; return (vector unsigned long long) { a, b }; // 629;} // 630;// P8: lxvd2x, xxswapd // 631;// P9: lxvx (even lxv) // 632;vector unsigned long long fromDiffConstsConvftoull() { // 633; return (vector unsigned long long) { 24.46f, 234.f }; // 634;} // 635;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds // 636;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds // 637;vector unsigned long long fromDiffMemConsAConvftoull(float *ptr) { // 638; return (vector unsigned long long) { ptr[0], ptr[1] }; // 639;} // 640;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds // 641;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds // 642;vector unsigned long long fromDiffMemConsDConvftoull(float *ptr) { // 643; return (vector unsigned long long) { ptr[3], ptr[2] }; // 644;} // 645;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds // 646;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds // 647;vector unsigned long long fromDiffMemVarAConvftoull(float *arr, int elem) { // 648; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 649;} // 650;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds // 651;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds // 652;vector unsigned long long fromDiffMemVarDConvftoull(float *arr, int elem) { // 653; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 654;} // 655;// P8: xscvdpuxds, xxspltd // 656;// P9: xscvdpuxds, xxspltd // 657;vector unsigned long long spltRegValConvftoull(float val) { // 658; return (vector unsigned long long) val; // 659;} // 660;// P8: lxsspx, xscvdpuxds, xxspltd // 661;// P9: lfs, xscvdpuxds, xxspltd // 662;vector unsigned long long spltMemValConvftoull(float *ptr) { // 663; return (vector unsigned long long)*ptr; // 664;} // 665;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 666;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 667;vector unsigned long long spltCnstConvdtoull() { // 668; return (vector unsigned long long) 4.74; // 669;} // 670;// P8: xxmrghd, xvcvdpuxds // 671;// P9: xxmrghd, xvcvdpuxds // 672;vector unsigned long long fromRegsConvdtoull(double a, double b) { // 673; return (vector unsigned long long) { a, b }; // 674;} // 675;// P8: lxvd2x, xxswapd // 676;// P9: lxvx (even lxv) // 677;vector unsigned long long fromDiffConstsConvdtoull() { // 678; return (vector unsigned long long) { 24.46, 234. }; // 679;} // 680;// P8: lxvd2x, xxswapd, xvcvdpuxds // 681;// P9: lxvx, xvcvdpuxds // 682;vector unsigned long long fromDiffMemConsAConvdtoull(double *ptr) { // 683; return (vector unsigned long long) { ptr[0], ptr[1] }; // 684;} // 685;// P8: lxvd2x, xvcvdpuxds // 686;// P9: lxvx, xxswapd, xvcvdpuxds // 687;vector unsigned long long fromDiffMemConsDConvdtoull(double *ptr) { // 688; return (vector unsigned long long) { ptr[3], ptr[2] }; // 689;} // 690;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpuxds // 691;// P9: sldi 3, lxvx, xvcvdpuxds // 692;vector unsigned long long fromDiffMemVarAConvdtoull(double *arr, int elem) { // 693; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 694;} // 695;// P8: sldi 3, lxvd2x, xvcvdpuxds // 696;// P9: sldi 3, lxvx, xxswapd, xvcvdpuxds // 697;vector unsigned long long fromDiffMemVarDConvdtoull(double *arr, int elem) { // 698; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 699;} // 700;// P8: xscvdpuxds, xxspltd // 701;// P9: xscvdpuxds, xxspltd // 702;vector unsigned long long spltRegValConvdtoull(double val) { // 703; return (vector unsigned long long) val; // 704;} // 705;// P8: lxvdsx, xvcvdpuxds // 706;// P9: lxvdsx, xvcvdpuxds // 707;vector unsigned long long spltMemValConvdtoull(double *ptr) { // 708; return (vector unsigned long long)*ptr; // 709;} // 710;/*========================== unsigned long long ==============================*/ 711 712; Function Attrs: norecurse nounwind readnone 713define <4 x i32> @allZeroi() { 714; P9BE-LABEL: allZeroi: 715; P9BE: # %bb.0: # %entry 716; P9BE-NEXT: xxlxor v2, v2, v2 717; P9BE-NEXT: blr 718; 719; P9LE-LABEL: allZeroi: 720; P9LE: # %bb.0: # %entry 721; P9LE-NEXT: xxlxor v2, v2, v2 722; P9LE-NEXT: blr 723; 724; P8BE-LABEL: allZeroi: 725; P8BE: # %bb.0: # %entry 726; P8BE-NEXT: xxlxor v2, v2, v2 727; P8BE-NEXT: blr 728; 729; P8LE-LABEL: allZeroi: 730; P8LE: # %bb.0: # %entry 731; P8LE-NEXT: xxlxor v2, v2, v2 732; P8LE-NEXT: blr 733entry: 734 ret <4 x i32> zeroinitializer 735} 736 737; Function Attrs: norecurse nounwind readnone 738define <4 x i32> @spltConst1i() { 739; P9BE-LABEL: spltConst1i: 740; P9BE: # %bb.0: # %entry 741; P9BE-NEXT: vspltisw v2, 1 742; P9BE-NEXT: blr 743; 744; P9LE-LABEL: spltConst1i: 745; P9LE: # %bb.0: # %entry 746; P9LE-NEXT: vspltisw v2, 1 747; P9LE-NEXT: blr 748; 749; P8BE-LABEL: spltConst1i: 750; P8BE: # %bb.0: # %entry 751; P8BE-NEXT: vspltisw v2, 1 752; P8BE-NEXT: blr 753; 754; P8LE-LABEL: spltConst1i: 755; P8LE: # %bb.0: # %entry 756; P8LE-NEXT: vspltisw v2, 1 757; P8LE-NEXT: blr 758entry: 759 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1> 760} 761 762; Function Attrs: norecurse nounwind readnone 763define <4 x i32> @spltConst16ki() { 764; P9BE-LABEL: spltConst16ki: 765; P9BE: # %bb.0: # %entry 766; P9BE-NEXT: vspltisw v2, -15 767; P9BE-NEXT: vsrw v2, v2, v2 768; P9BE-NEXT: blr 769; 770; P9LE-LABEL: spltConst16ki: 771; P9LE: # %bb.0: # %entry 772; P9LE-NEXT: vspltisw v2, -15 773; P9LE-NEXT: vsrw v2, v2, v2 774; P9LE-NEXT: blr 775; 776; P8BE-LABEL: spltConst16ki: 777; P8BE: # %bb.0: # %entry 778; P8BE-NEXT: vspltisw v2, -15 779; P8BE-NEXT: vsrw v2, v2, v2 780; P8BE-NEXT: blr 781; 782; P8LE-LABEL: spltConst16ki: 783; P8LE: # %bb.0: # %entry 784; P8LE-NEXT: vspltisw v2, -15 785; P8LE-NEXT: vsrw v2, v2, v2 786; P8LE-NEXT: blr 787entry: 788 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 789} 790 791; Function Attrs: norecurse nounwind readnone 792define <4 x i32> @spltConst32ki() { 793; P9BE-LABEL: spltConst32ki: 794; P9BE: # %bb.0: # %entry 795; P9BE-NEXT: vspltisw v2, -16 796; P9BE-NEXT: vsrw v2, v2, v2 797; P9BE-NEXT: blr 798; 799; P9LE-LABEL: spltConst32ki: 800; P9LE: # %bb.0: # %entry 801; P9LE-NEXT: vspltisw v2, -16 802; P9LE-NEXT: vsrw v2, v2, v2 803; P9LE-NEXT: blr 804; 805; P8BE-LABEL: spltConst32ki: 806; P8BE: # %bb.0: # %entry 807; P8BE-NEXT: vspltisw v2, -16 808; P8BE-NEXT: vsrw v2, v2, v2 809; P8BE-NEXT: blr 810; 811; P8LE-LABEL: spltConst32ki: 812; P8LE: # %bb.0: # %entry 813; P8LE-NEXT: vspltisw v2, -16 814; P8LE-NEXT: vsrw v2, v2, v2 815; P8LE-NEXT: blr 816entry: 817 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 818} 819 820; Function Attrs: norecurse nounwind readnone 821define <4 x i32> @fromRegsi(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) { 822; P9BE-LABEL: fromRegsi: 823; P9BE: # %bb.0: # %entry 824; P9BE-NEXT: rldimi r6, r5, 32, 0 825; P9BE-NEXT: rldimi r4, r3, 32, 0 826; P9BE-NEXT: mtvsrdd v2, r4, r6 827; P9BE-NEXT: blr 828; 829; P9LE-LABEL: fromRegsi: 830; P9LE: # %bb.0: # %entry 831; P9LE-NEXT: rldimi r3, r4, 32, 0 832; P9LE-NEXT: rldimi r5, r6, 32, 0 833; P9LE-NEXT: mtvsrdd v2, r5, r3 834; P9LE-NEXT: blr 835; 836; P8BE-LABEL: fromRegsi: 837; P8BE: # %bb.0: # %entry 838; P8BE-NEXT: rldimi r6, r5, 32, 0 839; P8BE-NEXT: rldimi r4, r3, 32, 0 840; P8BE-NEXT: mtvsrd f0, r6 841; P8BE-NEXT: mtvsrd f1, r4 842; P8BE-NEXT: xxmrghd v2, vs1, vs0 843; P8BE-NEXT: blr 844; 845; P8LE-LABEL: fromRegsi: 846; P8LE: # %bb.0: # %entry 847; P8LE-NEXT: rldimi r3, r4, 32, 0 848; P8LE-NEXT: rldimi r5, r6, 32, 0 849; P8LE-NEXT: mtvsrd f0, r3 850; P8LE-NEXT: mtvsrd f1, r5 851; P8LE-NEXT: xxmrghd v2, vs1, vs0 852; P8LE-NEXT: blr 853entry: 854 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 855 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 856 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 857 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3 858 ret <4 x i32> %vecinit3 859} 860 861; Function Attrs: norecurse nounwind readnone 862define <4 x i32> @fromDiffConstsi() { 863; P9BE-LABEL: fromDiffConstsi: 864; P9BE: # %bb.0: # %entry 865; P9BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha 866; P9BE-NEXT: addi r3, r3, .LCPI5_0@toc@l 867; P9BE-NEXT: lxvx v2, 0, r3 868; P9BE-NEXT: blr 869; 870; P9LE-LABEL: fromDiffConstsi: 871; P9LE: # %bb.0: # %entry 872; P9LE-NEXT: addis r3, r2, .LCPI5_0@toc@ha 873; P9LE-NEXT: addi r3, r3, .LCPI5_0@toc@l 874; P9LE-NEXT: lxvx v2, 0, r3 875; P9LE-NEXT: blr 876; 877; P8BE-LABEL: fromDiffConstsi: 878; P8BE: # %bb.0: # %entry 879; P8BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha 880; P8BE-NEXT: addi r3, r3, .LCPI5_0@toc@l 881; P8BE-NEXT: lxvw4x v2, 0, r3 882; P8BE-NEXT: blr 883; 884; P8LE-LABEL: fromDiffConstsi: 885; P8LE: # %bb.0: # %entry 886; P8LE-NEXT: addis r3, r2, .LCPI5_0@toc@ha 887; P8LE-NEXT: addi r3, r3, .LCPI5_0@toc@l 888; P8LE-NEXT: lvx v2, 0, r3 889; P8LE-NEXT: blr 890entry: 891 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19> 892} 893 894; Function Attrs: norecurse nounwind readonly 895define <4 x i32> @fromDiffMemConsAi(i32* nocapture readonly %arr) { 896; P9BE-LABEL: fromDiffMemConsAi: 897; P9BE: # %bb.0: # %entry 898; P9BE-NEXT: lxv v2, 0(r3) 899; P9BE-NEXT: blr 900; 901; P9LE-LABEL: fromDiffMemConsAi: 902; P9LE: # %bb.0: # %entry 903; P9LE-NEXT: lxv v2, 0(r3) 904; P9LE-NEXT: blr 905; 906; P8BE-LABEL: fromDiffMemConsAi: 907; P8BE: # %bb.0: # %entry 908; P8BE-NEXT: lxvw4x v2, 0, r3 909; P8BE-NEXT: blr 910; 911; P8LE-LABEL: fromDiffMemConsAi: 912; P8LE: # %bb.0: # %entry 913; P8LE-NEXT: lxvd2x vs0, 0, r3 914; P8LE-NEXT: xxswapd v2, vs0 915; P8LE-NEXT: blr 916entry: 917 %0 = load i32, i32* %arr, align 4 918 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 919 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 1 920 %1 = load i32, i32* %arrayidx1, align 4 921 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 922 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 923 %2 = load i32, i32* %arrayidx3, align 4 924 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 925 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 3 926 %3 = load i32, i32* %arrayidx5, align 4 927 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 928 ret <4 x i32> %vecinit6 929} 930 931; Function Attrs: norecurse nounwind readonly 932define <4 x i32> @fromDiffMemConsDi(i32* nocapture readonly %arr) { 933; P9BE-LABEL: fromDiffMemConsDi: 934; P9BE: # %bb.0: # %entry 935; P9BE-NEXT: lxv v2, 0(r3) 936; P9BE-NEXT: addis r3, r2, .LCPI7_0@toc@ha 937; P9BE-NEXT: addi r3, r3, .LCPI7_0@toc@l 938; P9BE-NEXT: lxvx v3, 0, r3 939; P9BE-NEXT: vperm v2, v2, v2, v3 940; P9BE-NEXT: blr 941; 942; P9LE-LABEL: fromDiffMemConsDi: 943; P9LE: # %bb.0: # %entry 944; P9LE-NEXT: lxvw4x v2, 0, r3 945; P9LE-NEXT: blr 946; 947; P8BE-LABEL: fromDiffMemConsDi: 948; P8BE: # %bb.0: # %entry 949; P8BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha 950; P8BE-NEXT: lxvw4x v2, 0, r3 951; P8BE-NEXT: addi r4, r4, .LCPI7_0@toc@l 952; P8BE-NEXT: lxvw4x v3, 0, r4 953; P8BE-NEXT: vperm v2, v2, v2, v3 954; P8BE-NEXT: blr 955; 956; P8LE-LABEL: fromDiffMemConsDi: 957; P8LE: # %bb.0: # %entry 958; P8LE-NEXT: lxvd2x vs0, 0, r3 959; P8LE-NEXT: addis r4, r2, .LCPI7_0@toc@ha 960; P8LE-NEXT: addi r3, r4, .LCPI7_0@toc@l 961; P8LE-NEXT: lvx v2, 0, r3 962; P8LE-NEXT: xxswapd v3, vs0 963; P8LE-NEXT: vperm v2, v3, v3, v2 964; P8LE-NEXT: blr 965entry: 966 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3 967 %0 = load i32, i32* %arrayidx, align 4 968 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 969 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 970 %1 = load i32, i32* %arrayidx1, align 4 971 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 972 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 1 973 %2 = load i32, i32* %arrayidx3, align 4 974 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 975 %3 = load i32, i32* %arr, align 4 976 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 977 ret <4 x i32> %vecinit6 978} 979 980; Function Attrs: norecurse nounwind readonly 981define <4 x i32> @fromDiffMemVarAi(i32* nocapture readonly %arr, i32 signext %elem) { 982; P9BE-LABEL: fromDiffMemVarAi: 983; P9BE: # %bb.0: # %entry 984; P9BE-NEXT: sldi r4, r4, 2 985; P9BE-NEXT: lxvx v2, r3, r4 986; P9BE-NEXT: blr 987; 988; P9LE-LABEL: fromDiffMemVarAi: 989; P9LE: # %bb.0: # %entry 990; P9LE-NEXT: sldi r4, r4, 2 991; P9LE-NEXT: lxvx v2, r3, r4 992; P9LE-NEXT: blr 993; 994; P8BE-LABEL: fromDiffMemVarAi: 995; P8BE: # %bb.0: # %entry 996; P8BE-NEXT: sldi r4, r4, 2 997; P8BE-NEXT: lxvw4x v2, r3, r4 998; P8BE-NEXT: blr 999; 1000; P8LE-LABEL: fromDiffMemVarAi: 1001; P8LE: # %bb.0: # %entry 1002; P8LE-NEXT: sldi r4, r4, 2 1003; P8LE-NEXT: lxvd2x vs0, r3, r4 1004; P8LE-NEXT: xxswapd v2, vs0 1005; P8LE-NEXT: blr 1006entry: 1007 %idxprom = sext i32 %elem to i64 1008 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 1009 %0 = load i32, i32* %arrayidx, align 4 1010 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1011 %add = add nsw i32 %elem, 1 1012 %idxprom1 = sext i32 %add to i64 1013 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 1014 %1 = load i32, i32* %arrayidx2, align 4 1015 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1016 %add4 = add nsw i32 %elem, 2 1017 %idxprom5 = sext i32 %add4 to i64 1018 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 1019 %2 = load i32, i32* %arrayidx6, align 4 1020 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 1021 %add8 = add nsw i32 %elem, 3 1022 %idxprom9 = sext i32 %add8 to i64 1023 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 1024 %3 = load i32, i32* %arrayidx10, align 4 1025 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 1026 ret <4 x i32> %vecinit11 1027} 1028 1029; Function Attrs: norecurse nounwind readonly 1030define <4 x i32> @fromDiffMemVarDi(i32* nocapture readonly %arr, i32 signext %elem) { 1031; P9BE-LABEL: fromDiffMemVarDi: 1032; P9BE: # %bb.0: # %entry 1033; P9BE-NEXT: sldi r4, r4, 2 1034; P9BE-NEXT: add r3, r3, r4 1035; P9BE-NEXT: addi r3, r3, -12 1036; P9BE-NEXT: lxvx v2, 0, r3 1037; P9BE-NEXT: addis r3, r2, .LCPI9_0@toc@ha 1038; P9BE-NEXT: addi r3, r3, .LCPI9_0@toc@l 1039; P9BE-NEXT: lxvx v3, 0, r3 1040; P9BE-NEXT: vperm v2, v2, v2, v3 1041; P9BE-NEXT: blr 1042; 1043; P9LE-LABEL: fromDiffMemVarDi: 1044; P9LE: # %bb.0: # %entry 1045; P9LE-NEXT: sldi r4, r4, 2 1046; P9LE-NEXT: add r3, r3, r4 1047; P9LE-NEXT: addi r3, r3, -12 1048; P9LE-NEXT: lxvx v2, 0, r3 1049; P9LE-NEXT: addis r3, r2, .LCPI9_0@toc@ha 1050; P9LE-NEXT: addi r3, r3, .LCPI9_0@toc@l 1051; P9LE-NEXT: lxvx v3, 0, r3 1052; P9LE-NEXT: vperm v2, v2, v2, v3 1053; P9LE-NEXT: blr 1054; 1055; P8BE-LABEL: fromDiffMemVarDi: 1056; P8BE: # %bb.0: # %entry 1057; P8BE-NEXT: sldi r4, r4, 2 1058; P8BE-NEXT: addis r5, r2, .LCPI9_0@toc@ha 1059; P8BE-NEXT: add r3, r3, r4 1060; P8BE-NEXT: addi r4, r5, .LCPI9_0@toc@l 1061; P8BE-NEXT: addi r3, r3, -12 1062; P8BE-NEXT: lxvw4x v3, 0, r4 1063; P8BE-NEXT: lxvw4x v2, 0, r3 1064; P8BE-NEXT: vperm v2, v2, v2, v3 1065; P8BE-NEXT: blr 1066; 1067; P8LE-LABEL: fromDiffMemVarDi: 1068; P8LE: # %bb.0: # %entry 1069; P8LE-NEXT: sldi r4, r4, 2 1070; P8LE-NEXT: addis r5, r2, .LCPI9_0@toc@ha 1071; P8LE-NEXT: add r3, r3, r4 1072; P8LE-NEXT: addi r3, r3, -12 1073; P8LE-NEXT: lxvd2x vs0, 0, r3 1074; P8LE-NEXT: addi r3, r5, .LCPI9_0@toc@l 1075; P8LE-NEXT: lvx v3, 0, r3 1076; P8LE-NEXT: xxswapd v2, vs0 1077; P8LE-NEXT: vperm v2, v2, v2, v3 1078; P8LE-NEXT: blr 1079entry: 1080 %idxprom = sext i32 %elem to i64 1081 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 1082 %0 = load i32, i32* %arrayidx, align 4 1083 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1084 %sub = add nsw i32 %elem, -1 1085 %idxprom1 = sext i32 %sub to i64 1086 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 1087 %1 = load i32, i32* %arrayidx2, align 4 1088 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1089 %sub4 = add nsw i32 %elem, -2 1090 %idxprom5 = sext i32 %sub4 to i64 1091 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 1092 %2 = load i32, i32* %arrayidx6, align 4 1093 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 1094 %sub8 = add nsw i32 %elem, -3 1095 %idxprom9 = sext i32 %sub8 to i64 1096 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 1097 %3 = load i32, i32* %arrayidx10, align 4 1098 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 1099 ret <4 x i32> %vecinit11 1100} 1101 1102; Function Attrs: norecurse nounwind readonly 1103define <4 x i32> @fromRandMemConsi(i32* nocapture readonly %arr) { 1104; P9BE-LABEL: fromRandMemConsi: 1105; P9BE: # %bb.0: # %entry 1106; P9BE-NEXT: lwz r4, 16(r3) 1107; P9BE-NEXT: lwz r5, 72(r3) 1108; P9BE-NEXT: lwz r6, 8(r3) 1109; P9BE-NEXT: lwz r3, 352(r3) 1110; P9BE-NEXT: rldimi r3, r6, 32, 0 1111; P9BE-NEXT: rldimi r5, r4, 32, 0 1112; P9BE-NEXT: mtvsrdd v2, r5, r3 1113; P9BE-NEXT: blr 1114; 1115; P9LE-LABEL: fromRandMemConsi: 1116; P9LE: # %bb.0: # %entry 1117; P9LE-NEXT: lwz r4, 16(r3) 1118; P9LE-NEXT: lwz r5, 72(r3) 1119; P9LE-NEXT: lwz r6, 8(r3) 1120; P9LE-NEXT: lwz r3, 352(r3) 1121; P9LE-NEXT: rldimi r4, r5, 32, 0 1122; P9LE-NEXT: rldimi r6, r3, 32, 0 1123; P9LE-NEXT: mtvsrdd v2, r6, r4 1124; P9LE-NEXT: blr 1125; 1126; P8BE-LABEL: fromRandMemConsi: 1127; P8BE: # %bb.0: # %entry 1128; P8BE-NEXT: lwz r4, 8(r3) 1129; P8BE-NEXT: lwz r5, 352(r3) 1130; P8BE-NEXT: lwz r6, 16(r3) 1131; P8BE-NEXT: lwz r3, 72(r3) 1132; P8BE-NEXT: rldimi r5, r4, 32, 0 1133; P8BE-NEXT: rldimi r3, r6, 32, 0 1134; P8BE-NEXT: mtvsrd f0, r5 1135; P8BE-NEXT: mtvsrd f1, r3 1136; P8BE-NEXT: xxmrghd v2, vs1, vs0 1137; P8BE-NEXT: blr 1138; 1139; P8LE-LABEL: fromRandMemConsi: 1140; P8LE: # %bb.0: # %entry 1141; P8LE-NEXT: lwz r4, 16(r3) 1142; P8LE-NEXT: lwz r5, 72(r3) 1143; P8LE-NEXT: lwz r6, 8(r3) 1144; P8LE-NEXT: lwz r3, 352(r3) 1145; P8LE-NEXT: rldimi r4, r5, 32, 0 1146; P8LE-NEXT: rldimi r6, r3, 32, 0 1147; P8LE-NEXT: mtvsrd f0, r4 1148; P8LE-NEXT: mtvsrd f1, r6 1149; P8LE-NEXT: xxmrghd v2, vs1, vs0 1150; P8LE-NEXT: blr 1151entry: 1152 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4 1153 %0 = load i32, i32* %arrayidx, align 4 1154 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1155 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18 1156 %1 = load i32, i32* %arrayidx1, align 4 1157 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1158 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 1159 %2 = load i32, i32* %arrayidx3, align 4 1160 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 1161 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 88 1162 %3 = load i32, i32* %arrayidx5, align 4 1163 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 1164 ret <4 x i32> %vecinit6 1165} 1166 1167; Function Attrs: norecurse nounwind readonly 1168define <4 x i32> @fromRandMemVari(i32* nocapture readonly %arr, i32 signext %elem) { 1169; P9BE-LABEL: fromRandMemVari: 1170; P9BE: # %bb.0: # %entry 1171; P9BE-NEXT: sldi r4, r4, 2 1172; P9BE-NEXT: add r3, r3, r4 1173; P9BE-NEXT: lwz r4, 16(r3) 1174; P9BE-NEXT: lwz r5, 4(r3) 1175; P9BE-NEXT: lwz r6, 8(r3) 1176; P9BE-NEXT: lwz r3, 32(r3) 1177; P9BE-NEXT: rldimi r3, r6, 32, 0 1178; P9BE-NEXT: rldimi r5, r4, 32, 0 1179; P9BE-NEXT: mtvsrdd v2, r5, r3 1180; P9BE-NEXT: blr 1181; 1182; P9LE-LABEL: fromRandMemVari: 1183; P9LE: # %bb.0: # %entry 1184; P9LE-NEXT: sldi r4, r4, 2 1185; P9LE-NEXT: add r3, r3, r4 1186; P9LE-NEXT: lwz r4, 16(r3) 1187; P9LE-NEXT: lwz r5, 4(r3) 1188; P9LE-NEXT: lwz r6, 8(r3) 1189; P9LE-NEXT: lwz r3, 32(r3) 1190; P9LE-NEXT: rldimi r4, r5, 32, 0 1191; P9LE-NEXT: rldimi r6, r3, 32, 0 1192; P9LE-NEXT: mtvsrdd v2, r6, r4 1193; P9LE-NEXT: blr 1194; 1195; P8BE-LABEL: fromRandMemVari: 1196; P8BE: # %bb.0: # %entry 1197; P8BE-NEXT: sldi r4, r4, 2 1198; P8BE-NEXT: add r3, r3, r4 1199; P8BE-NEXT: lwz r4, 8(r3) 1200; P8BE-NEXT: lwz r5, 32(r3) 1201; P8BE-NEXT: lwz r6, 16(r3) 1202; P8BE-NEXT: lwz r3, 4(r3) 1203; P8BE-NEXT: rldimi r5, r4, 32, 0 1204; P8BE-NEXT: rldimi r3, r6, 32, 0 1205; P8BE-NEXT: mtvsrd f0, r5 1206; P8BE-NEXT: mtvsrd f1, r3 1207; P8BE-NEXT: xxmrghd v2, vs1, vs0 1208; P8BE-NEXT: blr 1209; 1210; P8LE-LABEL: fromRandMemVari: 1211; P8LE: # %bb.0: # %entry 1212; P8LE-NEXT: sldi r4, r4, 2 1213; P8LE-NEXT: add r3, r3, r4 1214; P8LE-NEXT: lwz r4, 16(r3) 1215; P8LE-NEXT: lwz r5, 4(r3) 1216; P8LE-NEXT: lwz r6, 8(r3) 1217; P8LE-NEXT: lwz r3, 32(r3) 1218; P8LE-NEXT: rldimi r4, r5, 32, 0 1219; P8LE-NEXT: rldimi r6, r3, 32, 0 1220; P8LE-NEXT: mtvsrd f0, r4 1221; P8LE-NEXT: mtvsrd f1, r6 1222; P8LE-NEXT: xxmrghd v2, vs1, vs0 1223; P8LE-NEXT: blr 1224entry: 1225 %add = add nsw i32 %elem, 4 1226 %idxprom = sext i32 %add to i64 1227 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 1228 %0 = load i32, i32* %arrayidx, align 4 1229 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1230 %add1 = add nsw i32 %elem, 1 1231 %idxprom2 = sext i32 %add1 to i64 1232 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 %idxprom2 1233 %1 = load i32, i32* %arrayidx3, align 4 1234 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1235 %add5 = add nsw i32 %elem, 2 1236 %idxprom6 = sext i32 %add5 to i64 1237 %arrayidx7 = getelementptr inbounds i32, i32* %arr, i64 %idxprom6 1238 %2 = load i32, i32* %arrayidx7, align 4 1239 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2 1240 %add9 = add nsw i32 %elem, 8 1241 %idxprom10 = sext i32 %add9 to i64 1242 %arrayidx11 = getelementptr inbounds i32, i32* %arr, i64 %idxprom10 1243 %3 = load i32, i32* %arrayidx11, align 4 1244 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3 1245 ret <4 x i32> %vecinit12 1246} 1247 1248; Function Attrs: norecurse nounwind readnone 1249define <4 x i32> @spltRegVali(i32 signext %val) { 1250; P9BE-LABEL: spltRegVali: 1251; P9BE: # %bb.0: # %entry 1252; P9BE-NEXT: mtvsrws v2, r3 1253; P9BE-NEXT: blr 1254; 1255; P9LE-LABEL: spltRegVali: 1256; P9LE: # %bb.0: # %entry 1257; P9LE-NEXT: mtvsrws v2, r3 1258; P9LE-NEXT: blr 1259; 1260; P8BE-LABEL: spltRegVali: 1261; P8BE: # %bb.0: # %entry 1262; P8BE-NEXT: mtvsrwz f0, r3 1263; P8BE-NEXT: xxspltw v2, vs0, 1 1264; P8BE-NEXT: blr 1265; 1266; P8LE-LABEL: spltRegVali: 1267; P8LE: # %bb.0: # %entry 1268; P8LE-NEXT: mtvsrwz f0, r3 1269; P8LE-NEXT: xxspltw v2, vs0, 1 1270; P8LE-NEXT: blr 1271entry: 1272 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0 1273 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1274 ret <4 x i32> %splat.splat 1275} 1276 1277; Function Attrs: norecurse nounwind readonly 1278define <4 x i32> @spltMemVali(i32* nocapture readonly %ptr) { 1279; P9BE-LABEL: spltMemVali: 1280; P9BE: # %bb.0: # %entry 1281; P9BE-NEXT: lxvwsx v2, 0, r3 1282; P9BE-NEXT: blr 1283; 1284; P9LE-LABEL: spltMemVali: 1285; P9LE: # %bb.0: # %entry 1286; P9LE-NEXT: lxvwsx v2, 0, r3 1287; P9LE-NEXT: blr 1288; 1289; P8BE-LABEL: spltMemVali: 1290; P8BE: # %bb.0: # %entry 1291; P8BE-NEXT: lfiwzx f0, 0, r3 1292; P8BE-NEXT: xxsldwi vs0, f0, f0, 1 1293; P8BE-NEXT: xxspltw v2, vs0, 0 1294; P8BE-NEXT: blr 1295; 1296; P8LE-LABEL: spltMemVali: 1297; P8LE: # %bb.0: # %entry 1298; P8LE-NEXT: lfiwzx f0, 0, r3 1299; P8LE-NEXT: xxpermdi vs0, f0, f0, 2 1300; P8LE-NEXT: xxspltw v2, vs0, 3 1301; P8LE-NEXT: blr 1302entry: 1303 %0 = load i32, i32* %ptr, align 4 1304 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 1305 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1306 ret <4 x i32> %splat.splat 1307} 1308 1309; Function Attrs: norecurse nounwind readnone 1310define <4 x i32> @spltCnstConvftoi() { 1311; P9BE-LABEL: spltCnstConvftoi: 1312; P9BE: # %bb.0: # %entry 1313; P9BE-NEXT: vspltisw v2, 4 1314; P9BE-NEXT: blr 1315; 1316; P9LE-LABEL: spltCnstConvftoi: 1317; P9LE: # %bb.0: # %entry 1318; P9LE-NEXT: vspltisw v2, 4 1319; P9LE-NEXT: blr 1320; 1321; P8BE-LABEL: spltCnstConvftoi: 1322; P8BE: # %bb.0: # %entry 1323; P8BE-NEXT: vspltisw v2, 4 1324; P8BE-NEXT: blr 1325; 1326; P8LE-LABEL: spltCnstConvftoi: 1327; P8LE: # %bb.0: # %entry 1328; P8LE-NEXT: vspltisw v2, 4 1329; P8LE-NEXT: blr 1330entry: 1331 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 1332} 1333 1334; Function Attrs: norecurse nounwind readnone 1335define <4 x i32> @fromRegsConvftoi(float %a, float %b, float %c, float %d) { 1336; P9BE-LABEL: fromRegsConvftoi: 1337; P9BE: # %bb.0: # %entry 1338; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1339; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1340; P9BE-NEXT: xxmrghd vs0, vs2, vs4 1341; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1342; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1343; P9BE-NEXT: xvcvdpsxws v2, vs0 1344; P9BE-NEXT: xxmrghd vs0, vs1, vs3 1345; P9BE-NEXT: xvcvdpsxws v3, vs0 1346; P9BE-NEXT: vmrgew v2, v3, v2 1347; P9BE-NEXT: blr 1348; 1349; P9LE-LABEL: fromRegsConvftoi: 1350; P9LE: # %bb.0: # %entry 1351; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1352; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1353; P9LE-NEXT: xxmrghd vs0, vs3, vs1 1354; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1355; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1356; P9LE-NEXT: xvcvdpsxws v2, vs0 1357; P9LE-NEXT: xxmrghd vs0, vs4, vs2 1358; P9LE-NEXT: xvcvdpsxws v3, vs0 1359; P9LE-NEXT: vmrgew v2, v3, v2 1360; P9LE-NEXT: blr 1361; 1362; P8BE-LABEL: fromRegsConvftoi: 1363; P8BE: # %bb.0: # %entry 1364; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1365; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1366; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1367; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1368; P8BE-NEXT: xxmrghd vs0, vs2, vs4 1369; P8BE-NEXT: xxmrghd vs1, vs1, vs3 1370; P8BE-NEXT: xvcvdpsxws v2, vs0 1371; P8BE-NEXT: xvcvdpsxws v3, vs1 1372; P8BE-NEXT: vmrgew v2, v3, v2 1373; P8BE-NEXT: blr 1374; 1375; P8LE-LABEL: fromRegsConvftoi: 1376; P8LE: # %bb.0: # %entry 1377; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1378; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1379; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1380; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1381; P8LE-NEXT: xxmrghd vs0, vs3, vs1 1382; P8LE-NEXT: xxmrghd vs1, vs4, vs2 1383; P8LE-NEXT: xvcvdpsxws v2, vs0 1384; P8LE-NEXT: xvcvdpsxws v3, vs1 1385; P8LE-NEXT: vmrgew v2, v3, v2 1386; P8LE-NEXT: blr 1387entry: 1388 %conv = fptosi float %a to i32 1389 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1390 %conv1 = fptosi float %b to i32 1391 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 1392 %conv3 = fptosi float %c to i32 1393 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 1394 %conv5 = fptosi float %d to i32 1395 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 1396 ret <4 x i32> %vecinit6 1397} 1398 1399; Function Attrs: norecurse nounwind readnone 1400define <4 x i32> @fromDiffConstsConvftoi() { 1401; P9BE-LABEL: fromDiffConstsConvftoi: 1402; P9BE: # %bb.0: # %entry 1403; P9BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha 1404; P9BE-NEXT: addi r3, r3, .LCPI16_0@toc@l 1405; P9BE-NEXT: lxvx v2, 0, r3 1406; P9BE-NEXT: blr 1407; 1408; P9LE-LABEL: fromDiffConstsConvftoi: 1409; P9LE: # %bb.0: # %entry 1410; P9LE-NEXT: addis r3, r2, .LCPI16_0@toc@ha 1411; P9LE-NEXT: addi r3, r3, .LCPI16_0@toc@l 1412; P9LE-NEXT: lxvx v2, 0, r3 1413; P9LE-NEXT: blr 1414; 1415; P8BE-LABEL: fromDiffConstsConvftoi: 1416; P8BE: # %bb.0: # %entry 1417; P8BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha 1418; P8BE-NEXT: addi r3, r3, .LCPI16_0@toc@l 1419; P8BE-NEXT: lxvw4x v2, 0, r3 1420; P8BE-NEXT: blr 1421; 1422; P8LE-LABEL: fromDiffConstsConvftoi: 1423; P8LE: # %bb.0: # %entry 1424; P8LE-NEXT: addis r3, r2, .LCPI16_0@toc@ha 1425; P8LE-NEXT: addi r3, r3, .LCPI16_0@toc@l 1426; P8LE-NEXT: lvx v2, 0, r3 1427; P8LE-NEXT: blr 1428entry: 1429 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 1430} 1431 1432; Function Attrs: norecurse nounwind readonly 1433define <4 x i32> @fromDiffMemConsAConvftoi(float* nocapture readonly %ptr) { 1434; P9BE-LABEL: fromDiffMemConsAConvftoi: 1435; P9BE: # %bb.0: # %entry 1436; P9BE-NEXT: lxv vs0, 0(r3) 1437; P9BE-NEXT: xvcvspsxws v2, vs0 1438; P9BE-NEXT: blr 1439; 1440; P9LE-LABEL: fromDiffMemConsAConvftoi: 1441; P9LE: # %bb.0: # %entry 1442; P9LE-NEXT: lxv vs0, 0(r3) 1443; P9LE-NEXT: xvcvspsxws v2, vs0 1444; P9LE-NEXT: blr 1445; 1446; P8BE-LABEL: fromDiffMemConsAConvftoi: 1447; P8BE: # %bb.0: # %entry 1448; P8BE-NEXT: lxvw4x vs0, 0, r3 1449; P8BE-NEXT: xvcvspsxws v2, vs0 1450; P8BE-NEXT: blr 1451; 1452; P8LE-LABEL: fromDiffMemConsAConvftoi: 1453; P8LE: # %bb.0: # %entry 1454; P8LE-NEXT: lxvd2x vs0, 0, r3 1455; P8LE-NEXT: xxswapd v2, vs0 1456; P8LE-NEXT: xvcvspsxws v2, v2 1457; P8LE-NEXT: blr 1458entry: 1459 %0 = bitcast float* %ptr to <4 x float>* 1460 %1 = load <4 x float>, <4 x float>* %0, align 4 1461 %2 = fptosi <4 x float> %1 to <4 x i32> 1462 ret <4 x i32> %2 1463} 1464 1465; Function Attrs: norecurse nounwind readonly 1466define <4 x i32> @fromDiffMemConsDConvftoi(float* nocapture readonly %ptr) { 1467; P9BE-LABEL: fromDiffMemConsDConvftoi: 1468; P9BE: # %bb.0: # %entry 1469; P9BE-NEXT: lxv v2, 0(r3) 1470; P9BE-NEXT: addis r3, r2, .LCPI18_0@toc@ha 1471; P9BE-NEXT: addi r3, r3, .LCPI18_0@toc@l 1472; P9BE-NEXT: lxvx v3, 0, r3 1473; P9BE-NEXT: vperm v2, v2, v2, v3 1474; P9BE-NEXT: xvcvspsxws v2, v2 1475; P9BE-NEXT: blr 1476; 1477; P9LE-LABEL: fromDiffMemConsDConvftoi: 1478; P9LE: # %bb.0: # %entry 1479; P9LE-NEXT: lxv v2, 0(r3) 1480; P9LE-NEXT: addis r3, r2, .LCPI18_0@toc@ha 1481; P9LE-NEXT: addi r3, r3, .LCPI18_0@toc@l 1482; P9LE-NEXT: lxvx v3, 0, r3 1483; P9LE-NEXT: vperm v2, v2, v2, v3 1484; P9LE-NEXT: xvcvspsxws v2, v2 1485; P9LE-NEXT: blr 1486; 1487; P8BE-LABEL: fromDiffMemConsDConvftoi: 1488; P8BE: # %bb.0: # %entry 1489; P8BE-NEXT: addis r4, r2, .LCPI18_0@toc@ha 1490; P8BE-NEXT: lxvw4x v2, 0, r3 1491; P8BE-NEXT: addi r4, r4, .LCPI18_0@toc@l 1492; P8BE-NEXT: lxvw4x v3, 0, r4 1493; P8BE-NEXT: vperm v2, v2, v2, v3 1494; P8BE-NEXT: xvcvspsxws v2, v2 1495; P8BE-NEXT: blr 1496; 1497; P8LE-LABEL: fromDiffMemConsDConvftoi: 1498; P8LE: # %bb.0: # %entry 1499; P8LE-NEXT: lxvd2x vs0, 0, r3 1500; P8LE-NEXT: addis r4, r2, .LCPI18_0@toc@ha 1501; P8LE-NEXT: addi r3, r4, .LCPI18_0@toc@l 1502; P8LE-NEXT: lvx v2, 0, r3 1503; P8LE-NEXT: xxswapd v3, vs0 1504; P8LE-NEXT: vperm v2, v3, v3, v2 1505; P8LE-NEXT: xvcvspsxws v2, v2 1506; P8LE-NEXT: blr 1507entry: 1508 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 1509 %0 = load float, float* %arrayidx, align 4 1510 %conv = fptosi float %0 to i32 1511 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1512 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 1513 %1 = load float, float* %arrayidx1, align 4 1514 %conv2 = fptosi float %1 to i32 1515 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 1516 %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1 1517 %2 = load float, float* %arrayidx4, align 4 1518 %conv5 = fptosi float %2 to i32 1519 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 1520 %3 = load float, float* %ptr, align 4 1521 %conv8 = fptosi float %3 to i32 1522 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 1523 ret <4 x i32> %vecinit9 1524} 1525 1526; Function Attrs: norecurse nounwind readonly 1527define <4 x i32> @fromDiffMemVarAConvftoi(float* nocapture readonly %arr, i32 signext %elem) { 1528; P9BE-LABEL: fromDiffMemVarAConvftoi: 1529; P9BE: # %bb.0: # %entry 1530; P9BE-NEXT: sldi r4, r4, 2 1531; P9BE-NEXT: lfsux f0, r3, r4 1532; P9BE-NEXT: lfs f1, 12(r3) 1533; P9BE-NEXT: lfs f2, 4(r3) 1534; P9BE-NEXT: xxmrghd vs1, vs2, vs1 1535; P9BE-NEXT: xvcvdpsp v2, vs1 1536; P9BE-NEXT: lfs f1, 8(r3) 1537; P9BE-NEXT: xxmrghd vs0, vs0, vs1 1538; P9BE-NEXT: xvcvdpsp v3, vs0 1539; P9BE-NEXT: vmrgew v2, v3, v2 1540; P9BE-NEXT: xvcvspsxws v2, v2 1541; P9BE-NEXT: blr 1542; 1543; P9LE-LABEL: fromDiffMemVarAConvftoi: 1544; P9LE: # %bb.0: # %entry 1545; P9LE-NEXT: sldi r4, r4, 2 1546; P9LE-NEXT: lfsux f0, r3, r4 1547; P9LE-NEXT: lfs f1, 8(r3) 1548; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1549; P9LE-NEXT: lfs f1, 12(r3) 1550; P9LE-NEXT: xvcvdpsp v2, vs0 1551; P9LE-NEXT: lfs f0, 4(r3) 1552; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1553; P9LE-NEXT: xvcvdpsp v3, vs0 1554; P9LE-NEXT: vmrgew v2, v3, v2 1555; P9LE-NEXT: xvcvspsxws v2, v2 1556; P9LE-NEXT: blr 1557; 1558; P8BE-LABEL: fromDiffMemVarAConvftoi: 1559; P8BE: # %bb.0: # %entry 1560; P8BE-NEXT: sldi r4, r4, 2 1561; P8BE-NEXT: lfsux f0, r3, r4 1562; P8BE-NEXT: lfs f1, 12(r3) 1563; P8BE-NEXT: lfs f2, 4(r3) 1564; P8BE-NEXT: lfs f3, 8(r3) 1565; P8BE-NEXT: xxmrghd vs1, vs2, vs1 1566; P8BE-NEXT: xxmrghd vs0, vs0, vs3 1567; P8BE-NEXT: xvcvdpsp v2, vs1 1568; P8BE-NEXT: xvcvdpsp v3, vs0 1569; P8BE-NEXT: vmrgew v2, v3, v2 1570; P8BE-NEXT: xvcvspsxws v2, v2 1571; P8BE-NEXT: blr 1572; 1573; P8LE-LABEL: fromDiffMemVarAConvftoi: 1574; P8LE: # %bb.0: # %entry 1575; P8LE-NEXT: sldi r4, r4, 2 1576; P8LE-NEXT: lfsux f0, r3, r4 1577; P8LE-NEXT: lfs f1, 8(r3) 1578; P8LE-NEXT: lfs f2, 4(r3) 1579; P8LE-NEXT: lfs f3, 12(r3) 1580; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1581; P8LE-NEXT: xxmrghd vs1, vs3, vs2 1582; P8LE-NEXT: xvcvdpsp v2, vs0 1583; P8LE-NEXT: xvcvdpsp v3, vs1 1584; P8LE-NEXT: vmrgew v2, v3, v2 1585; P8LE-NEXT: xvcvspsxws v2, v2 1586; P8LE-NEXT: blr 1587entry: 1588 %idxprom = sext i32 %elem to i64 1589 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 1590 %0 = load float, float* %arrayidx, align 4 1591 %conv = fptosi float %0 to i32 1592 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1593 %add = add nsw i32 %elem, 1 1594 %idxprom1 = sext i32 %add to i64 1595 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 1596 %1 = load float, float* %arrayidx2, align 4 1597 %conv3 = fptosi float %1 to i32 1598 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1599 %add5 = add nsw i32 %elem, 2 1600 %idxprom6 = sext i32 %add5 to i64 1601 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 1602 %2 = load float, float* %arrayidx7, align 4 1603 %conv8 = fptosi float %2 to i32 1604 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1605 %add10 = add nsw i32 %elem, 3 1606 %idxprom11 = sext i32 %add10 to i64 1607 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 1608 %3 = load float, float* %arrayidx12, align 4 1609 %conv13 = fptosi float %3 to i32 1610 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1611 ret <4 x i32> %vecinit14 1612; FIXME: implement finding consecutive loads with pre-inc 1613} 1614 1615; Function Attrs: norecurse nounwind readonly 1616define <4 x i32> @fromDiffMemVarDConvftoi(float* nocapture readonly %arr, i32 signext %elem) { 1617; P9BE-LABEL: fromDiffMemVarDConvftoi: 1618; P9BE: # %bb.0: # %entry 1619; P9BE-NEXT: sldi r4, r4, 2 1620; P9BE-NEXT: lfsux f0, r3, r4 1621; P9BE-NEXT: lfs f1, -12(r3) 1622; P9BE-NEXT: lfs f2, -4(r3) 1623; P9BE-NEXT: xxmrghd vs1, vs2, vs1 1624; P9BE-NEXT: xvcvdpsp v2, vs1 1625; P9BE-NEXT: lfs f1, -8(r3) 1626; P9BE-NEXT: xxmrghd vs0, vs0, vs1 1627; P9BE-NEXT: xvcvdpsp v3, vs0 1628; P9BE-NEXT: vmrgew v2, v3, v2 1629; P9BE-NEXT: xvcvspsxws v2, v2 1630; P9BE-NEXT: blr 1631; 1632; P9LE-LABEL: fromDiffMemVarDConvftoi: 1633; P9LE: # %bb.0: # %entry 1634; P9LE-NEXT: sldi r4, r4, 2 1635; P9LE-NEXT: lfsux f0, r3, r4 1636; P9LE-NEXT: lfs f1, -8(r3) 1637; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1638; P9LE-NEXT: lfs f1, -12(r3) 1639; P9LE-NEXT: xvcvdpsp v2, vs0 1640; P9LE-NEXT: lfs f0, -4(r3) 1641; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1642; P9LE-NEXT: xvcvdpsp v3, vs0 1643; P9LE-NEXT: vmrgew v2, v3, v2 1644; P9LE-NEXT: xvcvspsxws v2, v2 1645; P9LE-NEXT: blr 1646; 1647; P8BE-LABEL: fromDiffMemVarDConvftoi: 1648; P8BE: # %bb.0: # %entry 1649; P8BE-NEXT: sldi r4, r4, 2 1650; P8BE-NEXT: lfsux f0, r3, r4 1651; P8BE-NEXT: lfs f1, -12(r3) 1652; P8BE-NEXT: lfs f2, -4(r3) 1653; P8BE-NEXT: lfs f3, -8(r3) 1654; P8BE-NEXT: xxmrghd vs1, vs2, vs1 1655; P8BE-NEXT: xxmrghd vs0, vs0, vs3 1656; P8BE-NEXT: xvcvdpsp v2, vs1 1657; P8BE-NEXT: xvcvdpsp v3, vs0 1658; P8BE-NEXT: vmrgew v2, v3, v2 1659; P8BE-NEXT: xvcvspsxws v2, v2 1660; P8BE-NEXT: blr 1661; 1662; P8LE-LABEL: fromDiffMemVarDConvftoi: 1663; P8LE: # %bb.0: # %entry 1664; P8LE-NEXT: sldi r4, r4, 2 1665; P8LE-NEXT: lfsux f0, r3, r4 1666; P8LE-NEXT: lfs f1, -8(r3) 1667; P8LE-NEXT: lfs f2, -4(r3) 1668; P8LE-NEXT: lfs f3, -12(r3) 1669; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1670; P8LE-NEXT: xxmrghd vs1, vs3, vs2 1671; P8LE-NEXT: xvcvdpsp v2, vs0 1672; P8LE-NEXT: xvcvdpsp v3, vs1 1673; P8LE-NEXT: vmrgew v2, v3, v2 1674; P8LE-NEXT: xvcvspsxws v2, v2 1675; P8LE-NEXT: blr 1676entry: 1677 %idxprom = sext i32 %elem to i64 1678 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 1679 %0 = load float, float* %arrayidx, align 4 1680 %conv = fptosi float %0 to i32 1681 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1682 %sub = add nsw i32 %elem, -1 1683 %idxprom1 = sext i32 %sub to i64 1684 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 1685 %1 = load float, float* %arrayidx2, align 4 1686 %conv3 = fptosi float %1 to i32 1687 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1688 %sub5 = add nsw i32 %elem, -2 1689 %idxprom6 = sext i32 %sub5 to i64 1690 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 1691 %2 = load float, float* %arrayidx7, align 4 1692 %conv8 = fptosi float %2 to i32 1693 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1694 %sub10 = add nsw i32 %elem, -3 1695 %idxprom11 = sext i32 %sub10 to i64 1696 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 1697 %3 = load float, float* %arrayidx12, align 4 1698 %conv13 = fptosi float %3 to i32 1699 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1700 ret <4 x i32> %vecinit14 1701; FIXME: implement finding consecutive loads with pre-inc 1702} 1703 1704; Function Attrs: norecurse nounwind readnone 1705define <4 x i32> @spltRegValConvftoi(float %val) { 1706; P9BE-LABEL: spltRegValConvftoi: 1707; P9BE: # %bb.0: # %entry 1708; P9BE-NEXT: xscvdpsxws f0, f1 1709; P9BE-NEXT: xxspltw v2, vs0, 1 1710; P9BE-NEXT: blr 1711; 1712; P9LE-LABEL: spltRegValConvftoi: 1713; P9LE: # %bb.0: # %entry 1714; P9LE-NEXT: xscvdpsxws f0, f1 1715; P9LE-NEXT: xxspltw v2, vs0, 1 1716; P9LE-NEXT: blr 1717; 1718; P8BE-LABEL: spltRegValConvftoi: 1719; P8BE: # %bb.0: # %entry 1720; P8BE-NEXT: xscvdpsxws f0, f1 1721; P8BE-NEXT: xxspltw v2, vs0, 1 1722; P8BE-NEXT: blr 1723; 1724; P8LE-LABEL: spltRegValConvftoi: 1725; P8LE: # %bb.0: # %entry 1726; P8LE-NEXT: xscvdpsxws f0, f1 1727; P8LE-NEXT: xxspltw v2, vs0, 1 1728; P8LE-NEXT: blr 1729entry: 1730 %conv = fptosi float %val to i32 1731 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1732 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1733 ret <4 x i32> %splat.splat 1734} 1735 1736; Function Attrs: norecurse nounwind readonly 1737define <4 x i32> @spltMemValConvftoi(float* nocapture readonly %ptr) { 1738; P9BE-LABEL: spltMemValConvftoi: 1739; P9BE: # %bb.0: # %entry 1740; P9BE-NEXT: lxvwsx vs0, 0, r3 1741; P9BE-NEXT: xvcvspsxws v2, vs0 1742; P9BE-NEXT: blr 1743; 1744; P9LE-LABEL: spltMemValConvftoi: 1745; P9LE: # %bb.0: # %entry 1746; P9LE-NEXT: lxvwsx vs0, 0, r3 1747; P9LE-NEXT: xvcvspsxws v2, vs0 1748; P9LE-NEXT: blr 1749; 1750; P8BE-LABEL: spltMemValConvftoi: 1751; P8BE: # %bb.0: # %entry 1752; P8BE-NEXT: lfsx f0, 0, r3 1753; P8BE-NEXT: xscvdpsxws f0, f0 1754; P8BE-NEXT: xxspltw v2, vs0, 1 1755; P8BE-NEXT: blr 1756; 1757; P8LE-LABEL: spltMemValConvftoi: 1758; P8LE: # %bb.0: # %entry 1759; P8LE-NEXT: lfsx f0, 0, r3 1760; P8LE-NEXT: xscvdpsxws f0, f0 1761; P8LE-NEXT: xxspltw v2, vs0, 1 1762; P8LE-NEXT: blr 1763entry: 1764 %0 = load float, float* %ptr, align 4 1765 %conv = fptosi float %0 to i32 1766 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1767 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1768 ret <4 x i32> %splat.splat 1769} 1770 1771; Function Attrs: norecurse nounwind readnone 1772define <4 x i32> @spltCnstConvdtoi() { 1773; P9BE-LABEL: spltCnstConvdtoi: 1774; P9BE: # %bb.0: # %entry 1775; P9BE-NEXT: vspltisw v2, 4 1776; P9BE-NEXT: blr 1777; 1778; P9LE-LABEL: spltCnstConvdtoi: 1779; P9LE: # %bb.0: # %entry 1780; P9LE-NEXT: vspltisw v2, 4 1781; P9LE-NEXT: blr 1782; 1783; P8BE-LABEL: spltCnstConvdtoi: 1784; P8BE: # %bb.0: # %entry 1785; P8BE-NEXT: vspltisw v2, 4 1786; P8BE-NEXT: blr 1787; 1788; P8LE-LABEL: spltCnstConvdtoi: 1789; P8LE: # %bb.0: # %entry 1790; P8LE-NEXT: vspltisw v2, 4 1791; P8LE-NEXT: blr 1792entry: 1793 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 1794} 1795 1796; Function Attrs: norecurse nounwind readnone 1797define <4 x i32> @fromRegsConvdtoi(double %a, double %b, double %c, double %d) { 1798; P9BE-LABEL: fromRegsConvdtoi: 1799; P9BE: # %bb.0: # %entry 1800; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1801; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1802; P9BE-NEXT: xxmrghd vs0, vs2, vs4 1803; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1804; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1805; P9BE-NEXT: xvcvdpsxws v2, vs0 1806; P9BE-NEXT: xxmrghd vs0, vs1, vs3 1807; P9BE-NEXT: xvcvdpsxws v3, vs0 1808; P9BE-NEXT: vmrgew v2, v3, v2 1809; P9BE-NEXT: blr 1810; 1811; P9LE-LABEL: fromRegsConvdtoi: 1812; P9LE: # %bb.0: # %entry 1813; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1814; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1815; P9LE-NEXT: xxmrghd vs0, vs3, vs1 1816; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1817; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1818; P9LE-NEXT: xvcvdpsxws v2, vs0 1819; P9LE-NEXT: xxmrghd vs0, vs4, vs2 1820; P9LE-NEXT: xvcvdpsxws v3, vs0 1821; P9LE-NEXT: vmrgew v2, v3, v2 1822; P9LE-NEXT: blr 1823; 1824; P8BE-LABEL: fromRegsConvdtoi: 1825; P8BE: # %bb.0: # %entry 1826; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1827; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1828; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1829; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1830; P8BE-NEXT: xxmrghd vs0, vs2, vs4 1831; P8BE-NEXT: xxmrghd vs1, vs1, vs3 1832; P8BE-NEXT: xvcvdpsxws v2, vs0 1833; P8BE-NEXT: xvcvdpsxws v3, vs1 1834; P8BE-NEXT: vmrgew v2, v3, v2 1835; P8BE-NEXT: blr 1836; 1837; P8LE-LABEL: fromRegsConvdtoi: 1838; P8LE: # %bb.0: # %entry 1839; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1840; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1841; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1842; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1843; P8LE-NEXT: xxmrghd vs0, vs3, vs1 1844; P8LE-NEXT: xxmrghd vs1, vs4, vs2 1845; P8LE-NEXT: xvcvdpsxws v2, vs0 1846; P8LE-NEXT: xvcvdpsxws v3, vs1 1847; P8LE-NEXT: vmrgew v2, v3, v2 1848; P8LE-NEXT: blr 1849entry: 1850 %conv = fptosi double %a to i32 1851 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1852 %conv1 = fptosi double %b to i32 1853 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 1854 %conv3 = fptosi double %c to i32 1855 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 1856 %conv5 = fptosi double %d to i32 1857 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 1858 ret <4 x i32> %vecinit6 1859} 1860 1861; Function Attrs: norecurse nounwind readnone 1862define <4 x i32> @fromDiffConstsConvdtoi() { 1863; P9BE-LABEL: fromDiffConstsConvdtoi: 1864; P9BE: # %bb.0: # %entry 1865; P9BE-NEXT: addis r3, r2, .LCPI25_0@toc@ha 1866; P9BE-NEXT: addi r3, r3, .LCPI25_0@toc@l 1867; P9BE-NEXT: lxvx v2, 0, r3 1868; P9BE-NEXT: blr 1869; 1870; P9LE-LABEL: fromDiffConstsConvdtoi: 1871; P9LE: # %bb.0: # %entry 1872; P9LE-NEXT: addis r3, r2, .LCPI25_0@toc@ha 1873; P9LE-NEXT: addi r3, r3, .LCPI25_0@toc@l 1874; P9LE-NEXT: lxvx v2, 0, r3 1875; P9LE-NEXT: blr 1876; 1877; P8BE-LABEL: fromDiffConstsConvdtoi: 1878; P8BE: # %bb.0: # %entry 1879; P8BE-NEXT: addis r3, r2, .LCPI25_0@toc@ha 1880; P8BE-NEXT: addi r3, r3, .LCPI25_0@toc@l 1881; P8BE-NEXT: lxvw4x v2, 0, r3 1882; P8BE-NEXT: blr 1883; 1884; P8LE-LABEL: fromDiffConstsConvdtoi: 1885; P8LE: # %bb.0: # %entry 1886; P8LE-NEXT: addis r3, r2, .LCPI25_0@toc@ha 1887; P8LE-NEXT: addi r3, r3, .LCPI25_0@toc@l 1888; P8LE-NEXT: lvx v2, 0, r3 1889; P8LE-NEXT: blr 1890entry: 1891 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 1892} 1893 1894; Function Attrs: norecurse nounwind readonly 1895define <4 x i32> @fromDiffMemConsAConvdtoi(double* nocapture readonly %ptr) { 1896; P9BE-LABEL: fromDiffMemConsAConvdtoi: 1897; P9BE: # %bb.0: # %entry 1898; P9BE-NEXT: lxv vs0, 0(r3) 1899; P9BE-NEXT: lxv vs1, 16(r3) 1900; P9BE-NEXT: xxmrgld vs2, vs0, vs1 1901; P9BE-NEXT: xxmrghd vs0, vs0, vs1 1902; P9BE-NEXT: xvcvdpsxws v2, vs2 1903; P9BE-NEXT: xvcvdpsxws v3, vs0 1904; P9BE-NEXT: vmrgew v2, v3, v2 1905; P9BE-NEXT: blr 1906; 1907; P9LE-LABEL: fromDiffMemConsAConvdtoi: 1908; P9LE: # %bb.0: # %entry 1909; P9LE-NEXT: lxv vs0, 0(r3) 1910; P9LE-NEXT: lxv vs1, 16(r3) 1911; P9LE-NEXT: xxmrgld vs2, vs1, vs0 1912; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1913; P9LE-NEXT: xvcvdpsxws v2, vs2 1914; P9LE-NEXT: xvcvdpsxws v3, vs0 1915; P9LE-NEXT: vmrgew v2, v3, v2 1916; P9LE-NEXT: blr 1917; 1918; P8BE-LABEL: fromDiffMemConsAConvdtoi: 1919; P8BE: # %bb.0: # %entry 1920; P8BE-NEXT: li r4, 16 1921; P8BE-NEXT: lxvd2x vs0, 0, r3 1922; P8BE-NEXT: lxvd2x vs1, r3, r4 1923; P8BE-NEXT: xxmrgld vs2, vs0, vs1 1924; P8BE-NEXT: xxmrghd vs0, vs0, vs1 1925; P8BE-NEXT: xvcvdpsxws v2, vs2 1926; P8BE-NEXT: xvcvdpsxws v3, vs0 1927; P8BE-NEXT: vmrgew v2, v3, v2 1928; P8BE-NEXT: blr 1929; 1930; P8LE-LABEL: fromDiffMemConsAConvdtoi: 1931; P8LE: # %bb.0: # %entry 1932; P8LE-NEXT: li r4, 16 1933; P8LE-NEXT: lxvd2x vs0, 0, r3 1934; P8LE-NEXT: lxvd2x vs1, r3, r4 1935; P8LE-NEXT: xxswapd vs0, vs0 1936; P8LE-NEXT: xxswapd vs1, vs1 1937; P8LE-NEXT: xxmrgld vs2, vs1, vs0 1938; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1939; P8LE-NEXT: xvcvdpsxws v2, vs2 1940; P8LE-NEXT: xvcvdpsxws v3, vs0 1941; P8LE-NEXT: vmrgew v2, v3, v2 1942; P8LE-NEXT: blr 1943entry: 1944 %0 = bitcast double* %ptr to <2 x double>* 1945 %1 = load <2 x double>, <2 x double>* %0, align 8 1946 %2 = fptosi <2 x double> %1 to <2 x i32> 1947 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 2 1948 %3 = bitcast double* %arrayidx4 to <2 x double>* 1949 %4 = load <2 x double>, <2 x double>* %3, align 8 1950 %5 = fptosi <2 x double> %4 to <2 x i32> 1951 %vecinit9 = shufflevector <2 x i32> %2, <2 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 1952 ret <4 x i32> %vecinit9 1953} 1954 1955; Function Attrs: norecurse nounwind readonly 1956define <4 x i32> @fromDiffMemConsDConvdtoi(double* nocapture readonly %ptr) { 1957; P9BE-LABEL: fromDiffMemConsDConvdtoi: 1958; P9BE: # %bb.0: # %entry 1959; P9BE-NEXT: lfd f0, 24(r3) 1960; P9BE-NEXT: lfd f1, 16(r3) 1961; P9BE-NEXT: lfd f2, 8(r3) 1962; P9BE-NEXT: xxmrghd vs0, vs0, vs2 1963; P9BE-NEXT: lfd f3, 0(r3) 1964; P9BE-NEXT: xxmrghd vs1, vs1, vs3 1965; P9BE-NEXT: xvcvdpsxws v2, vs1 1966; P9BE-NEXT: xvcvdpsxws v3, vs0 1967; P9BE-NEXT: vmrgew v2, v3, v2 1968; P9BE-NEXT: blr 1969; 1970; P9LE-LABEL: fromDiffMemConsDConvdtoi: 1971; P9LE: # %bb.0: # %entry 1972; P9LE-NEXT: lfd f0, 24(r3) 1973; P9LE-NEXT: lfd f2, 8(r3) 1974; P9LE-NEXT: xxmrghd vs0, vs2, vs0 1975; P9LE-NEXT: lfd f1, 16(r3) 1976; P9LE-NEXT: lfd f3, 0(r3) 1977; P9LE-NEXT: xvcvdpsxws v2, vs0 1978; P9LE-NEXT: xxmrghd vs0, vs3, vs1 1979; P9LE-NEXT: xvcvdpsxws v3, vs0 1980; P9LE-NEXT: vmrgew v2, v3, v2 1981; P9LE-NEXT: blr 1982; 1983; P8BE-LABEL: fromDiffMemConsDConvdtoi: 1984; P8BE: # %bb.0: # %entry 1985; P8BE-NEXT: lfdx f3, 0, r3 1986; P8BE-NEXT: lfd f0, 24(r3) 1987; P8BE-NEXT: lfd f1, 8(r3) 1988; P8BE-NEXT: lfd f2, 16(r3) 1989; P8BE-NEXT: xxmrghd vs0, vs0, vs1 1990; P8BE-NEXT: xxmrghd vs1, vs2, vs3 1991; P8BE-NEXT: xvcvdpsxws v2, vs0 1992; P8BE-NEXT: xvcvdpsxws v3, vs1 1993; P8BE-NEXT: vmrgew v2, v2, v3 1994; P8BE-NEXT: blr 1995; 1996; P8LE-LABEL: fromDiffMemConsDConvdtoi: 1997; P8LE: # %bb.0: # %entry 1998; P8LE-NEXT: lfdx f3, 0, r3 1999; P8LE-NEXT: lfd f0, 24(r3) 2000; P8LE-NEXT: lfd f1, 8(r3) 2001; P8LE-NEXT: lfd f2, 16(r3) 2002; P8LE-NEXT: xxmrghd vs0, vs1, vs0 2003; P8LE-NEXT: xxmrghd vs1, vs3, vs2 2004; P8LE-NEXT: xvcvdpsxws v2, vs0 2005; P8LE-NEXT: xvcvdpsxws v3, vs1 2006; P8LE-NEXT: vmrgew v2, v3, v2 2007; P8LE-NEXT: blr 2008entry: 2009 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 2010 %0 = load double, double* %arrayidx, align 8 2011 %conv = fptosi double %0 to i32 2012 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2013 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 2014 %1 = load double, double* %arrayidx1, align 8 2015 %conv2 = fptosi double %1 to i32 2016 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 2017 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 1 2018 %2 = load double, double* %arrayidx4, align 8 2019 %conv5 = fptosi double %2 to i32 2020 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 2021 %3 = load double, double* %ptr, align 8 2022 %conv8 = fptosi double %3 to i32 2023 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 2024 ret <4 x i32> %vecinit9 2025} 2026 2027; Function Attrs: norecurse nounwind readonly 2028define <4 x i32> @fromDiffMemVarAConvdtoi(double* nocapture readonly %arr, i32 signext %elem) { 2029; P9BE-LABEL: fromDiffMemVarAConvdtoi: 2030; P9BE: # %bb.0: # %entry 2031; P9BE-NEXT: sldi r4, r4, 3 2032; P9BE-NEXT: lfdux f0, r3, r4 2033; P9BE-NEXT: lfd f1, 8(r3) 2034; P9BE-NEXT: lfd f2, 16(r3) 2035; P9BE-NEXT: lfd f3, 24(r3) 2036; P9BE-NEXT: xxmrghd vs1, vs1, vs3 2037; P9BE-NEXT: xxmrghd vs0, vs0, vs2 2038; P9BE-NEXT: xvcvdpsxws v2, vs1 2039; P9BE-NEXT: xvcvdpsxws v3, vs0 2040; P9BE-NEXT: vmrgew v2, v3, v2 2041; P9BE-NEXT: blr 2042; 2043; P9LE-LABEL: fromDiffMemVarAConvdtoi: 2044; P9LE: # %bb.0: # %entry 2045; P9LE-NEXT: sldi r4, r4, 3 2046; P9LE-NEXT: lfdux f0, r3, r4 2047; P9LE-NEXT: lfd f2, 16(r3) 2048; P9LE-NEXT: lfd f1, 8(r3) 2049; P9LE-NEXT: lfd f3, 24(r3) 2050; P9LE-NEXT: xxmrghd vs0, vs2, vs0 2051; P9LE-NEXT: xvcvdpsxws v2, vs0 2052; P9LE-NEXT: xxmrghd vs0, vs3, vs1 2053; P9LE-NEXT: xvcvdpsxws v3, vs0 2054; P9LE-NEXT: vmrgew v2, v3, v2 2055; P9LE-NEXT: blr 2056; 2057; P8BE-LABEL: fromDiffMemVarAConvdtoi: 2058; P8BE: # %bb.0: # %entry 2059; P8BE-NEXT: sldi r4, r4, 3 2060; P8BE-NEXT: lfdux f0, r3, r4 2061; P8BE-NEXT: lfd f1, 8(r3) 2062; P8BE-NEXT: lfd f2, 24(r3) 2063; P8BE-NEXT: lfd f3, 16(r3) 2064; P8BE-NEXT: xxmrghd vs1, vs1, vs2 2065; P8BE-NEXT: xxmrghd vs0, vs0, vs3 2066; P8BE-NEXT: xvcvdpsxws v2, vs1 2067; P8BE-NEXT: xvcvdpsxws v3, vs0 2068; P8BE-NEXT: vmrgew v2, v3, v2 2069; P8BE-NEXT: blr 2070; 2071; P8LE-LABEL: fromDiffMemVarAConvdtoi: 2072; P8LE: # %bb.0: # %entry 2073; P8LE-NEXT: sldi r4, r4, 3 2074; P8LE-NEXT: lfdux f0, r3, r4 2075; P8LE-NEXT: lfd f1, 16(r3) 2076; P8LE-NEXT: lfd f2, 8(r3) 2077; P8LE-NEXT: lfd f3, 24(r3) 2078; P8LE-NEXT: xxmrghd vs0, vs1, vs0 2079; P8LE-NEXT: xxmrghd vs1, vs3, vs2 2080; P8LE-NEXT: xvcvdpsxws v2, vs0 2081; P8LE-NEXT: xvcvdpsxws v3, vs1 2082; P8LE-NEXT: vmrgew v2, v3, v2 2083; P8LE-NEXT: blr 2084entry: 2085 %idxprom = sext i32 %elem to i64 2086 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 2087 %0 = load double, double* %arrayidx, align 8 2088 %conv = fptosi double %0 to i32 2089 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2090 %add = add nsw i32 %elem, 1 2091 %idxprom1 = sext i32 %add to i64 2092 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 2093 %1 = load double, double* %arrayidx2, align 8 2094 %conv3 = fptosi double %1 to i32 2095 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2096 %add5 = add nsw i32 %elem, 2 2097 %idxprom6 = sext i32 %add5 to i64 2098 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 2099 %2 = load double, double* %arrayidx7, align 8 2100 %conv8 = fptosi double %2 to i32 2101 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2102 %add10 = add nsw i32 %elem, 3 2103 %idxprom11 = sext i32 %add10 to i64 2104 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 2105 %3 = load double, double* %arrayidx12, align 8 2106 %conv13 = fptosi double %3 to i32 2107 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2108 ret <4 x i32> %vecinit14 2109} 2110 2111; Function Attrs: norecurse nounwind readonly 2112define <4 x i32> @fromDiffMemVarDConvdtoi(double* nocapture readonly %arr, i32 signext %elem) { 2113; P9BE-LABEL: fromDiffMemVarDConvdtoi: 2114; P9BE: # %bb.0: # %entry 2115; P9BE-NEXT: sldi r4, r4, 3 2116; P9BE-NEXT: lfdux f0, r3, r4 2117; P9BE-NEXT: lfd f1, -8(r3) 2118; P9BE-NEXT: lfd f2, -16(r3) 2119; P9BE-NEXT: lfd f3, -24(r3) 2120; P9BE-NEXT: xxmrghd vs1, vs1, vs3 2121; P9BE-NEXT: xxmrghd vs0, vs0, vs2 2122; P9BE-NEXT: xvcvdpsxws v2, vs1 2123; P9BE-NEXT: xvcvdpsxws v3, vs0 2124; P9BE-NEXT: vmrgew v2, v3, v2 2125; P9BE-NEXT: blr 2126; 2127; P9LE-LABEL: fromDiffMemVarDConvdtoi: 2128; P9LE: # %bb.0: # %entry 2129; P9LE-NEXT: sldi r4, r4, 3 2130; P9LE-NEXT: lfdux f0, r3, r4 2131; P9LE-NEXT: lfd f2, -16(r3) 2132; P9LE-NEXT: lfd f1, -8(r3) 2133; P9LE-NEXT: lfd f3, -24(r3) 2134; P9LE-NEXT: xxmrghd vs0, vs2, vs0 2135; P9LE-NEXT: xvcvdpsxws v2, vs0 2136; P9LE-NEXT: xxmrghd vs0, vs3, vs1 2137; P9LE-NEXT: xvcvdpsxws v3, vs0 2138; P9LE-NEXT: vmrgew v2, v3, v2 2139; P9LE-NEXT: blr 2140; 2141; P8BE-LABEL: fromDiffMemVarDConvdtoi: 2142; P8BE: # %bb.0: # %entry 2143; P8BE-NEXT: sldi r4, r4, 3 2144; P8BE-NEXT: lfdux f0, r3, r4 2145; P8BE-NEXT: lfd f1, -8(r3) 2146; P8BE-NEXT: lfd f2, -24(r3) 2147; P8BE-NEXT: lfd f3, -16(r3) 2148; P8BE-NEXT: xxmrghd vs1, vs1, vs2 2149; P8BE-NEXT: xxmrghd vs0, vs0, vs3 2150; P8BE-NEXT: xvcvdpsxws v2, vs1 2151; P8BE-NEXT: xvcvdpsxws v3, vs0 2152; P8BE-NEXT: vmrgew v2, v3, v2 2153; P8BE-NEXT: blr 2154; 2155; P8LE-LABEL: fromDiffMemVarDConvdtoi: 2156; P8LE: # %bb.0: # %entry 2157; P8LE-NEXT: sldi r4, r4, 3 2158; P8LE-NEXT: lfdux f0, r3, r4 2159; P8LE-NEXT: lfd f1, -16(r3) 2160; P8LE-NEXT: lfd f2, -8(r3) 2161; P8LE-NEXT: lfd f3, -24(r3) 2162; P8LE-NEXT: xxmrghd vs0, vs1, vs0 2163; P8LE-NEXT: xxmrghd vs1, vs3, vs2 2164; P8LE-NEXT: xvcvdpsxws v2, vs0 2165; P8LE-NEXT: xvcvdpsxws v3, vs1 2166; P8LE-NEXT: vmrgew v2, v3, v2 2167; P8LE-NEXT: blr 2168entry: 2169 %idxprom = sext i32 %elem to i64 2170 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 2171 %0 = load double, double* %arrayidx, align 8 2172 %conv = fptosi double %0 to i32 2173 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2174 %sub = add nsw i32 %elem, -1 2175 %idxprom1 = sext i32 %sub to i64 2176 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 2177 %1 = load double, double* %arrayidx2, align 8 2178 %conv3 = fptosi double %1 to i32 2179 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2180 %sub5 = add nsw i32 %elem, -2 2181 %idxprom6 = sext i32 %sub5 to i64 2182 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 2183 %2 = load double, double* %arrayidx7, align 8 2184 %conv8 = fptosi double %2 to i32 2185 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2186 %sub10 = add nsw i32 %elem, -3 2187 %idxprom11 = sext i32 %sub10 to i64 2188 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 2189 %3 = load double, double* %arrayidx12, align 8 2190 %conv13 = fptosi double %3 to i32 2191 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2192 ret <4 x i32> %vecinit14 2193} 2194 2195; Function Attrs: norecurse nounwind readnone 2196define <4 x i32> @spltRegValConvdtoi(double %val) { 2197; P9BE-LABEL: spltRegValConvdtoi: 2198; P9BE: # %bb.0: # %entry 2199; P9BE-NEXT: xscvdpsxws f0, f1 2200; P9BE-NEXT: xxspltw v2, vs0, 1 2201; P9BE-NEXT: blr 2202; 2203; P9LE-LABEL: spltRegValConvdtoi: 2204; P9LE: # %bb.0: # %entry 2205; P9LE-NEXT: xscvdpsxws f0, f1 2206; P9LE-NEXT: xxspltw v2, vs0, 1 2207; P9LE-NEXT: blr 2208; 2209; P8BE-LABEL: spltRegValConvdtoi: 2210; P8BE: # %bb.0: # %entry 2211; P8BE-NEXT: xscvdpsxws f0, f1 2212; P8BE-NEXT: xxspltw v2, vs0, 1 2213; P8BE-NEXT: blr 2214; 2215; P8LE-LABEL: spltRegValConvdtoi: 2216; P8LE: # %bb.0: # %entry 2217; P8LE-NEXT: xscvdpsxws f0, f1 2218; P8LE-NEXT: xxspltw v2, vs0, 1 2219; P8LE-NEXT: blr 2220entry: 2221 %conv = fptosi double %val to i32 2222 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2223 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2224 ret <4 x i32> %splat.splat 2225} 2226 2227; Function Attrs: norecurse nounwind readonly 2228define <4 x i32> @spltMemValConvdtoi(double* nocapture readonly %ptr) { 2229; P9BE-LABEL: spltMemValConvdtoi: 2230; P9BE: # %bb.0: # %entry 2231; P9BE-NEXT: lfd f0, 0(r3) 2232; P9BE-NEXT: xscvdpsxws f0, f0 2233; P9BE-NEXT: xxspltw v2, vs0, 1 2234; P9BE-NEXT: blr 2235; 2236; P9LE-LABEL: spltMemValConvdtoi: 2237; P9LE: # %bb.0: # %entry 2238; P9LE-NEXT: lfd f0, 0(r3) 2239; P9LE-NEXT: xscvdpsxws f0, f0 2240; P9LE-NEXT: xxspltw v2, vs0, 1 2241; P9LE-NEXT: blr 2242; 2243; P8BE-LABEL: spltMemValConvdtoi: 2244; P8BE: # %bb.0: # %entry 2245; P8BE-NEXT: lfdx f0, 0, r3 2246; P8BE-NEXT: xscvdpsxws f0, f0 2247; P8BE-NEXT: xxspltw v2, vs0, 1 2248; P8BE-NEXT: blr 2249; 2250; P8LE-LABEL: spltMemValConvdtoi: 2251; P8LE: # %bb.0: # %entry 2252; P8LE-NEXT: lfdx f0, 0, r3 2253; P8LE-NEXT: xscvdpsxws f0, f0 2254; P8LE-NEXT: xxspltw v2, vs0, 1 2255; P8LE-NEXT: blr 2256entry: 2257 %0 = load double, double* %ptr, align 8 2258 %conv = fptosi double %0 to i32 2259 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2260 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2261 ret <4 x i32> %splat.splat 2262} 2263; Function Attrs: norecurse nounwind readnone 2264define <4 x i32> @allZeroui() { 2265; P9BE-LABEL: allZeroui: 2266; P9BE: # %bb.0: # %entry 2267; P9BE-NEXT: xxlxor v2, v2, v2 2268; P9BE-NEXT: blr 2269; 2270; P9LE-LABEL: allZeroui: 2271; P9LE: # %bb.0: # %entry 2272; P9LE-NEXT: xxlxor v2, v2, v2 2273; P9LE-NEXT: blr 2274; 2275; P8BE-LABEL: allZeroui: 2276; P8BE: # %bb.0: # %entry 2277; P8BE-NEXT: xxlxor v2, v2, v2 2278; P8BE-NEXT: blr 2279; 2280; P8LE-LABEL: allZeroui: 2281; P8LE: # %bb.0: # %entry 2282; P8LE-NEXT: xxlxor v2, v2, v2 2283; P8LE-NEXT: blr 2284entry: 2285 ret <4 x i32> zeroinitializer 2286} 2287 2288; Function Attrs: norecurse nounwind readnone 2289define <4 x i32> @spltConst1ui() { 2290; P9BE-LABEL: spltConst1ui: 2291; P9BE: # %bb.0: # %entry 2292; P9BE-NEXT: vspltisw v2, 1 2293; P9BE-NEXT: blr 2294; 2295; P9LE-LABEL: spltConst1ui: 2296; P9LE: # %bb.0: # %entry 2297; P9LE-NEXT: vspltisw v2, 1 2298; P9LE-NEXT: blr 2299; 2300; P8BE-LABEL: spltConst1ui: 2301; P8BE: # %bb.0: # %entry 2302; P8BE-NEXT: vspltisw v2, 1 2303; P8BE-NEXT: blr 2304; 2305; P8LE-LABEL: spltConst1ui: 2306; P8LE: # %bb.0: # %entry 2307; P8LE-NEXT: vspltisw v2, 1 2308; P8LE-NEXT: blr 2309entry: 2310 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1> 2311} 2312 2313; Function Attrs: norecurse nounwind readnone 2314define <4 x i32> @spltConst16kui() { 2315; P9BE-LABEL: spltConst16kui: 2316; P9BE: # %bb.0: # %entry 2317; P9BE-NEXT: vspltisw v2, -15 2318; P9BE-NEXT: vsrw v2, v2, v2 2319; P9BE-NEXT: blr 2320; 2321; P9LE-LABEL: spltConst16kui: 2322; P9LE: # %bb.0: # %entry 2323; P9LE-NEXT: vspltisw v2, -15 2324; P9LE-NEXT: vsrw v2, v2, v2 2325; P9LE-NEXT: blr 2326; 2327; P8BE-LABEL: spltConst16kui: 2328; P8BE: # %bb.0: # %entry 2329; P8BE-NEXT: vspltisw v2, -15 2330; P8BE-NEXT: vsrw v2, v2, v2 2331; P8BE-NEXT: blr 2332; 2333; P8LE-LABEL: spltConst16kui: 2334; P8LE: # %bb.0: # %entry 2335; P8LE-NEXT: vspltisw v2, -15 2336; P8LE-NEXT: vsrw v2, v2, v2 2337; P8LE-NEXT: blr 2338entry: 2339 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 2340} 2341 2342; Function Attrs: norecurse nounwind readnone 2343define <4 x i32> @spltConst32kui() { 2344; P9BE-LABEL: spltConst32kui: 2345; P9BE: # %bb.0: # %entry 2346; P9BE-NEXT: vspltisw v2, -16 2347; P9BE-NEXT: vsrw v2, v2, v2 2348; P9BE-NEXT: blr 2349; 2350; P9LE-LABEL: spltConst32kui: 2351; P9LE: # %bb.0: # %entry 2352; P9LE-NEXT: vspltisw v2, -16 2353; P9LE-NEXT: vsrw v2, v2, v2 2354; P9LE-NEXT: blr 2355; 2356; P8BE-LABEL: spltConst32kui: 2357; P8BE: # %bb.0: # %entry 2358; P8BE-NEXT: vspltisw v2, -16 2359; P8BE-NEXT: vsrw v2, v2, v2 2360; P8BE-NEXT: blr 2361; 2362; P8LE-LABEL: spltConst32kui: 2363; P8LE: # %bb.0: # %entry 2364; P8LE-NEXT: vspltisw v2, -16 2365; P8LE-NEXT: vsrw v2, v2, v2 2366; P8LE-NEXT: blr 2367entry: 2368 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 2369} 2370 2371; Function Attrs: norecurse nounwind readnone 2372define <4 x i32> @fromRegsui(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c, i32 zeroext %d) { 2373; P9BE-LABEL: fromRegsui: 2374; P9BE: # %bb.0: # %entry 2375; P9BE-NEXT: rldimi r6, r5, 32, 0 2376; P9BE-NEXT: rldimi r4, r3, 32, 0 2377; P9BE-NEXT: mtvsrdd v2, r4, r6 2378; P9BE-NEXT: blr 2379; 2380; P9LE-LABEL: fromRegsui: 2381; P9LE: # %bb.0: # %entry 2382; P9LE-NEXT: rldimi r3, r4, 32, 0 2383; P9LE-NEXT: rldimi r5, r6, 32, 0 2384; P9LE-NEXT: mtvsrdd v2, r5, r3 2385; P9LE-NEXT: blr 2386; 2387; P8BE-LABEL: fromRegsui: 2388; P8BE: # %bb.0: # %entry 2389; P8BE-NEXT: rldimi r6, r5, 32, 0 2390; P8BE-NEXT: rldimi r4, r3, 32, 0 2391; P8BE-NEXT: mtvsrd f0, r6 2392; P8BE-NEXT: mtvsrd f1, r4 2393; P8BE-NEXT: xxmrghd v2, vs1, vs0 2394; P8BE-NEXT: blr 2395; 2396; P8LE-LABEL: fromRegsui: 2397; P8LE: # %bb.0: # %entry 2398; P8LE-NEXT: rldimi r3, r4, 32, 0 2399; P8LE-NEXT: rldimi r5, r6, 32, 0 2400; P8LE-NEXT: mtvsrd f0, r3 2401; P8LE-NEXT: mtvsrd f1, r5 2402; P8LE-NEXT: xxmrghd v2, vs1, vs0 2403; P8LE-NEXT: blr 2404entry: 2405 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 2406 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 2407 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 2408 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3 2409 ret <4 x i32> %vecinit3 2410} 2411 2412; Function Attrs: norecurse nounwind readnone 2413define <4 x i32> @fromDiffConstsui() { 2414; P9BE-LABEL: fromDiffConstsui: 2415; P9BE: # %bb.0: # %entry 2416; P9BE-NEXT: addis r3, r2, .LCPI37_0@toc@ha 2417; P9BE-NEXT: addi r3, r3, .LCPI37_0@toc@l 2418; P9BE-NEXT: lxvx v2, 0, r3 2419; P9BE-NEXT: blr 2420; 2421; P9LE-LABEL: fromDiffConstsui: 2422; P9LE: # %bb.0: # %entry 2423; P9LE-NEXT: addis r3, r2, .LCPI37_0@toc@ha 2424; P9LE-NEXT: addi r3, r3, .LCPI37_0@toc@l 2425; P9LE-NEXT: lxvx v2, 0, r3 2426; P9LE-NEXT: blr 2427; 2428; P8BE-LABEL: fromDiffConstsui: 2429; P8BE: # %bb.0: # %entry 2430; P8BE-NEXT: addis r3, r2, .LCPI37_0@toc@ha 2431; P8BE-NEXT: addi r3, r3, .LCPI37_0@toc@l 2432; P8BE-NEXT: lxvw4x v2, 0, r3 2433; P8BE-NEXT: blr 2434; 2435; P8LE-LABEL: fromDiffConstsui: 2436; P8LE: # %bb.0: # %entry 2437; P8LE-NEXT: addis r3, r2, .LCPI37_0@toc@ha 2438; P8LE-NEXT: addi r3, r3, .LCPI37_0@toc@l 2439; P8LE-NEXT: lvx v2, 0, r3 2440; P8LE-NEXT: blr 2441entry: 2442 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19> 2443} 2444 2445; Function Attrs: norecurse nounwind readonly 2446define <4 x i32> @fromDiffMemConsAui(i32* nocapture readonly %arr) { 2447; P9BE-LABEL: fromDiffMemConsAui: 2448; P9BE: # %bb.0: # %entry 2449; P9BE-NEXT: lxv v2, 0(r3) 2450; P9BE-NEXT: blr 2451; 2452; P9LE-LABEL: fromDiffMemConsAui: 2453; P9LE: # %bb.0: # %entry 2454; P9LE-NEXT: lxv v2, 0(r3) 2455; P9LE-NEXT: blr 2456; 2457; P8BE-LABEL: fromDiffMemConsAui: 2458; P8BE: # %bb.0: # %entry 2459; P8BE-NEXT: lxvw4x v2, 0, r3 2460; P8BE-NEXT: blr 2461; 2462; P8LE-LABEL: fromDiffMemConsAui: 2463; P8LE: # %bb.0: # %entry 2464; P8LE-NEXT: lxvd2x vs0, 0, r3 2465; P8LE-NEXT: xxswapd v2, vs0 2466; P8LE-NEXT: blr 2467entry: 2468 %0 = load i32, i32* %arr, align 4 2469 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2470 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 1 2471 %1 = load i32, i32* %arrayidx1, align 4 2472 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2473 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 2474 %2 = load i32, i32* %arrayidx3, align 4 2475 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2476 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 3 2477 %3 = load i32, i32* %arrayidx5, align 4 2478 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2479 ret <4 x i32> %vecinit6 2480} 2481 2482; Function Attrs: norecurse nounwind readonly 2483define <4 x i32> @fromDiffMemConsDui(i32* nocapture readonly %arr) { 2484; P9BE-LABEL: fromDiffMemConsDui: 2485; P9BE: # %bb.0: # %entry 2486; P9BE-NEXT: lxv v2, 0(r3) 2487; P9BE-NEXT: addis r3, r2, .LCPI39_0@toc@ha 2488; P9BE-NEXT: addi r3, r3, .LCPI39_0@toc@l 2489; P9BE-NEXT: lxvx v3, 0, r3 2490; P9BE-NEXT: vperm v2, v2, v2, v3 2491; P9BE-NEXT: blr 2492; 2493; P9LE-LABEL: fromDiffMemConsDui: 2494; P9LE: # %bb.0: # %entry 2495; P9LE-NEXT: lxvw4x v2, 0, r3 2496; P9LE-NEXT: blr 2497; 2498; P8BE-LABEL: fromDiffMemConsDui: 2499; P8BE: # %bb.0: # %entry 2500; P8BE-NEXT: addis r4, r2, .LCPI39_0@toc@ha 2501; P8BE-NEXT: lxvw4x v2, 0, r3 2502; P8BE-NEXT: addi r4, r4, .LCPI39_0@toc@l 2503; P8BE-NEXT: lxvw4x v3, 0, r4 2504; P8BE-NEXT: vperm v2, v2, v2, v3 2505; P8BE-NEXT: blr 2506; 2507; P8LE-LABEL: fromDiffMemConsDui: 2508; P8LE: # %bb.0: # %entry 2509; P8LE-NEXT: lxvd2x vs0, 0, r3 2510; P8LE-NEXT: addis r4, r2, .LCPI39_0@toc@ha 2511; P8LE-NEXT: addi r3, r4, .LCPI39_0@toc@l 2512; P8LE-NEXT: lvx v2, 0, r3 2513; P8LE-NEXT: xxswapd v3, vs0 2514; P8LE-NEXT: vperm v2, v3, v3, v2 2515; P8LE-NEXT: blr 2516entry: 2517 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3 2518 %0 = load i32, i32* %arrayidx, align 4 2519 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2520 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 2521 %1 = load i32, i32* %arrayidx1, align 4 2522 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2523 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 1 2524 %2 = load i32, i32* %arrayidx3, align 4 2525 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2526 %3 = load i32, i32* %arr, align 4 2527 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2528 ret <4 x i32> %vecinit6 2529} 2530 2531; Function Attrs: norecurse nounwind readonly 2532define <4 x i32> @fromDiffMemVarAui(i32* nocapture readonly %arr, i32 signext %elem) { 2533; P9BE-LABEL: fromDiffMemVarAui: 2534; P9BE: # %bb.0: # %entry 2535; P9BE-NEXT: sldi r4, r4, 2 2536; P9BE-NEXT: lxvx v2, r3, r4 2537; P9BE-NEXT: blr 2538; 2539; P9LE-LABEL: fromDiffMemVarAui: 2540; P9LE: # %bb.0: # %entry 2541; P9LE-NEXT: sldi r4, r4, 2 2542; P9LE-NEXT: lxvx v2, r3, r4 2543; P9LE-NEXT: blr 2544; 2545; P8BE-LABEL: fromDiffMemVarAui: 2546; P8BE: # %bb.0: # %entry 2547; P8BE-NEXT: sldi r4, r4, 2 2548; P8BE-NEXT: lxvw4x v2, r3, r4 2549; P8BE-NEXT: blr 2550; 2551; P8LE-LABEL: fromDiffMemVarAui: 2552; P8LE: # %bb.0: # %entry 2553; P8LE-NEXT: sldi r4, r4, 2 2554; P8LE-NEXT: lxvd2x vs0, r3, r4 2555; P8LE-NEXT: xxswapd v2, vs0 2556; P8LE-NEXT: blr 2557entry: 2558 %idxprom = sext i32 %elem to i64 2559 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2560 %0 = load i32, i32* %arrayidx, align 4 2561 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2562 %add = add nsw i32 %elem, 1 2563 %idxprom1 = sext i32 %add to i64 2564 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 2565 %1 = load i32, i32* %arrayidx2, align 4 2566 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2567 %add4 = add nsw i32 %elem, 2 2568 %idxprom5 = sext i32 %add4 to i64 2569 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 2570 %2 = load i32, i32* %arrayidx6, align 4 2571 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 2572 %add8 = add nsw i32 %elem, 3 2573 %idxprom9 = sext i32 %add8 to i64 2574 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 2575 %3 = load i32, i32* %arrayidx10, align 4 2576 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 2577 ret <4 x i32> %vecinit11 2578} 2579 2580; Function Attrs: norecurse nounwind readonly 2581define <4 x i32> @fromDiffMemVarDui(i32* nocapture readonly %arr, i32 signext %elem) { 2582; P9BE-LABEL: fromDiffMemVarDui: 2583; P9BE: # %bb.0: # %entry 2584; P9BE-NEXT: sldi r4, r4, 2 2585; P9BE-NEXT: add r3, r3, r4 2586; P9BE-NEXT: addi r3, r3, -12 2587; P9BE-NEXT: lxvx v2, 0, r3 2588; P9BE-NEXT: addis r3, r2, .LCPI41_0@toc@ha 2589; P9BE-NEXT: addi r3, r3, .LCPI41_0@toc@l 2590; P9BE-NEXT: lxvx v3, 0, r3 2591; P9BE-NEXT: vperm v2, v2, v2, v3 2592; P9BE-NEXT: blr 2593; 2594; P9LE-LABEL: fromDiffMemVarDui: 2595; P9LE: # %bb.0: # %entry 2596; P9LE-NEXT: sldi r4, r4, 2 2597; P9LE-NEXT: add r3, r3, r4 2598; P9LE-NEXT: addi r3, r3, -12 2599; P9LE-NEXT: lxvx v2, 0, r3 2600; P9LE-NEXT: addis r3, r2, .LCPI41_0@toc@ha 2601; P9LE-NEXT: addi r3, r3, .LCPI41_0@toc@l 2602; P9LE-NEXT: lxvx v3, 0, r3 2603; P9LE-NEXT: vperm v2, v2, v2, v3 2604; P9LE-NEXT: blr 2605; 2606; P8BE-LABEL: fromDiffMemVarDui: 2607; P8BE: # %bb.0: # %entry 2608; P8BE-NEXT: sldi r4, r4, 2 2609; P8BE-NEXT: addis r5, r2, .LCPI41_0@toc@ha 2610; P8BE-NEXT: add r3, r3, r4 2611; P8BE-NEXT: addi r4, r5, .LCPI41_0@toc@l 2612; P8BE-NEXT: addi r3, r3, -12 2613; P8BE-NEXT: lxvw4x v3, 0, r4 2614; P8BE-NEXT: lxvw4x v2, 0, r3 2615; P8BE-NEXT: vperm v2, v2, v2, v3 2616; P8BE-NEXT: blr 2617; 2618; P8LE-LABEL: fromDiffMemVarDui: 2619; P8LE: # %bb.0: # %entry 2620; P8LE-NEXT: sldi r4, r4, 2 2621; P8LE-NEXT: addis r5, r2, .LCPI41_0@toc@ha 2622; P8LE-NEXT: add r3, r3, r4 2623; P8LE-NEXT: addi r3, r3, -12 2624; P8LE-NEXT: lxvd2x vs0, 0, r3 2625; P8LE-NEXT: addi r3, r5, .LCPI41_0@toc@l 2626; P8LE-NEXT: lvx v3, 0, r3 2627; P8LE-NEXT: xxswapd v2, vs0 2628; P8LE-NEXT: vperm v2, v2, v2, v3 2629; P8LE-NEXT: blr 2630entry: 2631 %idxprom = sext i32 %elem to i64 2632 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2633 %0 = load i32, i32* %arrayidx, align 4 2634 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2635 %sub = add nsw i32 %elem, -1 2636 %idxprom1 = sext i32 %sub to i64 2637 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 2638 %1 = load i32, i32* %arrayidx2, align 4 2639 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2640 %sub4 = add nsw i32 %elem, -2 2641 %idxprom5 = sext i32 %sub4 to i64 2642 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 2643 %2 = load i32, i32* %arrayidx6, align 4 2644 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 2645 %sub8 = add nsw i32 %elem, -3 2646 %idxprom9 = sext i32 %sub8 to i64 2647 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 2648 %3 = load i32, i32* %arrayidx10, align 4 2649 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 2650 ret <4 x i32> %vecinit11 2651} 2652 2653; Function Attrs: norecurse nounwind readonly 2654define <4 x i32> @fromRandMemConsui(i32* nocapture readonly %arr) { 2655; P9BE-LABEL: fromRandMemConsui: 2656; P9BE: # %bb.0: # %entry 2657; P9BE-NEXT: lwz r4, 16(r3) 2658; P9BE-NEXT: lwz r5, 72(r3) 2659; P9BE-NEXT: lwz r6, 8(r3) 2660; P9BE-NEXT: lwz r3, 352(r3) 2661; P9BE-NEXT: rldimi r3, r6, 32, 0 2662; P9BE-NEXT: rldimi r5, r4, 32, 0 2663; P9BE-NEXT: mtvsrdd v2, r5, r3 2664; P9BE-NEXT: blr 2665; 2666; P9LE-LABEL: fromRandMemConsui: 2667; P9LE: # %bb.0: # %entry 2668; P9LE-NEXT: lwz r4, 16(r3) 2669; P9LE-NEXT: lwz r5, 72(r3) 2670; P9LE-NEXT: lwz r6, 8(r3) 2671; P9LE-NEXT: lwz r3, 352(r3) 2672; P9LE-NEXT: rldimi r4, r5, 32, 0 2673; P9LE-NEXT: rldimi r6, r3, 32, 0 2674; P9LE-NEXT: mtvsrdd v2, r6, r4 2675; P9LE-NEXT: blr 2676; 2677; P8BE-LABEL: fromRandMemConsui: 2678; P8BE: # %bb.0: # %entry 2679; P8BE-NEXT: lwz r4, 8(r3) 2680; P8BE-NEXT: lwz r5, 352(r3) 2681; P8BE-NEXT: lwz r6, 16(r3) 2682; P8BE-NEXT: lwz r3, 72(r3) 2683; P8BE-NEXT: rldimi r5, r4, 32, 0 2684; P8BE-NEXT: rldimi r3, r6, 32, 0 2685; P8BE-NEXT: mtvsrd f0, r5 2686; P8BE-NEXT: mtvsrd f1, r3 2687; P8BE-NEXT: xxmrghd v2, vs1, vs0 2688; P8BE-NEXT: blr 2689; 2690; P8LE-LABEL: fromRandMemConsui: 2691; P8LE: # %bb.0: # %entry 2692; P8LE-NEXT: lwz r4, 16(r3) 2693; P8LE-NEXT: lwz r5, 72(r3) 2694; P8LE-NEXT: lwz r6, 8(r3) 2695; P8LE-NEXT: lwz r3, 352(r3) 2696; P8LE-NEXT: rldimi r4, r5, 32, 0 2697; P8LE-NEXT: rldimi r6, r3, 32, 0 2698; P8LE-NEXT: mtvsrd f0, r4 2699; P8LE-NEXT: mtvsrd f1, r6 2700; P8LE-NEXT: xxmrghd v2, vs1, vs0 2701; P8LE-NEXT: blr 2702entry: 2703 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4 2704 %0 = load i32, i32* %arrayidx, align 4 2705 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2706 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18 2707 %1 = load i32, i32* %arrayidx1, align 4 2708 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2709 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 2710 %2 = load i32, i32* %arrayidx3, align 4 2711 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2712 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 88 2713 %3 = load i32, i32* %arrayidx5, align 4 2714 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2715 ret <4 x i32> %vecinit6 2716} 2717 2718; Function Attrs: norecurse nounwind readonly 2719define <4 x i32> @fromRandMemVarui(i32* nocapture readonly %arr, i32 signext %elem) { 2720; P9BE-LABEL: fromRandMemVarui: 2721; P9BE: # %bb.0: # %entry 2722; P9BE-NEXT: sldi r4, r4, 2 2723; P9BE-NEXT: add r3, r3, r4 2724; P9BE-NEXT: lwz r4, 16(r3) 2725; P9BE-NEXT: lwz r5, 4(r3) 2726; P9BE-NEXT: lwz r6, 8(r3) 2727; P9BE-NEXT: lwz r3, 32(r3) 2728; P9BE-NEXT: rldimi r3, r6, 32, 0 2729; P9BE-NEXT: rldimi r5, r4, 32, 0 2730; P9BE-NEXT: mtvsrdd v2, r5, r3 2731; P9BE-NEXT: blr 2732; 2733; P9LE-LABEL: fromRandMemVarui: 2734; P9LE: # %bb.0: # %entry 2735; P9LE-NEXT: sldi r4, r4, 2 2736; P9LE-NEXT: add r3, r3, r4 2737; P9LE-NEXT: lwz r4, 16(r3) 2738; P9LE-NEXT: lwz r5, 4(r3) 2739; P9LE-NEXT: lwz r6, 8(r3) 2740; P9LE-NEXT: lwz r3, 32(r3) 2741; P9LE-NEXT: rldimi r4, r5, 32, 0 2742; P9LE-NEXT: rldimi r6, r3, 32, 0 2743; P9LE-NEXT: mtvsrdd v2, r6, r4 2744; P9LE-NEXT: blr 2745; 2746; P8BE-LABEL: fromRandMemVarui: 2747; P8BE: # %bb.0: # %entry 2748; P8BE-NEXT: sldi r4, r4, 2 2749; P8BE-NEXT: add r3, r3, r4 2750; P8BE-NEXT: lwz r4, 8(r3) 2751; P8BE-NEXT: lwz r5, 32(r3) 2752; P8BE-NEXT: lwz r6, 16(r3) 2753; P8BE-NEXT: lwz r3, 4(r3) 2754; P8BE-NEXT: rldimi r5, r4, 32, 0 2755; P8BE-NEXT: rldimi r3, r6, 32, 0 2756; P8BE-NEXT: mtvsrd f0, r5 2757; P8BE-NEXT: mtvsrd f1, r3 2758; P8BE-NEXT: xxmrghd v2, vs1, vs0 2759; P8BE-NEXT: blr 2760; 2761; P8LE-LABEL: fromRandMemVarui: 2762; P8LE: # %bb.0: # %entry 2763; P8LE-NEXT: sldi r4, r4, 2 2764; P8LE-NEXT: add r3, r3, r4 2765; P8LE-NEXT: lwz r4, 16(r3) 2766; P8LE-NEXT: lwz r5, 4(r3) 2767; P8LE-NEXT: lwz r6, 8(r3) 2768; P8LE-NEXT: lwz r3, 32(r3) 2769; P8LE-NEXT: rldimi r4, r5, 32, 0 2770; P8LE-NEXT: rldimi r6, r3, 32, 0 2771; P8LE-NEXT: mtvsrd f0, r4 2772; P8LE-NEXT: mtvsrd f1, r6 2773; P8LE-NEXT: xxmrghd v2, vs1, vs0 2774; P8LE-NEXT: blr 2775entry: 2776 %add = add nsw i32 %elem, 4 2777 %idxprom = sext i32 %add to i64 2778 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2779 %0 = load i32, i32* %arrayidx, align 4 2780 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2781 %add1 = add nsw i32 %elem, 1 2782 %idxprom2 = sext i32 %add1 to i64 2783 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 %idxprom2 2784 %1 = load i32, i32* %arrayidx3, align 4 2785 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2786 %add5 = add nsw i32 %elem, 2 2787 %idxprom6 = sext i32 %add5 to i64 2788 %arrayidx7 = getelementptr inbounds i32, i32* %arr, i64 %idxprom6 2789 %2 = load i32, i32* %arrayidx7, align 4 2790 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2 2791 %add9 = add nsw i32 %elem, 8 2792 %idxprom10 = sext i32 %add9 to i64 2793 %arrayidx11 = getelementptr inbounds i32, i32* %arr, i64 %idxprom10 2794 %3 = load i32, i32* %arrayidx11, align 4 2795 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3 2796 ret <4 x i32> %vecinit12 2797} 2798 2799; Function Attrs: norecurse nounwind readnone 2800define <4 x i32> @spltRegValui(i32 zeroext %val) { 2801; P9BE-LABEL: spltRegValui: 2802; P9BE: # %bb.0: # %entry 2803; P9BE-NEXT: mtvsrws v2, r3 2804; P9BE-NEXT: blr 2805; 2806; P9LE-LABEL: spltRegValui: 2807; P9LE: # %bb.0: # %entry 2808; P9LE-NEXT: mtvsrws v2, r3 2809; P9LE-NEXT: blr 2810; 2811; P8BE-LABEL: spltRegValui: 2812; P8BE: # %bb.0: # %entry 2813; P8BE-NEXT: mtvsrwz f0, r3 2814; P8BE-NEXT: xxspltw v2, vs0, 1 2815; P8BE-NEXT: blr 2816; 2817; P8LE-LABEL: spltRegValui: 2818; P8LE: # %bb.0: # %entry 2819; P8LE-NEXT: mtvsrwz f0, r3 2820; P8LE-NEXT: xxspltw v2, vs0, 1 2821; P8LE-NEXT: blr 2822entry: 2823 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0 2824 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2825 ret <4 x i32> %splat.splat 2826} 2827 2828; Function Attrs: norecurse nounwind readonly 2829define <4 x i32> @spltMemValui(i32* nocapture readonly %ptr) { 2830; P9BE-LABEL: spltMemValui: 2831; P9BE: # %bb.0: # %entry 2832; P9BE-NEXT: lxvwsx v2, 0, r3 2833; P9BE-NEXT: blr 2834; 2835; P9LE-LABEL: spltMemValui: 2836; P9LE: # %bb.0: # %entry 2837; P9LE-NEXT: lxvwsx v2, 0, r3 2838; P9LE-NEXT: blr 2839; 2840; P8BE-LABEL: spltMemValui: 2841; P8BE: # %bb.0: # %entry 2842; P8BE-NEXT: lfiwzx f0, 0, r3 2843; P8BE-NEXT: xxsldwi vs0, f0, f0, 1 2844; P8BE-NEXT: xxspltw v2, vs0, 0 2845; P8BE-NEXT: blr 2846; 2847; P8LE-LABEL: spltMemValui: 2848; P8LE: # %bb.0: # %entry 2849; P8LE-NEXT: lfiwzx f0, 0, r3 2850; P8LE-NEXT: xxpermdi vs0, f0, f0, 2 2851; P8LE-NEXT: xxspltw v2, vs0, 3 2852; P8LE-NEXT: blr 2853entry: 2854 %0 = load i32, i32* %ptr, align 4 2855 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 2856 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2857 ret <4 x i32> %splat.splat 2858} 2859 2860; Function Attrs: norecurse nounwind readnone 2861define <4 x i32> @spltCnstConvftoui() { 2862; P9BE-LABEL: spltCnstConvftoui: 2863; P9BE: # %bb.0: # %entry 2864; P9BE-NEXT: vspltisw v2, 4 2865; P9BE-NEXT: blr 2866; 2867; P9LE-LABEL: spltCnstConvftoui: 2868; P9LE: # %bb.0: # %entry 2869; P9LE-NEXT: vspltisw v2, 4 2870; P9LE-NEXT: blr 2871; 2872; P8BE-LABEL: spltCnstConvftoui: 2873; P8BE: # %bb.0: # %entry 2874; P8BE-NEXT: vspltisw v2, 4 2875; P8BE-NEXT: blr 2876; 2877; P8LE-LABEL: spltCnstConvftoui: 2878; P8LE: # %bb.0: # %entry 2879; P8LE-NEXT: vspltisw v2, 4 2880; P8LE-NEXT: blr 2881entry: 2882 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 2883} 2884 2885; Function Attrs: norecurse nounwind readnone 2886define <4 x i32> @fromRegsConvftoui(float %a, float %b, float %c, float %d) { 2887; P9BE-LABEL: fromRegsConvftoui: 2888; P9BE: # %bb.0: # %entry 2889; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2890; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 2891; P9BE-NEXT: xxmrghd vs0, vs2, vs4 2892; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2893; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2894; P9BE-NEXT: xvcvdpuxws v2, vs0 2895; P9BE-NEXT: xxmrghd vs0, vs1, vs3 2896; P9BE-NEXT: xvcvdpuxws v3, vs0 2897; P9BE-NEXT: vmrgew v2, v3, v2 2898; P9BE-NEXT: blr 2899; 2900; P9LE-LABEL: fromRegsConvftoui: 2901; P9LE: # %bb.0: # %entry 2902; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2903; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2904; P9LE-NEXT: xxmrghd vs0, vs3, vs1 2905; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2906; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 2907; P9LE-NEXT: xvcvdpuxws v2, vs0 2908; P9LE-NEXT: xxmrghd vs0, vs4, vs2 2909; P9LE-NEXT: xvcvdpuxws v3, vs0 2910; P9LE-NEXT: vmrgew v2, v3, v2 2911; P9LE-NEXT: blr 2912; 2913; P8BE-LABEL: fromRegsConvftoui: 2914; P8BE: # %bb.0: # %entry 2915; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2916; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2917; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2918; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 2919; P8BE-NEXT: xxmrghd vs0, vs2, vs4 2920; P8BE-NEXT: xxmrghd vs1, vs1, vs3 2921; P8BE-NEXT: xvcvdpuxws v2, vs0 2922; P8BE-NEXT: xvcvdpuxws v3, vs1 2923; P8BE-NEXT: vmrgew v2, v3, v2 2924; P8BE-NEXT: blr 2925; 2926; P8LE-LABEL: fromRegsConvftoui: 2927; P8LE: # %bb.0: # %entry 2928; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2929; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2930; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2931; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 2932; P8LE-NEXT: xxmrghd vs0, vs3, vs1 2933; P8LE-NEXT: xxmrghd vs1, vs4, vs2 2934; P8LE-NEXT: xvcvdpuxws v2, vs0 2935; P8LE-NEXT: xvcvdpuxws v3, vs1 2936; P8LE-NEXT: vmrgew v2, v3, v2 2937; P8LE-NEXT: blr 2938entry: 2939 %conv = fptoui float %a to i32 2940 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2941 %conv1 = fptoui float %b to i32 2942 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 2943 %conv3 = fptoui float %c to i32 2944 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 2945 %conv5 = fptoui float %d to i32 2946 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 2947 ret <4 x i32> %vecinit6 2948} 2949 2950; Function Attrs: norecurse nounwind readnone 2951define <4 x i32> @fromDiffConstsConvftoui() { 2952; P9BE-LABEL: fromDiffConstsConvftoui: 2953; P9BE: # %bb.0: # %entry 2954; P9BE-NEXT: addis r3, r2, .LCPI48_0@toc@ha 2955; P9BE-NEXT: addi r3, r3, .LCPI48_0@toc@l 2956; P9BE-NEXT: lxvx v2, 0, r3 2957; P9BE-NEXT: blr 2958; 2959; P9LE-LABEL: fromDiffConstsConvftoui: 2960; P9LE: # %bb.0: # %entry 2961; P9LE-NEXT: addis r3, r2, .LCPI48_0@toc@ha 2962; P9LE-NEXT: addi r3, r3, .LCPI48_0@toc@l 2963; P9LE-NEXT: lxvx v2, 0, r3 2964; P9LE-NEXT: blr 2965; 2966; P8BE-LABEL: fromDiffConstsConvftoui: 2967; P8BE: # %bb.0: # %entry 2968; P8BE-NEXT: addis r3, r2, .LCPI48_0@toc@ha 2969; P8BE-NEXT: addi r3, r3, .LCPI48_0@toc@l 2970; P8BE-NEXT: lxvw4x v2, 0, r3 2971; P8BE-NEXT: blr 2972; 2973; P8LE-LABEL: fromDiffConstsConvftoui: 2974; P8LE: # %bb.0: # %entry 2975; P8LE-NEXT: addis r3, r2, .LCPI48_0@toc@ha 2976; P8LE-NEXT: addi r3, r3, .LCPI48_0@toc@l 2977; P8LE-NEXT: lvx v2, 0, r3 2978; P8LE-NEXT: blr 2979entry: 2980 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 2981} 2982 2983; Function Attrs: norecurse nounwind readonly 2984define <4 x i32> @fromDiffMemConsAConvftoui(float* nocapture readonly %ptr) { 2985; P9BE-LABEL: fromDiffMemConsAConvftoui: 2986; P9BE: # %bb.0: # %entry 2987; P9BE-NEXT: lxv vs0, 0(r3) 2988; P9BE-NEXT: xvcvspuxws v2, vs0 2989; P9BE-NEXT: blr 2990; 2991; P9LE-LABEL: fromDiffMemConsAConvftoui: 2992; P9LE: # %bb.0: # %entry 2993; P9LE-NEXT: lxv vs0, 0(r3) 2994; P9LE-NEXT: xvcvspuxws v2, vs0 2995; P9LE-NEXT: blr 2996; 2997; P8BE-LABEL: fromDiffMemConsAConvftoui: 2998; P8BE: # %bb.0: # %entry 2999; P8BE-NEXT: lxvw4x vs0, 0, r3 3000; P8BE-NEXT: xvcvspuxws v2, vs0 3001; P8BE-NEXT: blr 3002; 3003; P8LE-LABEL: fromDiffMemConsAConvftoui: 3004; P8LE: # %bb.0: # %entry 3005; P8LE-NEXT: lxvd2x vs0, 0, r3 3006; P8LE-NEXT: xxswapd v2, vs0 3007; P8LE-NEXT: xvcvspuxws v2, v2 3008; P8LE-NEXT: blr 3009entry: 3010 %0 = bitcast float* %ptr to <4 x float>* 3011 %1 = load <4 x float>, <4 x float>* %0, align 4 3012 %2 = fptoui <4 x float> %1 to <4 x i32> 3013 ret <4 x i32> %2 3014} 3015 3016; Function Attrs: norecurse nounwind readonly 3017define <4 x i32> @fromDiffMemConsDConvftoui(float* nocapture readonly %ptr) { 3018; P9BE-LABEL: fromDiffMemConsDConvftoui: 3019; P9BE: # %bb.0: # %entry 3020; P9BE-NEXT: lxv v2, 0(r3) 3021; P9BE-NEXT: addis r3, r2, .LCPI50_0@toc@ha 3022; P9BE-NEXT: addi r3, r3, .LCPI50_0@toc@l 3023; P9BE-NEXT: lxvx v3, 0, r3 3024; P9BE-NEXT: vperm v2, v2, v2, v3 3025; P9BE-NEXT: xvcvspuxws v2, v2 3026; P9BE-NEXT: blr 3027; 3028; P9LE-LABEL: fromDiffMemConsDConvftoui: 3029; P9LE: # %bb.0: # %entry 3030; P9LE-NEXT: lxv v2, 0(r3) 3031; P9LE-NEXT: addis r3, r2, .LCPI50_0@toc@ha 3032; P9LE-NEXT: addi r3, r3, .LCPI50_0@toc@l 3033; P9LE-NEXT: lxvx v3, 0, r3 3034; P9LE-NEXT: vperm v2, v2, v2, v3 3035; P9LE-NEXT: xvcvspuxws v2, v2 3036; P9LE-NEXT: blr 3037; 3038; P8BE-LABEL: fromDiffMemConsDConvftoui: 3039; P8BE: # %bb.0: # %entry 3040; P8BE-NEXT: addis r4, r2, .LCPI50_0@toc@ha 3041; P8BE-NEXT: lxvw4x v2, 0, r3 3042; P8BE-NEXT: addi r4, r4, .LCPI50_0@toc@l 3043; P8BE-NEXT: lxvw4x v3, 0, r4 3044; P8BE-NEXT: vperm v2, v2, v2, v3 3045; P8BE-NEXT: xvcvspuxws v2, v2 3046; P8BE-NEXT: blr 3047; 3048; P8LE-LABEL: fromDiffMemConsDConvftoui: 3049; P8LE: # %bb.0: # %entry 3050; P8LE-NEXT: lxvd2x vs0, 0, r3 3051; P8LE-NEXT: addis r4, r2, .LCPI50_0@toc@ha 3052; P8LE-NEXT: addi r3, r4, .LCPI50_0@toc@l 3053; P8LE-NEXT: lvx v2, 0, r3 3054; P8LE-NEXT: xxswapd v3, vs0 3055; P8LE-NEXT: vperm v2, v3, v3, v2 3056; P8LE-NEXT: xvcvspuxws v2, v2 3057; P8LE-NEXT: blr 3058entry: 3059 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 3060 %0 = load float, float* %arrayidx, align 4 3061 %conv = fptoui float %0 to i32 3062 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3063 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 3064 %1 = load float, float* %arrayidx1, align 4 3065 %conv2 = fptoui float %1 to i32 3066 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 3067 %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1 3068 %2 = load float, float* %arrayidx4, align 4 3069 %conv5 = fptoui float %2 to i32 3070 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 3071 %3 = load float, float* %ptr, align 4 3072 %conv8 = fptoui float %3 to i32 3073 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 3074 ret <4 x i32> %vecinit9 3075} 3076 3077; Function Attrs: norecurse nounwind readonly 3078define <4 x i32> @fromDiffMemVarAConvftoui(float* nocapture readonly %arr, i32 signext %elem) { 3079; P9BE-LABEL: fromDiffMemVarAConvftoui: 3080; P9BE: # %bb.0: # %entry 3081; P9BE-NEXT: sldi r4, r4, 2 3082; P9BE-NEXT: lfsux f0, r3, r4 3083; P9BE-NEXT: lfs f1, 12(r3) 3084; P9BE-NEXT: lfs f2, 4(r3) 3085; P9BE-NEXT: xxmrghd vs1, vs2, vs1 3086; P9BE-NEXT: xvcvdpsp v2, vs1 3087; P9BE-NEXT: lfs f1, 8(r3) 3088; P9BE-NEXT: xxmrghd vs0, vs0, vs1 3089; P9BE-NEXT: xvcvdpsp v3, vs0 3090; P9BE-NEXT: vmrgew v2, v3, v2 3091; P9BE-NEXT: xvcvspuxws v2, v2 3092; P9BE-NEXT: blr 3093; 3094; P9LE-LABEL: fromDiffMemVarAConvftoui: 3095; P9LE: # %bb.0: # %entry 3096; P9LE-NEXT: sldi r4, r4, 2 3097; P9LE-NEXT: lfsux f0, r3, r4 3098; P9LE-NEXT: lfs f1, 8(r3) 3099; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3100; P9LE-NEXT: lfs f1, 12(r3) 3101; P9LE-NEXT: xvcvdpsp v2, vs0 3102; P9LE-NEXT: lfs f0, 4(r3) 3103; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3104; P9LE-NEXT: xvcvdpsp v3, vs0 3105; P9LE-NEXT: vmrgew v2, v3, v2 3106; P9LE-NEXT: xvcvspuxws v2, v2 3107; P9LE-NEXT: blr 3108; 3109; P8BE-LABEL: fromDiffMemVarAConvftoui: 3110; P8BE: # %bb.0: # %entry 3111; P8BE-NEXT: sldi r4, r4, 2 3112; P8BE-NEXT: lfsux f0, r3, r4 3113; P8BE-NEXT: lfs f1, 12(r3) 3114; P8BE-NEXT: lfs f2, 4(r3) 3115; P8BE-NEXT: lfs f3, 8(r3) 3116; P8BE-NEXT: xxmrghd vs1, vs2, vs1 3117; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3118; P8BE-NEXT: xvcvdpsp v2, vs1 3119; P8BE-NEXT: xvcvdpsp v3, vs0 3120; P8BE-NEXT: vmrgew v2, v3, v2 3121; P8BE-NEXT: xvcvspuxws v2, v2 3122; P8BE-NEXT: blr 3123; 3124; P8LE-LABEL: fromDiffMemVarAConvftoui: 3125; P8LE: # %bb.0: # %entry 3126; P8LE-NEXT: sldi r4, r4, 2 3127; P8LE-NEXT: lfsux f0, r3, r4 3128; P8LE-NEXT: lfs f1, 8(r3) 3129; P8LE-NEXT: lfs f2, 4(r3) 3130; P8LE-NEXT: lfs f3, 12(r3) 3131; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3132; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3133; P8LE-NEXT: xvcvdpsp v2, vs0 3134; P8LE-NEXT: xvcvdpsp v3, vs1 3135; P8LE-NEXT: vmrgew v2, v3, v2 3136; P8LE-NEXT: xvcvspuxws v2, v2 3137; P8LE-NEXT: blr 3138entry: 3139 %idxprom = sext i32 %elem to i64 3140 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 3141 %0 = load float, float* %arrayidx, align 4 3142 %conv = fptoui float %0 to i32 3143 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3144 %add = add nsw i32 %elem, 1 3145 %idxprom1 = sext i32 %add to i64 3146 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 3147 %1 = load float, float* %arrayidx2, align 4 3148 %conv3 = fptoui float %1 to i32 3149 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3150 %add5 = add nsw i32 %elem, 2 3151 %idxprom6 = sext i32 %add5 to i64 3152 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 3153 %2 = load float, float* %arrayidx7, align 4 3154 %conv8 = fptoui float %2 to i32 3155 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3156 %add10 = add nsw i32 %elem, 3 3157 %idxprom11 = sext i32 %add10 to i64 3158 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 3159 %3 = load float, float* %arrayidx12, align 4 3160 %conv13 = fptoui float %3 to i32 3161 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3162 ret <4 x i32> %vecinit14 3163; FIXME: implement finding consecutive loads with pre-inc 3164} 3165 3166; Function Attrs: norecurse nounwind readonly 3167define <4 x i32> @fromDiffMemVarDConvftoui(float* nocapture readonly %arr, i32 signext %elem) { 3168; P9BE-LABEL: fromDiffMemVarDConvftoui: 3169; P9BE: # %bb.0: # %entry 3170; P9BE-NEXT: sldi r4, r4, 2 3171; P9BE-NEXT: lfsux f0, r3, r4 3172; P9BE-NEXT: lfs f1, -12(r3) 3173; P9BE-NEXT: lfs f2, -4(r3) 3174; P9BE-NEXT: xxmrghd vs1, vs2, vs1 3175; P9BE-NEXT: xvcvdpsp v2, vs1 3176; P9BE-NEXT: lfs f1, -8(r3) 3177; P9BE-NEXT: xxmrghd vs0, vs0, vs1 3178; P9BE-NEXT: xvcvdpsp v3, vs0 3179; P9BE-NEXT: vmrgew v2, v3, v2 3180; P9BE-NEXT: xvcvspuxws v2, v2 3181; P9BE-NEXT: blr 3182; 3183; P9LE-LABEL: fromDiffMemVarDConvftoui: 3184; P9LE: # %bb.0: # %entry 3185; P9LE-NEXT: sldi r4, r4, 2 3186; P9LE-NEXT: lfsux f0, r3, r4 3187; P9LE-NEXT: lfs f1, -8(r3) 3188; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3189; P9LE-NEXT: lfs f1, -12(r3) 3190; P9LE-NEXT: xvcvdpsp v2, vs0 3191; P9LE-NEXT: lfs f0, -4(r3) 3192; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3193; P9LE-NEXT: xvcvdpsp v3, vs0 3194; P9LE-NEXT: vmrgew v2, v3, v2 3195; P9LE-NEXT: xvcvspuxws v2, v2 3196; P9LE-NEXT: blr 3197; 3198; P8BE-LABEL: fromDiffMemVarDConvftoui: 3199; P8BE: # %bb.0: # %entry 3200; P8BE-NEXT: sldi r4, r4, 2 3201; P8BE-NEXT: lfsux f0, r3, r4 3202; P8BE-NEXT: lfs f1, -12(r3) 3203; P8BE-NEXT: lfs f2, -4(r3) 3204; P8BE-NEXT: lfs f3, -8(r3) 3205; P8BE-NEXT: xxmrghd vs1, vs2, vs1 3206; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3207; P8BE-NEXT: xvcvdpsp v2, vs1 3208; P8BE-NEXT: xvcvdpsp v3, vs0 3209; P8BE-NEXT: vmrgew v2, v3, v2 3210; P8BE-NEXT: xvcvspuxws v2, v2 3211; P8BE-NEXT: blr 3212; 3213; P8LE-LABEL: fromDiffMemVarDConvftoui: 3214; P8LE: # %bb.0: # %entry 3215; P8LE-NEXT: sldi r4, r4, 2 3216; P8LE-NEXT: lfsux f0, r3, r4 3217; P8LE-NEXT: lfs f1, -8(r3) 3218; P8LE-NEXT: lfs f2, -4(r3) 3219; P8LE-NEXT: lfs f3, -12(r3) 3220; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3221; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3222; P8LE-NEXT: xvcvdpsp v2, vs0 3223; P8LE-NEXT: xvcvdpsp v3, vs1 3224; P8LE-NEXT: vmrgew v2, v3, v2 3225; P8LE-NEXT: xvcvspuxws v2, v2 3226; P8LE-NEXT: blr 3227entry: 3228 %idxprom = sext i32 %elem to i64 3229 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 3230 %0 = load float, float* %arrayidx, align 4 3231 %conv = fptoui float %0 to i32 3232 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3233 %sub = add nsw i32 %elem, -1 3234 %idxprom1 = sext i32 %sub to i64 3235 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 3236 %1 = load float, float* %arrayidx2, align 4 3237 %conv3 = fptoui float %1 to i32 3238 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3239 %sub5 = add nsw i32 %elem, -2 3240 %idxprom6 = sext i32 %sub5 to i64 3241 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 3242 %2 = load float, float* %arrayidx7, align 4 3243 %conv8 = fptoui float %2 to i32 3244 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3245 %sub10 = add nsw i32 %elem, -3 3246 %idxprom11 = sext i32 %sub10 to i64 3247 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 3248 %3 = load float, float* %arrayidx12, align 4 3249 %conv13 = fptoui float %3 to i32 3250 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3251 ret <4 x i32> %vecinit14 3252; FIXME: implement finding consecutive loads with pre-inc 3253} 3254 3255; Function Attrs: norecurse nounwind readnone 3256define <4 x i32> @spltRegValConvftoui(float %val) { 3257; P9BE-LABEL: spltRegValConvftoui: 3258; P9BE: # %bb.0: # %entry 3259; P9BE-NEXT: xscvdpuxws f0, f1 3260; P9BE-NEXT: xxspltw v2, vs0, 1 3261; P9BE-NEXT: blr 3262; 3263; P9LE-LABEL: spltRegValConvftoui: 3264; P9LE: # %bb.0: # %entry 3265; P9LE-NEXT: xscvdpuxws f0, f1 3266; P9LE-NEXT: xxspltw v2, vs0, 1 3267; P9LE-NEXT: blr 3268; 3269; P8BE-LABEL: spltRegValConvftoui: 3270; P8BE: # %bb.0: # %entry 3271; P8BE-NEXT: xscvdpuxws f0, f1 3272; P8BE-NEXT: xxspltw v2, vs0, 1 3273; P8BE-NEXT: blr 3274; 3275; P8LE-LABEL: spltRegValConvftoui: 3276; P8LE: # %bb.0: # %entry 3277; P8LE-NEXT: xscvdpuxws f0, f1 3278; P8LE-NEXT: xxspltw v2, vs0, 1 3279; P8LE-NEXT: blr 3280entry: 3281 %conv = fptoui float %val to i32 3282 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3283 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3284 ret <4 x i32> %splat.splat 3285} 3286 3287; Function Attrs: norecurse nounwind readonly 3288define <4 x i32> @spltMemValConvftoui(float* nocapture readonly %ptr) { 3289; P9BE-LABEL: spltMemValConvftoui: 3290; P9BE: # %bb.0: # %entry 3291; P9BE-NEXT: lxvwsx vs0, 0, r3 3292; P9BE-NEXT: xvcvspuxws v2, vs0 3293; P9BE-NEXT: blr 3294; 3295; P9LE-LABEL: spltMemValConvftoui: 3296; P9LE: # %bb.0: # %entry 3297; P9LE-NEXT: lxvwsx vs0, 0, r3 3298; P9LE-NEXT: xvcvspuxws v2, vs0 3299; P9LE-NEXT: blr 3300; 3301; P8BE-LABEL: spltMemValConvftoui: 3302; P8BE: # %bb.0: # %entry 3303; P8BE-NEXT: lfsx f0, 0, r3 3304; P8BE-NEXT: xscvdpuxws f0, f0 3305; P8BE-NEXT: xxspltw v2, vs0, 1 3306; P8BE-NEXT: blr 3307; 3308; P8LE-LABEL: spltMemValConvftoui: 3309; P8LE: # %bb.0: # %entry 3310; P8LE-NEXT: lfsx f0, 0, r3 3311; P8LE-NEXT: xscvdpuxws f0, f0 3312; P8LE-NEXT: xxspltw v2, vs0, 1 3313; P8LE-NEXT: blr 3314entry: 3315 %0 = load float, float* %ptr, align 4 3316 %conv = fptoui float %0 to i32 3317 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3318 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3319 ret <4 x i32> %splat.splat 3320} 3321 3322; Function Attrs: norecurse nounwind readnone 3323define <4 x i32> @spltCnstConvdtoui() { 3324; P9BE-LABEL: spltCnstConvdtoui: 3325; P9BE: # %bb.0: # %entry 3326; P9BE-NEXT: vspltisw v2, 4 3327; P9BE-NEXT: blr 3328; 3329; P9LE-LABEL: spltCnstConvdtoui: 3330; P9LE: # %bb.0: # %entry 3331; P9LE-NEXT: vspltisw v2, 4 3332; P9LE-NEXT: blr 3333; 3334; P8BE-LABEL: spltCnstConvdtoui: 3335; P8BE: # %bb.0: # %entry 3336; P8BE-NEXT: vspltisw v2, 4 3337; P8BE-NEXT: blr 3338; 3339; P8LE-LABEL: spltCnstConvdtoui: 3340; P8LE: # %bb.0: # %entry 3341; P8LE-NEXT: vspltisw v2, 4 3342; P8LE-NEXT: blr 3343entry: 3344 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 3345} 3346 3347; Function Attrs: norecurse nounwind readnone 3348define <4 x i32> @fromRegsConvdtoui(double %a, double %b, double %c, double %d) { 3349; P9BE-LABEL: fromRegsConvdtoui: 3350; P9BE: # %bb.0: # %entry 3351; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3352; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3353; P9BE-NEXT: xxmrghd vs0, vs2, vs4 3354; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3355; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3356; P9BE-NEXT: xvcvdpuxws v2, vs0 3357; P9BE-NEXT: xxmrghd vs0, vs1, vs3 3358; P9BE-NEXT: xvcvdpuxws v3, vs0 3359; P9BE-NEXT: vmrgew v2, v3, v2 3360; P9BE-NEXT: blr 3361; 3362; P9LE-LABEL: fromRegsConvdtoui: 3363; P9LE: # %bb.0: # %entry 3364; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3365; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3366; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3367; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3368; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3369; P9LE-NEXT: xvcvdpuxws v2, vs0 3370; P9LE-NEXT: xxmrghd vs0, vs4, vs2 3371; P9LE-NEXT: xvcvdpuxws v3, vs0 3372; P9LE-NEXT: vmrgew v2, v3, v2 3373; P9LE-NEXT: blr 3374; 3375; P8BE-LABEL: fromRegsConvdtoui: 3376; P8BE: # %bb.0: # %entry 3377; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3378; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3379; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3380; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3381; P8BE-NEXT: xxmrghd vs0, vs2, vs4 3382; P8BE-NEXT: xxmrghd vs1, vs1, vs3 3383; P8BE-NEXT: xvcvdpuxws v2, vs0 3384; P8BE-NEXT: xvcvdpuxws v3, vs1 3385; P8BE-NEXT: vmrgew v2, v3, v2 3386; P8BE-NEXT: blr 3387; 3388; P8LE-LABEL: fromRegsConvdtoui: 3389; P8LE: # %bb.0: # %entry 3390; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3391; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3392; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3393; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3394; P8LE-NEXT: xxmrghd vs0, vs3, vs1 3395; P8LE-NEXT: xxmrghd vs1, vs4, vs2 3396; P8LE-NEXT: xvcvdpuxws v2, vs0 3397; P8LE-NEXT: xvcvdpuxws v3, vs1 3398; P8LE-NEXT: vmrgew v2, v3, v2 3399; P8LE-NEXT: blr 3400entry: 3401 %conv = fptoui double %a to i32 3402 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3403 %conv1 = fptoui double %b to i32 3404 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 3405 %conv3 = fptoui double %c to i32 3406 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 3407 %conv5 = fptoui double %d to i32 3408 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 3409 ret <4 x i32> %vecinit6 3410} 3411 3412; Function Attrs: norecurse nounwind readnone 3413define <4 x i32> @fromDiffConstsConvdtoui() { 3414; P9BE-LABEL: fromDiffConstsConvdtoui: 3415; P9BE: # %bb.0: # %entry 3416; P9BE-NEXT: addis r3, r2, .LCPI57_0@toc@ha 3417; P9BE-NEXT: addi r3, r3, .LCPI57_0@toc@l 3418; P9BE-NEXT: lxvx v2, 0, r3 3419; P9BE-NEXT: blr 3420; 3421; P9LE-LABEL: fromDiffConstsConvdtoui: 3422; P9LE: # %bb.0: # %entry 3423; P9LE-NEXT: addis r3, r2, .LCPI57_0@toc@ha 3424; P9LE-NEXT: addi r3, r3, .LCPI57_0@toc@l 3425; P9LE-NEXT: lxvx v2, 0, r3 3426; P9LE-NEXT: blr 3427; 3428; P8BE-LABEL: fromDiffConstsConvdtoui: 3429; P8BE: # %bb.0: # %entry 3430; P8BE-NEXT: addis r3, r2, .LCPI57_0@toc@ha 3431; P8BE-NEXT: addi r3, r3, .LCPI57_0@toc@l 3432; P8BE-NEXT: lxvw4x v2, 0, r3 3433; P8BE-NEXT: blr 3434; 3435; P8LE-LABEL: fromDiffConstsConvdtoui: 3436; P8LE: # %bb.0: # %entry 3437; P8LE-NEXT: addis r3, r2, .LCPI57_0@toc@ha 3438; P8LE-NEXT: addi r3, r3, .LCPI57_0@toc@l 3439; P8LE-NEXT: lvx v2, 0, r3 3440; P8LE-NEXT: blr 3441entry: 3442 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 3443} 3444 3445; Function Attrs: norecurse nounwind readonly 3446define <4 x i32> @fromDiffMemConsAConvdtoui(double* nocapture readonly %ptr) { 3447; P9BE-LABEL: fromDiffMemConsAConvdtoui: 3448; P9BE: # %bb.0: # %entry 3449; P9BE-NEXT: lxv vs0, 0(r3) 3450; P9BE-NEXT: lxv vs1, 16(r3) 3451; P9BE-NEXT: xxmrgld vs2, vs0, vs1 3452; P9BE-NEXT: xxmrghd vs0, vs0, vs1 3453; P9BE-NEXT: xvcvdpuxws v2, vs2 3454; P9BE-NEXT: xvcvdpuxws v3, vs0 3455; P9BE-NEXT: vmrgew v2, v3, v2 3456; P9BE-NEXT: blr 3457; 3458; P9LE-LABEL: fromDiffMemConsAConvdtoui: 3459; P9LE: # %bb.0: # %entry 3460; P9LE-NEXT: lxv vs0, 0(r3) 3461; P9LE-NEXT: lxv vs1, 16(r3) 3462; P9LE-NEXT: xxmrgld vs2, vs1, vs0 3463; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3464; P9LE-NEXT: xvcvdpuxws v2, vs2 3465; P9LE-NEXT: xvcvdpuxws v3, vs0 3466; P9LE-NEXT: vmrgew v2, v3, v2 3467; P9LE-NEXT: blr 3468; 3469; P8BE-LABEL: fromDiffMemConsAConvdtoui: 3470; P8BE: # %bb.0: # %entry 3471; P8BE-NEXT: li r4, 16 3472; P8BE-NEXT: lxvd2x vs0, 0, r3 3473; P8BE-NEXT: lxvd2x vs1, r3, r4 3474; P8BE-NEXT: xxmrgld vs2, vs0, vs1 3475; P8BE-NEXT: xxmrghd vs0, vs0, vs1 3476; P8BE-NEXT: xvcvdpuxws v2, vs2 3477; P8BE-NEXT: xvcvdpuxws v3, vs0 3478; P8BE-NEXT: vmrgew v2, v3, v2 3479; P8BE-NEXT: blr 3480; 3481; P8LE-LABEL: fromDiffMemConsAConvdtoui: 3482; P8LE: # %bb.0: # %entry 3483; P8LE-NEXT: li r4, 16 3484; P8LE-NEXT: lxvd2x vs0, 0, r3 3485; P8LE-NEXT: lxvd2x vs1, r3, r4 3486; P8LE-NEXT: xxswapd vs0, vs0 3487; P8LE-NEXT: xxswapd vs1, vs1 3488; P8LE-NEXT: xxmrgld vs2, vs1, vs0 3489; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3490; P8LE-NEXT: xvcvdpuxws v2, vs2 3491; P8LE-NEXT: xvcvdpuxws v3, vs0 3492; P8LE-NEXT: vmrgew v2, v3, v2 3493; P8LE-NEXT: blr 3494entry: 3495 %0 = bitcast double* %ptr to <2 x double>* 3496 %1 = load <2 x double>, <2 x double>* %0, align 8 3497 %2 = fptoui <2 x double> %1 to <2 x i32> 3498 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 2 3499 %3 = bitcast double* %arrayidx4 to <2 x double>* 3500 %4 = load <2 x double>, <2 x double>* %3, align 8 3501 %5 = fptoui <2 x double> %4 to <2 x i32> 3502 %vecinit9 = shufflevector <2 x i32> %2, <2 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 3503 ret <4 x i32> %vecinit9 3504} 3505 3506; Function Attrs: norecurse nounwind readonly 3507define <4 x i32> @fromDiffMemConsDConvdtoui(double* nocapture readonly %ptr) { 3508; P9BE-LABEL: fromDiffMemConsDConvdtoui: 3509; P9BE: # %bb.0: # %entry 3510; P9BE-NEXT: lfd f0, 24(r3) 3511; P9BE-NEXT: lfd f1, 16(r3) 3512; P9BE-NEXT: lfd f2, 8(r3) 3513; P9BE-NEXT: xxmrghd vs0, vs0, vs2 3514; P9BE-NEXT: lfd f3, 0(r3) 3515; P9BE-NEXT: xxmrghd vs1, vs1, vs3 3516; P9BE-NEXT: xvcvdpuxws v2, vs1 3517; P9BE-NEXT: xvcvdpuxws v3, vs0 3518; P9BE-NEXT: vmrgew v2, v3, v2 3519; P9BE-NEXT: blr 3520; 3521; P9LE-LABEL: fromDiffMemConsDConvdtoui: 3522; P9LE: # %bb.0: # %entry 3523; P9LE-NEXT: lfd f0, 24(r3) 3524; P9LE-NEXT: lfd f2, 8(r3) 3525; P9LE-NEXT: xxmrghd vs0, vs2, vs0 3526; P9LE-NEXT: lfd f1, 16(r3) 3527; P9LE-NEXT: lfd f3, 0(r3) 3528; P9LE-NEXT: xvcvdpuxws v2, vs0 3529; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3530; P9LE-NEXT: xvcvdpuxws v3, vs0 3531; P9LE-NEXT: vmrgew v2, v3, v2 3532; P9LE-NEXT: blr 3533; 3534; P8BE-LABEL: fromDiffMemConsDConvdtoui: 3535; P8BE: # %bb.0: # %entry 3536; P8BE-NEXT: lfdx f3, 0, r3 3537; P8BE-NEXT: lfd f0, 24(r3) 3538; P8BE-NEXT: lfd f1, 8(r3) 3539; P8BE-NEXT: lfd f2, 16(r3) 3540; P8BE-NEXT: xxmrghd vs0, vs0, vs1 3541; P8BE-NEXT: xxmrghd vs1, vs2, vs3 3542; P8BE-NEXT: xvcvdpuxws v2, vs0 3543; P8BE-NEXT: xvcvdpuxws v3, vs1 3544; P8BE-NEXT: vmrgew v2, v2, v3 3545; P8BE-NEXT: blr 3546; 3547; P8LE-LABEL: fromDiffMemConsDConvdtoui: 3548; P8LE: # %bb.0: # %entry 3549; P8LE-NEXT: lfdx f3, 0, r3 3550; P8LE-NEXT: lfd f0, 24(r3) 3551; P8LE-NEXT: lfd f1, 8(r3) 3552; P8LE-NEXT: lfd f2, 16(r3) 3553; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3554; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3555; P8LE-NEXT: xvcvdpuxws v2, vs0 3556; P8LE-NEXT: xvcvdpuxws v3, vs1 3557; P8LE-NEXT: vmrgew v2, v3, v2 3558; P8LE-NEXT: blr 3559entry: 3560 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 3561 %0 = load double, double* %arrayidx, align 8 3562 %conv = fptoui double %0 to i32 3563 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3564 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 3565 %1 = load double, double* %arrayidx1, align 8 3566 %conv2 = fptoui double %1 to i32 3567 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 3568 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 1 3569 %2 = load double, double* %arrayidx4, align 8 3570 %conv5 = fptoui double %2 to i32 3571 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 3572 %3 = load double, double* %ptr, align 8 3573 %conv8 = fptoui double %3 to i32 3574 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 3575 ret <4 x i32> %vecinit9 3576} 3577 3578; Function Attrs: norecurse nounwind readonly 3579define <4 x i32> @fromDiffMemVarAConvdtoui(double* nocapture readonly %arr, i32 signext %elem) { 3580; P9BE-LABEL: fromDiffMemVarAConvdtoui: 3581; P9BE: # %bb.0: # %entry 3582; P9BE-NEXT: sldi r4, r4, 3 3583; P9BE-NEXT: lfdux f0, r3, r4 3584; P9BE-NEXT: lfd f1, 8(r3) 3585; P9BE-NEXT: lfd f2, 16(r3) 3586; P9BE-NEXT: lfd f3, 24(r3) 3587; P9BE-NEXT: xxmrghd vs1, vs1, vs3 3588; P9BE-NEXT: xxmrghd vs0, vs0, vs2 3589; P9BE-NEXT: xvcvdpuxws v2, vs1 3590; P9BE-NEXT: xvcvdpuxws v3, vs0 3591; P9BE-NEXT: vmrgew v2, v3, v2 3592; P9BE-NEXT: blr 3593; 3594; P9LE-LABEL: fromDiffMemVarAConvdtoui: 3595; P9LE: # %bb.0: # %entry 3596; P9LE-NEXT: sldi r4, r4, 3 3597; P9LE-NEXT: lfdux f0, r3, r4 3598; P9LE-NEXT: lfd f2, 16(r3) 3599; P9LE-NEXT: lfd f1, 8(r3) 3600; P9LE-NEXT: lfd f3, 24(r3) 3601; P9LE-NEXT: xxmrghd vs0, vs2, vs0 3602; P9LE-NEXT: xvcvdpuxws v2, vs0 3603; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3604; P9LE-NEXT: xvcvdpuxws v3, vs0 3605; P9LE-NEXT: vmrgew v2, v3, v2 3606; P9LE-NEXT: blr 3607; 3608; P8BE-LABEL: fromDiffMemVarAConvdtoui: 3609; P8BE: # %bb.0: # %entry 3610; P8BE-NEXT: sldi r4, r4, 3 3611; P8BE-NEXT: lfdux f0, r3, r4 3612; P8BE-NEXT: lfd f1, 8(r3) 3613; P8BE-NEXT: lfd f2, 24(r3) 3614; P8BE-NEXT: lfd f3, 16(r3) 3615; P8BE-NEXT: xxmrghd vs1, vs1, vs2 3616; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3617; P8BE-NEXT: xvcvdpuxws v2, vs1 3618; P8BE-NEXT: xvcvdpuxws v3, vs0 3619; P8BE-NEXT: vmrgew v2, v3, v2 3620; P8BE-NEXT: blr 3621; 3622; P8LE-LABEL: fromDiffMemVarAConvdtoui: 3623; P8LE: # %bb.0: # %entry 3624; P8LE-NEXT: sldi r4, r4, 3 3625; P8LE-NEXT: lfdux f0, r3, r4 3626; P8LE-NEXT: lfd f1, 16(r3) 3627; P8LE-NEXT: lfd f2, 8(r3) 3628; P8LE-NEXT: lfd f3, 24(r3) 3629; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3630; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3631; P8LE-NEXT: xvcvdpuxws v2, vs0 3632; P8LE-NEXT: xvcvdpuxws v3, vs1 3633; P8LE-NEXT: vmrgew v2, v3, v2 3634; P8LE-NEXT: blr 3635entry: 3636 %idxprom = sext i32 %elem to i64 3637 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 3638 %0 = load double, double* %arrayidx, align 8 3639 %conv = fptoui double %0 to i32 3640 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3641 %add = add nsw i32 %elem, 1 3642 %idxprom1 = sext i32 %add to i64 3643 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 3644 %1 = load double, double* %arrayidx2, align 8 3645 %conv3 = fptoui double %1 to i32 3646 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3647 %add5 = add nsw i32 %elem, 2 3648 %idxprom6 = sext i32 %add5 to i64 3649 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 3650 %2 = load double, double* %arrayidx7, align 8 3651 %conv8 = fptoui double %2 to i32 3652 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3653 %add10 = add nsw i32 %elem, 3 3654 %idxprom11 = sext i32 %add10 to i64 3655 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 3656 %3 = load double, double* %arrayidx12, align 8 3657 %conv13 = fptoui double %3 to i32 3658 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3659 ret <4 x i32> %vecinit14 3660} 3661 3662; Function Attrs: norecurse nounwind readonly 3663define <4 x i32> @fromDiffMemVarDConvdtoui(double* nocapture readonly %arr, i32 signext %elem) { 3664; P9BE-LABEL: fromDiffMemVarDConvdtoui: 3665; P9BE: # %bb.0: # %entry 3666; P9BE-NEXT: sldi r4, r4, 3 3667; P9BE-NEXT: lfdux f0, r3, r4 3668; P9BE-NEXT: lfd f1, -8(r3) 3669; P9BE-NEXT: lfd f2, -16(r3) 3670; P9BE-NEXT: lfd f3, -24(r3) 3671; P9BE-NEXT: xxmrghd vs1, vs1, vs3 3672; P9BE-NEXT: xxmrghd vs0, vs0, vs2 3673; P9BE-NEXT: xvcvdpuxws v2, vs1 3674; P9BE-NEXT: xvcvdpuxws v3, vs0 3675; P9BE-NEXT: vmrgew v2, v3, v2 3676; P9BE-NEXT: blr 3677; 3678; P9LE-LABEL: fromDiffMemVarDConvdtoui: 3679; P9LE: # %bb.0: # %entry 3680; P9LE-NEXT: sldi r4, r4, 3 3681; P9LE-NEXT: lfdux f0, r3, r4 3682; P9LE-NEXT: lfd f2, -16(r3) 3683; P9LE-NEXT: lfd f1, -8(r3) 3684; P9LE-NEXT: lfd f3, -24(r3) 3685; P9LE-NEXT: xxmrghd vs0, vs2, vs0 3686; P9LE-NEXT: xvcvdpuxws v2, vs0 3687; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3688; P9LE-NEXT: xvcvdpuxws v3, vs0 3689; P9LE-NEXT: vmrgew v2, v3, v2 3690; P9LE-NEXT: blr 3691; 3692; P8BE-LABEL: fromDiffMemVarDConvdtoui: 3693; P8BE: # %bb.0: # %entry 3694; P8BE-NEXT: sldi r4, r4, 3 3695; P8BE-NEXT: lfdux f0, r3, r4 3696; P8BE-NEXT: lfd f1, -8(r3) 3697; P8BE-NEXT: lfd f2, -24(r3) 3698; P8BE-NEXT: lfd f3, -16(r3) 3699; P8BE-NEXT: xxmrghd vs1, vs1, vs2 3700; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3701; P8BE-NEXT: xvcvdpuxws v2, vs1 3702; P8BE-NEXT: xvcvdpuxws v3, vs0 3703; P8BE-NEXT: vmrgew v2, v3, v2 3704; P8BE-NEXT: blr 3705; 3706; P8LE-LABEL: fromDiffMemVarDConvdtoui: 3707; P8LE: # %bb.0: # %entry 3708; P8LE-NEXT: sldi r4, r4, 3 3709; P8LE-NEXT: lfdux f0, r3, r4 3710; P8LE-NEXT: lfd f1, -16(r3) 3711; P8LE-NEXT: lfd f2, -8(r3) 3712; P8LE-NEXT: lfd f3, -24(r3) 3713; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3714; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3715; P8LE-NEXT: xvcvdpuxws v2, vs0 3716; P8LE-NEXT: xvcvdpuxws v3, vs1 3717; P8LE-NEXT: vmrgew v2, v3, v2 3718; P8LE-NEXT: blr 3719entry: 3720 %idxprom = sext i32 %elem to i64 3721 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 3722 %0 = load double, double* %arrayidx, align 8 3723 %conv = fptoui double %0 to i32 3724 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3725 %sub = add nsw i32 %elem, -1 3726 %idxprom1 = sext i32 %sub to i64 3727 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 3728 %1 = load double, double* %arrayidx2, align 8 3729 %conv3 = fptoui double %1 to i32 3730 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3731 %sub5 = add nsw i32 %elem, -2 3732 %idxprom6 = sext i32 %sub5 to i64 3733 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 3734 %2 = load double, double* %arrayidx7, align 8 3735 %conv8 = fptoui double %2 to i32 3736 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3737 %sub10 = add nsw i32 %elem, -3 3738 %idxprom11 = sext i32 %sub10 to i64 3739 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 3740 %3 = load double, double* %arrayidx12, align 8 3741 %conv13 = fptoui double %3 to i32 3742 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3743 ret <4 x i32> %vecinit14 3744} 3745 3746; Function Attrs: norecurse nounwind readnone 3747define <4 x i32> @spltRegValConvdtoui(double %val) { 3748; P9BE-LABEL: spltRegValConvdtoui: 3749; P9BE: # %bb.0: # %entry 3750; P9BE-NEXT: xscvdpuxws f0, f1 3751; P9BE-NEXT: xxspltw v2, vs0, 1 3752; P9BE-NEXT: blr 3753; 3754; P9LE-LABEL: spltRegValConvdtoui: 3755; P9LE: # %bb.0: # %entry 3756; P9LE-NEXT: xscvdpuxws f0, f1 3757; P9LE-NEXT: xxspltw v2, vs0, 1 3758; P9LE-NEXT: blr 3759; 3760; P8BE-LABEL: spltRegValConvdtoui: 3761; P8BE: # %bb.0: # %entry 3762; P8BE-NEXT: xscvdpuxws f0, f1 3763; P8BE-NEXT: xxspltw v2, vs0, 1 3764; P8BE-NEXT: blr 3765; 3766; P8LE-LABEL: spltRegValConvdtoui: 3767; P8LE: # %bb.0: # %entry 3768; P8LE-NEXT: xscvdpuxws f0, f1 3769; P8LE-NEXT: xxspltw v2, vs0, 1 3770; P8LE-NEXT: blr 3771entry: 3772 %conv = fptoui double %val to i32 3773 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3774 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3775 ret <4 x i32> %splat.splat 3776} 3777 3778; Function Attrs: norecurse nounwind readonly 3779define <4 x i32> @spltMemValConvdtoui(double* nocapture readonly %ptr) { 3780; P9BE-LABEL: spltMemValConvdtoui: 3781; P9BE: # %bb.0: # %entry 3782; P9BE-NEXT: lfd f0, 0(r3) 3783; P9BE-NEXT: xscvdpuxws f0, f0 3784; P9BE-NEXT: xxspltw v2, vs0, 1 3785; P9BE-NEXT: blr 3786; 3787; P9LE-LABEL: spltMemValConvdtoui: 3788; P9LE: # %bb.0: # %entry 3789; P9LE-NEXT: lfd f0, 0(r3) 3790; P9LE-NEXT: xscvdpuxws f0, f0 3791; P9LE-NEXT: xxspltw v2, vs0, 1 3792; P9LE-NEXT: blr 3793; 3794; P8BE-LABEL: spltMemValConvdtoui: 3795; P8BE: # %bb.0: # %entry 3796; P8BE-NEXT: lfdx f0, 0, r3 3797; P8BE-NEXT: xscvdpuxws f0, f0 3798; P8BE-NEXT: xxspltw v2, vs0, 1 3799; P8BE-NEXT: blr 3800; 3801; P8LE-LABEL: spltMemValConvdtoui: 3802; P8LE: # %bb.0: # %entry 3803; P8LE-NEXT: lfdx f0, 0, r3 3804; P8LE-NEXT: xscvdpuxws f0, f0 3805; P8LE-NEXT: xxspltw v2, vs0, 1 3806; P8LE-NEXT: blr 3807entry: 3808 %0 = load double, double* %ptr, align 8 3809 %conv = fptoui double %0 to i32 3810 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3811 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3812 ret <4 x i32> %splat.splat 3813} 3814; Function Attrs: norecurse nounwind readnone 3815define <2 x i64> @allZeroll() { 3816; P9BE-LABEL: allZeroll: 3817; P9BE: # %bb.0: # %entry 3818; P9BE-NEXT: xxlxor v2, v2, v2 3819; P9BE-NEXT: blr 3820; 3821; P9LE-LABEL: allZeroll: 3822; P9LE: # %bb.0: # %entry 3823; P9LE-NEXT: xxlxor v2, v2, v2 3824; P9LE-NEXT: blr 3825; 3826; P8BE-LABEL: allZeroll: 3827; P8BE: # %bb.0: # %entry 3828; P8BE-NEXT: xxlxor v2, v2, v2 3829; P8BE-NEXT: blr 3830; 3831; P8LE-LABEL: allZeroll: 3832; P8LE: # %bb.0: # %entry 3833; P8LE-NEXT: xxlxor v2, v2, v2 3834; P8LE-NEXT: blr 3835entry: 3836 ret <2 x i64> zeroinitializer 3837} 3838 3839; Function Attrs: norecurse nounwind readnone 3840define <2 x i64> @spltConst1ll() { 3841; P9BE-LABEL: spltConst1ll: 3842; P9BE: # %bb.0: # %entry 3843; P9BE-NEXT: addis r3, r2, .LCPI65_0@toc@ha 3844; P9BE-NEXT: addi r3, r3, .LCPI65_0@toc@l 3845; P9BE-NEXT: lxvx v2, 0, r3 3846; P9BE-NEXT: blr 3847; 3848; P9LE-LABEL: spltConst1ll: 3849; P9LE: # %bb.0: # %entry 3850; P9LE-NEXT: addis r3, r2, .LCPI65_0@toc@ha 3851; P9LE-NEXT: addi r3, r3, .LCPI65_0@toc@l 3852; P9LE-NEXT: lxvx v2, 0, r3 3853; P9LE-NEXT: blr 3854; 3855; P8BE-LABEL: spltConst1ll: 3856; P8BE: # %bb.0: # %entry 3857; P8BE-NEXT: addis r3, r2, .LCPI65_0@toc@ha 3858; P8BE-NEXT: addi r3, r3, .LCPI65_0@toc@l 3859; P8BE-NEXT: lxvd2x v2, 0, r3 3860; P8BE-NEXT: blr 3861; 3862; P8LE-LABEL: spltConst1ll: 3863; P8LE: # %bb.0: # %entry 3864; P8LE-NEXT: addis r3, r2, .LCPI65_0@toc@ha 3865; P8LE-NEXT: addi r3, r3, .LCPI65_0@toc@l 3866; P8LE-NEXT: lxvd2x vs0, 0, r3 3867; P8LE-NEXT: xxswapd v2, vs0 3868; P8LE-NEXT: blr 3869entry: 3870 ret <2 x i64> <i64 1, i64 1> 3871} 3872 3873; Function Attrs: norecurse nounwind readnone 3874define <2 x i64> @spltConst16kll() { 3875; P9BE-LABEL: spltConst16kll: 3876; P9BE: # %bb.0: # %entry 3877; P9BE-NEXT: addis r3, r2, .LCPI66_0@toc@ha 3878; P9BE-NEXT: addi r3, r3, .LCPI66_0@toc@l 3879; P9BE-NEXT: lxvx v2, 0, r3 3880; P9BE-NEXT: blr 3881; 3882; P9LE-LABEL: spltConst16kll: 3883; P9LE: # %bb.0: # %entry 3884; P9LE-NEXT: addis r3, r2, .LCPI66_0@toc@ha 3885; P9LE-NEXT: addi r3, r3, .LCPI66_0@toc@l 3886; P9LE-NEXT: lxvx v2, 0, r3 3887; P9LE-NEXT: blr 3888; 3889; P8BE-LABEL: spltConst16kll: 3890; P8BE: # %bb.0: # %entry 3891; P8BE-NEXT: addis r3, r2, .LCPI66_0@toc@ha 3892; P8BE-NEXT: addi r3, r3, .LCPI66_0@toc@l 3893; P8BE-NEXT: lxvd2x v2, 0, r3 3894; P8BE-NEXT: blr 3895; 3896; P8LE-LABEL: spltConst16kll: 3897; P8LE: # %bb.0: # %entry 3898; P8LE-NEXT: addis r3, r2, .LCPI66_0@toc@ha 3899; P8LE-NEXT: addi r3, r3, .LCPI66_0@toc@l 3900; P8LE-NEXT: lxvd2x vs0, 0, r3 3901; P8LE-NEXT: xxswapd v2, vs0 3902; P8LE-NEXT: blr 3903entry: 3904 ret <2 x i64> <i64 32767, i64 32767> 3905} 3906 3907; Function Attrs: norecurse nounwind readnone 3908define <2 x i64> @spltConst32kll() { 3909; P9BE-LABEL: spltConst32kll: 3910; P9BE: # %bb.0: # %entry 3911; P9BE-NEXT: addis r3, r2, .LCPI67_0@toc@ha 3912; P9BE-NEXT: addi r3, r3, .LCPI67_0@toc@l 3913; P9BE-NEXT: lxvx v2, 0, r3 3914; P9BE-NEXT: blr 3915; 3916; P9LE-LABEL: spltConst32kll: 3917; P9LE: # %bb.0: # %entry 3918; P9LE-NEXT: addis r3, r2, .LCPI67_0@toc@ha 3919; P9LE-NEXT: addi r3, r3, .LCPI67_0@toc@l 3920; P9LE-NEXT: lxvx v2, 0, r3 3921; P9LE-NEXT: blr 3922; 3923; P8BE-LABEL: spltConst32kll: 3924; P8BE: # %bb.0: # %entry 3925; P8BE-NEXT: addis r3, r2, .LCPI67_0@toc@ha 3926; P8BE-NEXT: addi r3, r3, .LCPI67_0@toc@l 3927; P8BE-NEXT: lxvd2x v2, 0, r3 3928; P8BE-NEXT: blr 3929; 3930; P8LE-LABEL: spltConst32kll: 3931; P8LE: # %bb.0: # %entry 3932; P8LE-NEXT: addis r3, r2, .LCPI67_0@toc@ha 3933; P8LE-NEXT: addi r3, r3, .LCPI67_0@toc@l 3934; P8LE-NEXT: lxvd2x vs0, 0, r3 3935; P8LE-NEXT: xxswapd v2, vs0 3936; P8LE-NEXT: blr 3937entry: 3938 ret <2 x i64> <i64 65535, i64 65535> 3939} 3940 3941; Function Attrs: norecurse nounwind readnone 3942define <2 x i64> @fromRegsll(i64 %a, i64 %b) { 3943; P9BE-LABEL: fromRegsll: 3944; P9BE: # %bb.0: # %entry 3945; P9BE-NEXT: mtvsrdd v2, r3, r4 3946; P9BE-NEXT: blr 3947; 3948; P9LE-LABEL: fromRegsll: 3949; P9LE: # %bb.0: # %entry 3950; P9LE-NEXT: mtvsrdd v2, r4, r3 3951; P9LE-NEXT: blr 3952; 3953; P8BE-LABEL: fromRegsll: 3954; P8BE: # %bb.0: # %entry 3955; P8BE-NEXT: mtvsrd f0, r4 3956; P8BE-NEXT: mtvsrd f1, r3 3957; P8BE-NEXT: xxmrghd v2, vs1, vs0 3958; P8BE-NEXT: blr 3959; 3960; P8LE-LABEL: fromRegsll: 3961; P8LE: # %bb.0: # %entry 3962; P8LE-NEXT: mtvsrd f0, r3 3963; P8LE-NEXT: mtvsrd f1, r4 3964; P8LE-NEXT: xxmrghd v2, vs1, vs0 3965; P8LE-NEXT: blr 3966entry: 3967 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 3968 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 3969 ret <2 x i64> %vecinit1 3970} 3971 3972; Function Attrs: norecurse nounwind readnone 3973define <2 x i64> @fromDiffConstsll() { 3974; P9BE-LABEL: fromDiffConstsll: 3975; P9BE: # %bb.0: # %entry 3976; P9BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3977; P9BE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3978; P9BE-NEXT: lxvx v2, 0, r3 3979; P9BE-NEXT: blr 3980; 3981; P9LE-LABEL: fromDiffConstsll: 3982; P9LE: # %bb.0: # %entry 3983; P9LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3984; P9LE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3985; P9LE-NEXT: lxvx v2, 0, r3 3986; P9LE-NEXT: blr 3987; 3988; P8BE-LABEL: fromDiffConstsll: 3989; P8BE: # %bb.0: # %entry 3990; P8BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3991; P8BE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3992; P8BE-NEXT: lxvd2x v2, 0, r3 3993; P8BE-NEXT: blr 3994; 3995; P8LE-LABEL: fromDiffConstsll: 3996; P8LE: # %bb.0: # %entry 3997; P8LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3998; P8LE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3999; P8LE-NEXT: lxvd2x vs0, 0, r3 4000; P8LE-NEXT: xxswapd v2, vs0 4001; P8LE-NEXT: blr 4002entry: 4003 ret <2 x i64> <i64 242, i64 -113> 4004} 4005 4006; Function Attrs: norecurse nounwind readonly 4007define <2 x i64> @fromDiffMemConsAll(i64* nocapture readonly %arr) { 4008; P9BE-LABEL: fromDiffMemConsAll: 4009; P9BE: # %bb.0: # %entry 4010; P9BE-NEXT: lxv v2, 0(r3) 4011; P9BE-NEXT: blr 4012; 4013; P9LE-LABEL: fromDiffMemConsAll: 4014; P9LE: # %bb.0: # %entry 4015; P9LE-NEXT: lxv v2, 0(r3) 4016; P9LE-NEXT: blr 4017; 4018; P8BE-LABEL: fromDiffMemConsAll: 4019; P8BE: # %bb.0: # %entry 4020; P8BE-NEXT: lxvd2x v2, 0, r3 4021; P8BE-NEXT: blr 4022; 4023; P8LE-LABEL: fromDiffMemConsAll: 4024; P8LE: # %bb.0: # %entry 4025; P8LE-NEXT: lxvd2x vs0, 0, r3 4026; P8LE-NEXT: xxswapd v2, vs0 4027; P8LE-NEXT: blr 4028entry: 4029 %0 = load i64, i64* %arr, align 8 4030 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4031 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 1 4032 %1 = load i64, i64* %arrayidx1, align 8 4033 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4034 ret <2 x i64> %vecinit2 4035} 4036 4037; Function Attrs: norecurse nounwind readonly 4038define <2 x i64> @fromDiffMemConsDll(i64* nocapture readonly %arr) { 4039; P9BE-LABEL: fromDiffMemConsDll: 4040; P9BE: # %bb.0: # %entry 4041; P9BE-NEXT: lxv v2, 16(r3) 4042; P9BE-NEXT: xxswapd v2, v2 4043; P9BE-NEXT: blr 4044; 4045; P9LE-LABEL: fromDiffMemConsDll: 4046; P9LE: # %bb.0: # %entry 4047; P9LE-NEXT: addi r3, r3, 16 4048; P9LE-NEXT: lxvd2x v2, 0, r3 4049; P9LE-NEXT: blr 4050; 4051; P8BE-LABEL: fromDiffMemConsDll: 4052; P8BE: # %bb.0: # %entry 4053; P8BE-NEXT: addi r3, r3, 16 4054; P8BE-NEXT: lxvd2x v2, 0, r3 4055; P8BE-NEXT: xxswapd v2, v2 4056; P8BE-NEXT: blr 4057; 4058; P8LE-LABEL: fromDiffMemConsDll: 4059; P8LE: # %bb.0: # %entry 4060; P8LE-NEXT: addi r3, r3, 16 4061; P8LE-NEXT: lxvd2x v2, 0, r3 4062; P8LE-NEXT: blr 4063entry: 4064 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 3 4065 %0 = load i64, i64* %arrayidx, align 8 4066 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4067 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 2 4068 %1 = load i64, i64* %arrayidx1, align 8 4069 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4070 ret <2 x i64> %vecinit2 4071} 4072 4073; Function Attrs: norecurse nounwind readonly 4074define <2 x i64> @fromDiffMemVarAll(i64* nocapture readonly %arr, i32 signext %elem) { 4075; P9BE-LABEL: fromDiffMemVarAll: 4076; P9BE: # %bb.0: # %entry 4077; P9BE-NEXT: sldi r4, r4, 3 4078; P9BE-NEXT: lxvx v2, r3, r4 4079; P9BE-NEXT: blr 4080; 4081; P9LE-LABEL: fromDiffMemVarAll: 4082; P9LE: # %bb.0: # %entry 4083; P9LE-NEXT: sldi r4, r4, 3 4084; P9LE-NEXT: lxvx v2, r3, r4 4085; P9LE-NEXT: blr 4086; 4087; P8BE-LABEL: fromDiffMemVarAll: 4088; P8BE: # %bb.0: # %entry 4089; P8BE-NEXT: sldi r4, r4, 3 4090; P8BE-NEXT: lxvd2x v2, r3, r4 4091; P8BE-NEXT: blr 4092; 4093; P8LE-LABEL: fromDiffMemVarAll: 4094; P8LE: # %bb.0: # %entry 4095; P8LE-NEXT: sldi r4, r4, 3 4096; P8LE-NEXT: lxvd2x vs0, r3, r4 4097; P8LE-NEXT: xxswapd v2, vs0 4098; P8LE-NEXT: blr 4099entry: 4100 %idxprom = sext i32 %elem to i64 4101 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4102 %0 = load i64, i64* %arrayidx, align 8 4103 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4104 %add = add nsw i32 %elem, 1 4105 %idxprom1 = sext i32 %add to i64 4106 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 4107 %1 = load i64, i64* %arrayidx2, align 8 4108 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4109 ret <2 x i64> %vecinit3 4110} 4111 4112; Function Attrs: norecurse nounwind readonly 4113define <2 x i64> @fromDiffMemVarDll(i64* nocapture readonly %arr, i32 signext %elem) { 4114; P9BE-LABEL: fromDiffMemVarDll: 4115; P9BE: # %bb.0: # %entry 4116; P9BE-NEXT: sldi r4, r4, 3 4117; P9BE-NEXT: add r3, r3, r4 4118; P9BE-NEXT: li r4, -8 4119; P9BE-NEXT: lxvx v2, r3, r4 4120; P9BE-NEXT: xxswapd v2, v2 4121; P9BE-NEXT: blr 4122; 4123; P9LE-LABEL: fromDiffMemVarDll: 4124; P9LE: # %bb.0: # %entry 4125; P9LE-NEXT: sldi r4, r4, 3 4126; P9LE-NEXT: add r3, r3, r4 4127; P9LE-NEXT: addi r3, r3, -8 4128; P9LE-NEXT: lxvd2x v2, 0, r3 4129; P9LE-NEXT: blr 4130; 4131; P8BE-LABEL: fromDiffMemVarDll: 4132; P8BE: # %bb.0: # %entry 4133; P8BE-NEXT: sldi r4, r4, 3 4134; P8BE-NEXT: add r3, r3, r4 4135; P8BE-NEXT: addi r3, r3, -8 4136; P8BE-NEXT: lxvd2x v2, 0, r3 4137; P8BE-NEXT: xxswapd v2, v2 4138; P8BE-NEXT: blr 4139; 4140; P8LE-LABEL: fromDiffMemVarDll: 4141; P8LE: # %bb.0: # %entry 4142; P8LE-NEXT: sldi r4, r4, 3 4143; P8LE-NEXT: add r3, r3, r4 4144; P8LE-NEXT: addi r3, r3, -8 4145; P8LE-NEXT: lxvd2x v2, 0, r3 4146; P8LE-NEXT: blr 4147entry: 4148 %idxprom = sext i32 %elem to i64 4149 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4150 %0 = load i64, i64* %arrayidx, align 8 4151 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4152 %sub = add nsw i32 %elem, -1 4153 %idxprom1 = sext i32 %sub to i64 4154 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 4155 %1 = load i64, i64* %arrayidx2, align 8 4156 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4157 ret <2 x i64> %vecinit3 4158} 4159 4160; Function Attrs: norecurse nounwind readonly 4161define <2 x i64> @fromRandMemConsll(i64* nocapture readonly %arr) { 4162; P9BE-LABEL: fromRandMemConsll: 4163; P9BE: # %bb.0: # %entry 4164; P9BE-NEXT: ld r4, 32(r3) 4165; P9BE-NEXT: ld r3, 144(r3) 4166; P9BE-NEXT: mtvsrdd v2, r4, r3 4167; P9BE-NEXT: blr 4168; 4169; P9LE-LABEL: fromRandMemConsll: 4170; P9LE: # %bb.0: # %entry 4171; P9LE-NEXT: ld r4, 32(r3) 4172; P9LE-NEXT: ld r3, 144(r3) 4173; P9LE-NEXT: mtvsrdd v2, r3, r4 4174; P9LE-NEXT: blr 4175; 4176; P8BE-LABEL: fromRandMemConsll: 4177; P8BE: # %bb.0: # %entry 4178; P8BE-NEXT: ld r4, 144(r3) 4179; P8BE-NEXT: ld r3, 32(r3) 4180; P8BE-NEXT: mtvsrd f0, r4 4181; P8BE-NEXT: mtvsrd f1, r3 4182; P8BE-NEXT: xxmrghd v2, vs1, vs0 4183; P8BE-NEXT: blr 4184; 4185; P8LE-LABEL: fromRandMemConsll: 4186; P8LE: # %bb.0: # %entry 4187; P8LE-NEXT: ld r4, 32(r3) 4188; P8LE-NEXT: ld r3, 144(r3) 4189; P8LE-NEXT: mtvsrd f0, r4 4190; P8LE-NEXT: mtvsrd f1, r3 4191; P8LE-NEXT: xxmrghd v2, vs1, vs0 4192; P8LE-NEXT: blr 4193entry: 4194 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4 4195 %0 = load i64, i64* %arrayidx, align 8 4196 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4197 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18 4198 %1 = load i64, i64* %arrayidx1, align 8 4199 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4200 ret <2 x i64> %vecinit2 4201} 4202 4203; Function Attrs: norecurse nounwind readonly 4204define <2 x i64> @fromRandMemVarll(i64* nocapture readonly %arr, i32 signext %elem) { 4205; P9BE-LABEL: fromRandMemVarll: 4206; P9BE: # %bb.0: # %entry 4207; P9BE-NEXT: sldi r4, r4, 3 4208; P9BE-NEXT: add r3, r3, r4 4209; P9BE-NEXT: ld r4, 32(r3) 4210; P9BE-NEXT: ld r3, 8(r3) 4211; P9BE-NEXT: mtvsrdd v2, r4, r3 4212; P9BE-NEXT: blr 4213; 4214; P9LE-LABEL: fromRandMemVarll: 4215; P9LE: # %bb.0: # %entry 4216; P9LE-NEXT: sldi r4, r4, 3 4217; P9LE-NEXT: add r3, r3, r4 4218; P9LE-NEXT: ld r4, 32(r3) 4219; P9LE-NEXT: ld r3, 8(r3) 4220; P9LE-NEXT: mtvsrdd v2, r3, r4 4221; P9LE-NEXT: blr 4222; 4223; P8BE-LABEL: fromRandMemVarll: 4224; P8BE: # %bb.0: # %entry 4225; P8BE-NEXT: sldi r4, r4, 3 4226; P8BE-NEXT: add r3, r3, r4 4227; P8BE-NEXT: ld r4, 8(r3) 4228; P8BE-NEXT: ld r3, 32(r3) 4229; P8BE-NEXT: mtvsrd f0, r4 4230; P8BE-NEXT: mtvsrd f1, r3 4231; P8BE-NEXT: xxmrghd v2, vs1, vs0 4232; P8BE-NEXT: blr 4233; 4234; P8LE-LABEL: fromRandMemVarll: 4235; P8LE: # %bb.0: # %entry 4236; P8LE-NEXT: sldi r4, r4, 3 4237; P8LE-NEXT: add r3, r3, r4 4238; P8LE-NEXT: ld r4, 32(r3) 4239; P8LE-NEXT: ld r3, 8(r3) 4240; P8LE-NEXT: mtvsrd f0, r4 4241; P8LE-NEXT: mtvsrd f1, r3 4242; P8LE-NEXT: xxmrghd v2, vs1, vs0 4243; P8LE-NEXT: blr 4244entry: 4245 %add = add nsw i32 %elem, 4 4246 %idxprom = sext i32 %add to i64 4247 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4248 %0 = load i64, i64* %arrayidx, align 8 4249 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4250 %add1 = add nsw i32 %elem, 1 4251 %idxprom2 = sext i32 %add1 to i64 4252 %arrayidx3 = getelementptr inbounds i64, i64* %arr, i64 %idxprom2 4253 %1 = load i64, i64* %arrayidx3, align 8 4254 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4255 ret <2 x i64> %vecinit4 4256} 4257 4258; Function Attrs: norecurse nounwind readnone 4259define <2 x i64> @spltRegValll(i64 %val) { 4260; P9BE-LABEL: spltRegValll: 4261; P9BE: # %bb.0: # %entry 4262; P9BE-NEXT: mtvsrdd v2, r3, r3 4263; P9BE-NEXT: blr 4264; 4265; P9LE-LABEL: spltRegValll: 4266; P9LE: # %bb.0: # %entry 4267; P9LE-NEXT: mtvsrdd v2, r3, r3 4268; P9LE-NEXT: blr 4269; 4270; P8BE-LABEL: spltRegValll: 4271; P8BE: # %bb.0: # %entry 4272; P8BE-NEXT: mtvsrd f0, r3 4273; P8BE-NEXT: xxspltd v2, vs0, 0 4274; P8BE-NEXT: blr 4275; 4276; P8LE-LABEL: spltRegValll: 4277; P8LE: # %bb.0: # %entry 4278; P8LE-NEXT: mtvsrd f0, r3 4279; P8LE-NEXT: xxspltd v2, vs0, 0 4280; P8LE-NEXT: blr 4281entry: 4282 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0 4283 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4284 ret <2 x i64> %splat.splat 4285} 4286 4287; Function Attrs: norecurse nounwind readonly 4288define <2 x i64> @spltMemValll(i64* nocapture readonly %ptr) { 4289; P9BE-LABEL: spltMemValll: 4290; P9BE: # %bb.0: # %entry 4291; P9BE-NEXT: lxvdsx v2, 0, r3 4292; P9BE-NEXT: blr 4293; 4294; P9LE-LABEL: spltMemValll: 4295; P9LE: # %bb.0: # %entry 4296; P9LE-NEXT: lxvdsx v2, 0, r3 4297; P9LE-NEXT: blr 4298; 4299; P8BE-LABEL: spltMemValll: 4300; P8BE: # %bb.0: # %entry 4301; P8BE-NEXT: lxvdsx v2, 0, r3 4302; P8BE-NEXT: blr 4303; 4304; P8LE-LABEL: spltMemValll: 4305; P8LE: # %bb.0: # %entry 4306; P8LE-NEXT: lxvdsx v2, 0, r3 4307; P8LE-NEXT: blr 4308entry: 4309 %0 = load i64, i64* %ptr, align 8 4310 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 4311 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4312 ret <2 x i64> %splat.splat 4313} 4314 4315; Function Attrs: norecurse nounwind readnone 4316define <2 x i64> @spltCnstConvftoll() { 4317; P9BE-LABEL: spltCnstConvftoll: 4318; P9BE: # %bb.0: # %entry 4319; P9BE-NEXT: addis r3, r2, .LCPI78_0@toc@ha 4320; P9BE-NEXT: addi r3, r3, .LCPI78_0@toc@l 4321; P9BE-NEXT: lxvx v2, 0, r3 4322; P9BE-NEXT: blr 4323; 4324; P9LE-LABEL: spltCnstConvftoll: 4325; P9LE: # %bb.0: # %entry 4326; P9LE-NEXT: addis r3, r2, .LCPI78_0@toc@ha 4327; P9LE-NEXT: addi r3, r3, .LCPI78_0@toc@l 4328; P9LE-NEXT: lxvx v2, 0, r3 4329; P9LE-NEXT: blr 4330; 4331; P8BE-LABEL: spltCnstConvftoll: 4332; P8BE: # %bb.0: # %entry 4333; P8BE-NEXT: addis r3, r2, .LCPI78_0@toc@ha 4334; P8BE-NEXT: addi r3, r3, .LCPI78_0@toc@l 4335; P8BE-NEXT: lxvd2x v2, 0, r3 4336; P8BE-NEXT: blr 4337; 4338; P8LE-LABEL: spltCnstConvftoll: 4339; P8LE: # %bb.0: # %entry 4340; P8LE-NEXT: addis r3, r2, .LCPI78_0@toc@ha 4341; P8LE-NEXT: addi r3, r3, .LCPI78_0@toc@l 4342; P8LE-NEXT: lxvd2x vs0, 0, r3 4343; P8LE-NEXT: xxswapd v2, vs0 4344; P8LE-NEXT: blr 4345entry: 4346 ret <2 x i64> <i64 4, i64 4> 4347} 4348 4349; Function Attrs: norecurse nounwind readnone 4350define <2 x i64> @fromRegsConvftoll(float %a, float %b) { 4351; P9BE-LABEL: fromRegsConvftoll: 4352; P9BE: # %bb.0: # %entry 4353; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4354; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4355; P9BE-NEXT: xxmrghd vs0, vs1, vs2 4356; P9BE-NEXT: xvcvdpsxds v2, vs0 4357; P9BE-NEXT: blr 4358; 4359; P9LE-LABEL: fromRegsConvftoll: 4360; P9LE: # %bb.0: # %entry 4361; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4362; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4363; P9LE-NEXT: xxmrghd vs0, vs2, vs1 4364; P9LE-NEXT: xvcvdpsxds v2, vs0 4365; P9LE-NEXT: blr 4366; 4367; P8BE-LABEL: fromRegsConvftoll: 4368; P8BE: # %bb.0: # %entry 4369; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4370; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4371; P8BE-NEXT: xxmrghd vs0, vs1, vs2 4372; P8BE-NEXT: xvcvdpsxds v2, vs0 4373; P8BE-NEXT: blr 4374; 4375; P8LE-LABEL: fromRegsConvftoll: 4376; P8LE: # %bb.0: # %entry 4377; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4378; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4379; P8LE-NEXT: xxmrghd vs0, vs2, vs1 4380; P8LE-NEXT: xvcvdpsxds v2, vs0 4381; P8LE-NEXT: blr 4382entry: 4383 %conv = fptosi float %a to i64 4384 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4385 %conv1 = fptosi float %b to i64 4386 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 4387 ret <2 x i64> %vecinit2 4388} 4389 4390; Function Attrs: norecurse nounwind readnone 4391define <2 x i64> @fromDiffConstsConvftoll() { 4392; P9BE-LABEL: fromDiffConstsConvftoll: 4393; P9BE: # %bb.0: # %entry 4394; P9BE-NEXT: addis r3, r2, .LCPI80_0@toc@ha 4395; P9BE-NEXT: addi r3, r3, .LCPI80_0@toc@l 4396; P9BE-NEXT: lxvx v2, 0, r3 4397; P9BE-NEXT: blr 4398; 4399; P9LE-LABEL: fromDiffConstsConvftoll: 4400; P9LE: # %bb.0: # %entry 4401; P9LE-NEXT: addis r3, r2, .LCPI80_0@toc@ha 4402; P9LE-NEXT: addi r3, r3, .LCPI80_0@toc@l 4403; P9LE-NEXT: lxvx v2, 0, r3 4404; P9LE-NEXT: blr 4405; 4406; P8BE-LABEL: fromDiffConstsConvftoll: 4407; P8BE: # %bb.0: # %entry 4408; P8BE-NEXT: addis r3, r2, .LCPI80_0@toc@ha 4409; P8BE-NEXT: addi r3, r3, .LCPI80_0@toc@l 4410; P8BE-NEXT: lxvd2x v2, 0, r3 4411; P8BE-NEXT: blr 4412; 4413; P8LE-LABEL: fromDiffConstsConvftoll: 4414; P8LE: # %bb.0: # %entry 4415; P8LE-NEXT: addis r3, r2, .LCPI80_0@toc@ha 4416; P8LE-NEXT: addi r3, r3, .LCPI80_0@toc@l 4417; P8LE-NEXT: lxvd2x vs0, 0, r3 4418; P8LE-NEXT: xxswapd v2, vs0 4419; P8LE-NEXT: blr 4420entry: 4421 ret <2 x i64> <i64 24, i64 234> 4422} 4423 4424; Function Attrs: norecurse nounwind readonly 4425define <2 x i64> @fromDiffMemConsAConvftoll(float* nocapture readonly %ptr) { 4426; P9BE-LABEL: fromDiffMemConsAConvftoll: 4427; P9BE: # %bb.0: # %entry 4428; P9BE-NEXT: lfs f0, 0(r3) 4429; P9BE-NEXT: lfs f1, 4(r3) 4430; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4431; P9BE-NEXT: xvcvdpsxds v2, vs0 4432; P9BE-NEXT: blr 4433; 4434; P9LE-LABEL: fromDiffMemConsAConvftoll: 4435; P9LE: # %bb.0: # %entry 4436; P9LE-NEXT: lfs f0, 0(r3) 4437; P9LE-NEXT: lfs f1, 4(r3) 4438; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4439; P9LE-NEXT: xvcvdpsxds v2, vs0 4440; P9LE-NEXT: blr 4441; 4442; P8BE-LABEL: fromDiffMemConsAConvftoll: 4443; P8BE: # %bb.0: # %entry 4444; P8BE-NEXT: lfsx f0, 0, r3 4445; P8BE-NEXT: lfs f1, 4(r3) 4446; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4447; P8BE-NEXT: xvcvdpsxds v2, vs0 4448; P8BE-NEXT: blr 4449; 4450; P8LE-LABEL: fromDiffMemConsAConvftoll: 4451; P8LE: # %bb.0: # %entry 4452; P8LE-NEXT: lfsx f0, 0, r3 4453; P8LE-NEXT: lfs f1, 4(r3) 4454; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4455; P8LE-NEXT: xvcvdpsxds v2, vs0 4456; P8LE-NEXT: blr 4457entry: 4458 %0 = load float, float* %ptr, align 4 4459 %conv = fptosi float %0 to i64 4460 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4461 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1 4462 %1 = load float, float* %arrayidx1, align 4 4463 %conv2 = fptosi float %1 to i64 4464 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4465 ret <2 x i64> %vecinit3 4466} 4467 4468; Function Attrs: norecurse nounwind readonly 4469define <2 x i64> @fromDiffMemConsDConvftoll(float* nocapture readonly %ptr) { 4470; P9BE-LABEL: fromDiffMemConsDConvftoll: 4471; P9BE: # %bb.0: # %entry 4472; P9BE-NEXT: lfs f0, 12(r3) 4473; P9BE-NEXT: lfs f1, 8(r3) 4474; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4475; P9BE-NEXT: xvcvdpsxds v2, vs0 4476; P9BE-NEXT: blr 4477; 4478; P9LE-LABEL: fromDiffMemConsDConvftoll: 4479; P9LE: # %bb.0: # %entry 4480; P9LE-NEXT: lfs f0, 12(r3) 4481; P9LE-NEXT: lfs f1, 8(r3) 4482; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4483; P9LE-NEXT: xvcvdpsxds v2, vs0 4484; P9LE-NEXT: blr 4485; 4486; P8BE-LABEL: fromDiffMemConsDConvftoll: 4487; P8BE: # %bb.0: # %entry 4488; P8BE-NEXT: lfs f0, 12(r3) 4489; P8BE-NEXT: lfs f1, 8(r3) 4490; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4491; P8BE-NEXT: xvcvdpsxds v2, vs0 4492; P8BE-NEXT: blr 4493; 4494; P8LE-LABEL: fromDiffMemConsDConvftoll: 4495; P8LE: # %bb.0: # %entry 4496; P8LE-NEXT: lfs f0, 12(r3) 4497; P8LE-NEXT: lfs f1, 8(r3) 4498; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4499; P8LE-NEXT: xvcvdpsxds v2, vs0 4500; P8LE-NEXT: blr 4501entry: 4502 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 4503 %0 = load float, float* %arrayidx, align 4 4504 %conv = fptosi float %0 to i64 4505 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4506 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 4507 %1 = load float, float* %arrayidx1, align 4 4508 %conv2 = fptosi float %1 to i64 4509 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4510 ret <2 x i64> %vecinit3 4511} 4512 4513; Function Attrs: norecurse nounwind readonly 4514define <2 x i64> @fromDiffMemVarAConvftoll(float* nocapture readonly %arr, i32 signext %elem) { 4515; P9BE-LABEL: fromDiffMemVarAConvftoll: 4516; P9BE: # %bb.0: # %entry 4517; P9BE-NEXT: sldi r4, r4, 2 4518; P9BE-NEXT: lfsux f0, r3, r4 4519; P9BE-NEXT: lfs f1, 4(r3) 4520; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4521; P9BE-NEXT: xvcvdpsxds v2, vs0 4522; P9BE-NEXT: blr 4523; 4524; P9LE-LABEL: fromDiffMemVarAConvftoll: 4525; P9LE: # %bb.0: # %entry 4526; P9LE-NEXT: sldi r4, r4, 2 4527; P9LE-NEXT: lfsux f0, r3, r4 4528; P9LE-NEXT: lfs f1, 4(r3) 4529; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4530; P9LE-NEXT: xvcvdpsxds v2, vs0 4531; P9LE-NEXT: blr 4532; 4533; P8BE-LABEL: fromDiffMemVarAConvftoll: 4534; P8BE: # %bb.0: # %entry 4535; P8BE-NEXT: sldi r4, r4, 2 4536; P8BE-NEXT: lfsux f0, r3, r4 4537; P8BE-NEXT: lfs f1, 4(r3) 4538; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4539; P8BE-NEXT: xvcvdpsxds v2, vs0 4540; P8BE-NEXT: blr 4541; 4542; P8LE-LABEL: fromDiffMemVarAConvftoll: 4543; P8LE: # %bb.0: # %entry 4544; P8LE-NEXT: sldi r4, r4, 2 4545; P8LE-NEXT: lfsux f0, r3, r4 4546; P8LE-NEXT: lfs f1, 4(r3) 4547; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4548; P8LE-NEXT: xvcvdpsxds v2, vs0 4549; P8LE-NEXT: blr 4550entry: 4551 %idxprom = sext i32 %elem to i64 4552 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 4553 %0 = load float, float* %arrayidx, align 4 4554 %conv = fptosi float %0 to i64 4555 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4556 %add = add nsw i32 %elem, 1 4557 %idxprom1 = sext i32 %add to i64 4558 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 4559 %1 = load float, float* %arrayidx2, align 4 4560 %conv3 = fptosi float %1 to i64 4561 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4562 ret <2 x i64> %vecinit4 4563} 4564 4565; Function Attrs: norecurse nounwind readonly 4566define <2 x i64> @fromDiffMemVarDConvftoll(float* nocapture readonly %arr, i32 signext %elem) { 4567; P9BE-LABEL: fromDiffMemVarDConvftoll: 4568; P9BE: # %bb.0: # %entry 4569; P9BE-NEXT: sldi r4, r4, 2 4570; P9BE-NEXT: lfsux f0, r3, r4 4571; P9BE-NEXT: lfs f1, -4(r3) 4572; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4573; P9BE-NEXT: xvcvdpsxds v2, vs0 4574; P9BE-NEXT: blr 4575; 4576; P9LE-LABEL: fromDiffMemVarDConvftoll: 4577; P9LE: # %bb.0: # %entry 4578; P9LE-NEXT: sldi r4, r4, 2 4579; P9LE-NEXT: lfsux f0, r3, r4 4580; P9LE-NEXT: lfs f1, -4(r3) 4581; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4582; P9LE-NEXT: xvcvdpsxds v2, vs0 4583; P9LE-NEXT: blr 4584; 4585; P8BE-LABEL: fromDiffMemVarDConvftoll: 4586; P8BE: # %bb.0: # %entry 4587; P8BE-NEXT: sldi r4, r4, 2 4588; P8BE-NEXT: lfsux f0, r3, r4 4589; P8BE-NEXT: lfs f1, -4(r3) 4590; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4591; P8BE-NEXT: xvcvdpsxds v2, vs0 4592; P8BE-NEXT: blr 4593; 4594; P8LE-LABEL: fromDiffMemVarDConvftoll: 4595; P8LE: # %bb.0: # %entry 4596; P8LE-NEXT: sldi r4, r4, 2 4597; P8LE-NEXT: lfsux f0, r3, r4 4598; P8LE-NEXT: lfs f1, -4(r3) 4599; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4600; P8LE-NEXT: xvcvdpsxds v2, vs0 4601; P8LE-NEXT: blr 4602entry: 4603 %idxprom = sext i32 %elem to i64 4604 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 4605 %0 = load float, float* %arrayidx, align 4 4606 %conv = fptosi float %0 to i64 4607 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4608 %sub = add nsw i32 %elem, -1 4609 %idxprom1 = sext i32 %sub to i64 4610 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 4611 %1 = load float, float* %arrayidx2, align 4 4612 %conv3 = fptosi float %1 to i64 4613 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4614 ret <2 x i64> %vecinit4 4615} 4616 4617; Function Attrs: norecurse nounwind readnone 4618define <2 x i64> @spltRegValConvftoll(float %val) { 4619; P9BE-LABEL: spltRegValConvftoll: 4620; P9BE: # %bb.0: # %entry 4621; P9BE-NEXT: xscvdpsxds f0, f1 4622; P9BE-NEXT: xxspltd v2, f0, 0 4623; P9BE-NEXT: blr 4624; 4625; P9LE-LABEL: spltRegValConvftoll: 4626; P9LE: # %bb.0: # %entry 4627; P9LE-NEXT: xscvdpsxds f0, f1 4628; P9LE-NEXT: xxspltd v2, f0, 0 4629; P9LE-NEXT: blr 4630; 4631; P8BE-LABEL: spltRegValConvftoll: 4632; P8BE: # %bb.0: # %entry 4633; P8BE-NEXT: xscvdpsxds f0, f1 4634; P8BE-NEXT: xxspltd v2, f0, 0 4635; P8BE-NEXT: blr 4636; 4637; P8LE-LABEL: spltRegValConvftoll: 4638; P8LE: # %bb.0: # %entry 4639; P8LE-NEXT: xscvdpsxds f0, f1 4640; P8LE-NEXT: xxspltd v2, f0, 0 4641; P8LE-NEXT: blr 4642entry: 4643 %conv = fptosi float %val to i64 4644 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4645 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4646 ret <2 x i64> %splat.splat 4647} 4648 4649; Function Attrs: norecurse nounwind readonly 4650define <2 x i64> @spltMemValConvftoll(float* nocapture readonly %ptr) { 4651; P9BE-LABEL: spltMemValConvftoll: 4652; P9BE: # %bb.0: # %entry 4653; P9BE-NEXT: lfs f0, 0(r3) 4654; P9BE-NEXT: xscvdpsxds f0, f0 4655; P9BE-NEXT: xxspltd v2, f0, 0 4656; P9BE-NEXT: blr 4657; 4658; P9LE-LABEL: spltMemValConvftoll: 4659; P9LE: # %bb.0: # %entry 4660; P9LE-NEXT: lfs f0, 0(r3) 4661; P9LE-NEXT: xscvdpsxds f0, f0 4662; P9LE-NEXT: xxspltd v2, f0, 0 4663; P9LE-NEXT: blr 4664; 4665; P8BE-LABEL: spltMemValConvftoll: 4666; P8BE: # %bb.0: # %entry 4667; P8BE-NEXT: lfsx f0, 0, r3 4668; P8BE-NEXT: xscvdpsxds f0, f0 4669; P8BE-NEXT: xxspltd v2, f0, 0 4670; P8BE-NEXT: blr 4671; 4672; P8LE-LABEL: spltMemValConvftoll: 4673; P8LE: # %bb.0: # %entry 4674; P8LE-NEXT: lfsx f0, 0, r3 4675; P8LE-NEXT: xscvdpsxds f0, f0 4676; P8LE-NEXT: xxspltd v2, f0, 0 4677; P8LE-NEXT: blr 4678entry: 4679 %0 = load float, float* %ptr, align 4 4680 %conv = fptosi float %0 to i64 4681 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4682 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4683 ret <2 x i64> %splat.splat 4684} 4685 4686; Function Attrs: norecurse nounwind readnone 4687define <2 x i64> @spltCnstConvdtoll() { 4688; P9BE-LABEL: spltCnstConvdtoll: 4689; P9BE: # %bb.0: # %entry 4690; P9BE-NEXT: addis r3, r2, .LCPI87_0@toc@ha 4691; P9BE-NEXT: addi r3, r3, .LCPI87_0@toc@l 4692; P9BE-NEXT: lxvx v2, 0, r3 4693; P9BE-NEXT: blr 4694; 4695; P9LE-LABEL: spltCnstConvdtoll: 4696; P9LE: # %bb.0: # %entry 4697; P9LE-NEXT: addis r3, r2, .LCPI87_0@toc@ha 4698; P9LE-NEXT: addi r3, r3, .LCPI87_0@toc@l 4699; P9LE-NEXT: lxvx v2, 0, r3 4700; P9LE-NEXT: blr 4701; 4702; P8BE-LABEL: spltCnstConvdtoll: 4703; P8BE: # %bb.0: # %entry 4704; P8BE-NEXT: addis r3, r2, .LCPI87_0@toc@ha 4705; P8BE-NEXT: addi r3, r3, .LCPI87_0@toc@l 4706; P8BE-NEXT: lxvd2x v2, 0, r3 4707; P8BE-NEXT: blr 4708; 4709; P8LE-LABEL: spltCnstConvdtoll: 4710; P8LE: # %bb.0: # %entry 4711; P8LE-NEXT: addis r3, r2, .LCPI87_0@toc@ha 4712; P8LE-NEXT: addi r3, r3, .LCPI87_0@toc@l 4713; P8LE-NEXT: lxvd2x vs0, 0, r3 4714; P8LE-NEXT: xxswapd v2, vs0 4715; P8LE-NEXT: blr 4716entry: 4717 ret <2 x i64> <i64 4, i64 4> 4718} 4719 4720; Function Attrs: norecurse nounwind readnone 4721define <2 x i64> @fromRegsConvdtoll(double %a, double %b) { 4722; P9BE-LABEL: fromRegsConvdtoll: 4723; P9BE: # %bb.0: # %entry 4724; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4725; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4726; P9BE-NEXT: xxmrghd vs0, vs1, vs2 4727; P9BE-NEXT: xvcvdpsxds v2, vs0 4728; P9BE-NEXT: blr 4729; 4730; P9LE-LABEL: fromRegsConvdtoll: 4731; P9LE: # %bb.0: # %entry 4732; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4733; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4734; P9LE-NEXT: xxmrghd vs0, vs2, vs1 4735; P9LE-NEXT: xvcvdpsxds v2, vs0 4736; P9LE-NEXT: blr 4737; 4738; P8BE-LABEL: fromRegsConvdtoll: 4739; P8BE: # %bb.0: # %entry 4740; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4741; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4742; P8BE-NEXT: xxmrghd vs0, vs1, vs2 4743; P8BE-NEXT: xvcvdpsxds v2, vs0 4744; P8BE-NEXT: blr 4745; 4746; P8LE-LABEL: fromRegsConvdtoll: 4747; P8LE: # %bb.0: # %entry 4748; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4749; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4750; P8LE-NEXT: xxmrghd vs0, vs2, vs1 4751; P8LE-NEXT: xvcvdpsxds v2, vs0 4752; P8LE-NEXT: blr 4753entry: 4754 %conv = fptosi double %a to i64 4755 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4756 %conv1 = fptosi double %b to i64 4757 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 4758 ret <2 x i64> %vecinit2 4759} 4760 4761; Function Attrs: norecurse nounwind readnone 4762define <2 x i64> @fromDiffConstsConvdtoll() { 4763; P9BE-LABEL: fromDiffConstsConvdtoll: 4764; P9BE: # %bb.0: # %entry 4765; P9BE-NEXT: addis r3, r2, .LCPI89_0@toc@ha 4766; P9BE-NEXT: addi r3, r3, .LCPI89_0@toc@l 4767; P9BE-NEXT: lxvx v2, 0, r3 4768; P9BE-NEXT: blr 4769; 4770; P9LE-LABEL: fromDiffConstsConvdtoll: 4771; P9LE: # %bb.0: # %entry 4772; P9LE-NEXT: addis r3, r2, .LCPI89_0@toc@ha 4773; P9LE-NEXT: addi r3, r3, .LCPI89_0@toc@l 4774; P9LE-NEXT: lxvx v2, 0, r3 4775; P9LE-NEXT: blr 4776; 4777; P8BE-LABEL: fromDiffConstsConvdtoll: 4778; P8BE: # %bb.0: # %entry 4779; P8BE-NEXT: addis r3, r2, .LCPI89_0@toc@ha 4780; P8BE-NEXT: addi r3, r3, .LCPI89_0@toc@l 4781; P8BE-NEXT: lxvd2x v2, 0, r3 4782; P8BE-NEXT: blr 4783; 4784; P8LE-LABEL: fromDiffConstsConvdtoll: 4785; P8LE: # %bb.0: # %entry 4786; P8LE-NEXT: addis r3, r2, .LCPI89_0@toc@ha 4787; P8LE-NEXT: addi r3, r3, .LCPI89_0@toc@l 4788; P8LE-NEXT: lxvd2x vs0, 0, r3 4789; P8LE-NEXT: xxswapd v2, vs0 4790; P8LE-NEXT: blr 4791entry: 4792 ret <2 x i64> <i64 24, i64 234> 4793} 4794 4795; Function Attrs: norecurse nounwind readonly 4796define <2 x i64> @fromDiffMemConsAConvdtoll(double* nocapture readonly %ptr) { 4797; P9BE-LABEL: fromDiffMemConsAConvdtoll: 4798; P9BE: # %bb.0: # %entry 4799; P9BE-NEXT: lxv vs0, 0(r3) 4800; P9BE-NEXT: xvcvdpsxds v2, vs0 4801; P9BE-NEXT: blr 4802; 4803; P9LE-LABEL: fromDiffMemConsAConvdtoll: 4804; P9LE: # %bb.0: # %entry 4805; P9LE-NEXT: lxv vs0, 0(r3) 4806; P9LE-NEXT: xvcvdpsxds v2, vs0 4807; P9LE-NEXT: blr 4808; 4809; P8BE-LABEL: fromDiffMemConsAConvdtoll: 4810; P8BE: # %bb.0: # %entry 4811; P8BE-NEXT: lxvd2x vs0, 0, r3 4812; P8BE-NEXT: xvcvdpsxds v2, vs0 4813; P8BE-NEXT: blr 4814; 4815; P8LE-LABEL: fromDiffMemConsAConvdtoll: 4816; P8LE: # %bb.0: # %entry 4817; P8LE-NEXT: lxvd2x vs0, 0, r3 4818; P8LE-NEXT: xxswapd vs0, vs0 4819; P8LE-NEXT: xvcvdpsxds v2, vs0 4820; P8LE-NEXT: blr 4821entry: 4822 %0 = bitcast double* %ptr to <2 x double>* 4823 %1 = load <2 x double>, <2 x double>* %0, align 8 4824 %2 = fptosi <2 x double> %1 to <2 x i64> 4825 ret <2 x i64> %2 4826} 4827 4828; Function Attrs: norecurse nounwind readonly 4829define <2 x i64> @fromDiffMemConsDConvdtoll(double* nocapture readonly %ptr) { 4830; P9BE-LABEL: fromDiffMemConsDConvdtoll: 4831; P9BE: # %bb.0: # %entry 4832; P9BE-NEXT: lxv vs0, 16(r3) 4833; P9BE-NEXT: xxswapd vs0, vs0 4834; P9BE-NEXT: xvcvdpsxds v2, vs0 4835; P9BE-NEXT: blr 4836; 4837; P9LE-LABEL: fromDiffMemConsDConvdtoll: 4838; P9LE: # %bb.0: # %entry 4839; P9LE-NEXT: addi r3, r3, 16 4840; P9LE-NEXT: lxvd2x vs0, 0, r3 4841; P9LE-NEXT: xvcvdpsxds v2, vs0 4842; P9LE-NEXT: blr 4843; 4844; P8BE-LABEL: fromDiffMemConsDConvdtoll: 4845; P8BE: # %bb.0: # %entry 4846; P8BE-NEXT: addi r3, r3, 16 4847; P8BE-NEXT: lxvd2x vs0, 0, r3 4848; P8BE-NEXT: xxswapd vs0, vs0 4849; P8BE-NEXT: xvcvdpsxds v2, vs0 4850; P8BE-NEXT: blr 4851; 4852; P8LE-LABEL: fromDiffMemConsDConvdtoll: 4853; P8LE: # %bb.0: # %entry 4854; P8LE-NEXT: addi r3, r3, 16 4855; P8LE-NEXT: lxvd2x vs0, 0, r3 4856; P8LE-NEXT: xvcvdpsxds v2, vs0 4857; P8LE-NEXT: blr 4858entry: 4859 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 4860 %0 = load double, double* %arrayidx, align 8 4861 %conv = fptosi double %0 to i64 4862 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4863 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 4864 %1 = load double, double* %arrayidx1, align 8 4865 %conv2 = fptosi double %1 to i64 4866 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4867 ret <2 x i64> %vecinit3 4868} 4869 4870; Function Attrs: norecurse nounwind readonly 4871define <2 x i64> @fromDiffMemVarAConvdtoll(double* nocapture readonly %arr, i32 signext %elem) { 4872; P9BE-LABEL: fromDiffMemVarAConvdtoll: 4873; P9BE: # %bb.0: # %entry 4874; P9BE-NEXT: sldi r4, r4, 3 4875; P9BE-NEXT: lxvx vs0, r3, r4 4876; P9BE-NEXT: xvcvdpsxds v2, vs0 4877; P9BE-NEXT: blr 4878; 4879; P9LE-LABEL: fromDiffMemVarAConvdtoll: 4880; P9LE: # %bb.0: # %entry 4881; P9LE-NEXT: sldi r4, r4, 3 4882; P9LE-NEXT: lxvx vs0, r3, r4 4883; P9LE-NEXT: xvcvdpsxds v2, vs0 4884; P9LE-NEXT: blr 4885; 4886; P8BE-LABEL: fromDiffMemVarAConvdtoll: 4887; P8BE: # %bb.0: # %entry 4888; P8BE-NEXT: sldi r4, r4, 3 4889; P8BE-NEXT: lxvd2x vs0, r3, r4 4890; P8BE-NEXT: xvcvdpsxds v2, vs0 4891; P8BE-NEXT: blr 4892; 4893; P8LE-LABEL: fromDiffMemVarAConvdtoll: 4894; P8LE: # %bb.0: # %entry 4895; P8LE-NEXT: sldi r4, r4, 3 4896; P8LE-NEXT: lxvd2x vs0, r3, r4 4897; P8LE-NEXT: xxswapd vs0, vs0 4898; P8LE-NEXT: xvcvdpsxds v2, vs0 4899; P8LE-NEXT: blr 4900entry: 4901 %idxprom = sext i32 %elem to i64 4902 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 4903 %0 = load double, double* %arrayidx, align 8 4904 %conv = fptosi double %0 to i64 4905 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4906 %add = add nsw i32 %elem, 1 4907 %idxprom1 = sext i32 %add to i64 4908 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 4909 %1 = load double, double* %arrayidx2, align 8 4910 %conv3 = fptosi double %1 to i64 4911 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4912 ret <2 x i64> %vecinit4 4913} 4914 4915; Function Attrs: norecurse nounwind readonly 4916define <2 x i64> @fromDiffMemVarDConvdtoll(double* nocapture readonly %arr, i32 signext %elem) { 4917; P9BE-LABEL: fromDiffMemVarDConvdtoll: 4918; P9BE: # %bb.0: # %entry 4919; P9BE-NEXT: sldi r4, r4, 3 4920; P9BE-NEXT: add r3, r3, r4 4921; P9BE-NEXT: li r4, -8 4922; P9BE-NEXT: lxvx vs0, r3, r4 4923; P9BE-NEXT: xxswapd vs0, vs0 4924; P9BE-NEXT: xvcvdpsxds v2, vs0 4925; P9BE-NEXT: blr 4926; 4927; P9LE-LABEL: fromDiffMemVarDConvdtoll: 4928; P9LE: # %bb.0: # %entry 4929; P9LE-NEXT: sldi r4, r4, 3 4930; P9LE-NEXT: add r3, r3, r4 4931; P9LE-NEXT: addi r3, r3, -8 4932; P9LE-NEXT: lxvd2x vs0, 0, r3 4933; P9LE-NEXT: xvcvdpsxds v2, vs0 4934; P9LE-NEXT: blr 4935; 4936; P8BE-LABEL: fromDiffMemVarDConvdtoll: 4937; P8BE: # %bb.0: # %entry 4938; P8BE-NEXT: sldi r4, r4, 3 4939; P8BE-NEXT: add r3, r3, r4 4940; P8BE-NEXT: addi r3, r3, -8 4941; P8BE-NEXT: lxvd2x vs0, 0, r3 4942; P8BE-NEXT: xxswapd vs0, vs0 4943; P8BE-NEXT: xvcvdpsxds v2, vs0 4944; P8BE-NEXT: blr 4945; 4946; P8LE-LABEL: fromDiffMemVarDConvdtoll: 4947; P8LE: # %bb.0: # %entry 4948; P8LE-NEXT: sldi r4, r4, 3 4949; P8LE-NEXT: add r3, r3, r4 4950; P8LE-NEXT: addi r3, r3, -8 4951; P8LE-NEXT: lxvd2x vs0, 0, r3 4952; P8LE-NEXT: xvcvdpsxds v2, vs0 4953; P8LE-NEXT: blr 4954entry: 4955 %idxprom = sext i32 %elem to i64 4956 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 4957 %0 = load double, double* %arrayidx, align 8 4958 %conv = fptosi double %0 to i64 4959 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4960 %sub = add nsw i32 %elem, -1 4961 %idxprom1 = sext i32 %sub to i64 4962 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 4963 %1 = load double, double* %arrayidx2, align 8 4964 %conv3 = fptosi double %1 to i64 4965 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4966 ret <2 x i64> %vecinit4 4967} 4968 4969; Function Attrs: norecurse nounwind readnone 4970define <2 x i64> @spltRegValConvdtoll(double %val) { 4971; P9BE-LABEL: spltRegValConvdtoll: 4972; P9BE: # %bb.0: # %entry 4973; P9BE-NEXT: xscvdpsxds f0, f1 4974; P9BE-NEXT: xxspltd v2, vs0, 0 4975; P9BE-NEXT: blr 4976; 4977; P9LE-LABEL: spltRegValConvdtoll: 4978; P9LE: # %bb.0: # %entry 4979; P9LE-NEXT: xscvdpsxds f0, f1 4980; P9LE-NEXT: xxspltd v2, vs0, 0 4981; P9LE-NEXT: blr 4982; 4983; P8BE-LABEL: spltRegValConvdtoll: 4984; P8BE: # %bb.0: # %entry 4985; P8BE-NEXT: xscvdpsxds f0, f1 4986; P8BE-NEXT: xxspltd v2, vs0, 0 4987; P8BE-NEXT: blr 4988; 4989; P8LE-LABEL: spltRegValConvdtoll: 4990; P8LE: # %bb.0: # %entry 4991; P8LE-NEXT: xscvdpsxds f0, f1 4992; P8LE-NEXT: xxspltd v2, vs0, 0 4993; P8LE-NEXT: blr 4994entry: 4995 %conv = fptosi double %val to i64 4996 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4997 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4998 ret <2 x i64> %splat.splat 4999} 5000 5001; Function Attrs: norecurse nounwind readonly 5002define <2 x i64> @spltMemValConvdtoll(double* nocapture readonly %ptr) { 5003; P9BE-LABEL: spltMemValConvdtoll: 5004; P9BE: # %bb.0: # %entry 5005; P9BE-NEXT: lxvdsx vs0, 0, r3 5006; P9BE-NEXT: xvcvdpsxds v2, vs0 5007; P9BE-NEXT: blr 5008; 5009; P9LE-LABEL: spltMemValConvdtoll: 5010; P9LE: # %bb.0: # %entry 5011; P9LE-NEXT: lxvdsx vs0, 0, r3 5012; P9LE-NEXT: xvcvdpsxds v2, vs0 5013; P9LE-NEXT: blr 5014; 5015; P8BE-LABEL: spltMemValConvdtoll: 5016; P8BE: # %bb.0: # %entry 5017; P8BE-NEXT: lxvdsx vs0, 0, r3 5018; P8BE-NEXT: xvcvdpsxds v2, vs0 5019; P8BE-NEXT: blr 5020; 5021; P8LE-LABEL: spltMemValConvdtoll: 5022; P8LE: # %bb.0: # %entry 5023; P8LE-NEXT: lxvdsx vs0, 0, r3 5024; P8LE-NEXT: xvcvdpsxds v2, vs0 5025; P8LE-NEXT: blr 5026entry: 5027 %0 = load double, double* %ptr, align 8 5028 %conv = fptosi double %0 to i64 5029 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 5030 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5031 ret <2 x i64> %splat.splat 5032} 5033 5034; Function Attrs: norecurse nounwind readnone 5035define <2 x i64> @allZeroull() { 5036; P9BE-LABEL: allZeroull: 5037; P9BE: # %bb.0: # %entry 5038; P9BE-NEXT: xxlxor v2, v2, v2 5039; P9BE-NEXT: blr 5040; 5041; P9LE-LABEL: allZeroull: 5042; P9LE: # %bb.0: # %entry 5043; P9LE-NEXT: xxlxor v2, v2, v2 5044; P9LE-NEXT: blr 5045; 5046; P8BE-LABEL: allZeroull: 5047; P8BE: # %bb.0: # %entry 5048; P8BE-NEXT: xxlxor v2, v2, v2 5049; P8BE-NEXT: blr 5050; 5051; P8LE-LABEL: allZeroull: 5052; P8LE: # %bb.0: # %entry 5053; P8LE-NEXT: xxlxor v2, v2, v2 5054; P8LE-NEXT: blr 5055entry: 5056 ret <2 x i64> zeroinitializer 5057} 5058 5059; Function Attrs: norecurse nounwind readnone 5060define <2 x i64> @spltConst1ull() { 5061; P9BE-LABEL: spltConst1ull: 5062; P9BE: # %bb.0: # %entry 5063; P9BE-NEXT: addis r3, r2, .LCPI97_0@toc@ha 5064; P9BE-NEXT: addi r3, r3, .LCPI97_0@toc@l 5065; P9BE-NEXT: lxvx v2, 0, r3 5066; P9BE-NEXT: blr 5067; 5068; P9LE-LABEL: spltConst1ull: 5069; P9LE: # %bb.0: # %entry 5070; P9LE-NEXT: addis r3, r2, .LCPI97_0@toc@ha 5071; P9LE-NEXT: addi r3, r3, .LCPI97_0@toc@l 5072; P9LE-NEXT: lxvx v2, 0, r3 5073; P9LE-NEXT: blr 5074; 5075; P8BE-LABEL: spltConst1ull: 5076; P8BE: # %bb.0: # %entry 5077; P8BE-NEXT: addis r3, r2, .LCPI97_0@toc@ha 5078; P8BE-NEXT: addi r3, r3, .LCPI97_0@toc@l 5079; P8BE-NEXT: lxvd2x v2, 0, r3 5080; P8BE-NEXT: blr 5081; 5082; P8LE-LABEL: spltConst1ull: 5083; P8LE: # %bb.0: # %entry 5084; P8LE-NEXT: addis r3, r2, .LCPI97_0@toc@ha 5085; P8LE-NEXT: addi r3, r3, .LCPI97_0@toc@l 5086; P8LE-NEXT: lxvd2x vs0, 0, r3 5087; P8LE-NEXT: xxswapd v2, vs0 5088; P8LE-NEXT: blr 5089entry: 5090 ret <2 x i64> <i64 1, i64 1> 5091} 5092 5093; Function Attrs: norecurse nounwind readnone 5094define <2 x i64> @spltConst16kull() { 5095; P9BE-LABEL: spltConst16kull: 5096; P9BE: # %bb.0: # %entry 5097; P9BE-NEXT: addis r3, r2, .LCPI98_0@toc@ha 5098; P9BE-NEXT: addi r3, r3, .LCPI98_0@toc@l 5099; P9BE-NEXT: lxvx v2, 0, r3 5100; P9BE-NEXT: blr 5101; 5102; P9LE-LABEL: spltConst16kull: 5103; P9LE: # %bb.0: # %entry 5104; P9LE-NEXT: addis r3, r2, .LCPI98_0@toc@ha 5105; P9LE-NEXT: addi r3, r3, .LCPI98_0@toc@l 5106; P9LE-NEXT: lxvx v2, 0, r3 5107; P9LE-NEXT: blr 5108; 5109; P8BE-LABEL: spltConst16kull: 5110; P8BE: # %bb.0: # %entry 5111; P8BE-NEXT: addis r3, r2, .LCPI98_0@toc@ha 5112; P8BE-NEXT: addi r3, r3, .LCPI98_0@toc@l 5113; P8BE-NEXT: lxvd2x v2, 0, r3 5114; P8BE-NEXT: blr 5115; 5116; P8LE-LABEL: spltConst16kull: 5117; P8LE: # %bb.0: # %entry 5118; P8LE-NEXT: addis r3, r2, .LCPI98_0@toc@ha 5119; P8LE-NEXT: addi r3, r3, .LCPI98_0@toc@l 5120; P8LE-NEXT: lxvd2x vs0, 0, r3 5121; P8LE-NEXT: xxswapd v2, vs0 5122; P8LE-NEXT: blr 5123entry: 5124 ret <2 x i64> <i64 32767, i64 32767> 5125} 5126 5127; Function Attrs: norecurse nounwind readnone 5128define <2 x i64> @spltConst32kull() { 5129; P9BE-LABEL: spltConst32kull: 5130; P9BE: # %bb.0: # %entry 5131; P9BE-NEXT: addis r3, r2, .LCPI99_0@toc@ha 5132; P9BE-NEXT: addi r3, r3, .LCPI99_0@toc@l 5133; P9BE-NEXT: lxvx v2, 0, r3 5134; P9BE-NEXT: blr 5135; 5136; P9LE-LABEL: spltConst32kull: 5137; P9LE: # %bb.0: # %entry 5138; P9LE-NEXT: addis r3, r2, .LCPI99_0@toc@ha 5139; P9LE-NEXT: addi r3, r3, .LCPI99_0@toc@l 5140; P9LE-NEXT: lxvx v2, 0, r3 5141; P9LE-NEXT: blr 5142; 5143; P8BE-LABEL: spltConst32kull: 5144; P8BE: # %bb.0: # %entry 5145; P8BE-NEXT: addis r3, r2, .LCPI99_0@toc@ha 5146; P8BE-NEXT: addi r3, r3, .LCPI99_0@toc@l 5147; P8BE-NEXT: lxvd2x v2, 0, r3 5148; P8BE-NEXT: blr 5149; 5150; P8LE-LABEL: spltConst32kull: 5151; P8LE: # %bb.0: # %entry 5152; P8LE-NEXT: addis r3, r2, .LCPI99_0@toc@ha 5153; P8LE-NEXT: addi r3, r3, .LCPI99_0@toc@l 5154; P8LE-NEXT: lxvd2x vs0, 0, r3 5155; P8LE-NEXT: xxswapd v2, vs0 5156; P8LE-NEXT: blr 5157entry: 5158 ret <2 x i64> <i64 65535, i64 65535> 5159} 5160 5161; Function Attrs: norecurse nounwind readnone 5162define <2 x i64> @fromRegsull(i64 %a, i64 %b) { 5163; P9BE-LABEL: fromRegsull: 5164; P9BE: # %bb.0: # %entry 5165; P9BE-NEXT: mtvsrdd v2, r3, r4 5166; P9BE-NEXT: blr 5167; 5168; P9LE-LABEL: fromRegsull: 5169; P9LE: # %bb.0: # %entry 5170; P9LE-NEXT: mtvsrdd v2, r4, r3 5171; P9LE-NEXT: blr 5172; 5173; P8BE-LABEL: fromRegsull: 5174; P8BE: # %bb.0: # %entry 5175; P8BE-NEXT: mtvsrd f0, r4 5176; P8BE-NEXT: mtvsrd f1, r3 5177; P8BE-NEXT: xxmrghd v2, vs1, vs0 5178; P8BE-NEXT: blr 5179; 5180; P8LE-LABEL: fromRegsull: 5181; P8LE: # %bb.0: # %entry 5182; P8LE-NEXT: mtvsrd f0, r3 5183; P8LE-NEXT: mtvsrd f1, r4 5184; P8LE-NEXT: xxmrghd v2, vs1, vs0 5185; P8LE-NEXT: blr 5186entry: 5187 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 5188 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 5189 ret <2 x i64> %vecinit1 5190} 5191 5192; Function Attrs: norecurse nounwind readnone 5193define <2 x i64> @fromDiffConstsull() { 5194; P9BE-LABEL: fromDiffConstsull: 5195; P9BE: # %bb.0: # %entry 5196; P9BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5197; P9BE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5198; P9BE-NEXT: lxvx v2, 0, r3 5199; P9BE-NEXT: blr 5200; 5201; P9LE-LABEL: fromDiffConstsull: 5202; P9LE: # %bb.0: # %entry 5203; P9LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5204; P9LE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5205; P9LE-NEXT: lxvx v2, 0, r3 5206; P9LE-NEXT: blr 5207; 5208; P8BE-LABEL: fromDiffConstsull: 5209; P8BE: # %bb.0: # %entry 5210; P8BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5211; P8BE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5212; P8BE-NEXT: lxvd2x v2, 0, r3 5213; P8BE-NEXT: blr 5214; 5215; P8LE-LABEL: fromDiffConstsull: 5216; P8LE: # %bb.0: # %entry 5217; P8LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5218; P8LE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5219; P8LE-NEXT: lxvd2x vs0, 0, r3 5220; P8LE-NEXT: xxswapd v2, vs0 5221; P8LE-NEXT: blr 5222entry: 5223 ret <2 x i64> <i64 242, i64 -113> 5224} 5225 5226; Function Attrs: norecurse nounwind readonly 5227define <2 x i64> @fromDiffMemConsAull(i64* nocapture readonly %arr) { 5228; P9BE-LABEL: fromDiffMemConsAull: 5229; P9BE: # %bb.0: # %entry 5230; P9BE-NEXT: lxv v2, 0(r3) 5231; P9BE-NEXT: blr 5232; 5233; P9LE-LABEL: fromDiffMemConsAull: 5234; P9LE: # %bb.0: # %entry 5235; P9LE-NEXT: lxv v2, 0(r3) 5236; P9LE-NEXT: blr 5237; 5238; P8BE-LABEL: fromDiffMemConsAull: 5239; P8BE: # %bb.0: # %entry 5240; P8BE-NEXT: lxvd2x v2, 0, r3 5241; P8BE-NEXT: blr 5242; 5243; P8LE-LABEL: fromDiffMemConsAull: 5244; P8LE: # %bb.0: # %entry 5245; P8LE-NEXT: lxvd2x vs0, 0, r3 5246; P8LE-NEXT: xxswapd v2, vs0 5247; P8LE-NEXT: blr 5248entry: 5249 %0 = load i64, i64* %arr, align 8 5250 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5251 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 1 5252 %1 = load i64, i64* %arrayidx1, align 8 5253 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5254 ret <2 x i64> %vecinit2 5255} 5256 5257; Function Attrs: norecurse nounwind readonly 5258define <2 x i64> @fromDiffMemConsDull(i64* nocapture readonly %arr) { 5259; P9BE-LABEL: fromDiffMemConsDull: 5260; P9BE: # %bb.0: # %entry 5261; P9BE-NEXT: lxv v2, 16(r3) 5262; P9BE-NEXT: xxswapd v2, v2 5263; P9BE-NEXT: blr 5264; 5265; P9LE-LABEL: fromDiffMemConsDull: 5266; P9LE: # %bb.0: # %entry 5267; P9LE-NEXT: addi r3, r3, 16 5268; P9LE-NEXT: lxvd2x v2, 0, r3 5269; P9LE-NEXT: blr 5270; 5271; P8BE-LABEL: fromDiffMemConsDull: 5272; P8BE: # %bb.0: # %entry 5273; P8BE-NEXT: addi r3, r3, 16 5274; P8BE-NEXT: lxvd2x v2, 0, r3 5275; P8BE-NEXT: xxswapd v2, v2 5276; P8BE-NEXT: blr 5277; 5278; P8LE-LABEL: fromDiffMemConsDull: 5279; P8LE: # %bb.0: # %entry 5280; P8LE-NEXT: addi r3, r3, 16 5281; P8LE-NEXT: lxvd2x v2, 0, r3 5282; P8LE-NEXT: blr 5283entry: 5284 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 3 5285 %0 = load i64, i64* %arrayidx, align 8 5286 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5287 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 2 5288 %1 = load i64, i64* %arrayidx1, align 8 5289 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5290 ret <2 x i64> %vecinit2 5291} 5292 5293; Function Attrs: norecurse nounwind readonly 5294define <2 x i64> @fromDiffMemVarAull(i64* nocapture readonly %arr, i32 signext %elem) { 5295; P9BE-LABEL: fromDiffMemVarAull: 5296; P9BE: # %bb.0: # %entry 5297; P9BE-NEXT: sldi r4, r4, 3 5298; P9BE-NEXT: lxvx v2, r3, r4 5299; P9BE-NEXT: blr 5300; 5301; P9LE-LABEL: fromDiffMemVarAull: 5302; P9LE: # %bb.0: # %entry 5303; P9LE-NEXT: sldi r4, r4, 3 5304; P9LE-NEXT: lxvx v2, r3, r4 5305; P9LE-NEXT: blr 5306; 5307; P8BE-LABEL: fromDiffMemVarAull: 5308; P8BE: # %bb.0: # %entry 5309; P8BE-NEXT: sldi r4, r4, 3 5310; P8BE-NEXT: lxvd2x v2, r3, r4 5311; P8BE-NEXT: blr 5312; 5313; P8LE-LABEL: fromDiffMemVarAull: 5314; P8LE: # %bb.0: # %entry 5315; P8LE-NEXT: sldi r4, r4, 3 5316; P8LE-NEXT: lxvd2x vs0, r3, r4 5317; P8LE-NEXT: xxswapd v2, vs0 5318; P8LE-NEXT: blr 5319entry: 5320 %idxprom = sext i32 %elem to i64 5321 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 5322 %0 = load i64, i64* %arrayidx, align 8 5323 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5324 %add = add nsw i32 %elem, 1 5325 %idxprom1 = sext i32 %add to i64 5326 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 5327 %1 = load i64, i64* %arrayidx2, align 8 5328 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5329 ret <2 x i64> %vecinit3 5330} 5331 5332; Function Attrs: norecurse nounwind readonly 5333define <2 x i64> @fromDiffMemVarDull(i64* nocapture readonly %arr, i32 signext %elem) { 5334; P9BE-LABEL: fromDiffMemVarDull: 5335; P9BE: # %bb.0: # %entry 5336; P9BE-NEXT: sldi r4, r4, 3 5337; P9BE-NEXT: add r3, r3, r4 5338; P9BE-NEXT: li r4, -8 5339; P9BE-NEXT: lxvx v2, r3, r4 5340; P9BE-NEXT: xxswapd v2, v2 5341; P9BE-NEXT: blr 5342; 5343; P9LE-LABEL: fromDiffMemVarDull: 5344; P9LE: # %bb.0: # %entry 5345; P9LE-NEXT: sldi r4, r4, 3 5346; P9LE-NEXT: add r3, r3, r4 5347; P9LE-NEXT: addi r3, r3, -8 5348; P9LE-NEXT: lxvd2x v2, 0, r3 5349; P9LE-NEXT: blr 5350; 5351; P8BE-LABEL: fromDiffMemVarDull: 5352; P8BE: # %bb.0: # %entry 5353; P8BE-NEXT: sldi r4, r4, 3 5354; P8BE-NEXT: add r3, r3, r4 5355; P8BE-NEXT: addi r3, r3, -8 5356; P8BE-NEXT: lxvd2x v2, 0, r3 5357; P8BE-NEXT: xxswapd v2, v2 5358; P8BE-NEXT: blr 5359; 5360; P8LE-LABEL: fromDiffMemVarDull: 5361; P8LE: # %bb.0: # %entry 5362; P8LE-NEXT: sldi r4, r4, 3 5363; P8LE-NEXT: add r3, r3, r4 5364; P8LE-NEXT: addi r3, r3, -8 5365; P8LE-NEXT: lxvd2x v2, 0, r3 5366; P8LE-NEXT: blr 5367entry: 5368 %idxprom = sext i32 %elem to i64 5369 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 5370 %0 = load i64, i64* %arrayidx, align 8 5371 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5372 %sub = add nsw i32 %elem, -1 5373 %idxprom1 = sext i32 %sub to i64 5374 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 5375 %1 = load i64, i64* %arrayidx2, align 8 5376 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5377 ret <2 x i64> %vecinit3 5378} 5379 5380; Function Attrs: norecurse nounwind readonly 5381define <2 x i64> @fromRandMemConsull(i64* nocapture readonly %arr) { 5382; P9BE-LABEL: fromRandMemConsull: 5383; P9BE: # %bb.0: # %entry 5384; P9BE-NEXT: ld r4, 32(r3) 5385; P9BE-NEXT: ld r3, 144(r3) 5386; P9BE-NEXT: mtvsrdd v2, r4, r3 5387; P9BE-NEXT: blr 5388; 5389; P9LE-LABEL: fromRandMemConsull: 5390; P9LE: # %bb.0: # %entry 5391; P9LE-NEXT: ld r4, 32(r3) 5392; P9LE-NEXT: ld r3, 144(r3) 5393; P9LE-NEXT: mtvsrdd v2, r3, r4 5394; P9LE-NEXT: blr 5395; 5396; P8BE-LABEL: fromRandMemConsull: 5397; P8BE: # %bb.0: # %entry 5398; P8BE-NEXT: ld r4, 144(r3) 5399; P8BE-NEXT: ld r3, 32(r3) 5400; P8BE-NEXT: mtvsrd f0, r4 5401; P8BE-NEXT: mtvsrd f1, r3 5402; P8BE-NEXT: xxmrghd v2, vs1, vs0 5403; P8BE-NEXT: blr 5404; 5405; P8LE-LABEL: fromRandMemConsull: 5406; P8LE: # %bb.0: # %entry 5407; P8LE-NEXT: ld r4, 32(r3) 5408; P8LE-NEXT: ld r3, 144(r3) 5409; P8LE-NEXT: mtvsrd f0, r4 5410; P8LE-NEXT: mtvsrd f1, r3 5411; P8LE-NEXT: xxmrghd v2, vs1, vs0 5412; P8LE-NEXT: blr 5413entry: 5414 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4 5415 %0 = load i64, i64* %arrayidx, align 8 5416 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5417 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18 5418 %1 = load i64, i64* %arrayidx1, align 8 5419 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5420 ret <2 x i64> %vecinit2 5421} 5422 5423; Function Attrs: norecurse nounwind readonly 5424define <2 x i64> @fromRandMemVarull(i64* nocapture readonly %arr, i32 signext %elem) { 5425; P9BE-LABEL: fromRandMemVarull: 5426; P9BE: # %bb.0: # %entry 5427; P9BE-NEXT: sldi r4, r4, 3 5428; P9BE-NEXT: add r3, r3, r4 5429; P9BE-NEXT: ld r4, 32(r3) 5430; P9BE-NEXT: ld r3, 8(r3) 5431; P9BE-NEXT: mtvsrdd v2, r4, r3 5432; P9BE-NEXT: blr 5433; 5434; P9LE-LABEL: fromRandMemVarull: 5435; P9LE: # %bb.0: # %entry 5436; P9LE-NEXT: sldi r4, r4, 3 5437; P9LE-NEXT: add r3, r3, r4 5438; P9LE-NEXT: ld r4, 32(r3) 5439; P9LE-NEXT: ld r3, 8(r3) 5440; P9LE-NEXT: mtvsrdd v2, r3, r4 5441; P9LE-NEXT: blr 5442; 5443; P8BE-LABEL: fromRandMemVarull: 5444; P8BE: # %bb.0: # %entry 5445; P8BE-NEXT: sldi r4, r4, 3 5446; P8BE-NEXT: add r3, r3, r4 5447; P8BE-NEXT: ld r4, 8(r3) 5448; P8BE-NEXT: ld r3, 32(r3) 5449; P8BE-NEXT: mtvsrd f0, r4 5450; P8BE-NEXT: mtvsrd f1, r3 5451; P8BE-NEXT: xxmrghd v2, vs1, vs0 5452; P8BE-NEXT: blr 5453; 5454; P8LE-LABEL: fromRandMemVarull: 5455; P8LE: # %bb.0: # %entry 5456; P8LE-NEXT: sldi r4, r4, 3 5457; P8LE-NEXT: add r3, r3, r4 5458; P8LE-NEXT: ld r4, 32(r3) 5459; P8LE-NEXT: ld r3, 8(r3) 5460; P8LE-NEXT: mtvsrd f0, r4 5461; P8LE-NEXT: mtvsrd f1, r3 5462; P8LE-NEXT: xxmrghd v2, vs1, vs0 5463; P8LE-NEXT: blr 5464entry: 5465 %add = add nsw i32 %elem, 4 5466 %idxprom = sext i32 %add to i64 5467 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 5468 %0 = load i64, i64* %arrayidx, align 8 5469 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5470 %add1 = add nsw i32 %elem, 1 5471 %idxprom2 = sext i32 %add1 to i64 5472 %arrayidx3 = getelementptr inbounds i64, i64* %arr, i64 %idxprom2 5473 %1 = load i64, i64* %arrayidx3, align 8 5474 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5475 ret <2 x i64> %vecinit4 5476} 5477 5478; Function Attrs: norecurse nounwind readnone 5479define <2 x i64> @spltRegValull(i64 %val) { 5480; P9BE-LABEL: spltRegValull: 5481; P9BE: # %bb.0: # %entry 5482; P9BE-NEXT: mtvsrdd v2, r3, r3 5483; P9BE-NEXT: blr 5484; 5485; P9LE-LABEL: spltRegValull: 5486; P9LE: # %bb.0: # %entry 5487; P9LE-NEXT: mtvsrdd v2, r3, r3 5488; P9LE-NEXT: blr 5489; 5490; P8BE-LABEL: spltRegValull: 5491; P8BE: # %bb.0: # %entry 5492; P8BE-NEXT: mtvsrd f0, r3 5493; P8BE-NEXT: xxspltd v2, vs0, 0 5494; P8BE-NEXT: blr 5495; 5496; P8LE-LABEL: spltRegValull: 5497; P8LE: # %bb.0: # %entry 5498; P8LE-NEXT: mtvsrd f0, r3 5499; P8LE-NEXT: xxspltd v2, vs0, 0 5500; P8LE-NEXT: blr 5501entry: 5502 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0 5503 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5504 ret <2 x i64> %splat.splat 5505} 5506 5507; Function Attrs: norecurse nounwind readonly 5508define <2 x i64> @spltMemValull(i64* nocapture readonly %ptr) { 5509; P9BE-LABEL: spltMemValull: 5510; P9BE: # %bb.0: # %entry 5511; P9BE-NEXT: lxvdsx v2, 0, r3 5512; P9BE-NEXT: blr 5513; 5514; P9LE-LABEL: spltMemValull: 5515; P9LE: # %bb.0: # %entry 5516; P9LE-NEXT: lxvdsx v2, 0, r3 5517; P9LE-NEXT: blr 5518; 5519; P8BE-LABEL: spltMemValull: 5520; P8BE: # %bb.0: # %entry 5521; P8BE-NEXT: lxvdsx v2, 0, r3 5522; P8BE-NEXT: blr 5523; 5524; P8LE-LABEL: spltMemValull: 5525; P8LE: # %bb.0: # %entry 5526; P8LE-NEXT: lxvdsx v2, 0, r3 5527; P8LE-NEXT: blr 5528entry: 5529 %0 = load i64, i64* %ptr, align 8 5530 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 5531 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5532 ret <2 x i64> %splat.splat 5533} 5534 5535; Function Attrs: norecurse nounwind readnone 5536define <2 x i64> @spltCnstConvftoull() { 5537; P9BE-LABEL: spltCnstConvftoull: 5538; P9BE: # %bb.0: # %entry 5539; P9BE-NEXT: addis r3, r2, .LCPI110_0@toc@ha 5540; P9BE-NEXT: addi r3, r3, .LCPI110_0@toc@l 5541; P9BE-NEXT: lxvx v2, 0, r3 5542; P9BE-NEXT: blr 5543; 5544; P9LE-LABEL: spltCnstConvftoull: 5545; P9LE: # %bb.0: # %entry 5546; P9LE-NEXT: addis r3, r2, .LCPI110_0@toc@ha 5547; P9LE-NEXT: addi r3, r3, .LCPI110_0@toc@l 5548; P9LE-NEXT: lxvx v2, 0, r3 5549; P9LE-NEXT: blr 5550; 5551; P8BE-LABEL: spltCnstConvftoull: 5552; P8BE: # %bb.0: # %entry 5553; P8BE-NEXT: addis r3, r2, .LCPI110_0@toc@ha 5554; P8BE-NEXT: addi r3, r3, .LCPI110_0@toc@l 5555; P8BE-NEXT: lxvd2x v2, 0, r3 5556; P8BE-NEXT: blr 5557; 5558; P8LE-LABEL: spltCnstConvftoull: 5559; P8LE: # %bb.0: # %entry 5560; P8LE-NEXT: addis r3, r2, .LCPI110_0@toc@ha 5561; P8LE-NEXT: addi r3, r3, .LCPI110_0@toc@l 5562; P8LE-NEXT: lxvd2x vs0, 0, r3 5563; P8LE-NEXT: xxswapd v2, vs0 5564; P8LE-NEXT: blr 5565entry: 5566 ret <2 x i64> <i64 4, i64 4> 5567} 5568 5569; Function Attrs: norecurse nounwind readnone 5570define <2 x i64> @fromRegsConvftoull(float %a, float %b) { 5571; P9BE-LABEL: fromRegsConvftoull: 5572; P9BE: # %bb.0: # %entry 5573; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5574; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5575; P9BE-NEXT: xxmrghd vs0, vs1, vs2 5576; P9BE-NEXT: xvcvdpuxds v2, vs0 5577; P9BE-NEXT: blr 5578; 5579; P9LE-LABEL: fromRegsConvftoull: 5580; P9LE: # %bb.0: # %entry 5581; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5582; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5583; P9LE-NEXT: xxmrghd vs0, vs2, vs1 5584; P9LE-NEXT: xvcvdpuxds v2, vs0 5585; P9LE-NEXT: blr 5586; 5587; P8BE-LABEL: fromRegsConvftoull: 5588; P8BE: # %bb.0: # %entry 5589; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5590; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5591; P8BE-NEXT: xxmrghd vs0, vs1, vs2 5592; P8BE-NEXT: xvcvdpuxds v2, vs0 5593; P8BE-NEXT: blr 5594; 5595; P8LE-LABEL: fromRegsConvftoull: 5596; P8LE: # %bb.0: # %entry 5597; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5598; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5599; P8LE-NEXT: xxmrghd vs0, vs2, vs1 5600; P8LE-NEXT: xvcvdpuxds v2, vs0 5601; P8LE-NEXT: blr 5602entry: 5603 %conv = fptoui float %a to i64 5604 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5605 %conv1 = fptoui float %b to i64 5606 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 5607 ret <2 x i64> %vecinit2 5608} 5609 5610; Function Attrs: norecurse nounwind readnone 5611define <2 x i64> @fromDiffConstsConvftoull() { 5612; P9BE-LABEL: fromDiffConstsConvftoull: 5613; P9BE: # %bb.0: # %entry 5614; P9BE-NEXT: addis r3, r2, .LCPI112_0@toc@ha 5615; P9BE-NEXT: addi r3, r3, .LCPI112_0@toc@l 5616; P9BE-NEXT: lxvx v2, 0, r3 5617; P9BE-NEXT: blr 5618; 5619; P9LE-LABEL: fromDiffConstsConvftoull: 5620; P9LE: # %bb.0: # %entry 5621; P9LE-NEXT: addis r3, r2, .LCPI112_0@toc@ha 5622; P9LE-NEXT: addi r3, r3, .LCPI112_0@toc@l 5623; P9LE-NEXT: lxvx v2, 0, r3 5624; P9LE-NEXT: blr 5625; 5626; P8BE-LABEL: fromDiffConstsConvftoull: 5627; P8BE: # %bb.0: # %entry 5628; P8BE-NEXT: addis r3, r2, .LCPI112_0@toc@ha 5629; P8BE-NEXT: addi r3, r3, .LCPI112_0@toc@l 5630; P8BE-NEXT: lxvd2x v2, 0, r3 5631; P8BE-NEXT: blr 5632; 5633; P8LE-LABEL: fromDiffConstsConvftoull: 5634; P8LE: # %bb.0: # %entry 5635; P8LE-NEXT: addis r3, r2, .LCPI112_0@toc@ha 5636; P8LE-NEXT: addi r3, r3, .LCPI112_0@toc@l 5637; P8LE-NEXT: lxvd2x vs0, 0, r3 5638; P8LE-NEXT: xxswapd v2, vs0 5639; P8LE-NEXT: blr 5640entry: 5641 ret <2 x i64> <i64 24, i64 234> 5642} 5643 5644; Function Attrs: norecurse nounwind readonly 5645define <2 x i64> @fromDiffMemConsAConvftoull(float* nocapture readonly %ptr) { 5646; P9BE-LABEL: fromDiffMemConsAConvftoull: 5647; P9BE: # %bb.0: # %entry 5648; P9BE-NEXT: lfs f0, 0(r3) 5649; P9BE-NEXT: lfs f1, 4(r3) 5650; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5651; P9BE-NEXT: xvcvdpuxds v2, vs0 5652; P9BE-NEXT: blr 5653; 5654; P9LE-LABEL: fromDiffMemConsAConvftoull: 5655; P9LE: # %bb.0: # %entry 5656; P9LE-NEXT: lfs f0, 0(r3) 5657; P9LE-NEXT: lfs f1, 4(r3) 5658; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5659; P9LE-NEXT: xvcvdpuxds v2, vs0 5660; P9LE-NEXT: blr 5661; 5662; P8BE-LABEL: fromDiffMemConsAConvftoull: 5663; P8BE: # %bb.0: # %entry 5664; P8BE-NEXT: lfsx f0, 0, r3 5665; P8BE-NEXT: lfs f1, 4(r3) 5666; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5667; P8BE-NEXT: xvcvdpuxds v2, vs0 5668; P8BE-NEXT: blr 5669; 5670; P8LE-LABEL: fromDiffMemConsAConvftoull: 5671; P8LE: # %bb.0: # %entry 5672; P8LE-NEXT: lfsx f0, 0, r3 5673; P8LE-NEXT: lfs f1, 4(r3) 5674; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5675; P8LE-NEXT: xvcvdpuxds v2, vs0 5676; P8LE-NEXT: blr 5677entry: 5678 %0 = load float, float* %ptr, align 4 5679 %conv = fptoui float %0 to i64 5680 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5681 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1 5682 %1 = load float, float* %arrayidx1, align 4 5683 %conv2 = fptoui float %1 to i64 5684 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 5685 ret <2 x i64> %vecinit3 5686} 5687 5688; Function Attrs: norecurse nounwind readonly 5689define <2 x i64> @fromDiffMemConsDConvftoull(float* nocapture readonly %ptr) { 5690; P9BE-LABEL: fromDiffMemConsDConvftoull: 5691; P9BE: # %bb.0: # %entry 5692; P9BE-NEXT: lfs f0, 12(r3) 5693; P9BE-NEXT: lfs f1, 8(r3) 5694; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5695; P9BE-NEXT: xvcvdpuxds v2, vs0 5696; P9BE-NEXT: blr 5697; 5698; P9LE-LABEL: fromDiffMemConsDConvftoull: 5699; P9LE: # %bb.0: # %entry 5700; P9LE-NEXT: lfs f0, 12(r3) 5701; P9LE-NEXT: lfs f1, 8(r3) 5702; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5703; P9LE-NEXT: xvcvdpuxds v2, vs0 5704; P9LE-NEXT: blr 5705; 5706; P8BE-LABEL: fromDiffMemConsDConvftoull: 5707; P8BE: # %bb.0: # %entry 5708; P8BE-NEXT: lfs f0, 12(r3) 5709; P8BE-NEXT: lfs f1, 8(r3) 5710; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5711; P8BE-NEXT: xvcvdpuxds v2, vs0 5712; P8BE-NEXT: blr 5713; 5714; P8LE-LABEL: fromDiffMemConsDConvftoull: 5715; P8LE: # %bb.0: # %entry 5716; P8LE-NEXT: lfs f0, 12(r3) 5717; P8LE-NEXT: lfs f1, 8(r3) 5718; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5719; P8LE-NEXT: xvcvdpuxds v2, vs0 5720; P8LE-NEXT: blr 5721entry: 5722 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 5723 %0 = load float, float* %arrayidx, align 4 5724 %conv = fptoui float %0 to i64 5725 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5726 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 5727 %1 = load float, float* %arrayidx1, align 4 5728 %conv2 = fptoui float %1 to i64 5729 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 5730 ret <2 x i64> %vecinit3 5731} 5732 5733; Function Attrs: norecurse nounwind readonly 5734define <2 x i64> @fromDiffMemVarAConvftoull(float* nocapture readonly %arr, i32 signext %elem) { 5735; P9BE-LABEL: fromDiffMemVarAConvftoull: 5736; P9BE: # %bb.0: # %entry 5737; P9BE-NEXT: sldi r4, r4, 2 5738; P9BE-NEXT: lfsux f0, r3, r4 5739; P9BE-NEXT: lfs f1, 4(r3) 5740; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5741; P9BE-NEXT: xvcvdpuxds v2, vs0 5742; P9BE-NEXT: blr 5743; 5744; P9LE-LABEL: fromDiffMemVarAConvftoull: 5745; P9LE: # %bb.0: # %entry 5746; P9LE-NEXT: sldi r4, r4, 2 5747; P9LE-NEXT: lfsux f0, r3, r4 5748; P9LE-NEXT: lfs f1, 4(r3) 5749; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5750; P9LE-NEXT: xvcvdpuxds v2, vs0 5751; P9LE-NEXT: blr 5752; 5753; P8BE-LABEL: fromDiffMemVarAConvftoull: 5754; P8BE: # %bb.0: # %entry 5755; P8BE-NEXT: sldi r4, r4, 2 5756; P8BE-NEXT: lfsux f0, r3, r4 5757; P8BE-NEXT: lfs f1, 4(r3) 5758; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5759; P8BE-NEXT: xvcvdpuxds v2, vs0 5760; P8BE-NEXT: blr 5761; 5762; P8LE-LABEL: fromDiffMemVarAConvftoull: 5763; P8LE: # %bb.0: # %entry 5764; P8LE-NEXT: sldi r4, r4, 2 5765; P8LE-NEXT: lfsux f0, r3, r4 5766; P8LE-NEXT: lfs f1, 4(r3) 5767; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5768; P8LE-NEXT: xvcvdpuxds v2, vs0 5769; P8LE-NEXT: blr 5770entry: 5771 %idxprom = sext i32 %elem to i64 5772 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 5773 %0 = load float, float* %arrayidx, align 4 5774 %conv = fptoui float %0 to i64 5775 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5776 %add = add nsw i32 %elem, 1 5777 %idxprom1 = sext i32 %add to i64 5778 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 5779 %1 = load float, float* %arrayidx2, align 4 5780 %conv3 = fptoui float %1 to i64 5781 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 5782 ret <2 x i64> %vecinit4 5783} 5784 5785; Function Attrs: norecurse nounwind readonly 5786define <2 x i64> @fromDiffMemVarDConvftoull(float* nocapture readonly %arr, i32 signext %elem) { 5787; P9BE-LABEL: fromDiffMemVarDConvftoull: 5788; P9BE: # %bb.0: # %entry 5789; P9BE-NEXT: sldi r4, r4, 2 5790; P9BE-NEXT: lfsux f0, r3, r4 5791; P9BE-NEXT: lfs f1, -4(r3) 5792; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5793; P9BE-NEXT: xvcvdpuxds v2, vs0 5794; P9BE-NEXT: blr 5795; 5796; P9LE-LABEL: fromDiffMemVarDConvftoull: 5797; P9LE: # %bb.0: # %entry 5798; P9LE-NEXT: sldi r4, r4, 2 5799; P9LE-NEXT: lfsux f0, r3, r4 5800; P9LE-NEXT: lfs f1, -4(r3) 5801; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5802; P9LE-NEXT: xvcvdpuxds v2, vs0 5803; P9LE-NEXT: blr 5804; 5805; P8BE-LABEL: fromDiffMemVarDConvftoull: 5806; P8BE: # %bb.0: # %entry 5807; P8BE-NEXT: sldi r4, r4, 2 5808; P8BE-NEXT: lfsux f0, r3, r4 5809; P8BE-NEXT: lfs f1, -4(r3) 5810; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5811; P8BE-NEXT: xvcvdpuxds v2, vs0 5812; P8BE-NEXT: blr 5813; 5814; P8LE-LABEL: fromDiffMemVarDConvftoull: 5815; P8LE: # %bb.0: # %entry 5816; P8LE-NEXT: sldi r4, r4, 2 5817; P8LE-NEXT: lfsux f0, r3, r4 5818; P8LE-NEXT: lfs f1, -4(r3) 5819; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5820; P8LE-NEXT: xvcvdpuxds v2, vs0 5821; P8LE-NEXT: blr 5822entry: 5823 %idxprom = sext i32 %elem to i64 5824 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 5825 %0 = load float, float* %arrayidx, align 4 5826 %conv = fptoui float %0 to i64 5827 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5828 %sub = add nsw i32 %elem, -1 5829 %idxprom1 = sext i32 %sub to i64 5830 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 5831 %1 = load float, float* %arrayidx2, align 4 5832 %conv3 = fptoui float %1 to i64 5833 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 5834 ret <2 x i64> %vecinit4 5835} 5836 5837; Function Attrs: norecurse nounwind readnone 5838define <2 x i64> @spltRegValConvftoull(float %val) { 5839; P9BE-LABEL: spltRegValConvftoull: 5840; P9BE: # %bb.0: # %entry 5841; P9BE-NEXT: xscvdpuxds f0, f1 5842; P9BE-NEXT: xxspltd v2, f0, 0 5843; P9BE-NEXT: blr 5844; 5845; P9LE-LABEL: spltRegValConvftoull: 5846; P9LE: # %bb.0: # %entry 5847; P9LE-NEXT: xscvdpuxds f0, f1 5848; P9LE-NEXT: xxspltd v2, f0, 0 5849; P9LE-NEXT: blr 5850; 5851; P8BE-LABEL: spltRegValConvftoull: 5852; P8BE: # %bb.0: # %entry 5853; P8BE-NEXT: xscvdpuxds f0, f1 5854; P8BE-NEXT: xxspltd v2, f0, 0 5855; P8BE-NEXT: blr 5856; 5857; P8LE-LABEL: spltRegValConvftoull: 5858; P8LE: # %bb.0: # %entry 5859; P8LE-NEXT: xscvdpuxds f0, f1 5860; P8LE-NEXT: xxspltd v2, f0, 0 5861; P8LE-NEXT: blr 5862entry: 5863 %conv = fptoui float %val to i64 5864 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 5865 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5866 ret <2 x i64> %splat.splat 5867} 5868 5869; Function Attrs: norecurse nounwind readonly 5870define <2 x i64> @spltMemValConvftoull(float* nocapture readonly %ptr) { 5871; P9BE-LABEL: spltMemValConvftoull: 5872; P9BE: # %bb.0: # %entry 5873; P9BE-NEXT: lfs f0, 0(r3) 5874; P9BE-NEXT: xscvdpuxds f0, f0 5875; P9BE-NEXT: xxspltd v2, f0, 0 5876; P9BE-NEXT: blr 5877; 5878; P9LE-LABEL: spltMemValConvftoull: 5879; P9LE: # %bb.0: # %entry 5880; P9LE-NEXT: lfs f0, 0(r3) 5881; P9LE-NEXT: xscvdpuxds f0, f0 5882; P9LE-NEXT: xxspltd v2, f0, 0 5883; P9LE-NEXT: blr 5884; 5885; P8BE-LABEL: spltMemValConvftoull: 5886; P8BE: # %bb.0: # %entry 5887; P8BE-NEXT: lfsx f0, 0, r3 5888; P8BE-NEXT: xscvdpuxds f0, f0 5889; P8BE-NEXT: xxspltd v2, f0, 0 5890; P8BE-NEXT: blr 5891; 5892; P8LE-LABEL: spltMemValConvftoull: 5893; P8LE: # %bb.0: # %entry 5894; P8LE-NEXT: lfsx f0, 0, r3 5895; P8LE-NEXT: xscvdpuxds f0, f0 5896; P8LE-NEXT: xxspltd v2, f0, 0 5897; P8LE-NEXT: blr 5898entry: 5899 %0 = load float, float* %ptr, align 4 5900 %conv = fptoui float %0 to i64 5901 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 5902 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5903 ret <2 x i64> %splat.splat 5904} 5905 5906; Function Attrs: norecurse nounwind readnone 5907define <2 x i64> @spltCnstConvdtoull() { 5908; P9BE-LABEL: spltCnstConvdtoull: 5909; P9BE: # %bb.0: # %entry 5910; P9BE-NEXT: addis r3, r2, .LCPI119_0@toc@ha 5911; P9BE-NEXT: addi r3, r3, .LCPI119_0@toc@l 5912; P9BE-NEXT: lxvx v2, 0, r3 5913; P9BE-NEXT: blr 5914; 5915; P9LE-LABEL: spltCnstConvdtoull: 5916; P9LE: # %bb.0: # %entry 5917; P9LE-NEXT: addis r3, r2, .LCPI119_0@toc@ha 5918; P9LE-NEXT: addi r3, r3, .LCPI119_0@toc@l 5919; P9LE-NEXT: lxvx v2, 0, r3 5920; P9LE-NEXT: blr 5921; 5922; P8BE-LABEL: spltCnstConvdtoull: 5923; P8BE: # %bb.0: # %entry 5924; P8BE-NEXT: addis r3, r2, .LCPI119_0@toc@ha 5925; P8BE-NEXT: addi r3, r3, .LCPI119_0@toc@l 5926; P8BE-NEXT: lxvd2x v2, 0, r3 5927; P8BE-NEXT: blr 5928; 5929; P8LE-LABEL: spltCnstConvdtoull: 5930; P8LE: # %bb.0: # %entry 5931; P8LE-NEXT: addis r3, r2, .LCPI119_0@toc@ha 5932; P8LE-NEXT: addi r3, r3, .LCPI119_0@toc@l 5933; P8LE-NEXT: lxvd2x vs0, 0, r3 5934; P8LE-NEXT: xxswapd v2, vs0 5935; P8LE-NEXT: blr 5936entry: 5937 ret <2 x i64> <i64 4, i64 4> 5938} 5939 5940; Function Attrs: norecurse nounwind readnone 5941define <2 x i64> @fromRegsConvdtoull(double %a, double %b) { 5942; P9BE-LABEL: fromRegsConvdtoull: 5943; P9BE: # %bb.0: # %entry 5944; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5945; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5946; P9BE-NEXT: xxmrghd vs0, vs1, vs2 5947; P9BE-NEXT: xvcvdpuxds v2, vs0 5948; P9BE-NEXT: blr 5949; 5950; P9LE-LABEL: fromRegsConvdtoull: 5951; P9LE: # %bb.0: # %entry 5952; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5953; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5954; P9LE-NEXT: xxmrghd vs0, vs2, vs1 5955; P9LE-NEXT: xvcvdpuxds v2, vs0 5956; P9LE-NEXT: blr 5957; 5958; P8BE-LABEL: fromRegsConvdtoull: 5959; P8BE: # %bb.0: # %entry 5960; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5961; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5962; P8BE-NEXT: xxmrghd vs0, vs1, vs2 5963; P8BE-NEXT: xvcvdpuxds v2, vs0 5964; P8BE-NEXT: blr 5965; 5966; P8LE-LABEL: fromRegsConvdtoull: 5967; P8LE: # %bb.0: # %entry 5968; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5969; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5970; P8LE-NEXT: xxmrghd vs0, vs2, vs1 5971; P8LE-NEXT: xvcvdpuxds v2, vs0 5972; P8LE-NEXT: blr 5973entry: 5974 %conv = fptoui double %a to i64 5975 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5976 %conv1 = fptoui double %b to i64 5977 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 5978 ret <2 x i64> %vecinit2 5979} 5980 5981; Function Attrs: norecurse nounwind readnone 5982define <2 x i64> @fromDiffConstsConvdtoull() { 5983; P9BE-LABEL: fromDiffConstsConvdtoull: 5984; P9BE: # %bb.0: # %entry 5985; P9BE-NEXT: addis r3, r2, .LCPI121_0@toc@ha 5986; P9BE-NEXT: addi r3, r3, .LCPI121_0@toc@l 5987; P9BE-NEXT: lxvx v2, 0, r3 5988; P9BE-NEXT: blr 5989; 5990; P9LE-LABEL: fromDiffConstsConvdtoull: 5991; P9LE: # %bb.0: # %entry 5992; P9LE-NEXT: addis r3, r2, .LCPI121_0@toc@ha 5993; P9LE-NEXT: addi r3, r3, .LCPI121_0@toc@l 5994; P9LE-NEXT: lxvx v2, 0, r3 5995; P9LE-NEXT: blr 5996; 5997; P8BE-LABEL: fromDiffConstsConvdtoull: 5998; P8BE: # %bb.0: # %entry 5999; P8BE-NEXT: addis r3, r2, .LCPI121_0@toc@ha 6000; P8BE-NEXT: addi r3, r3, .LCPI121_0@toc@l 6001; P8BE-NEXT: lxvd2x v2, 0, r3 6002; P8BE-NEXT: blr 6003; 6004; P8LE-LABEL: fromDiffConstsConvdtoull: 6005; P8LE: # %bb.0: # %entry 6006; P8LE-NEXT: addis r3, r2, .LCPI121_0@toc@ha 6007; P8LE-NEXT: addi r3, r3, .LCPI121_0@toc@l 6008; P8LE-NEXT: lxvd2x vs0, 0, r3 6009; P8LE-NEXT: xxswapd v2, vs0 6010; P8LE-NEXT: blr 6011entry: 6012 ret <2 x i64> <i64 24, i64 234> 6013} 6014 6015; Function Attrs: norecurse nounwind readonly 6016define <2 x i64> @fromDiffMemConsAConvdtoull(double* nocapture readonly %ptr) { 6017; P9BE-LABEL: fromDiffMemConsAConvdtoull: 6018; P9BE: # %bb.0: # %entry 6019; P9BE-NEXT: lxv vs0, 0(r3) 6020; P9BE-NEXT: xvcvdpuxds v2, vs0 6021; P9BE-NEXT: blr 6022; 6023; P9LE-LABEL: fromDiffMemConsAConvdtoull: 6024; P9LE: # %bb.0: # %entry 6025; P9LE-NEXT: lxv vs0, 0(r3) 6026; P9LE-NEXT: xvcvdpuxds v2, vs0 6027; P9LE-NEXT: blr 6028; 6029; P8BE-LABEL: fromDiffMemConsAConvdtoull: 6030; P8BE: # %bb.0: # %entry 6031; P8BE-NEXT: lxvd2x vs0, 0, r3 6032; P8BE-NEXT: xvcvdpuxds v2, vs0 6033; P8BE-NEXT: blr 6034; 6035; P8LE-LABEL: fromDiffMemConsAConvdtoull: 6036; P8LE: # %bb.0: # %entry 6037; P8LE-NEXT: lxvd2x vs0, 0, r3 6038; P8LE-NEXT: xxswapd vs0, vs0 6039; P8LE-NEXT: xvcvdpuxds v2, vs0 6040; P8LE-NEXT: blr 6041entry: 6042 %0 = bitcast double* %ptr to <2 x double>* 6043 %1 = load <2 x double>, <2 x double>* %0, align 8 6044 %2 = fptoui <2 x double> %1 to <2 x i64> 6045 ret <2 x i64> %2 6046} 6047 6048; Function Attrs: norecurse nounwind readonly 6049define <2 x i64> @fromDiffMemConsDConvdtoull(double* nocapture readonly %ptr) { 6050; P9BE-LABEL: fromDiffMemConsDConvdtoull: 6051; P9BE: # %bb.0: # %entry 6052; P9BE-NEXT: lxv vs0, 16(r3) 6053; P9BE-NEXT: xxswapd vs0, vs0 6054; P9BE-NEXT: xvcvdpuxds v2, vs0 6055; P9BE-NEXT: blr 6056; 6057; P9LE-LABEL: fromDiffMemConsDConvdtoull: 6058; P9LE: # %bb.0: # %entry 6059; P9LE-NEXT: addi r3, r3, 16 6060; P9LE-NEXT: lxvd2x vs0, 0, r3 6061; P9LE-NEXT: xvcvdpuxds v2, vs0 6062; P9LE-NEXT: blr 6063; 6064; P8BE-LABEL: fromDiffMemConsDConvdtoull: 6065; P8BE: # %bb.0: # %entry 6066; P8BE-NEXT: addi r3, r3, 16 6067; P8BE-NEXT: lxvd2x vs0, 0, r3 6068; P8BE-NEXT: xxswapd vs0, vs0 6069; P8BE-NEXT: xvcvdpuxds v2, vs0 6070; P8BE-NEXT: blr 6071; 6072; P8LE-LABEL: fromDiffMemConsDConvdtoull: 6073; P8LE: # %bb.0: # %entry 6074; P8LE-NEXT: addi r3, r3, 16 6075; P8LE-NEXT: lxvd2x vs0, 0, r3 6076; P8LE-NEXT: xvcvdpuxds v2, vs0 6077; P8LE-NEXT: blr 6078entry: 6079 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 6080 %0 = load double, double* %arrayidx, align 8 6081 %conv = fptoui double %0 to i64 6082 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6083 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 6084 %1 = load double, double* %arrayidx1, align 8 6085 %conv2 = fptoui double %1 to i64 6086 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 6087 ret <2 x i64> %vecinit3 6088} 6089 6090; Function Attrs: norecurse nounwind readonly 6091define <2 x i64> @fromDiffMemVarAConvdtoull(double* nocapture readonly %arr, i32 signext %elem) { 6092; P9BE-LABEL: fromDiffMemVarAConvdtoull: 6093; P9BE: # %bb.0: # %entry 6094; P9BE-NEXT: sldi r4, r4, 3 6095; P9BE-NEXT: lxvx vs0, r3, r4 6096; P9BE-NEXT: xvcvdpuxds v2, vs0 6097; P9BE-NEXT: blr 6098; 6099; P9LE-LABEL: fromDiffMemVarAConvdtoull: 6100; P9LE: # %bb.0: # %entry 6101; P9LE-NEXT: sldi r4, r4, 3 6102; P9LE-NEXT: lxvx vs0, r3, r4 6103; P9LE-NEXT: xvcvdpuxds v2, vs0 6104; P9LE-NEXT: blr 6105; 6106; P8BE-LABEL: fromDiffMemVarAConvdtoull: 6107; P8BE: # %bb.0: # %entry 6108; P8BE-NEXT: sldi r4, r4, 3 6109; P8BE-NEXT: lxvd2x vs0, r3, r4 6110; P8BE-NEXT: xvcvdpuxds v2, vs0 6111; P8BE-NEXT: blr 6112; 6113; P8LE-LABEL: fromDiffMemVarAConvdtoull: 6114; P8LE: # %bb.0: # %entry 6115; P8LE-NEXT: sldi r4, r4, 3 6116; P8LE-NEXT: lxvd2x vs0, r3, r4 6117; P8LE-NEXT: xxswapd vs0, vs0 6118; P8LE-NEXT: xvcvdpuxds v2, vs0 6119; P8LE-NEXT: blr 6120entry: 6121 %idxprom = sext i32 %elem to i64 6122 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 6123 %0 = load double, double* %arrayidx, align 8 6124 %conv = fptoui double %0 to i64 6125 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6126 %add = add nsw i32 %elem, 1 6127 %idxprom1 = sext i32 %add to i64 6128 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 6129 %1 = load double, double* %arrayidx2, align 8 6130 %conv3 = fptoui double %1 to i64 6131 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 6132 ret <2 x i64> %vecinit4 6133} 6134 6135; Function Attrs: norecurse nounwind readonly 6136define <2 x i64> @fromDiffMemVarDConvdtoull(double* nocapture readonly %arr, i32 signext %elem) { 6137; P9BE-LABEL: fromDiffMemVarDConvdtoull: 6138; P9BE: # %bb.0: # %entry 6139; P9BE-NEXT: sldi r4, r4, 3 6140; P9BE-NEXT: add r3, r3, r4 6141; P9BE-NEXT: li r4, -8 6142; P9BE-NEXT: lxvx vs0, r3, r4 6143; P9BE-NEXT: xxswapd vs0, vs0 6144; P9BE-NEXT: xvcvdpuxds v2, vs0 6145; P9BE-NEXT: blr 6146; 6147; P9LE-LABEL: fromDiffMemVarDConvdtoull: 6148; P9LE: # %bb.0: # %entry 6149; P9LE-NEXT: sldi r4, r4, 3 6150; P9LE-NEXT: add r3, r3, r4 6151; P9LE-NEXT: addi r3, r3, -8 6152; P9LE-NEXT: lxvd2x vs0, 0, r3 6153; P9LE-NEXT: xvcvdpuxds v2, vs0 6154; P9LE-NEXT: blr 6155; 6156; P8BE-LABEL: fromDiffMemVarDConvdtoull: 6157; P8BE: # %bb.0: # %entry 6158; P8BE-NEXT: sldi r4, r4, 3 6159; P8BE-NEXT: add r3, r3, r4 6160; P8BE-NEXT: addi r3, r3, -8 6161; P8BE-NEXT: lxvd2x vs0, 0, r3 6162; P8BE-NEXT: xxswapd vs0, vs0 6163; P8BE-NEXT: xvcvdpuxds v2, vs0 6164; P8BE-NEXT: blr 6165; 6166; P8LE-LABEL: fromDiffMemVarDConvdtoull: 6167; P8LE: # %bb.0: # %entry 6168; P8LE-NEXT: sldi r4, r4, 3 6169; P8LE-NEXT: add r3, r3, r4 6170; P8LE-NEXT: addi r3, r3, -8 6171; P8LE-NEXT: lxvd2x vs0, 0, r3 6172; P8LE-NEXT: xvcvdpuxds v2, vs0 6173; P8LE-NEXT: blr 6174entry: 6175 %idxprom = sext i32 %elem to i64 6176 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 6177 %0 = load double, double* %arrayidx, align 8 6178 %conv = fptoui double %0 to i64 6179 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6180 %sub = add nsw i32 %elem, -1 6181 %idxprom1 = sext i32 %sub to i64 6182 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 6183 %1 = load double, double* %arrayidx2, align 8 6184 %conv3 = fptoui double %1 to i64 6185 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 6186 ret <2 x i64> %vecinit4 6187} 6188 6189; Function Attrs: norecurse nounwind readnone 6190define <2 x i64> @spltRegValConvdtoull(double %val) { 6191; P9BE-LABEL: spltRegValConvdtoull: 6192; P9BE: # %bb.0: # %entry 6193; P9BE-NEXT: xscvdpuxds f0, f1 6194; P9BE-NEXT: xxspltd v2, vs0, 0 6195; P9BE-NEXT: blr 6196; 6197; P9LE-LABEL: spltRegValConvdtoull: 6198; P9LE: # %bb.0: # %entry 6199; P9LE-NEXT: xscvdpuxds f0, f1 6200; P9LE-NEXT: xxspltd v2, vs0, 0 6201; P9LE-NEXT: blr 6202; 6203; P8BE-LABEL: spltRegValConvdtoull: 6204; P8BE: # %bb.0: # %entry 6205; P8BE-NEXT: xscvdpuxds f0, f1 6206; P8BE-NEXT: xxspltd v2, vs0, 0 6207; P8BE-NEXT: blr 6208; 6209; P8LE-LABEL: spltRegValConvdtoull: 6210; P8LE: # %bb.0: # %entry 6211; P8LE-NEXT: xscvdpuxds f0, f1 6212; P8LE-NEXT: xxspltd v2, vs0, 0 6213; P8LE-NEXT: blr 6214entry: 6215 %conv = fptoui double %val to i64 6216 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 6217 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 6218 ret <2 x i64> %splat.splat 6219} 6220 6221; Function Attrs: norecurse nounwind readonly 6222define <2 x i64> @spltMemValConvdtoull(double* nocapture readonly %ptr) { 6223; P9BE-LABEL: spltMemValConvdtoull: 6224; P9BE: # %bb.0: # %entry 6225; P9BE-NEXT: lxvdsx vs0, 0, r3 6226; P9BE-NEXT: xvcvdpuxds v2, vs0 6227; P9BE-NEXT: blr 6228; 6229; P9LE-LABEL: spltMemValConvdtoull: 6230; P9LE: # %bb.0: # %entry 6231; P9LE-NEXT: lxvdsx vs0, 0, r3 6232; P9LE-NEXT: xvcvdpuxds v2, vs0 6233; P9LE-NEXT: blr 6234; 6235; P8BE-LABEL: spltMemValConvdtoull: 6236; P8BE: # %bb.0: # %entry 6237; P8BE-NEXT: lxvdsx vs0, 0, r3 6238; P8BE-NEXT: xvcvdpuxds v2, vs0 6239; P8BE-NEXT: blr 6240; 6241; P8LE-LABEL: spltMemValConvdtoull: 6242; P8LE: # %bb.0: # %entry 6243; P8LE-NEXT: lxvdsx vs0, 0, r3 6244; P8LE-NEXT: xvcvdpuxds v2, vs0 6245; P8LE-NEXT: blr 6246entry: 6247 %0 = load double, double* %ptr, align 8 6248 %conv = fptoui double %0 to i64 6249 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 6250 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 6251 ret <2 x i64> %splat.splat 6252} 6253