1; RUN: llc -mcpu=pwr9 -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown \ 2; RUN: < %s | FileCheck %s -check-prefix=P9BE -implicit-check-not frsp 3; RUN: llc -mcpu=pwr9 -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown \ 4; RUN: < %s | FileCheck %s -check-prefix=P9LE -implicit-check-not frsp 5; RUN: llc -mcpu=pwr8 -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown \ 6; RUN: < %s | FileCheck %s -check-prefix=P8BE -implicit-check-not frsp 7; RUN: llc -mcpu=pwr8 -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown \ 8; RUN: < %s | FileCheck %s -check-prefix=P8LE -implicit-check-not frsp 9 10; This test case comes from the following C test case (included as it may be 11; slightly more readable than the LLVM IR. 12 13;/* This test case provides various ways of building vectors to ensure we 14; produce optimal code for all cases. The cases are (for each type): 15; - All zeros 16; - All ones 17; - Splat of a constant 18; - From different values already in registers 19; - From different constants 20; - From different values in memory 21; - Splat of a value in register 22; - Splat of a value in memory 23; - Inserting element into existing vector 24; - Inserting element from existing vector into existing vector 25; 26; With conversions (float <-> int) 27; - Splat of a constant 28; - From different values already in registers 29; - From different constants 30; - From different values in memory 31; - Splat of a value in register 32; - Splat of a value in memory 33; - Inserting element into existing vector 34; - Inserting element from existing vector into existing vector 35;*/ 36; 37;/*=================================== int ===================================*/ 38;// P8: xxlxor // 39;// P9: xxlxor // 40;vector int allZeroi() { // 41; return (vector int)0; // 42;} // 43;// P8: vspltisb -1 // 44;// P9: xxspltisb 255 // 45;vector int allOnei() { // 46; return (vector int)-1; // 47;} // 48;// P8: vspltisw 1 // 49;// P9: vspltisw 1 // 50;vector int spltConst1i() { // 51; return (vector int)1; // 52;} // 53;// P8: vspltisw -15; vsrw // 54;// P9: vspltisw -15; vsrw // 55;vector int spltConst16ki() { // 56; return (vector int)((1<<15) - 1); // 57;} // 58;// P8: vspltisw -16; vsrw // 59;// P9: vspltisw -16; vsrw // 60;vector int spltConst32ki() { // 61; return (vector int)((1<<16) - 1); // 62;} // 63;// P8: 4 x mtvsrwz, 2 x xxmrgh, vmrgow // 64;// P9: 2 x mtvsrdd, vmrgow // 65;vector int fromRegsi(int a, int b, int c, int d) { // 66; return (vector int){ a, b, c, d }; // 67;} // 68;// P8: lxvd2x, xxswapd // 69;// P9: lxvx (or even lxv) // 70;vector int fromDiffConstsi() { // 71; return (vector int) { 242, -113, 889, 19 }; // 72;} // 73;// P8: lxvd2x, xxswapd // 74;// P9: lxvx // 75;vector int fromDiffMemConsAi(int *arr) { // 76; return (vector int) { arr[0], arr[1], arr[2], arr[3] }; // 77;} // 78;// P8: 2 x lxvd2x, 2 x xxswapd, vperm // 79;// P9: 2 x lxvx, vperm // 80;vector int fromDiffMemConsDi(int *arr) { // 81; return (vector int) { arr[3], arr[2], arr[1], arr[0] }; // 82;} // 83;// P8: sldi 2, lxvd2x, xxswapd // 84;// P9: sldi 2, lxvx // 85;vector int fromDiffMemVarAi(int *arr, int elem) { // 86; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 87;} // 88;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm // 89;// P9: sldi 2, 2 x lxvx, vperm // 90;vector int fromDiffMemVarDi(int *arr, int elem) { // 91; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 92;} // 93;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 94;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow // 95;vector int fromRandMemConsi(int *arr) { // 96; return (vector int) { arr[4], arr[18], arr[2], arr[88] }; // 97;} // 98;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 99;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow // 100;vector int fromRandMemVari(int *arr, int elem) { // 101; return (vector int) { arr[elem+4], arr[elem+1], arr[elem+2], arr[elem+8] };// 102;} // 103;// P8: mtvsrwz, xxspltw // 104;// P9: mtvsrws // 105;vector int spltRegVali(int val) { // 106; return (vector int) val; // 107;} // 108;// P8: lxsiwax, xxspltw // 109;// P9: lxvwsx // 110;vector int spltMemVali(int *ptr) { // 111; return (vector int)*ptr; // 112;} // 113;// P8: vspltisw // 114;// P9: vspltisw // 115;vector int spltCnstConvftoi() { // 116; return (vector int) 4.74f; // 117;} // 118;// P8: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws // 119;// P9: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvdpsxws // 120;vector int fromRegsConvftoi(float a, float b, float c, float d) { // 121; return (vector int) { a, b, c, d }; // 122;} // 123;// P8: lxvd2x, xxswapd // 124;// P9: lxvx (even lxv) // 125;vector int fromDiffConstsConvftoi() { // 126; return (vector int) { 24.46f, 234.f, 988.19f, 422.39f }; // 127;} // 128;// P8: lxvd2x, xxswapd, xvcvspsxws // 129;// P9: lxvx, xvcvspsxws // 130;vector int fromDiffMemConsAConvftoi(float *ptr) { // 131; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 132;} // 133;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspsxws // 134;// P9: 2 x lxvx, vperm, xvcvspsxws // 135;vector int fromDiffMemConsDConvftoi(float *ptr) { // 136; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 137;} // 138;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws // 139;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws // 140;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 141;// sldi 2, load, xvcvspuxws // 142;vector int fromDiffMemVarAConvftoi(float *arr, int elem) { // 143; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 144;} // 145;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws // 146;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws // 147;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 148;// sldi 2, 2 x load, vperm, xvcvspuxws // 149;vector int fromDiffMemVarDConvftoi(float *arr, int elem) { // 150; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 151;} // 152;// P8: xscvdpsxws, xxspltw // 153;// P9: xscvdpsxws, xxspltw // 154;vector int spltRegValConvftoi(float val) { // 155; return (vector int) val; // 156;} // 157;// P8: lxsspx, xscvdpsxws, xxspltw // 158;// P9: lxvwsx, xvcvspsxws // 159;vector int spltMemValConvftoi(float *ptr) { // 160; return (vector int)*ptr; // 161;} // 162;// P8: vspltisw // 163;// P9: vspltisw // 164;vector int spltCnstConvdtoi() { // 165; return (vector int) 4.74; // 166;} // 167;// P8: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws // 168;// P9: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws // 169;vector int fromRegsConvdtoi(double a, double b, double c, double d) { // 170; return (vector int) { a, b, c, d }; // 171;} // 172;// P8: lxvd2x, xxswapd // 173;// P9: lxvx (even lxv) // 174;vector int fromDiffConstsConvdtoi() { // 175; return (vector int) { 24.46, 234., 988.19, 422.39 }; // 176;} // 177;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvdpsp, vmrgew, // 178;// xvcvspsxws // 179;// P9: 2 x lxvx, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvdpsp, vmrgew, // 180;// xvcvspsxws // 181;vector int fromDiffMemConsAConvdtoi(double *ptr) { // 182; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 183;} // 184;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws // 185;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws // 186;vector int fromDiffMemConsDConvdtoi(double *ptr) { // 187; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 188;} // 189;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws // 190;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws // 191;vector int fromDiffMemVarAConvdtoi(double *arr, int elem) { // 192; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 193;} // 194;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws // 195;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws // 196;vector int fromDiffMemVarDConvdtoi(double *arr, int elem) { // 197; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 198;} // 199;// P8: xscvdpsxws, xxspltw // 200;// P9: xscvdpsxws, xxspltw // 201;vector int spltRegValConvdtoi(double val) { // 202; return (vector int) val; // 203;} // 204;// P8: lxsdx, xscvdpsxws, xxspltw // 205;// P9: lxssp, xscvdpsxws, xxspltw // 206;vector int spltMemValConvdtoi(double *ptr) { // 207; return (vector int)*ptr; // 208;} // 209;/*=================================== int ===================================*/ 210;/*=============================== unsigned int ==============================*/ 211;// P8: xxlxor // 212;// P9: xxlxor // 213;vector unsigned int allZeroui() { // 214; return (vector unsigned int)0; // 215;} // 216;// P8: vspltisb -1 // 217;// P9: xxspltisb 255 // 218;vector unsigned int allOneui() { // 219; return (vector unsigned int)-1; // 220;} // 221;// P8: vspltisw 1 // 222;// P9: vspltisw 1 // 223;vector unsigned int spltConst1ui() { // 224; return (vector unsigned int)1; // 225;} // 226;// P8: vspltisw -15; vsrw // 227;// P9: vspltisw -15; vsrw // 228;vector unsigned int spltConst16kui() { // 229; return (vector unsigned int)((1<<15) - 1); // 230;} // 231;// P8: vspltisw -16; vsrw // 232;// P9: vspltisw -16; vsrw // 233;vector unsigned int spltConst32kui() { // 234; return (vector unsigned int)((1<<16) - 1); // 235;} // 236;// P8: 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 237;// P9: 2 x mtvsrdd, vmrgow // 238;vector unsigned int fromRegsui(unsigned int a, unsigned int b, // 239; unsigned int c, unsigned int d) { // 240; return (vector unsigned int){ a, b, c, d }; // 241;} // 242;// P8: lxvd2x, xxswapd // 243;// P9: lxvx (or even lxv) // 244;vector unsigned int fromDiffConstsui() { // 245; return (vector unsigned int) { 242, -113, 889, 19 }; // 246;} // 247;// P8: lxvd2x, xxswapd // 248;// P9: lxvx // 249;vector unsigned int fromDiffMemConsAui(unsigned int *arr) { // 250; return (vector unsigned int) { arr[0], arr[1], arr[2], arr[3] }; // 251;} // 252;// P8: 2 x lxvd2x, 2 x xxswapd, vperm // 253;// P9: 2 x lxvx, vperm // 254;vector unsigned int fromDiffMemConsDui(unsigned int *arr) { // 255; return (vector unsigned int) { arr[3], arr[2], arr[1], arr[0] }; // 256;} // 257;// P8: sldi 2, lxvd2x, xxswapd // 258;// P9: sldi 2, lxvx // 259;vector unsigned int fromDiffMemVarAui(unsigned int *arr, int elem) { // 260; return (vector unsigned int) { arr[elem], arr[elem+1], // 261; arr[elem+2], arr[elem+3] }; // 262;} // 263;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm // 264;// P9: sldi 2, 2 x lxvx, vperm // 265;vector unsigned int fromDiffMemVarDui(unsigned int *arr, int elem) { // 266; return (vector unsigned int) { arr[elem], arr[elem-1], // 267; arr[elem-2], arr[elem-3] }; // 268;} // 269;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 270;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow // 271;vector unsigned int fromRandMemConsui(unsigned int *arr) { // 272; return (vector unsigned int) { arr[4], arr[18], arr[2], arr[88] }; // 273;} // 274;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 275;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow // 276;vector unsigned int fromRandMemVarui(unsigned int *arr, int elem) { // 277; return (vector unsigned int) { arr[elem+4], arr[elem+1], // 278; arr[elem+2], arr[elem+8] }; // 279;} // 280;// P8: mtvsrwz, xxspltw // 281;// P9: mtvsrws // 282;vector unsigned int spltRegValui(unsigned int val) { // 283; return (vector unsigned int) val; // 284;} // 285;// P8: lxsiwax, xxspltw // 286;// P9: lxvwsx // 287;vector unsigned int spltMemValui(unsigned int *ptr) { // 288; return (vector unsigned int)*ptr; // 289;} // 290;// P8: vspltisw // 291;// P9: vspltisw // 292;vector unsigned int spltCnstConvftoui() { // 293; return (vector unsigned int) 4.74f; // 294;} // 295;// P8: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 296;// P9: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 297;vector unsigned int fromRegsConvftoui(float a, float b, float c, float d) { // 298; return (vector unsigned int) { a, b, c, d }; // 299;} // 300;// P8: lxvd2x, xxswapd // 301;// P9: lxvx (even lxv) // 302;vector unsigned int fromDiffConstsConvftoui() { // 303; return (vector unsigned int) { 24.46f, 234.f, 988.19f, 422.39f }; // 304;} // 305;// P8: lxvd2x, xxswapd, xvcvspuxws // 306;// P9: lxvx, xvcvspuxws // 307;vector unsigned int fromDiffMemConsAConvftoui(float *ptr) { // 308; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 309;} // 310;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspuxws // 311;// P9: 2 x lxvx, vperm, xvcvspuxws // 312;vector unsigned int fromDiffMemConsDConvftoui(float *ptr) { // 313; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 314;} // 315;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 316;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 317;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 318;// sldi 2, load, xvcvspuxws // 319;vector unsigned int fromDiffMemVarAConvftoui(float *arr, int elem) { // 320; return (vector unsigned int) { arr[elem], arr[elem+1], // 321; arr[elem+2], arr[elem+3] }; // 322;} // 323;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 324;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 325;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 326;// sldi 2, 2 x load, vperm, xvcvspuxws // 327;vector unsigned int fromDiffMemVarDConvftoui(float *arr, int elem) { // 328; return (vector unsigned int) { arr[elem], arr[elem-1], // 329; arr[elem-2], arr[elem-3] }; // 330;} // 331;// P8: xscvdpuxws, xxspltw // 332;// P9: xscvdpuxws, xxspltw // 333;vector unsigned int spltRegValConvftoui(float val) { // 334; return (vector unsigned int) val; // 335;} // 336;// P8: lxsspx, xscvdpuxws, xxspltw // 337;// P9: lxvwsx, xvcvspuxws // 338;vector unsigned int spltMemValConvftoui(float *ptr) { // 339; return (vector unsigned int)*ptr; // 340;} // 341;// P8: vspltisw // 342;// P9: vspltisw // 343;vector unsigned int spltCnstConvdtoui() { // 344; return (vector unsigned int) 4.74; // 345;} // 346;// P8: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 347;// P9: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 348;vector unsigned int fromRegsConvdtoui(double a, double b, // 349; double c, double d) { // 350; return (vector unsigned int) { a, b, c, d }; // 351;} // 352;// P8: lxvd2x, xxswapd // 353;// P9: lxvx (even lxv) // 354;vector unsigned int fromDiffConstsConvdtoui() { // 355; return (vector unsigned int) { 24.46, 234., 988.19, 422.39 }; // 356;} // 357;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvdpsp, vmrgew, // 358;// xvcvspuxws // 359;// P9: 2 x lxvx, xxmrgld, xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 360;vector unsigned int fromDiffMemConsAConvdtoui(double *ptr) { // 361; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 362;} // 363;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 364;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 365;vector unsigned int fromDiffMemConsDConvdtoui(double *ptr) { // 366; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 367;} // 368;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 369;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 370;vector unsigned int fromDiffMemVarAConvdtoui(double *arr, int elem) { // 371; return (vector unsigned int) { arr[elem], arr[elem+1], // 372; arr[elem+2], arr[elem+3] }; // 373;} // 374;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 375;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 376;vector unsigned int fromDiffMemVarDConvdtoui(double *arr, int elem) { // 377; return (vector unsigned int) { arr[elem], arr[elem-1], // 378; arr[elem-2], arr[elem-3] }; // 379;} // 380;// P8: xscvdpuxws, xxspltw // 381;// P9: xscvdpuxws, xxspltw // 382;vector unsigned int spltRegValConvdtoui(double val) { // 383; return (vector unsigned int) val; // 384;} // 385;// P8: lxsspx, xscvdpuxws, xxspltw // 386;// P9: lfd, xscvdpuxws, xxspltw // 387;vector unsigned int spltMemValConvdtoui(double *ptr) { // 388; return (vector unsigned int)*ptr; // 389;} // 390;/*=============================== unsigned int ==============================*/ 391;/*=============================== long long =================================*/ 392;// P8: xxlxor // 393;// P9: xxlxor // 394;vector long long allZeroll() { // 395; return (vector long long)0; // 396;} // 397;// P8: vspltisb -1 // 398;// P9: xxspltisb 255 // 399;vector long long allOnell() { // 400; return (vector long long)-1; // 401;} // 402;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 403;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 404;vector long long spltConst1ll() { // 405; return (vector long long)1; // 406;} // 407;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 408;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 409;vector long long spltConst16kll() { // 410; return (vector long long)((1<<15) - 1); // 411;} // 412;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 413;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 414;vector long long spltConst32kll() { // 415; return (vector long long)((1<<16) - 1); // 416;} // 417;// P8: 2 x mtvsrd, xxmrghd // 418;// P9: mtvsrdd // 419;vector long long fromRegsll(long long a, long long b) { // 420; return (vector long long){ a, b }; // 421;} // 422;// P8: lxvd2x, xxswapd // 423;// P9: lxvx (or even lxv) // 424;vector long long fromDiffConstsll() { // 425; return (vector long long) { 242, -113 }; // 426;} // 427;// P8: lxvd2x, xxswapd // 428;// P9: lxvx // 429;vector long long fromDiffMemConsAll(long long *arr) { // 430; return (vector long long) { arr[0], arr[1] }; // 431;} // 432;// P8: lxvd2x // 433;// P9: lxvx, xxswapd (maybe just use lxvd2x) // 434;vector long long fromDiffMemConsDll(long long *arr) { // 435; return (vector long long) { arr[3], arr[2] }; // 436;} // 437;// P8: sldi 3, lxvd2x, xxswapd // 438;// P9: sldi 3, lxvx // 439;vector long long fromDiffMemVarAll(long long *arr, int elem) { // 440; return (vector long long) { arr[elem], arr[elem+1] }; // 441;} // 442;// P8: sldi 3, lxvd2x // 443;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) // 444;vector long long fromDiffMemVarDll(long long *arr, int elem) { // 445; return (vector long long) { arr[elem], arr[elem-1] }; // 446;} // 447;// P8: 2 x ld, 2 x mtvsrd, xxmrghd // 448;// P9: 2 x ld, mtvsrdd // 449;vector long long fromRandMemConsll(long long *arr) { // 450; return (vector long long) { arr[4], arr[18] }; // 451;} // 452;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd // 453;// P9: sldi 3, add, 2 x ld, mtvsrdd // 454;vector long long fromRandMemVarll(long long *arr, int elem) { // 455; return (vector long long) { arr[elem+4], arr[elem+1] }; // 456;} // 457;// P8: mtvsrd, xxspltd // 458;// P9: mtvsrdd // 459;vector long long spltRegValll(long long val) { // 460; return (vector long long) val; // 461;} // 462;// P8: lxvdsx // 463;// P9: lxvdsx // 464;vector long long spltMemValll(long long *ptr) { // 465; return (vector long long)*ptr; // 466;} // 467;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 468;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 469;vector long long spltCnstConvftoll() { // 470; return (vector long long) 4.74f; // 471;} // 472;// P8: xxmrghd, xvcvdpsxds // 473;// P9: xxmrghd, xvcvdpsxds // 474;vector long long fromRegsConvftoll(float a, float b) { // 475; return (vector long long) { a, b }; // 476;} // 477;// P8: lxvd2x, xxswapd // 478;// P9: lxvx (even lxv) // 479;vector long long fromDiffConstsConvftoll() { // 480; return (vector long long) { 24.46f, 234.f }; // 481;} // 482;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds // 483;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds // 484;vector long long fromDiffMemConsAConvftoll(float *ptr) { // 485; return (vector long long) { ptr[0], ptr[1] }; // 486;} // 487;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds // 488;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds // 489;vector long long fromDiffMemConsDConvftoll(float *ptr) { // 490; return (vector long long) { ptr[3], ptr[2] }; // 491;} // 492;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds // 493;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds // 494;vector long long fromDiffMemVarAConvftoll(float *arr, int elem) { // 495; return (vector long long) { arr[elem], arr[elem+1] }; // 496;} // 497;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds // 498;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds // 499;vector long long fromDiffMemVarDConvftoll(float *arr, int elem) { // 500; return (vector long long) { arr[elem], arr[elem-1] }; // 501;} // 502;// P8: xscvdpsxds, xxspltd // 503;// P9: xscvdpsxds, xxspltd // 504;vector long long spltRegValConvftoll(float val) { // 505; return (vector long long) val; // 506;} // 507;// P8: lxsspx, xscvdpsxds, xxspltd // 508;// P9: lfs, xscvdpsxds, xxspltd // 509;vector long long spltMemValConvftoll(float *ptr) { // 510; return (vector long long)*ptr; // 511;} // 512;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 513;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 514;vector long long spltCnstConvdtoll() { // 515; return (vector long long) 4.74; // 516;} // 517;// P8: xxmrghd, xvcvdpsxds // 518;// P9: xxmrghd, xvcvdpsxds // 519;vector long long fromRegsConvdtoll(double a, double b) { // 520; return (vector long long) { a, b }; // 521;} // 522;// P8: lxvd2x, xxswapd // 523;// P9: lxvx (even lxv) // 524;vector long long fromDiffConstsConvdtoll() { // 525; return (vector long long) { 24.46, 234. }; // 526;} // 527;// P8: lxvd2x, xxswapd, xvcvdpsxds // 528;// P9: lxvx, xvcvdpsxds // 529;vector long long fromDiffMemConsAConvdtoll(double *ptr) { // 530; return (vector long long) { ptr[0], ptr[1] }; // 531;} // 532;// P8: lxvd2x, xvcvdpsxds // 533;// P9: lxvx, xxswapd, xvcvdpsxds // 534;vector long long fromDiffMemConsDConvdtoll(double *ptr) { // 535; return (vector long long) { ptr[3], ptr[2] }; // 536;} // 537;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpsxds // 538;// P9: sldi 3, lxvx, xvcvdpsxds // 539;vector long long fromDiffMemVarAConvdtoll(double *arr, int elem) { // 540; return (vector long long) { arr[elem], arr[elem+1] }; // 541;} // 542;// P8: sldi 3, lxvd2x, xvcvdpsxds // 543;// P9: sldi 3, lxvx, xxswapd, xvcvdpsxds // 544;vector long long fromDiffMemVarDConvdtoll(double *arr, int elem) { // 545; return (vector long long) { arr[elem], arr[elem-1] }; // 546;} // 547;// P8: xscvdpsxds, xxspltd // 548;// P9: xscvdpsxds, xxspltd // 549;vector long long spltRegValConvdtoll(double val) { // 550; return (vector long long) val; // 551;} // 552;// P8: lxvdsx, xvcvdpsxds // 553;// P9: lxvdsx, xvcvdpsxds // 554;vector long long spltMemValConvdtoll(double *ptr) { // 555; return (vector long long)*ptr; // 556;} // 557;/*=============================== long long =================================*/ 558;/*========================== unsigned long long =============================*/ 559;// P8: xxlxor // 560;// P9: xxlxor // 561;vector unsigned long long allZeroull() { // 562; return (vector unsigned long long)0; // 563;} // 564;// P8: vspltisb -1 // 565;// P9: xxspltisb 255 // 566;vector unsigned long long allOneull() { // 567; return (vector unsigned long long)-1; // 568;} // 569;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 570;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 571;vector unsigned long long spltConst1ull() { // 572; return (vector unsigned long long)1; // 573;} // 574;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 575;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 576;vector unsigned long long spltConst16kull() { // 577; return (vector unsigned long long)((1<<15) - 1); // 578;} // 579;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 580;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 581;vector unsigned long long spltConst32kull() { // 582; return (vector unsigned long long)((1<<16) - 1); // 583;} // 584;// P8: 2 x mtvsrd, xxmrghd // 585;// P9: mtvsrdd // 586;vector unsigned long long fromRegsull(unsigned long long a, // 587; unsigned long long b) { // 588; return (vector unsigned long long){ a, b }; // 589;} // 590;// P8: lxvd2x, xxswapd // 591;// P9: lxvx (or even lxv) // 592;vector unsigned long long fromDiffConstsull() { // 593; return (vector unsigned long long) { 242, -113 }; // 594;} // 595;// P8: lxvd2x, xxswapd // 596;// P9: lxvx // 597;vector unsigned long long fromDiffMemConsAull(unsigned long long *arr) { // 598; return (vector unsigned long long) { arr[0], arr[1] }; // 599;} // 600;// P8: lxvd2x // 601;// P9: lxvx, xxswapd (maybe just use lxvd2x) // 602;vector unsigned long long fromDiffMemConsDull(unsigned long long *arr) { // 603; return (vector unsigned long long) { arr[3], arr[2] }; // 604;} // 605;// P8: sldi 3, lxvd2x, xxswapd // 606;// P9: sldi 3, lxvx // 607;vector unsigned long long fromDiffMemVarAull(unsigned long long *arr, // 608; int elem) { // 609; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 610;} // 611;// P8: sldi 3, lxvd2x // 612;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) // 613;vector unsigned long long fromDiffMemVarDull(unsigned long long *arr, // 614; int elem) { // 615; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 616;} // 617;// P8: 2 x ld, 2 x mtvsrd, xxmrghd // 618;// P9: 2 x ld, mtvsrdd // 619;vector unsigned long long fromRandMemConsull(unsigned long long *arr) { // 620; return (vector unsigned long long) { arr[4], arr[18] }; // 621;} // 622;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd // 623;// P9: sldi 3, add, 2 x ld, mtvsrdd // 624;vector unsigned long long fromRandMemVarull(unsigned long long *arr, // 625; int elem) { // 626; return (vector unsigned long long) { arr[elem+4], arr[elem+1] }; // 627;} // 628;// P8: mtvsrd, xxspltd // 629;// P9: mtvsrdd // 630;vector unsigned long long spltRegValull(unsigned long long val) { // 631; return (vector unsigned long long) val; // 632;} // 633;// P8: lxvdsx // 634;// P9: lxvdsx // 635;vector unsigned long long spltMemValull(unsigned long long *ptr) { // 636; return (vector unsigned long long)*ptr; // 637;} // 638;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 639;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 640;vector unsigned long long spltCnstConvftoull() { // 641; return (vector unsigned long long) 4.74f; // 642;} // 643;// P8: xxmrghd, xvcvdpuxds // 644;// P9: xxmrghd, xvcvdpuxds // 645;vector unsigned long long fromRegsConvftoull(float a, float b) { // 646; return (vector unsigned long long) { a, b }; // 647;} // 648;// P8: lxvd2x, xxswapd // 649;// P9: lxvx (even lxv) // 650;vector unsigned long long fromDiffConstsConvftoull() { // 651; return (vector unsigned long long) { 24.46f, 234.f }; // 652;} // 653;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds // 654;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds // 655;vector unsigned long long fromDiffMemConsAConvftoull(float *ptr) { // 656; return (vector unsigned long long) { ptr[0], ptr[1] }; // 657;} // 658;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds // 659;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds // 660;vector unsigned long long fromDiffMemConsDConvftoull(float *ptr) { // 661; return (vector unsigned long long) { ptr[3], ptr[2] }; // 662;} // 663;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds // 664;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds // 665;vector unsigned long long fromDiffMemVarAConvftoull(float *arr, int elem) { // 666; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 667;} // 668;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds // 669;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds // 670;vector unsigned long long fromDiffMemVarDConvftoull(float *arr, int elem) { // 671; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 672;} // 673;// P8: xscvdpuxds, xxspltd // 674;// P9: xscvdpuxds, xxspltd // 675;vector unsigned long long spltRegValConvftoull(float val) { // 676; return (vector unsigned long long) val; // 677;} // 678;// P8: lxsspx, xscvdpuxds, xxspltd // 679;// P9: lfs, xscvdpuxds, xxspltd // 680;vector unsigned long long spltMemValConvftoull(float *ptr) { // 681; return (vector unsigned long long)*ptr; // 682;} // 683;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 684;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 685;vector unsigned long long spltCnstConvdtoull() { // 686; return (vector unsigned long long) 4.74; // 687;} // 688;// P8: xxmrghd, xvcvdpuxds // 689;// P9: xxmrghd, xvcvdpuxds // 690;vector unsigned long long fromRegsConvdtoull(double a, double b) { // 691; return (vector unsigned long long) { a, b }; // 692;} // 693;// P8: lxvd2x, xxswapd // 694;// P9: lxvx (even lxv) // 695;vector unsigned long long fromDiffConstsConvdtoull() { // 696; return (vector unsigned long long) { 24.46, 234. }; // 697;} // 698;// P8: lxvd2x, xxswapd, xvcvdpuxds // 699;// P9: lxvx, xvcvdpuxds // 700;vector unsigned long long fromDiffMemConsAConvdtoull(double *ptr) { // 701; return (vector unsigned long long) { ptr[0], ptr[1] }; // 702;} // 703;// P8: lxvd2x, xvcvdpuxds // 704;// P9: lxvx, xxswapd, xvcvdpuxds // 705;vector unsigned long long fromDiffMemConsDConvdtoull(double *ptr) { // 706; return (vector unsigned long long) { ptr[3], ptr[2] }; // 707;} // 708;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpuxds // 709;// P9: sldi 3, lxvx, xvcvdpuxds // 710;vector unsigned long long fromDiffMemVarAConvdtoull(double *arr, int elem) { // 711; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 712;} // 713;// P8: sldi 3, lxvd2x, xvcvdpuxds // 714;// P9: sldi 3, lxvx, xxswapd, xvcvdpuxds // 715;vector unsigned long long fromDiffMemVarDConvdtoull(double *arr, int elem) { // 716; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 717;} // 718;// P8: xscvdpuxds, xxspltd // 719;// P9: xscvdpuxds, xxspltd // 720;vector unsigned long long spltRegValConvdtoull(double val) { // 721; return (vector unsigned long long) val; // 722;} // 723;// P8: lxvdsx, xvcvdpuxds // 724;// P9: lxvdsx, xvcvdpuxds // 725;vector unsigned long long spltMemValConvdtoull(double *ptr) { // 726; return (vector unsigned long long)*ptr; // 727;} // 728;/*========================== unsigned long long ==============================*/ 729 730; Function Attrs: norecurse nounwind readnone 731define <4 x i32> @allZeroi() { 732entry: 733 ret <4 x i32> zeroinitializer 734; P9BE-LABEL: allZeroi 735; P9LE-LABEL: allZeroi 736; P8BE-LABEL: allZeroi 737; P8LE-LABEL: allZeroi 738; P9BE: xxlxor v2, v2, v2 739; P9BE: blr 740; P9LE: xxlxor v2, v2, v2 741; P9LE: blr 742; P8BE: xxlxor v2, v2, v2 743; P8BE: blr 744; P8LE: xxlxor v2, v2, v2 745; P8LE: blr 746} 747 748; Function Attrs: norecurse nounwind readnone 749define <4 x i32> @allOnei() { 750entry: 751 ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> 752; P9BE-LABEL: allOnei 753; P9LE-LABEL: allOnei 754; P8BE-LABEL: allOnei 755; P8LE-LABEL: allOnei 756; P9BE: xxspltib v2, 255 757; P9BE: blr 758; P9LE: xxspltib v2, 255 759; P9LE: blr 760; P8BE: vspltisb v2, -1 761; P8BE: blr 762; P8LE: vspltisb v2, -1 763; P8LE: blr 764} 765 766; Function Attrs: norecurse nounwind readnone 767define <4 x i32> @spltConst1i() { 768entry: 769 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1> 770; P9BE-LABEL: spltConst1i 771; P9LE-LABEL: spltConst1i 772; P8BE-LABEL: spltConst1i 773; P8LE-LABEL: spltConst1i 774; P9BE: vspltisw v2, 1 775; P9BE: blr 776; P9LE: vspltisw v2, 1 777; P9LE: blr 778; P8BE: vspltisw v2, 1 779; P8BE: blr 780; P8LE: vspltisw v2, 1 781; P8LE: blr 782} 783 784; Function Attrs: norecurse nounwind readnone 785define <4 x i32> @spltConst16ki() { 786entry: 787 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 788; P9BE-LABEL: spltConst16ki 789; P9LE-LABEL: spltConst16ki 790; P8BE-LABEL: spltConst16ki 791; P8LE-LABEL: spltConst16ki 792; P9BE: vspltisw v2, -15 793; P9BE: vsrw v2, v2, v2 794; P9BE: blr 795; P9LE: vspltisw v2, -15 796; P9LE: vsrw v2, v2, v2 797; P9LE: blr 798; P8BE: vspltisw v2, -15 799; P8BE: vsrw v2, v2, v2 800; P8BE: blr 801; P8LE: vspltisw v2, -15 802; P8LE: vsrw v2, v2, v2 803; P8LE: blr 804} 805 806; Function Attrs: norecurse nounwind readnone 807define <4 x i32> @spltConst32ki() { 808entry: 809 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 810; P9BE-LABEL: spltConst32ki 811; P9LE-LABEL: spltConst32ki 812; P8BE-LABEL: spltConst32ki 813; P8LE-LABEL: spltConst32ki 814; P9BE: vspltisw v2, -16 815; P9BE: vsrw v2, v2, v2 816; P9BE: blr 817; P9LE: vspltisw v2, -16 818; P9LE: vsrw v2, v2, v2 819; P9LE: blr 820; P8BE: vspltisw v2, -16 821; P8BE: vsrw v2, v2, v2 822; P8BE: blr 823; P8LE: vspltisw v2, -16 824; P8LE: vsrw v2, v2, v2 825; P8LE: blr 826} 827 828; Function Attrs: norecurse nounwind readnone 829define <4 x i32> @fromRegsi(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) { 830entry: 831 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 832 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 833 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 834 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3 835 ret <4 x i32> %vecinit3 836; P9BE-LABEL: fromRegsi 837; P9LE-LABEL: fromRegsi 838; P8BE-LABEL: fromRegsi 839; P8LE-LABEL: fromRegsi 840; P9BE-DAG: mtvsrdd [[REG1:v[0-9]+]], r3, r5 841; P9BE-DAG: mtvsrdd [[REG2:v[0-9]+]], r4, r6 842; P9BE: vmrgow v2, [[REG1]], [[REG2]] 843; P9BE: blr 844; P9LE-DAG: mtvsrdd [[REG1:v[0-9]+]], r5, r3 845; P9LE-DAG: mtvsrdd [[REG2:v[0-9]+]], r6, r4 846; P9LE: vmrgow v2, [[REG2]], [[REG1]] 847; P9LE: blr 848; P8BE-DAG: mtvsrwz {{[vf]}}[[REG1:[0-9]+]], r3 849; P8BE-DAG: mtvsrwz {{[vf]}}[[REG2:[0-9]+]], r4 850; P8BE-DAG: mtvsrwz {{[vf]}}[[REG3:[0-9]+]], r5 851; P8BE-DAG: mtvsrwz {{[vf]}}[[REG4:[0-9]+]], r6 852; P8BE-DAG: xxmrghd [[REG5:v[0-9]+]], {{[v][s]*}}[[REG1]], {{[v][s]*}}[[REG3]] 853; P8BE-DAG: xxmrghd [[REG6:v[0-9]+]], {{[v][s]*}}[[REG2]], {{[v][s]*}}[[REG4]] 854; P8BE: vmrgow v2, [[REG5]], [[REG6]] 855; P8LE-DAG: mtvsrwz {{[vf]}}[[REG1:[0-9]+]], r3 856; P8LE-DAG: mtvsrwz {{[vf]}}[[REG2:[0-9]+]], r4 857; P8LE-DAG: mtvsrwz {{[vf]}}[[REG3:[0-9]+]], r5 858; P8LE-DAG: mtvsrwz {{[vf]}}[[REG4:[0-9]+]], r6 859; P8LE: xxmrghd [[REG5:v[0-9]+]], {{[v][s]*}}[[REG3]], {{[v][s]*}}[[REG1]] 860; P8LE: xxmrghd [[REG6:v[0-9]+]], {{[v][s]*}}[[REG4]], {{[v][s]*}}[[REG2]] 861; P8LE: vmrgow v2, [[REG6]], [[REG5]] 862} 863 864; Function Attrs: norecurse nounwind readnone 865define <4 x i32> @fromDiffConstsi() { 866entry: 867 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19> 868; P9BE-LABEL: fromDiffConstsi 869; P9LE-LABEL: fromDiffConstsi 870; P8BE-LABEL: fromDiffConstsi 871; P8LE-LABEL: fromDiffConstsi 872; P9BE: lxvx 873; P9BE: blr 874; P9LE: lxvx 875; P9LE: blr 876; P8BE: lxvw4x 877; P8BE: blr 878; P8LE: lxvd2x 879; P8LE: xxswapd 880; P8LE: blr 881} 882 883; Function Attrs: norecurse nounwind readonly 884define <4 x i32> @fromDiffMemConsAi(i32* nocapture readonly %arr) { 885entry: 886 %0 = load i32, i32* %arr, align 4 887 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 888 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 1 889 %1 = load i32, i32* %arrayidx1, align 4 890 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 891 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 892 %2 = load i32, i32* %arrayidx3, align 4 893 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 894 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 3 895 %3 = load i32, i32* %arrayidx5, align 4 896 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 897 ret <4 x i32> %vecinit6 898; P9BE-LABEL: fromDiffMemConsAi 899; P9LE-LABEL: fromDiffMemConsAi 900; P8BE-LABEL: fromDiffMemConsAi 901; P8LE-LABEL: fromDiffMemConsAi 902; P9BE: lxvx 903; P9BE: blr 904; P9LE: lxvx 905; P9LE: blr 906; P8BE: lxvw4x 907; P8BE: blr 908; P8LE: lxvd2x 909; P8LE: xxswapd 910; P8LE: blr 911} 912 913; Function Attrs: norecurse nounwind readonly 914define <4 x i32> @fromDiffMemConsDi(i32* nocapture readonly %arr) { 915entry: 916 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3 917 %0 = load i32, i32* %arrayidx, align 4 918 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 919 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 920 %1 = load i32, i32* %arrayidx1, align 4 921 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 922 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 1 923 %2 = load i32, i32* %arrayidx3, align 4 924 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 925 %3 = load i32, i32* %arr, align 4 926 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 927 ret <4 x i32> %vecinit6 928; P9BE-LABEL: fromDiffMemConsDi 929; P9LE-LABEL: fromDiffMemConsDi 930; P8BE-LABEL: fromDiffMemConsDi 931; P8LE-LABEL: fromDiffMemConsDi 932; P9BE: lxvx 933; P9BE: lxvx 934; P9BE: vperm 935; P9BE: blr 936; P9LE: lxvx 937; P9LE: lxvx 938; P9LE: vperm 939; P9LE: blr 940; P8BE: lxvw4x 941; P8BE: lxvw4x 942; P8BE: vperm 943; P8BE: blr 944; P8LE: lxvd2x 945; P8LE-DAG: lxvd2x 946; P8LE-DAG: xxswapd 947; P8LE: xxswapd 948; P8LE: vperm 949; P8LE: blr 950} 951 952; Function Attrs: norecurse nounwind readonly 953define <4 x i32> @fromDiffMemVarAi(i32* nocapture readonly %arr, i32 signext %elem) { 954entry: 955 %idxprom = sext i32 %elem to i64 956 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 957 %0 = load i32, i32* %arrayidx, align 4 958 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 959 %add = add nsw i32 %elem, 1 960 %idxprom1 = sext i32 %add to i64 961 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 962 %1 = load i32, i32* %arrayidx2, align 4 963 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 964 %add4 = add nsw i32 %elem, 2 965 %idxprom5 = sext i32 %add4 to i64 966 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 967 %2 = load i32, i32* %arrayidx6, align 4 968 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 969 %add8 = add nsw i32 %elem, 3 970 %idxprom9 = sext i32 %add8 to i64 971 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 972 %3 = load i32, i32* %arrayidx10, align 4 973 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 974 ret <4 x i32> %vecinit11 975; P9BE-LABEL: fromDiffMemVarAi 976; P9LE-LABEL: fromDiffMemVarAi 977; P8BE-LABEL: fromDiffMemVarAi 978; P8LE-LABEL: fromDiffMemVarAi 979; P9BE: sldi r4, r4, 2 980; P9BE: lxvx v2, r3, r4 981; P9BE: blr 982; P9LE: sldi r4, r4, 2 983; P9LE: lxvx v2, r3, r4 984; P9LE: blr 985; P8BE: sldi r4, r4, 2 986; P8BE: lxvw4x {{[vs0-9]+}}, r3, r4 987; P8BE: blr 988; P8LE: sldi r4, r4, 2 989; P8LE: lxvd2x {{[vs0-9]+}}, r3, r4 990; P8LE: xxswapd 991; P8LE: blr 992} 993 994; Function Attrs: norecurse nounwind readonly 995define <4 x i32> @fromDiffMemVarDi(i32* nocapture readonly %arr, i32 signext %elem) { 996entry: 997 %idxprom = sext i32 %elem to i64 998 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 999 %0 = load i32, i32* %arrayidx, align 4 1000 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1001 %sub = add nsw i32 %elem, -1 1002 %idxprom1 = sext i32 %sub to i64 1003 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 1004 %1 = load i32, i32* %arrayidx2, align 4 1005 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1006 %sub4 = add nsw i32 %elem, -2 1007 %idxprom5 = sext i32 %sub4 to i64 1008 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 1009 %2 = load i32, i32* %arrayidx6, align 4 1010 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 1011 %sub8 = add nsw i32 %elem, -3 1012 %idxprom9 = sext i32 %sub8 to i64 1013 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 1014 %3 = load i32, i32* %arrayidx10, align 4 1015 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 1016 ret <4 x i32> %vecinit11 1017; P9BE-LABEL: fromDiffMemVarDi 1018; P9LE-LABEL: fromDiffMemVarDi 1019; P8BE-LABEL: fromDiffMemVarDi 1020; P8LE-LABEL: fromDiffMemVarDi 1021; P9BE: sldi {{r[0-9]+}}, r4, 2 1022; P9BE-DAG: lxvx {{v[0-9]+}}, r3, 1023; P9BE-DAG: lxvx 1024; P9BE: vperm 1025; P9BE: blr 1026; P9LE: sldi {{r[0-9]+}}, r4, 2 1027; P9LE-DAG: lxvx {{v[0-9]+}}, r3, 1028; P9LE-DAG: lxvx 1029; P9LE: vperm 1030; P9LE: blr 1031; P8BE: sldi {{r[0-9]+}}, r4, 2 1032; P8BE-DAG: lxvw4x {{v[0-9]+}}, r3, 1033; P8BE-DAG: lxvw4x 1034; P8BE: vperm 1035; P8BE: blr 1036; P8LE: sldi {{r[0-9]+}}, r4, 2 1037; P8LE-DAG: lxvd2x 1038; P8LE-DAG: lxvd2x 1039; P8LE-DAG: xxswapd 1040; P8LE: xxswapd 1041; P8LE: vperm 1042; P8LE: blr 1043} 1044 1045; Function Attrs: norecurse nounwind readonly 1046define <4 x i32> @fromRandMemConsi(i32* nocapture readonly %arr) { 1047entry: 1048 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4 1049 %0 = load i32, i32* %arrayidx, align 4 1050 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1051 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18 1052 %1 = load i32, i32* %arrayidx1, align 4 1053 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1054 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 1055 %2 = load i32, i32* %arrayidx3, align 4 1056 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 1057 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 88 1058 %3 = load i32, i32* %arrayidx5, align 4 1059 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 1060 ret <4 x i32> %vecinit6 1061; P9BE-LABEL: fromRandMemConsi 1062; P9LE-LABEL: fromRandMemConsi 1063; P8BE-LABEL: fromRandMemConsi 1064; P8LE-LABEL: fromRandMemConsi 1065; P9BE: lwz 1066; P9BE: lwz 1067; P9BE: lwz 1068; P9BE: lwz 1069; P9BE: mtvsrdd 1070; P9BE: mtvsrdd 1071; P9BE: vmrgow 1072; P9LE: lwz 1073; P9LE: lwz 1074; P9LE: lwz 1075; P9LE: lwz 1076; P9LE: mtvsrdd 1077; P9LE: mtvsrdd 1078; P9LE: vmrgow 1079; P8BE: lwz 1080; P8BE: lwz 1081; P8BE: lwz 1082; P8BE: lwz 1083; P8BE: mtvsrwz 1084; P8BE: mtvsrwz 1085; P8BE: mtvsrwz 1086; P8BE: mtvsrwz 1087; P8BE: xxmrghd 1088; P8BE: xxmrghd 1089; P8BE: vmrgow 1090; P8LE: lwz 1091; P8LE: lwz 1092; P8LE: lwz 1093; P8LE: lwz 1094; P8LE: mtvsrwz 1095; P8LE: mtvsrwz 1096; P8LE: mtvsrwz 1097; P8LE: mtvsrwz 1098; P8LE: xxmrghd 1099; P8LE: xxmrghd 1100; P8LE: vmrgow 1101} 1102 1103; Function Attrs: norecurse nounwind readonly 1104define <4 x i32> @fromRandMemVari(i32* nocapture readonly %arr, i32 signext %elem) { 1105entry: 1106 %add = add nsw i32 %elem, 4 1107 %idxprom = sext i32 %add to i64 1108 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 1109 %0 = load i32, i32* %arrayidx, align 4 1110 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1111 %add1 = add nsw i32 %elem, 1 1112 %idxprom2 = sext i32 %add1 to i64 1113 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 %idxprom2 1114 %1 = load i32, i32* %arrayidx3, align 4 1115 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1116 %add5 = add nsw i32 %elem, 2 1117 %idxprom6 = sext i32 %add5 to i64 1118 %arrayidx7 = getelementptr inbounds i32, i32* %arr, i64 %idxprom6 1119 %2 = load i32, i32* %arrayidx7, align 4 1120 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2 1121 %add9 = add nsw i32 %elem, 8 1122 %idxprom10 = sext i32 %add9 to i64 1123 %arrayidx11 = getelementptr inbounds i32, i32* %arr, i64 %idxprom10 1124 %3 = load i32, i32* %arrayidx11, align 4 1125 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3 1126 ret <4 x i32> %vecinit12 1127; P9BE-LABEL: fromRandMemVari 1128; P9LE-LABEL: fromRandMemVari 1129; P8BE-LABEL: fromRandMemVari 1130; P8LE-LABEL: fromRandMemVari 1131; P9BE: sldi r4, r4, 2 1132; P9BE: lwz 1133; P9BE: lwz 1134; P9BE: lwz 1135; P9BE: lwz 1136; P9BE: mtvsrdd 1137; P9BE: mtvsrdd 1138; P9BE: vmrgow 1139; P9LE: sldi r4, r4, 2 1140; P9LE: lwz 1141; P9LE: lwz 1142; P9LE: lwz 1143; P9LE: lwz 1144; P9LE: mtvsrdd 1145; P9LE: mtvsrdd 1146; P9LE: vmrgow 1147; P8BE: sldi r4, r4, 2 1148; P8BE: lwz 1149; P8BE: lwz 1150; P8BE: lwz 1151; P8BE: lwz 1152; P8BE: mtvsrwz 1153; P8BE: mtvsrwz 1154; P8BE: mtvsrwz 1155; P8BE: mtvsrwz 1156; P8BE: xxmrghd 1157; P8BE: xxmrghd 1158; P8BE: vmrgow 1159; P8LE: sldi r4, r4, 2 1160; P8LE: lwz 1161; P8LE: lwz 1162; P8LE: lwz 1163; P8LE: lwz 1164; P8LE: mtvsrwz 1165; P8LE: mtvsrwz 1166; P8LE: mtvsrwz 1167; P8LE: mtvsrwz 1168; P8LE: xxmrghd 1169; P8LE: xxmrghd 1170; P8LE: vmrgow 1171} 1172 1173; Function Attrs: norecurse nounwind readnone 1174define <4 x i32> @spltRegVali(i32 signext %val) { 1175entry: 1176 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0 1177 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1178 ret <4 x i32> %splat.splat 1179; P9BE-LABEL: spltRegVali 1180; P9LE-LABEL: spltRegVali 1181; P8BE-LABEL: spltRegVali 1182; P8LE-LABEL: spltRegVali 1183; P9BE: mtvsrws v2, r3 1184; P9BE: blr 1185; P9LE: mtvsrws v2, r3 1186; P9LE: blr 1187; P8BE: mtvsrwz {{[vsf0-9]+}}, r3 1188; P8BE: xxspltw v2, {{[vsf0-9]+}}, 1 1189; P8BE: blr 1190; P8LE: mtvsrwz {{[vsf0-9]+}}, r3 1191; P8LE: xxspltw v2, {{[vsf0-9]+}}, 1 1192; P8LE: blr 1193} 1194 1195; Function Attrs: norecurse nounwind readonly 1196define <4 x i32> @spltMemVali(i32* nocapture readonly %ptr) { 1197entry: 1198 %0 = load i32, i32* %ptr, align 4 1199 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 1200 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1201 ret <4 x i32> %splat.splat 1202; P9BE-LABEL: spltMemVali 1203; P9LE-LABEL: spltMemVali 1204; P8BE-LABEL: spltMemVali 1205; P8LE-LABEL: spltMemVali 1206; P9BE: lxvwsx v2, 0, r3 1207; P9BE: blr 1208; P9LE: lxvwsx v2, 0, r3 1209; P9LE: blr 1210; P8BE: lxsiwax {{[vsf0-9]+}}, 0, r3 1211; P8BE: xxspltw v2, {{[vsf0-9]+}}, 1 1212; P8BE: blr 1213; P8LE: lxsiwax {{[vsf0-9]+}}, 0, r3 1214; P8LE: xxspltw v2, {{[vsf0-9]+}}, 1 1215; P8LE: blr 1216} 1217 1218; Function Attrs: norecurse nounwind readnone 1219define <4 x i32> @spltCnstConvftoi() { 1220entry: 1221 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 1222; P9BE-LABEL: spltCnstConvftoi 1223; P9LE-LABEL: spltCnstConvftoi 1224; P8BE-LABEL: spltCnstConvftoi 1225; P8LE-LABEL: spltCnstConvftoi 1226; P9BE: vspltisw v2, 4 1227; P9BE: blr 1228; P9LE: vspltisw v2, 4 1229; P9LE: blr 1230; P8BE: vspltisw v2, 4 1231; P8BE: blr 1232; P8LE: vspltisw v2, 4 1233; P8LE: blr 1234} 1235 1236; Function Attrs: norecurse nounwind readnone 1237define <4 x i32> @fromRegsConvftoi(float %a, float %b, float %c, float %d) { 1238entry: 1239 %conv = fptosi float %a to i32 1240 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1241 %conv1 = fptosi float %b to i32 1242 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 1243 %conv3 = fptosi float %c to i32 1244 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 1245 %conv5 = fptosi float %d to i32 1246 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 1247 ret <4 x i32> %vecinit6 1248; P9BE-LABEL: fromRegsConvftoi 1249; P9LE-LABEL: fromRegsConvftoi 1250; P8BE-LABEL: fromRegsConvftoi 1251; P8LE-LABEL: fromRegsConvftoi 1252; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 1253; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 1254; P9BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1255; P9BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1256; P9BE: vmrgew v2, [[REG3]], [[REG4]] 1257; P9BE: xvcvspsxws v2, v2 1258; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 1259; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 1260; P9LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1261; P9LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1262; P9LE: vmrgew v2, [[REG4]], [[REG3]] 1263; P9LE: xvcvspsxws v2, v2 1264; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 1265; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 1266; P8BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1267; P8BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1268; P8BE: vmrgew v2, [[REG3]], [[REG4]] 1269; P8BE: xvcvspsxws v2, v2 1270; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 1271; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 1272; P8LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1273; P8LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1274; P8LE: vmrgew v2, [[REG4]], [[REG3]] 1275; P8LE: xvcvspsxws v2, v2 1276} 1277 1278; Function Attrs: norecurse nounwind readnone 1279define <4 x i32> @fromDiffConstsConvftoi() { 1280entry: 1281 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 1282; P9BE-LABEL: fromDiffConstsConvftoi 1283; P9LE-LABEL: fromDiffConstsConvftoi 1284; P8BE-LABEL: fromDiffConstsConvftoi 1285; P8LE-LABEL: fromDiffConstsConvftoi 1286; P9BE: lxvx 1287; P9BE: blr 1288; P9LE: lxvx 1289; P9LE: blr 1290; P8BE: lxvw4x 1291; P8BE: blr 1292; P8LE: lxvd2x 1293; P8LE: xxswapd 1294; P8LE: blr 1295} 1296 1297; Function Attrs: norecurse nounwind readonly 1298define <4 x i32> @fromDiffMemConsAConvftoi(float* nocapture readonly %ptr) { 1299entry: 1300 %0 = bitcast float* %ptr to <4 x float>* 1301 %1 = load <4 x float>, <4 x float>* %0, align 4 1302 %2 = fptosi <4 x float> %1 to <4 x i32> 1303 ret <4 x i32> %2 1304; P9BE-LABEL: fromDiffMemConsAConvftoi 1305; P9LE-LABEL: fromDiffMemConsAConvftoi 1306; P8BE-LABEL: fromDiffMemConsAConvftoi 1307; P8LE-LABEL: fromDiffMemConsAConvftoi 1308; P9BE: lxvx [[REG1:[vs0-9]+]], 0, r3 1309; P9BE: xvcvspsxws v2, [[REG1]] 1310; P9BE: blr 1311; P9LE: lxvx [[REG1:[vs0-9]+]], 0, r3 1312; P9LE: xvcvspsxws v2, [[REG1]] 1313; P9LE: blr 1314; P8BE: lxvw4x [[REG1:[vs0-9]+]], 0, r3 1315; P8BE: xvcvspsxws v2, [[REG1]] 1316; P8BE: blr 1317; P8LE: lxvd2x [[REG1:[vs0-9]+]], 0, r3 1318; P8LE: xxswapd v2, [[REG1]] 1319; P8LE: xvcvspsxws v2, v2 1320; P8LE: blr 1321} 1322 1323; Function Attrs: norecurse nounwind readonly 1324define <4 x i32> @fromDiffMemConsDConvftoi(float* nocapture readonly %ptr) { 1325entry: 1326 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 1327 %0 = load float, float* %arrayidx, align 4 1328 %conv = fptosi float %0 to i32 1329 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1330 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 1331 %1 = load float, float* %arrayidx1, align 4 1332 %conv2 = fptosi float %1 to i32 1333 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 1334 %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1 1335 %2 = load float, float* %arrayidx4, align 4 1336 %conv5 = fptosi float %2 to i32 1337 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 1338 %3 = load float, float* %ptr, align 4 1339 %conv8 = fptosi float %3 to i32 1340 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 1341 ret <4 x i32> %vecinit9 1342; P9BE-LABEL: fromDiffMemConsDConvftoi 1343; P9LE-LABEL: fromDiffMemConsDConvftoi 1344; P8BE-LABEL: fromDiffMemConsDConvftoi 1345; P8LE-LABEL: fromDiffMemConsDConvftoi 1346; P9BE: lxvx 1347; P9BE: lxvx 1348; P9BE: vperm 1349; P9BE: xvcvspsxws 1350; P9BE: blr 1351; P9LE: lxvx 1352; P9LE: lxvx 1353; P9LE: vperm 1354; P9LE: xvcvspsxws 1355; P9LE: blr 1356; P8BE: lxvw4x 1357; P8BE: lxvw4x 1358; P8BE: vperm 1359; P8BE: xvcvspsxws 1360; P8BE: blr 1361; P8LE: lxvd2x 1362; P8LE-DAG: lxvd2x 1363; P8LE-DAG: xxswapd 1364; P8LE: xxswapd 1365; P8LE: vperm 1366; P8LE: xvcvspsxws 1367; P8LE: blr 1368} 1369 1370; Function Attrs: norecurse nounwind readonly 1371define <4 x i32> @fromDiffMemVarAConvftoi(float* nocapture readonly %arr, i32 signext %elem) { 1372entry: 1373 %idxprom = sext i32 %elem to i64 1374 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 1375 %0 = load float, float* %arrayidx, align 4 1376 %conv = fptosi float %0 to i32 1377 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1378 %add = add nsw i32 %elem, 1 1379 %idxprom1 = sext i32 %add to i64 1380 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 1381 %1 = load float, float* %arrayidx2, align 4 1382 %conv3 = fptosi float %1 to i32 1383 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1384 %add5 = add nsw i32 %elem, 2 1385 %idxprom6 = sext i32 %add5 to i64 1386 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 1387 %2 = load float, float* %arrayidx7, align 4 1388 %conv8 = fptosi float %2 to i32 1389 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1390 %add10 = add nsw i32 %elem, 3 1391 %idxprom11 = sext i32 %add10 to i64 1392 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 1393 %3 = load float, float* %arrayidx12, align 4 1394 %conv13 = fptosi float %3 to i32 1395 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1396 ret <4 x i32> %vecinit14 1397; P9BE-LABEL: fromDiffMemVarAConvftoi 1398; P9LE-LABEL: fromDiffMemVarAConvftoi 1399; P8BE-LABEL: fromDiffMemVarAConvftoi 1400; P8LE-LABEL: fromDiffMemVarAConvftoi 1401; FIXME: implement finding consecutive loads with pre-inc 1402; P9BE: lfsux 1403; P9LE: lfsux 1404; P8BE: lfsux 1405; P8LE: lfsux 1406} 1407 1408; Function Attrs: norecurse nounwind readonly 1409define <4 x i32> @fromDiffMemVarDConvftoi(float* nocapture readonly %arr, i32 signext %elem) { 1410entry: 1411 %idxprom = sext i32 %elem to i64 1412 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 1413 %0 = load float, float* %arrayidx, align 4 1414 %conv = fptosi float %0 to i32 1415 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1416 %sub = add nsw i32 %elem, -1 1417 %idxprom1 = sext i32 %sub to i64 1418 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 1419 %1 = load float, float* %arrayidx2, align 4 1420 %conv3 = fptosi float %1 to i32 1421 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1422 %sub5 = add nsw i32 %elem, -2 1423 %idxprom6 = sext i32 %sub5 to i64 1424 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 1425 %2 = load float, float* %arrayidx7, align 4 1426 %conv8 = fptosi float %2 to i32 1427 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1428 %sub10 = add nsw i32 %elem, -3 1429 %idxprom11 = sext i32 %sub10 to i64 1430 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 1431 %3 = load float, float* %arrayidx12, align 4 1432 %conv13 = fptosi float %3 to i32 1433 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1434 ret <4 x i32> %vecinit14 1435; P9BE-LABEL: fromDiffMemVarDConvftoi 1436; P9LE-LABEL: fromDiffMemVarDConvftoi 1437; P8BE-LABEL: fromDiffMemVarDConvftoi 1438; P8LE-LABEL: fromDiffMemVarDConvftoi 1439; FIXME: implement finding consecutive loads with pre-inc 1440; P9BE: lfsux 1441; P9LE: lfsux 1442; P8BE: lfsux 1443; P8LE: lfsux 1444} 1445 1446; Function Attrs: norecurse nounwind readnone 1447define <4 x i32> @spltRegValConvftoi(float %val) { 1448entry: 1449 %conv = fptosi float %val to i32 1450 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1451 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1452 ret <4 x i32> %splat.splat 1453; P9BE-LABEL: spltRegValConvftoi 1454; P9LE-LABEL: spltRegValConvftoi 1455; P8BE-LABEL: spltRegValConvftoi 1456; P8LE-LABEL: spltRegValConvftoi 1457; P9BE: xscvdpsxws f[[REG1:[0-9]+]], f1 1458; P9BE: xxspltw v2, vs[[REG1]], 1 1459; P9BE: blr 1460; P9LE: xscvdpsxws f[[REG1:[0-9]+]], f1 1461; P9LE: xxspltw v2, vs[[REG1]], 1 1462; P9LE: blr 1463; P8BE: xscvdpsxws f[[REG1:[0-9]+]], f1 1464; P8BE: xxspltw v2, vs[[REG1]], 1 1465; P8BE: blr 1466; P8LE: xscvdpsxws f[[REG1:[0-9]+]], f1 1467; P8LE: xxspltw v2, vs[[REG1]], 1 1468; P8LE: blr 1469} 1470 1471; Function Attrs: norecurse nounwind readonly 1472define <4 x i32> @spltMemValConvftoi(float* nocapture readonly %ptr) { 1473entry: 1474 %0 = load float, float* %ptr, align 4 1475 %conv = fptosi float %0 to i32 1476 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1477 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1478 ret <4 x i32> %splat.splat 1479; P9BE-LABEL: spltMemValConvftoi 1480; P9LE-LABEL: spltMemValConvftoi 1481; P8BE-LABEL: spltMemValConvftoi 1482; P8LE-LABEL: spltMemValConvftoi 1483; P9BE: lxvwsx [[REG1:[vs0-9]+]], 0, r3 1484; P9BE: xvcvspsxws v2, [[REG1]] 1485; P9LE: [[REG1:[vs0-9]+]], 0, r3 1486; P9LE: xvcvspsxws v2, [[REG1]] 1487; P8BE: lxsspx [[REG1:f[0-9]+]], 0, r3 1488; P8BE: xscvdpsxws f[[REG2:[0-9]+]], [[REG1]] 1489; P8BE: xxspltw v2, vs[[REG2]], 1 1490; P8LE: lxsspx [[REG1:f[0-9]+]], 0, r3 1491; P8LE: xscvdpsxws f[[REG2:[vs0-9]+]], [[REG1]] 1492; P8LE: xxspltw v2, vs[[REG2]], 1 1493} 1494 1495; Function Attrs: norecurse nounwind readnone 1496define <4 x i32> @spltCnstConvdtoi() { 1497entry: 1498 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 1499; P9BE-LABEL: spltCnstConvdtoi 1500; P9LE-LABEL: spltCnstConvdtoi 1501; P8BE-LABEL: spltCnstConvdtoi 1502; P8LE-LABEL: spltCnstConvdtoi 1503; P9BE: vspltisw v2, 4 1504; P9BE: blr 1505; P9LE: vspltisw v2, 4 1506; P9LE: blr 1507; P8BE: vspltisw v2, 4 1508; P8BE: blr 1509; P8LE: vspltisw v2, 4 1510; P8LE: blr 1511} 1512 1513; Function Attrs: norecurse nounwind readnone 1514define <4 x i32> @fromRegsConvdtoi(double %a, double %b, double %c, double %d) { 1515entry: 1516 %conv = fptosi double %a to i32 1517 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1518 %conv1 = fptosi double %b to i32 1519 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 1520 %conv3 = fptosi double %c to i32 1521 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 1522 %conv5 = fptosi double %d to i32 1523 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 1524 ret <4 x i32> %vecinit6 1525; P9BE-LABEL: fromRegsConvdtoi 1526; P9LE-LABEL: fromRegsConvdtoi 1527; P8BE-LABEL: fromRegsConvdtoi 1528; P8LE-LABEL: fromRegsConvdtoi 1529; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 1530; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 1531; P9BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1532; P9BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1533; P9BE: vmrgew v2, [[REG3]], [[REG4]] 1534; P9BE: xvcvspsxws v2, v2 1535; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 1536; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 1537; P9LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1538; P9LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1539; P9LE: vmrgew v2, [[REG4]], [[REG3]] 1540; P9LE: xvcvspsxws v2, v2 1541; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 1542; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 1543; P8BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1544; P8BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1545; P8BE: vmrgew v2, [[REG3]], [[REG4]] 1546; P8BE: xvcvspsxws v2, v2 1547; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 1548; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 1549; P8LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1550; P8LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1551; P8LE: vmrgew v2, [[REG4]], [[REG3]] 1552; P8LE: xvcvspsxws v2, v2 1553} 1554 1555; Function Attrs: norecurse nounwind readnone 1556define <4 x i32> @fromDiffConstsConvdtoi() { 1557entry: 1558 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 1559; P9BE-LABEL: fromDiffConstsConvdtoi 1560; P9LE-LABEL: fromDiffConstsConvdtoi 1561; P8BE-LABEL: fromDiffConstsConvdtoi 1562; P8LE-LABEL: fromDiffConstsConvdtoi 1563; P9BE: lxvx 1564; P9BE: blr 1565; P9LE: lxvx 1566; P9LE: blr 1567; P8BE: lxvw4x 1568; P8BE: blr 1569; P8LE: lxvd2x 1570; P8LE: xxswapd 1571; P8LE: blr 1572} 1573 1574; Function Attrs: norecurse nounwind readonly 1575define <4 x i32> @fromDiffMemConsAConvdtoi(double* nocapture readonly %ptr) { 1576entry: 1577 %0 = bitcast double* %ptr to <2 x double>* 1578 %1 = load <2 x double>, <2 x double>* %0, align 8 1579 %2 = fptosi <2 x double> %1 to <2 x i32> 1580 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 2 1581 %3 = bitcast double* %arrayidx4 to <2 x double>* 1582 %4 = load <2 x double>, <2 x double>* %3, align 8 1583 %5 = fptosi <2 x double> %4 to <2 x i32> 1584 %vecinit9 = shufflevector <2 x i32> %2, <2 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 1585 ret <4 x i32> %vecinit9 1586; P9BE-LABEL: fromDiffMemConsAConvdtoi 1587; P9LE-LABEL: fromDiffMemConsAConvdtoi 1588; P8BE-LABEL: fromDiffMemConsAConvdtoi 1589; P8LE-LABEL: fromDiffMemConsAConvdtoi 1590; P9BE: lxvx [[REG1:[vs0-9]+]], 0, r3 1591; P9BE: lxvx [[REG2:[vs0-9]+]], r3, r4 1592; P9BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]] 1593; P9BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]] 1594; P9BE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]] 1595; P9BE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]] 1596; P9BE: vmrgew v2, [[REG6]], [[REG5]] 1597; P9BE: xvcvspsxws v2, v2 1598; P9LE: lxvx [[REG1:[vs0-9]+]], 0, r3 1599; P9LE: lxvx [[REG2:[vs0-9]+]], r3, r4 1600; P9LE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG2]], [[REG1]] 1601; P9LE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG2]], [[REG1]] 1602; P9LE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]] 1603; P9LE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]] 1604; P9LE: vmrgew v2, [[REG6]], [[REG5]] 1605; P9LE: xvcvspsxws v2, v2 1606; P8BE: lxvd2x [[REG1:[vs0-9]+]], 0, r3 1607; P8BE: lxvd2x [[REG2:[vs0-9]+]], r3, r4 1608; P8BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]] 1609; P8BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]] 1610; P8BE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]] 1611; P8BE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]] 1612; P8BE: vmrgew v2, [[REG6]], [[REG5]] 1613; P8BE: xvcvspsxws v2, v2 1614; P8LE: lxvd2x [[REG1:[vs0-9]+]], 0, r3 1615; P8LE: lxvd2x [[REG2:[vs0-9]+]], r3, r4 1616; P8LE-DAG: xxswapd [[REG3:[vs0-9]+]], [[REG1]] 1617; P8LE-DAG: xxswapd [[REG4:[vs0-9]+]], [[REG2]] 1618; P8LE-DAG: xxmrgld [[REG5:[vs0-9]+]], [[REG4]], [[REG3]] 1619; P8LE-DAG: xxmrghd [[REG6:[vs0-9]+]], [[REG4]], [[REG3]] 1620; P8LE-DAG: xvcvdpsp [[REG7:[vs0-9]+]], [[REG5]] 1621; P8LE-DAG: xvcvdpsp [[REG8:[vs0-9]+]], [[REG6]] 1622; P8LE: vmrgew v2, [[REG8]], [[REG7]] 1623; P8LE: xvcvspsxws v2, v2 1624} 1625 1626; Function Attrs: norecurse nounwind readonly 1627define <4 x i32> @fromDiffMemConsDConvdtoi(double* nocapture readonly %ptr) { 1628entry: 1629 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 1630 %0 = load double, double* %arrayidx, align 8 1631 %conv = fptosi double %0 to i32 1632 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1633 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 1634 %1 = load double, double* %arrayidx1, align 8 1635 %conv2 = fptosi double %1 to i32 1636 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 1637 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 1 1638 %2 = load double, double* %arrayidx4, align 8 1639 %conv5 = fptosi double %2 to i32 1640 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 1641 %3 = load double, double* %ptr, align 8 1642 %conv8 = fptosi double %3 to i32 1643 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 1644 ret <4 x i32> %vecinit9 1645; P9BE-LABEL: fromDiffMemConsDConvdtoi 1646; P9LE-LABEL: fromDiffMemConsDConvdtoi 1647; P8BE-LABEL: fromDiffMemConsDConvdtoi 1648; P8LE-LABEL: fromDiffMemConsDConvdtoi 1649; P9BE: lfd 1650; P9BE: lfd 1651; P9BE: lfd 1652; P9BE: lfd 1653; P9BE: xxmrghd 1654; P9BE: xxmrghd 1655; P9BE: xvcvdpsp 1656; P9BE: xvcvdpsp 1657; P9BE: vmrgew 1658; P9BE: xvcvspsxws v2 1659; P9LE: lfd 1660; P9LE: lfd 1661; P9LE: lfd 1662; P9LE: lfd 1663; P9LE: xxmrghd 1664; P9LE: xxmrghd 1665; P9LE: xvcvdpsp 1666; P9LE: xvcvdpsp 1667; P9LE: vmrgew 1668; P9LE: xvcvspsxws v2 1669; P8BE: lxsdx 1670; P8BE: lxsdx 1671; P8BE: lxsdx 1672; P8BE: lxsdx 1673; P8BE: xxmrghd 1674; P8BE: xxmrghd 1675; P8BE: xvcvdpsp 1676; P8BE: xvcvdpsp 1677; P8BE: vmrgew 1678; P8BE: xvcvspsxws v2 1679; P8LE: lxsdx 1680; P8LE: lxsdx 1681; P8LE: lxsdx 1682; P8LE: lxsdx 1683; P8LE: xxmrghd 1684; P8LE: xxmrghd 1685; P8LE: xvcvdpsp 1686; P8LE: xvcvdpsp 1687; P8LE: vmrgew 1688; P8LE: xvcvspsxws v2 1689} 1690 1691; Function Attrs: norecurse nounwind readonly 1692define <4 x i32> @fromDiffMemVarAConvdtoi(double* nocapture readonly %arr, i32 signext %elem) { 1693entry: 1694 %idxprom = sext i32 %elem to i64 1695 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 1696 %0 = load double, double* %arrayidx, align 8 1697 %conv = fptosi double %0 to i32 1698 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1699 %add = add nsw i32 %elem, 1 1700 %idxprom1 = sext i32 %add to i64 1701 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 1702 %1 = load double, double* %arrayidx2, align 8 1703 %conv3 = fptosi double %1 to i32 1704 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1705 %add5 = add nsw i32 %elem, 2 1706 %idxprom6 = sext i32 %add5 to i64 1707 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 1708 %2 = load double, double* %arrayidx7, align 8 1709 %conv8 = fptosi double %2 to i32 1710 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1711 %add10 = add nsw i32 %elem, 3 1712 %idxprom11 = sext i32 %add10 to i64 1713 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 1714 %3 = load double, double* %arrayidx12, align 8 1715 %conv13 = fptosi double %3 to i32 1716 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1717 ret <4 x i32> %vecinit14 1718; P9BE-LABEL: fromDiffMemVarAConvdtoi 1719; P9LE-LABEL: fromDiffMemVarAConvdtoi 1720; P8BE-LABEL: fromDiffMemVarAConvdtoi 1721; P8LE-LABEL: fromDiffMemVarAConvdtoi 1722; P9BE: lfdux 1723; P9BE: lfd 1724; P9BE: lfd 1725; P9BE: lfd 1726; P9BE: xxmrghd 1727; P9BE: xxmrghd 1728; P9BE: xvcvdpsp 1729; P9BE: xvcvdpsp 1730; P9BE: vmrgew 1731; P9BE: xvcvspsxws v2 1732; P9LE: lfdux 1733; P9LE: lfd 1734; P9LE: lfd 1735; P9LE: lfd 1736; P9LE: xxmrghd 1737; P9LE: xxmrghd 1738; P9LE: xvcvdpsp 1739; P9LE: xvcvdpsp 1740; P9LE: vmrgew 1741; P9LE: xvcvspsxws v2 1742; P8BE: lfdux 1743; P8BE: lxsdx 1744; P8BE: lxsdx 1745; P8BE: lxsdx 1746; P8BE: xxmrghd 1747; P8BE: xxmrghd 1748; P8BE: xvcvdpsp 1749; P8BE: xvcvdpsp 1750; P8BE: vmrgew 1751; P8BE: xvcvspsxws v2 1752; P8LE: lfdux 1753; P8LE: lxsdx 1754; P8LE: lxsdx 1755; P8LE: lxsdx 1756; P8LE: xxmrghd 1757; P8LE: xxmrghd 1758; P8LE: xvcvdpsp 1759; P8LE: xvcvdpsp 1760; P8LE: vmrgew 1761; P8LE: xvcvspsxws v2 1762} 1763 1764; Function Attrs: norecurse nounwind readonly 1765define <4 x i32> @fromDiffMemVarDConvdtoi(double* nocapture readonly %arr, i32 signext %elem) { 1766entry: 1767 %idxprom = sext i32 %elem to i64 1768 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 1769 %0 = load double, double* %arrayidx, align 8 1770 %conv = fptosi double %0 to i32 1771 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1772 %sub = add nsw i32 %elem, -1 1773 %idxprom1 = sext i32 %sub to i64 1774 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 1775 %1 = load double, double* %arrayidx2, align 8 1776 %conv3 = fptosi double %1 to i32 1777 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1778 %sub5 = add nsw i32 %elem, -2 1779 %idxprom6 = sext i32 %sub5 to i64 1780 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 1781 %2 = load double, double* %arrayidx7, align 8 1782 %conv8 = fptosi double %2 to i32 1783 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1784 %sub10 = add nsw i32 %elem, -3 1785 %idxprom11 = sext i32 %sub10 to i64 1786 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 1787 %3 = load double, double* %arrayidx12, align 8 1788 %conv13 = fptosi double %3 to i32 1789 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1790 ret <4 x i32> %vecinit14 1791; P9BE-LABEL: fromDiffMemVarDConvdtoi 1792; P9LE-LABEL: fromDiffMemVarDConvdtoi 1793; P8BE-LABEL: fromDiffMemVarDConvdtoi 1794; P8LE-LABEL: fromDiffMemVarDConvdtoi 1795; P9BE: lfdux 1796; P9BE: lfd 1797; P9BE: lfd 1798; P9BE: lfd 1799; P9BE: xxmrghd 1800; P9BE: xxmrghd 1801; P9BE: xvcvdpsp 1802; P9BE: xvcvdpsp 1803; P9BE: vmrgew 1804; P9BE: xvcvspsxws v2 1805; P9LE: lfdux 1806; P9LE: lfd 1807; P9LE: lfd 1808; P9LE: lfd 1809; P9LE: xxmrghd 1810; P9LE: xxmrghd 1811; P9LE: xvcvdpsp 1812; P9LE: xvcvdpsp 1813; P9LE: vmrgew 1814; P9LE: xvcvspsxws v2 1815; P8BE: lfdux 1816; P8BE: lxsdx 1817; P8BE: lxsdx 1818; P8BE: lxsdx 1819; P8BE: xxmrghd 1820; P8BE: xxmrghd 1821; P8BE: xvcvdpsp 1822; P8BE: xvcvdpsp 1823; P8BE: vmrgew 1824; P8BE: xvcvspsxws v2 1825; P8LE: lfdux 1826; P8LE: lxsdx 1827; P8LE: lxsdx 1828; P8LE: lxsdx 1829; P8LE: xxmrghd 1830; P8LE: xxmrghd 1831; P8LE: xvcvdpsp 1832; P8LE: xvcvdpsp 1833; P8LE: vmrgew 1834; P8LE: xvcvspsxws v2 1835} 1836 1837; Function Attrs: norecurse nounwind readnone 1838define <4 x i32> @spltRegValConvdtoi(double %val) { 1839entry: 1840 %conv = fptosi double %val to i32 1841 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1842 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1843 ret <4 x i32> %splat.splat 1844; P9BE-LABEL: spltRegValConvdtoi 1845; P9LE-LABEL: spltRegValConvdtoi 1846; P8BE-LABEL: spltRegValConvdtoi 1847; P8LE-LABEL: spltRegValConvdtoi 1848; P9BE: xscvdpsxws 1849; P9BE: xxspltw 1850; P9BE: blr 1851; P9LE: xscvdpsxws 1852; P9LE: xxspltw 1853; P9LE: blr 1854; P8BE: xscvdpsxws 1855; P8BE: xxspltw 1856; P8BE: blr 1857; P8LE: xscvdpsxws 1858; P8LE: xxspltw 1859; P8LE: blr 1860} 1861 1862; Function Attrs: norecurse nounwind readonly 1863define <4 x i32> @spltMemValConvdtoi(double* nocapture readonly %ptr) { 1864entry: 1865 %0 = load double, double* %ptr, align 8 1866 %conv = fptosi double %0 to i32 1867 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1868 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1869 ret <4 x i32> %splat.splat 1870; P9BE-LABEL: spltMemValConvdtoi 1871; P9LE-LABEL: spltMemValConvdtoi 1872; P8BE-LABEL: spltMemValConvdtoi 1873; P8LE-LABEL: spltMemValConvdtoi 1874; P9BE: lfd 1875; P9BE: xscvdpsxws 1876; P9BE: xxspltw 1877; P9BE: blr 1878; P9LE: lfd 1879; P9LE: xscvdpsxws 1880; P9LE: xxspltw 1881; P9LE: blr 1882; P8BE: lxsdx 1883; P8BE: xscvdpsxws 1884; P8BE: xxspltw 1885; P8BE: blr 1886; P8LE: lxsdx 1887; P8LE: xscvdpsxws 1888; P8LE: xxspltw 1889; P8LE: blr 1890} 1891; Function Attrs: norecurse nounwind readnone 1892define <4 x i32> @allZeroui() { 1893entry: 1894 ret <4 x i32> zeroinitializer 1895; P9BE-LABEL: allZeroui 1896; P9LE-LABEL: allZeroui 1897; P8BE-LABEL: allZeroui 1898; P8LE-LABEL: allZeroui 1899; P9BE: xxlxor v2, v2, v2 1900; P9BE: blr 1901; P9LE: xxlxor v2, v2, v2 1902; P9LE: blr 1903; P8BE: xxlxor v2, v2, v2 1904; P8BE: blr 1905; P8LE: xxlxor v2, v2, v2 1906; P8LE: blr 1907} 1908 1909; Function Attrs: norecurse nounwind readnone 1910define <4 x i32> @allOneui() { 1911entry: 1912 ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> 1913; P9BE-LABEL: allOneui 1914; P9LE-LABEL: allOneui 1915; P8BE-LABEL: allOneui 1916; P8LE-LABEL: allOneui 1917; P9BE: xxspltib v2, 255 1918; P9BE: blr 1919; P9LE: xxspltib v2, 255 1920; P9LE: blr 1921; P8BE: vspltisb v2, -1 1922; P8BE: blr 1923; P8LE: vspltisb v2, -1 1924; P8LE: blr 1925} 1926 1927; Function Attrs: norecurse nounwind readnone 1928define <4 x i32> @spltConst1ui() { 1929entry: 1930 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1> 1931; P9BE-LABEL: spltConst1ui 1932; P9LE-LABEL: spltConst1ui 1933; P8BE-LABEL: spltConst1ui 1934; P8LE-LABEL: spltConst1ui 1935; P9BE: vspltisw v2, 1 1936; P9BE: blr 1937; P9LE: vspltisw v2, 1 1938; P9LE: blr 1939; P8BE: vspltisw v2, 1 1940; P8BE: blr 1941; P8LE: vspltisw v2, 1 1942; P8LE: blr 1943} 1944 1945; Function Attrs: norecurse nounwind readnone 1946define <4 x i32> @spltConst16kui() { 1947entry: 1948 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 1949; P9BE-LABEL: spltConst16kui 1950; P9LE-LABEL: spltConst16kui 1951; P8BE-LABEL: spltConst16kui 1952; P8LE-LABEL: spltConst16kui 1953; P9BE: vspltisw v2, -15 1954; P9BE: vsrw v2, v2, v2 1955; P9BE: blr 1956; P9LE: vspltisw v2, -15 1957; P9LE: vsrw v2, v2, v2 1958; P9LE: blr 1959; P8BE: vspltisw v2, -15 1960; P8BE: vsrw v2, v2, v2 1961; P8BE: blr 1962; P8LE: vspltisw v2, -15 1963; P8LE: vsrw v2, v2, v2 1964; P8LE: blr 1965} 1966 1967; Function Attrs: norecurse nounwind readnone 1968define <4 x i32> @spltConst32kui() { 1969entry: 1970 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 1971; P9BE-LABEL: spltConst32kui 1972; P9LE-LABEL: spltConst32kui 1973; P8BE-LABEL: spltConst32kui 1974; P8LE-LABEL: spltConst32kui 1975; P9BE: vspltisw v2, -16 1976; P9BE: vsrw v2, v2, v2 1977; P9BE: blr 1978; P9LE: vspltisw v2, -16 1979; P9LE: vsrw v2, v2, v2 1980; P9LE: blr 1981; P8BE: vspltisw v2, -16 1982; P8BE: vsrw v2, v2, v2 1983; P8BE: blr 1984; P8LE: vspltisw v2, -16 1985; P8LE: vsrw v2, v2, v2 1986; P8LE: blr 1987} 1988 1989; Function Attrs: norecurse nounwind readnone 1990define <4 x i32> @fromRegsui(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c, i32 zeroext %d) { 1991entry: 1992 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 1993 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 1994 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 1995 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3 1996 ret <4 x i32> %vecinit3 1997; P9BE-LABEL: fromRegsui 1998; P9LE-LABEL: fromRegsui 1999; P8BE-LABEL: fromRegsui 2000; P8LE-LABEL: fromRegsui 2001; P9BE-DAG: mtvsrdd [[REG1:v[0-9]+]], r3, r5 2002; P9BE-DAG: mtvsrdd [[REG2:v[0-9]+]], r4, r6 2003; P9BE: vmrgow v2, [[REG1]], [[REG2]] 2004; P9BE: blr 2005; P9LE-DAG: mtvsrdd [[REG1:v[0-9]+]], r5, r3 2006; P9LE-DAG: mtvsrdd [[REG2:v[0-9]+]], r6, r4 2007; P9LE: vmrgow v2, [[REG2]], [[REG1]] 2008; P9LE: blr 2009; P8BE-DAG: mtvsrwz {{[vf]}}[[REG1:[0-9]+]], r3 2010; P8BE-DAG: mtvsrwz {{[vf]}}[[REG2:[0-9]+]], r4 2011; P8BE-DAG: mtvsrwz {{[vf]}}[[REG3:[0-9]+]], r5 2012; P8BE-DAG: mtvsrwz {{[vf]}}[[REG4:[0-9]+]], r6 2013; P8BE-DAG: xxmrghd [[REG5:v[0-9]+]], {{[v][s]*}}[[REG1]], {{[v][s]*}}[[REG3]] 2014; P8BE-DAG: xxmrghd [[REG6:v[0-9]+]], {{[v][s]*}}[[REG2]], {{[v][s]*}}[[REG4]] 2015; P8BE: vmrgow v2, [[REG5]], [[REG6]] 2016; P8LE-DAG: mtvsrwz {{[vf]}}[[REG1:[0-9]+]], r3 2017; P8LE-DAG: mtvsrwz {{[vf]}}[[REG2:[0-9]+]], r4 2018; P8LE-DAG: mtvsrwz {{[vf]}}[[REG3:[0-9]+]], r5 2019; P8LE-DAG: mtvsrwz {{[vf]}}[[REG4:[0-9]+]], r6 2020; P8LE: xxmrghd [[REG5:v[0-9]+]], {{[v][s]*}}[[REG3]], {{[v][s]*}}[[REG1]] 2021; P8LE: xxmrghd [[REG6:v[0-9]+]], {{[v][s]*}}[[REG4]], {{[v][s]*}}[[REG2]] 2022; P8LE: vmrgow v2, [[REG6]], [[REG5]] 2023} 2024 2025; Function Attrs: norecurse nounwind readnone 2026define <4 x i32> @fromDiffConstsui() { 2027entry: 2028 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19> 2029; P9BE-LABEL: fromDiffConstsui 2030; P9LE-LABEL: fromDiffConstsui 2031; P8BE-LABEL: fromDiffConstsui 2032; P8LE-LABEL: fromDiffConstsui 2033; P9BE: lxvx 2034; P9BE: blr 2035; P9LE: lxvx 2036; P9LE: blr 2037; P8BE: lxvw4x 2038; P8BE: blr 2039; P8LE: lxvd2x 2040; P8LE: xxswapd 2041; P8LE: blr 2042} 2043 2044; Function Attrs: norecurse nounwind readonly 2045define <4 x i32> @fromDiffMemConsAui(i32* nocapture readonly %arr) { 2046entry: 2047 %0 = load i32, i32* %arr, align 4 2048 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2049 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 1 2050 %1 = load i32, i32* %arrayidx1, align 4 2051 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2052 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 2053 %2 = load i32, i32* %arrayidx3, align 4 2054 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2055 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 3 2056 %3 = load i32, i32* %arrayidx5, align 4 2057 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2058 ret <4 x i32> %vecinit6 2059; P9BE-LABEL: fromDiffMemConsAui 2060; P9LE-LABEL: fromDiffMemConsAui 2061; P8BE-LABEL: fromDiffMemConsAui 2062; P8LE-LABEL: fromDiffMemConsAui 2063; P9BE: lxvx 2064; P9BE: blr 2065; P9LE: lxvx 2066; P9LE: blr 2067; P8BE: lxvw4x 2068; P8BE: blr 2069; P8LE: lxvd2x 2070; P8LE: xxswapd 2071; P8LE: blr 2072} 2073 2074; Function Attrs: norecurse nounwind readonly 2075define <4 x i32> @fromDiffMemConsDui(i32* nocapture readonly %arr) { 2076entry: 2077 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3 2078 %0 = load i32, i32* %arrayidx, align 4 2079 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2080 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 2081 %1 = load i32, i32* %arrayidx1, align 4 2082 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2083 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 1 2084 %2 = load i32, i32* %arrayidx3, align 4 2085 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2086 %3 = load i32, i32* %arr, align 4 2087 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2088 ret <4 x i32> %vecinit6 2089; P9BE-LABEL: fromDiffMemConsDui 2090; P9LE-LABEL: fromDiffMemConsDui 2091; P8BE-LABEL: fromDiffMemConsDui 2092; P8LE-LABEL: fromDiffMemConsDui 2093; P9BE: lxvx 2094; P9BE: lxvx 2095; P9BE: vperm 2096; P9BE: blr 2097; P9LE: lxvx 2098; P9LE: lxvx 2099; P9LE: vperm 2100; P9LE: blr 2101; P8BE: lxvw4x 2102; P8BE: lxvw4x 2103; P8BE: vperm 2104; P8BE: blr 2105; P8LE: lxvd2x 2106; P8LE-DAG: lxvd2x 2107; P8LE-DAG: xxswapd 2108; P8LE: xxswapd 2109; P8LE: vperm 2110; P8LE: blr 2111} 2112 2113; Function Attrs: norecurse nounwind readonly 2114define <4 x i32> @fromDiffMemVarAui(i32* nocapture readonly %arr, i32 signext %elem) { 2115entry: 2116 %idxprom = sext i32 %elem to i64 2117 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2118 %0 = load i32, i32* %arrayidx, align 4 2119 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2120 %add = add nsw i32 %elem, 1 2121 %idxprom1 = sext i32 %add to i64 2122 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 2123 %1 = load i32, i32* %arrayidx2, align 4 2124 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2125 %add4 = add nsw i32 %elem, 2 2126 %idxprom5 = sext i32 %add4 to i64 2127 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 2128 %2 = load i32, i32* %arrayidx6, align 4 2129 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 2130 %add8 = add nsw i32 %elem, 3 2131 %idxprom9 = sext i32 %add8 to i64 2132 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 2133 %3 = load i32, i32* %arrayidx10, align 4 2134 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 2135 ret <4 x i32> %vecinit11 2136; P9BE-LABEL: fromDiffMemVarAui 2137; P9LE-LABEL: fromDiffMemVarAui 2138; P8BE-LABEL: fromDiffMemVarAui 2139; P8LE-LABEL: fromDiffMemVarAui 2140; P9BE: sldi r4, r4, 2 2141; P9BE: lxvx v2, r3, r4 2142; P9BE: blr 2143; P9LE: sldi r4, r4, 2 2144; P9LE: lxvx v2, r3, r4 2145; P9LE: blr 2146; P8BE: sldi r4, r4, 2 2147; P8BE: lxvw4x {{[vs0-9]+}}, r3, r4 2148; P8BE: blr 2149; P8LE: sldi r4, r4, 2 2150; P8LE: lxvd2x {{[vs0-9]+}}, r3, r4 2151; P8LE: xxswapd 2152; P8LE: blr 2153} 2154 2155; Function Attrs: norecurse nounwind readonly 2156define <4 x i32> @fromDiffMemVarDui(i32* nocapture readonly %arr, i32 signext %elem) { 2157entry: 2158 %idxprom = sext i32 %elem to i64 2159 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2160 %0 = load i32, i32* %arrayidx, align 4 2161 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2162 %sub = add nsw i32 %elem, -1 2163 %idxprom1 = sext i32 %sub to i64 2164 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 2165 %1 = load i32, i32* %arrayidx2, align 4 2166 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2167 %sub4 = add nsw i32 %elem, -2 2168 %idxprom5 = sext i32 %sub4 to i64 2169 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 2170 %2 = load i32, i32* %arrayidx6, align 4 2171 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 2172 %sub8 = add nsw i32 %elem, -3 2173 %idxprom9 = sext i32 %sub8 to i64 2174 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 2175 %3 = load i32, i32* %arrayidx10, align 4 2176 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 2177 ret <4 x i32> %vecinit11 2178; P9BE-LABEL: fromDiffMemVarDui 2179; P9LE-LABEL: fromDiffMemVarDui 2180; P8BE-LABEL: fromDiffMemVarDui 2181; P8LE-LABEL: fromDiffMemVarDui 2182; P9BE-DAG: sldi {{r[0-9]+}}, r4, 2 2183; P9BE-DAG: lxvx {{v[0-9]+}}, r3 2184; P9BE-DAG: lxvx 2185; P9BE: vperm 2186; P9BE: blr 2187; P9LE-DAG: sldi {{r[0-9]+}}, r4, 2 2188; P9LE-DAG: lxvx {{v[0-9]+}}, r3 2189; P9LE-DAG: lxvx 2190; P9LE: vperm 2191; P9LE: blr 2192; P8BE-DAG: sldi {{r[0-9]+}}, r4, 2 2193; P8BE-DAG: lxvw4x {{v[0-9]+}}, r3 2194; P8BE-DAG: lxvw4x 2195; P8BE: vperm 2196; P8BE: blr 2197; P8LE-DAG: sldi {{r[0-9]+}}, r4, 2 2198; P8LE-DAG: lxvd2x 2199; P8LE-DAG: lxvd2x 2200; P8LE-DAG: xxswapd 2201; P8LE: xxswapd 2202; P8LE: vperm 2203; P8LE: blr 2204} 2205 2206; Function Attrs: norecurse nounwind readonly 2207define <4 x i32> @fromRandMemConsui(i32* nocapture readonly %arr) { 2208entry: 2209 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4 2210 %0 = load i32, i32* %arrayidx, align 4 2211 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2212 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18 2213 %1 = load i32, i32* %arrayidx1, align 4 2214 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2215 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 2216 %2 = load i32, i32* %arrayidx3, align 4 2217 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2218 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 88 2219 %3 = load i32, i32* %arrayidx5, align 4 2220 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2221 ret <4 x i32> %vecinit6 2222; P9BE-LABEL: fromRandMemConsui 2223; P9LE-LABEL: fromRandMemConsui 2224; P8BE-LABEL: fromRandMemConsui 2225; P8LE-LABEL: fromRandMemConsui 2226; P9BE: lwz 2227; P9BE: lwz 2228; P9BE: lwz 2229; P9BE: lwz 2230; P9BE: mtvsrdd 2231; P9BE: mtvsrdd 2232; P9BE: vmrgow 2233; P9LE: lwz 2234; P9LE: lwz 2235; P9LE: lwz 2236; P9LE: lwz 2237; P9LE: mtvsrdd 2238; P9LE: mtvsrdd 2239; P9LE: vmrgow 2240; P8BE: lwz 2241; P8BE: lwz 2242; P8BE: lwz 2243; P8BE: lwz 2244; P8BE: mtvsrwz 2245; P8BE: mtvsrwz 2246; P8BE: mtvsrwz 2247; P8BE: mtvsrwz 2248; P8BE: xxmrghd 2249; P8BE: xxmrghd 2250; P8BE: vmrgow 2251; P8LE: lwz 2252; P8LE: lwz 2253; P8LE: lwz 2254; P8LE: lwz 2255; P8LE: mtvsrwz 2256; P8LE: mtvsrwz 2257; P8LE: mtvsrwz 2258; P8LE: mtvsrwz 2259; P8LE: xxmrghd 2260; P8LE: xxmrghd 2261; P8LE: vmrgow 2262} 2263 2264; Function Attrs: norecurse nounwind readonly 2265define <4 x i32> @fromRandMemVarui(i32* nocapture readonly %arr, i32 signext %elem) { 2266entry: 2267 %add = add nsw i32 %elem, 4 2268 %idxprom = sext i32 %add to i64 2269 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2270 %0 = load i32, i32* %arrayidx, align 4 2271 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2272 %add1 = add nsw i32 %elem, 1 2273 %idxprom2 = sext i32 %add1 to i64 2274 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 %idxprom2 2275 %1 = load i32, i32* %arrayidx3, align 4 2276 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2277 %add5 = add nsw i32 %elem, 2 2278 %idxprom6 = sext i32 %add5 to i64 2279 %arrayidx7 = getelementptr inbounds i32, i32* %arr, i64 %idxprom6 2280 %2 = load i32, i32* %arrayidx7, align 4 2281 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2 2282 %add9 = add nsw i32 %elem, 8 2283 %idxprom10 = sext i32 %add9 to i64 2284 %arrayidx11 = getelementptr inbounds i32, i32* %arr, i64 %idxprom10 2285 %3 = load i32, i32* %arrayidx11, align 4 2286 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3 2287 ret <4 x i32> %vecinit12 2288; P9BE-LABEL: fromRandMemVarui 2289; P9LE-LABEL: fromRandMemVarui 2290; P8BE-LABEL: fromRandMemVarui 2291; P8LE-LABEL: fromRandMemVarui 2292; P9BE: sldi r4, r4, 2 2293; P9BE: lwz 2294; P9BE: lwz 2295; P9BE: lwz 2296; P9BE: lwz 2297; P9BE: mtvsrdd 2298; P9BE: mtvsrdd 2299; P9BE: vmrgow 2300; P9LE: sldi r4, r4, 2 2301; P9LE: lwz 2302; P9LE: lwz 2303; P9LE: lwz 2304; P9LE: lwz 2305; P9LE: mtvsrdd 2306; P9LE: mtvsrdd 2307; P9LE: vmrgow 2308; P8BE: sldi r4, r4, 2 2309; P8BE: lwz 2310; P8BE: lwz 2311; P8BE: lwz 2312; P8BE: lwz 2313; P8BE: mtvsrwz 2314; P8BE: mtvsrwz 2315; P8BE: mtvsrwz 2316; P8BE: mtvsrwz 2317; P8BE: xxmrghd 2318; P8BE: xxmrghd 2319; P8BE: vmrgow 2320; P8LE: sldi r4, r4, 2 2321; P8LE: lwz 2322; P8LE: lwz 2323; P8LE: lwz 2324; P8LE: lwz 2325; P8LE: mtvsrwz 2326; P8LE: mtvsrwz 2327; P8LE: mtvsrwz 2328; P8LE: mtvsrwz 2329; P8LE: xxmrghd 2330; P8LE: xxmrghd 2331; P8LE: vmrgow 2332} 2333 2334; Function Attrs: norecurse nounwind readnone 2335define <4 x i32> @spltRegValui(i32 zeroext %val) { 2336entry: 2337 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0 2338 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2339 ret <4 x i32> %splat.splat 2340; P9BE-LABEL: spltRegValui 2341; P9LE-LABEL: spltRegValui 2342; P8BE-LABEL: spltRegValui 2343; P8LE-LABEL: spltRegValui 2344; P9BE: mtvsrws v2, r3 2345; P9BE: blr 2346; P9LE: mtvsrws v2, r3 2347; P9LE: blr 2348; P8BE: mtvsrwz {{[vsf0-9]+}}, r3 2349; P8BE: xxspltw v2, {{[vsf0-9]+}}, 1 2350; P8BE: blr 2351; P8LE: mtvsrwz {{[vsf0-9]+}}, r3 2352; P8LE: xxspltw v2, {{[vsf0-9]+}}, 1 2353; P8LE: blr 2354} 2355 2356; Function Attrs: norecurse nounwind readonly 2357define <4 x i32> @spltMemValui(i32* nocapture readonly %ptr) { 2358entry: 2359 %0 = load i32, i32* %ptr, align 4 2360 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 2361 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2362 ret <4 x i32> %splat.splat 2363; P9BE-LABEL: spltMemValui 2364; P9LE-LABEL: spltMemValui 2365; P8BE-LABEL: spltMemValui 2366; P8LE-LABEL: spltMemValui 2367; P9BE: lxvwsx v2, 0, r3 2368; P9BE: blr 2369; P9LE: lxvwsx v2, 0, r3 2370; P9LE: blr 2371; P8BE: lxsiwax {{[vsf0-9]+}}, 0, r3 2372; P8BE: xxspltw v2, {{[vsf0-9]+}}, 1 2373; P8BE: blr 2374; P8LE: lxsiwax {{[vsf0-9]+}}, 0, r3 2375; P8LE: xxspltw v2, {{[vsf0-9]+}}, 1 2376; P8LE: blr 2377} 2378 2379; Function Attrs: norecurse nounwind readnone 2380define <4 x i32> @spltCnstConvftoui() { 2381entry: 2382 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 2383; P9BE-LABEL: spltCnstConvftoui 2384; P9LE-LABEL: spltCnstConvftoui 2385; P8BE-LABEL: spltCnstConvftoui 2386; P8LE-LABEL: spltCnstConvftoui 2387; P9BE: vspltisw v2, 4 2388; P9BE: blr 2389; P9LE: vspltisw v2, 4 2390; P9LE: blr 2391; P8BE: vspltisw v2, 4 2392; P8BE: blr 2393; P8LE: vspltisw v2, 4 2394; P8LE: blr 2395} 2396 2397; Function Attrs: norecurse nounwind readnone 2398define <4 x i32> @fromRegsConvftoui(float %a, float %b, float %c, float %d) { 2399entry: 2400 %conv = fptoui float %a to i32 2401 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2402 %conv1 = fptoui float %b to i32 2403 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 2404 %conv3 = fptoui float %c to i32 2405 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 2406 %conv5 = fptoui float %d to i32 2407 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 2408 ret <4 x i32> %vecinit6 2409; P9BE-LABEL: fromRegsConvftoui 2410; P9LE-LABEL: fromRegsConvftoui 2411; P8BE-LABEL: fromRegsConvftoui 2412; P8LE-LABEL: fromRegsConvftoui 2413; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 2414; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 2415; P9BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2416; P9BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2417; P9BE: vmrgew v2, [[REG3]], [[REG4]] 2418; P9BE: xvcvspuxws v2, v2 2419; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 2420; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 2421; P9LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2422; P9LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2423; P9LE: vmrgew v2, [[REG4]], [[REG3]] 2424; P9LE: xvcvspuxws v2, v2 2425; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 2426; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 2427; P8BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2428; P8BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2429; P8BE: vmrgew v2, [[REG3]], [[REG4]] 2430; P8BE: xvcvspuxws v2, v2 2431; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 2432; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 2433; P8LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2434; P8LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2435; P8LE: vmrgew v2, [[REG4]], [[REG3]] 2436; P8LE: xvcvspuxws v2, v2 2437} 2438 2439; Function Attrs: norecurse nounwind readnone 2440define <4 x i32> @fromDiffConstsConvftoui() { 2441entry: 2442 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 2443; P9BE-LABEL: fromDiffConstsConvftoui 2444; P9LE-LABEL: fromDiffConstsConvftoui 2445; P8BE-LABEL: fromDiffConstsConvftoui 2446; P8LE-LABEL: fromDiffConstsConvftoui 2447; P9BE: lxvx 2448; P9BE: blr 2449; P9LE: lxvx 2450; P9LE: blr 2451; P8BE: lxvw4x 2452; P8BE: blr 2453; P8LE: lxvd2x 2454; P8LE: xxswapd 2455; P8LE: blr 2456} 2457 2458; Function Attrs: norecurse nounwind readonly 2459define <4 x i32> @fromDiffMemConsAConvftoui(float* nocapture readonly %ptr) { 2460entry: 2461 %0 = bitcast float* %ptr to <4 x float>* 2462 %1 = load <4 x float>, <4 x float>* %0, align 4 2463 %2 = fptoui <4 x float> %1 to <4 x i32> 2464 ret <4 x i32> %2 2465; P9BE-LABEL: fromDiffMemConsAConvftoui 2466; P9LE-LABEL: fromDiffMemConsAConvftoui 2467; P8BE-LABEL: fromDiffMemConsAConvftoui 2468; P8LE-LABEL: fromDiffMemConsAConvftoui 2469; P9BE: lxvx [[REG1:[vs0-9]+]], 0, r3 2470; P9BE: xvcvspuxws v2, [[REG1]] 2471; P9BE: blr 2472; P9LE: lxvx [[REG1:[vs0-9]+]], 0, r3 2473; P9LE: xvcvspuxws v2, [[REG1]] 2474; P9LE: blr 2475; P8BE: lxvw4x [[REG1:[vs0-9]+]], 0, r3 2476; P8BE: xvcvspuxws v2, [[REG1]] 2477; P8BE: blr 2478; P8LE: lxvd2x [[REG1:[vs0-9]+]], 0, r3 2479; P8LE: xxswapd v2, [[REG1]] 2480; P8LE: xvcvspuxws v2, v2 2481; P8LE: blr 2482} 2483 2484; Function Attrs: norecurse nounwind readonly 2485define <4 x i32> @fromDiffMemConsDConvftoui(float* nocapture readonly %ptr) { 2486entry: 2487 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 2488 %0 = load float, float* %arrayidx, align 4 2489 %conv = fptoui float %0 to i32 2490 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2491 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 2492 %1 = load float, float* %arrayidx1, align 4 2493 %conv2 = fptoui float %1 to i32 2494 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 2495 %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1 2496 %2 = load float, float* %arrayidx4, align 4 2497 %conv5 = fptoui float %2 to i32 2498 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 2499 %3 = load float, float* %ptr, align 4 2500 %conv8 = fptoui float %3 to i32 2501 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 2502 ret <4 x i32> %vecinit9 2503; P9BE-LABEL: fromDiffMemConsDConvftoui 2504; P9LE-LABEL: fromDiffMemConsDConvftoui 2505; P8BE-LABEL: fromDiffMemConsDConvftoui 2506; P8LE-LABEL: fromDiffMemConsDConvftoui 2507; P9BE: lxvx 2508; P9BE: lxvx 2509; P9BE: vperm 2510; P9BE: xvcvspuxws 2511; P9BE: blr 2512; P9LE: lxvx 2513; P9LE: lxvx 2514; P9LE: vperm 2515; P9LE: xvcvspuxws 2516; P9LE: blr 2517; P8BE: lxvw4x 2518; P8BE: lxvw4x 2519; P8BE: vperm 2520; P8BE: xvcvspuxws 2521; P8BE: blr 2522; P8LE: lxvd2x 2523; P8LE-DAG: lxvd2x 2524; P8LE-DAG: xxswapd 2525; P8LE: xxswapd 2526; P8LE: vperm 2527; P8LE: xvcvspuxws 2528; P8LE: blr 2529} 2530 2531; Function Attrs: norecurse nounwind readonly 2532define <4 x i32> @fromDiffMemVarAConvftoui(float* nocapture readonly %arr, i32 signext %elem) { 2533entry: 2534 %idxprom = sext i32 %elem to i64 2535 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 2536 %0 = load float, float* %arrayidx, align 4 2537 %conv = fptoui float %0 to i32 2538 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2539 %add = add nsw i32 %elem, 1 2540 %idxprom1 = sext i32 %add to i64 2541 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 2542 %1 = load float, float* %arrayidx2, align 4 2543 %conv3 = fptoui float %1 to i32 2544 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2545 %add5 = add nsw i32 %elem, 2 2546 %idxprom6 = sext i32 %add5 to i64 2547 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 2548 %2 = load float, float* %arrayidx7, align 4 2549 %conv8 = fptoui float %2 to i32 2550 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2551 %add10 = add nsw i32 %elem, 3 2552 %idxprom11 = sext i32 %add10 to i64 2553 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 2554 %3 = load float, float* %arrayidx12, align 4 2555 %conv13 = fptoui float %3 to i32 2556 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2557 ret <4 x i32> %vecinit14 2558; P9BE-LABEL: fromDiffMemVarAConvftoui 2559; P9LE-LABEL: fromDiffMemVarAConvftoui 2560; P8BE-LABEL: fromDiffMemVarAConvftoui 2561; P8LE-LABEL: fromDiffMemVarAConvftoui 2562; FIXME: implement finding consecutive loads with pre-inc 2563; P9BE: lfsux 2564; P9LE: lfsux 2565; P8BE: lfsux 2566; P8LE: lfsux 2567} 2568 2569; Function Attrs: norecurse nounwind readonly 2570define <4 x i32> @fromDiffMemVarDConvftoui(float* nocapture readonly %arr, i32 signext %elem) { 2571entry: 2572 %idxprom = sext i32 %elem to i64 2573 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 2574 %0 = load float, float* %arrayidx, align 4 2575 %conv = fptoui float %0 to i32 2576 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2577 %sub = add nsw i32 %elem, -1 2578 %idxprom1 = sext i32 %sub to i64 2579 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 2580 %1 = load float, float* %arrayidx2, align 4 2581 %conv3 = fptoui float %1 to i32 2582 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2583 %sub5 = add nsw i32 %elem, -2 2584 %idxprom6 = sext i32 %sub5 to i64 2585 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 2586 %2 = load float, float* %arrayidx7, align 4 2587 %conv8 = fptoui float %2 to i32 2588 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2589 %sub10 = add nsw i32 %elem, -3 2590 %idxprom11 = sext i32 %sub10 to i64 2591 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 2592 %3 = load float, float* %arrayidx12, align 4 2593 %conv13 = fptoui float %3 to i32 2594 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2595 ret <4 x i32> %vecinit14 2596; P9BE-LABEL: fromDiffMemVarDConvftoui 2597; P9LE-LABEL: fromDiffMemVarDConvftoui 2598; P8BE-LABEL: fromDiffMemVarDConvftoui 2599; P8LE-LABEL: fromDiffMemVarDConvftoui 2600; FIXME: implement finding consecutive loads with pre-inc 2601; P9BE: lfsux 2602; P9LE: lfsux 2603; P8BE: lfsux 2604; P8LE: lfsux 2605} 2606 2607; Function Attrs: norecurse nounwind readnone 2608define <4 x i32> @spltRegValConvftoui(float %val) { 2609entry: 2610 %conv = fptoui float %val to i32 2611 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2612 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2613 ret <4 x i32> %splat.splat 2614; P9BE-LABEL: spltRegValConvftoui 2615; P9LE-LABEL: spltRegValConvftoui 2616; P8BE-LABEL: spltRegValConvftoui 2617; P8LE-LABEL: spltRegValConvftoui 2618; P9BE: xscvdpuxws f[[REG1:[0-9]+]], f1 2619; P9BE: xxspltw v2, vs[[REG1]], 1 2620; P9BE: blr 2621; P9LE: xscvdpuxws f[[REG1:[0-9]+]], f1 2622; P9LE: xxspltw v2, vs[[REG1]], 1 2623; P9LE: blr 2624; P8BE: xscvdpuxws f[[REG1:[0-9]+]], f1 2625; P8BE: xxspltw v2, vs[[REG1]], 1 2626; P8BE: blr 2627; P8LE: xscvdpuxws f[[REG1:[0-9]+]], f1 2628; P8LE: xxspltw v2, vs[[REG1]], 1 2629; P8LE: blr 2630} 2631 2632; Function Attrs: norecurse nounwind readonly 2633define <4 x i32> @spltMemValConvftoui(float* nocapture readonly %ptr) { 2634entry: 2635 %0 = load float, float* %ptr, align 4 2636 %conv = fptoui float %0 to i32 2637 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2638 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2639 ret <4 x i32> %splat.splat 2640; P9BE-LABEL: spltMemValConvftoui 2641; P9LE-LABEL: spltMemValConvftoui 2642; P8BE-LABEL: spltMemValConvftoui 2643; P8LE-LABEL: spltMemValConvftoui 2644; P9BE: lxvwsx [[REG1:[vs0-9]+]], 0, r3 2645; P9BE: xvcvspuxws v2, [[REG1]] 2646; P9LE: [[REG1:[vs0-9]+]], 0, r3 2647; P9LE: xvcvspuxws v2, [[REG1]] 2648; P8BE: lxsspx [[REG1:f[0-9]+]], 0, r3 2649; P8BE: xscvdpuxws f[[REG2:[0-9]+]], [[REG1]] 2650; P8BE: xxspltw v2, vs[[REG2]], 1 2651; P8LE: lxsspx [[REG1:f[0-9]+]], 0, r3 2652; P8LE: xscvdpuxws f[[REG2:[vs0-9]+]], [[REG1]] 2653; P8LE: xxspltw v2, vs[[REG2]], 1 2654} 2655 2656; Function Attrs: norecurse nounwind readnone 2657define <4 x i32> @spltCnstConvdtoui() { 2658entry: 2659 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 2660; P9BE-LABEL: spltCnstConvdtoui 2661; P9LE-LABEL: spltCnstConvdtoui 2662; P8BE-LABEL: spltCnstConvdtoui 2663; P8LE-LABEL: spltCnstConvdtoui 2664; P9BE: vspltisw v2, 4 2665; P9BE: blr 2666; P9LE: vspltisw v2, 4 2667; P9LE: blr 2668; P8BE: vspltisw v2, 4 2669; P8BE: blr 2670; P8LE: vspltisw v2, 4 2671; P8LE: blr 2672} 2673 2674; Function Attrs: norecurse nounwind readnone 2675define <4 x i32> @fromRegsConvdtoui(double %a, double %b, double %c, double %d) { 2676entry: 2677 %conv = fptoui double %a to i32 2678 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2679 %conv1 = fptoui double %b to i32 2680 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 2681 %conv3 = fptoui double %c to i32 2682 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 2683 %conv5 = fptoui double %d to i32 2684 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 2685 ret <4 x i32> %vecinit6 2686; P9BE-LABEL: fromRegsConvdtoui 2687; P9LE-LABEL: fromRegsConvdtoui 2688; P8BE-LABEL: fromRegsConvdtoui 2689; P8LE-LABEL: fromRegsConvdtoui 2690; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 2691; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 2692; P9BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2693; P9BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2694; P9BE: vmrgew v2, [[REG3]], [[REG4]] 2695; P9BE: xvcvspuxws v2, v2 2696; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 2697; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 2698; P9LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2699; P9LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2700; P9LE: vmrgew v2, [[REG4]], [[REG3]] 2701; P9LE: xvcvspuxws v2, v2 2702; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 2703; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 2704; P8BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2705; P8BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2706; P8BE: vmrgew v2, [[REG3]], [[REG4]] 2707; P8BE: xvcvspuxws v2, v2 2708; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 2709; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 2710; P8LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2711; P8LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2712; P8LE: vmrgew v2, [[REG4]], [[REG3]] 2713; P8LE: xvcvspuxws v2, v2 2714} 2715 2716; Function Attrs: norecurse nounwind readnone 2717define <4 x i32> @fromDiffConstsConvdtoui() { 2718entry: 2719 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 2720; P9BE-LABEL: fromDiffConstsConvdtoui 2721; P9LE-LABEL: fromDiffConstsConvdtoui 2722; P8BE-LABEL: fromDiffConstsConvdtoui 2723; P8LE-LABEL: fromDiffConstsConvdtoui 2724; P9BE: lxvx 2725; P9BE: blr 2726; P9LE: lxvx 2727; P9LE: blr 2728; P8BE: lxvw4x 2729; P8BE: blr 2730; P8LE: lxvd2x 2731; P8LE: xxswapd 2732; P8LE: blr 2733} 2734 2735; Function Attrs: norecurse nounwind readonly 2736define <4 x i32> @fromDiffMemConsAConvdtoui(double* nocapture readonly %ptr) { 2737entry: 2738 %0 = bitcast double* %ptr to <2 x double>* 2739 %1 = load <2 x double>, <2 x double>* %0, align 8 2740 %2 = fptoui <2 x double> %1 to <2 x i32> 2741 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 2 2742 %3 = bitcast double* %arrayidx4 to <2 x double>* 2743 %4 = load <2 x double>, <2 x double>* %3, align 8 2744 %5 = fptoui <2 x double> %4 to <2 x i32> 2745 %vecinit9 = shufflevector <2 x i32> %2, <2 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 2746 ret <4 x i32> %vecinit9 2747; P9BE-LABEL: fromDiffMemConsAConvdtoui 2748; P9LE-LABEL: fromDiffMemConsAConvdtoui 2749; P8BE-LABEL: fromDiffMemConsAConvdtoui 2750; P8LE-LABEL: fromDiffMemConsAConvdtoui 2751; P9BE: lxvx [[REG1:[vs0-9]+]], 0, r3 2752; P9BE: lxvx [[REG2:[vs0-9]+]], r3, r4 2753; P9BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]] 2754; P9BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]] 2755; P9BE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]] 2756; P9BE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]] 2757; P9BE: vmrgew v2, [[REG6]], [[REG5]] 2758; P9BE: xvcvspuxws v2, v2 2759; P9LE: lxvx [[REG1:[vs0-9]+]], 0, r3 2760; P9LE: lxvx [[REG2:[vs0-9]+]], r3, r4 2761; P9LE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG2]], [[REG1]] 2762; P9LE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG2]], [[REG1]] 2763; P9LE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]] 2764; P9LE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]] 2765; P9LE: vmrgew v2, [[REG6]], [[REG5]] 2766; P9LE: xvcvspuxws v2, v2 2767; P8BE: lxvd2x [[REG1:[vs0-9]+]], 0, r3 2768; P8BE: lxvd2x [[REG2:[vs0-9]+]], r3, r4 2769; P8BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]] 2770; P8BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]] 2771; P8BE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]] 2772; P8BE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]] 2773; P8BE: vmrgew v2, [[REG6]], [[REG5]] 2774; P8BE: xvcvspuxws v2, v2 2775; P8LE: lxvd2x [[REG1:[vs0-9]+]], 0, r3 2776; P8LE: lxvd2x [[REG2:[vs0-9]+]], r3, r4 2777; P8LE-DAG: xxswapd [[REG3:[vs0-9]+]], [[REG1]] 2778; P8LE-DAG: xxswapd [[REG4:[vs0-9]+]], [[REG2]] 2779; P8LE-DAG: xxmrgld [[REG5:[vs0-9]+]], [[REG4]], [[REG3]] 2780; P8LE-DAG: xxmrghd [[REG6:[vs0-9]+]], [[REG4]], [[REG3]] 2781; P8LE-DAG: xvcvdpsp [[REG7:[vs0-9]+]], [[REG5]] 2782; P8LE-DAG: xvcvdpsp [[REG8:[vs0-9]+]], [[REG6]] 2783; P8LE: vmrgew v2, [[REG8]], [[REG7]] 2784; P8LE: xvcvspuxws v2, v2 2785} 2786 2787; Function Attrs: norecurse nounwind readonly 2788define <4 x i32> @fromDiffMemConsDConvdtoui(double* nocapture readonly %ptr) { 2789entry: 2790 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 2791 %0 = load double, double* %arrayidx, align 8 2792 %conv = fptoui double %0 to i32 2793 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2794 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 2795 %1 = load double, double* %arrayidx1, align 8 2796 %conv2 = fptoui double %1 to i32 2797 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 2798 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 1 2799 %2 = load double, double* %arrayidx4, align 8 2800 %conv5 = fptoui double %2 to i32 2801 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 2802 %3 = load double, double* %ptr, align 8 2803 %conv8 = fptoui double %3 to i32 2804 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 2805 ret <4 x i32> %vecinit9 2806; P9BE-LABEL: fromDiffMemConsDConvdtoui 2807; P9LE-LABEL: fromDiffMemConsDConvdtoui 2808; P8BE-LABEL: fromDiffMemConsDConvdtoui 2809; P8LE-LABEL: fromDiffMemConsDConvdtoui 2810; P9BE: lfd 2811; P9BE: lfd 2812; P9BE: lfd 2813; P9BE: lfd 2814; P9BE: xxmrghd 2815; P9BE: xxmrghd 2816; P9BE: xvcvdpsp 2817; P9BE: xvcvdpsp 2818; P9BE: vmrgew 2819; P9BE: xvcvspuxws v2 2820; P9LE: lfd 2821; P9LE: lfd 2822; P9LE: lfd 2823; P9LE: lfd 2824; P9LE: xxmrghd 2825; P9LE: xxmrghd 2826; P9LE: xvcvdpsp 2827; P9LE: xvcvdpsp 2828; P9LE: vmrgew 2829; P9LE: xvcvspuxws v2 2830; P8BE: lxsdx 2831; P8BE: lxsdx 2832; P8BE: lxsdx 2833; P8BE: lxsdx 2834; P8BE: xxmrghd 2835; P8BE: xxmrghd 2836; P8BE: xvcvdpsp 2837; P8BE: xvcvdpsp 2838; P8BE: vmrgew 2839; P8BE: xvcvspuxws v2 2840; P8LE: lxsdx 2841; P8LE: lxsdx 2842; P8LE: lxsdx 2843; P8LE: lxsdx 2844; P8LE: xxmrghd 2845; P8LE: xxmrghd 2846; P8LE: xvcvdpsp 2847; P8LE: xvcvdpsp 2848; P8LE: vmrgew 2849; P8LE: xvcvspuxws v2 2850} 2851 2852; Function Attrs: norecurse nounwind readonly 2853define <4 x i32> @fromDiffMemVarAConvdtoui(double* nocapture readonly %arr, i32 signext %elem) { 2854entry: 2855 %idxprom = sext i32 %elem to i64 2856 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 2857 %0 = load double, double* %arrayidx, align 8 2858 %conv = fptoui double %0 to i32 2859 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2860 %add = add nsw i32 %elem, 1 2861 %idxprom1 = sext i32 %add to i64 2862 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 2863 %1 = load double, double* %arrayidx2, align 8 2864 %conv3 = fptoui double %1 to i32 2865 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2866 %add5 = add nsw i32 %elem, 2 2867 %idxprom6 = sext i32 %add5 to i64 2868 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 2869 %2 = load double, double* %arrayidx7, align 8 2870 %conv8 = fptoui double %2 to i32 2871 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2872 %add10 = add nsw i32 %elem, 3 2873 %idxprom11 = sext i32 %add10 to i64 2874 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 2875 %3 = load double, double* %arrayidx12, align 8 2876 %conv13 = fptoui double %3 to i32 2877 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2878 ret <4 x i32> %vecinit14 2879; P9BE-LABEL: fromDiffMemVarAConvdtoui 2880; P9LE-LABEL: fromDiffMemVarAConvdtoui 2881; P8BE-LABEL: fromDiffMemVarAConvdtoui 2882; P8LE-LABEL: fromDiffMemVarAConvdtoui 2883; P9BE: lfdux 2884; P9BE: lfd 2885; P9BE: lfd 2886; P9BE: lfd 2887; P9BE: xxmrghd 2888; P9BE: xxmrghd 2889; P9BE: xvcvdpsp 2890; P9BE: xvcvdpsp 2891; P9BE: vmrgew 2892; P9BE: xvcvspuxws v2 2893; P9LE: lfdux 2894; P9LE: lfd 2895; P9LE: lfd 2896; P9LE: lfd 2897; P9LE: xxmrghd 2898; P9LE: xxmrghd 2899; P9LE: xvcvdpsp 2900; P9LE: xvcvdpsp 2901; P9LE: vmrgew 2902; P9LE: xvcvspuxws v2 2903; P8BE: lfdux 2904; P8BE: lxsdx 2905; P8BE: lxsdx 2906; P8BE: lxsdx 2907; P8BE: xxmrghd 2908; P8BE: xxmrghd 2909; P8BE: xvcvdpsp 2910; P8BE: xvcvdpsp 2911; P8BE: vmrgew 2912; P8BE: xvcvspuxws v2 2913; P8LE: lfdux 2914; P8LE: lxsdx 2915; P8LE: lxsdx 2916; P8LE: lxsdx 2917; P8LE: xxmrghd 2918; P8LE: xxmrghd 2919; P8LE: xvcvdpsp 2920; P8LE: xvcvdpsp 2921; P8LE: vmrgew 2922; P8LE: xvcvspuxws v2 2923} 2924 2925; Function Attrs: norecurse nounwind readonly 2926define <4 x i32> @fromDiffMemVarDConvdtoui(double* nocapture readonly %arr, i32 signext %elem) { 2927entry: 2928 %idxprom = sext i32 %elem to i64 2929 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 2930 %0 = load double, double* %arrayidx, align 8 2931 %conv = fptoui double %0 to i32 2932 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2933 %sub = add nsw i32 %elem, -1 2934 %idxprom1 = sext i32 %sub to i64 2935 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 2936 %1 = load double, double* %arrayidx2, align 8 2937 %conv3 = fptoui double %1 to i32 2938 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2939 %sub5 = add nsw i32 %elem, -2 2940 %idxprom6 = sext i32 %sub5 to i64 2941 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 2942 %2 = load double, double* %arrayidx7, align 8 2943 %conv8 = fptoui double %2 to i32 2944 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2945 %sub10 = add nsw i32 %elem, -3 2946 %idxprom11 = sext i32 %sub10 to i64 2947 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 2948 %3 = load double, double* %arrayidx12, align 8 2949 %conv13 = fptoui double %3 to i32 2950 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2951 ret <4 x i32> %vecinit14 2952; P9BE-LABEL: fromDiffMemVarDConvdtoui 2953; P9LE-LABEL: fromDiffMemVarDConvdtoui 2954; P8BE-LABEL: fromDiffMemVarDConvdtoui 2955; P8LE-LABEL: fromDiffMemVarDConvdtoui 2956; P9BE: lfdux 2957; P9BE: lfd 2958; P9BE: lfd 2959; P9BE: lfd 2960; P9BE: xxmrghd 2961; P9BE: xxmrghd 2962; P9BE: xvcvdpsp 2963; P9BE: xvcvdpsp 2964; P9BE: vmrgew 2965; P9BE: xvcvspuxws v2 2966; P9LE: lfdux 2967; P9LE: lfd 2968; P9LE: lfd 2969; P9LE: lfd 2970; P9LE: xxmrghd 2971; P9LE: xxmrghd 2972; P9LE: xvcvdpsp 2973; P9LE: xvcvdpsp 2974; P9LE: vmrgew 2975; P9LE: xvcvspuxws v2 2976; P8BE: lfdux 2977; P8BE: lxsdx 2978; P8BE: lxsdx 2979; P8BE: lxsdx 2980; P8BE: xxmrghd 2981; P8BE: xxmrghd 2982; P8BE: xvcvdpsp 2983; P8BE: xvcvdpsp 2984; P8BE: vmrgew 2985; P8BE: xvcvspuxws v2 2986; P8LE: lfdux 2987; P8LE: lxsdx 2988; P8LE: lxsdx 2989; P8LE: lxsdx 2990; P8LE: xxmrghd 2991; P8LE: xxmrghd 2992; P8LE: xvcvdpsp 2993; P8LE: xvcvdpsp 2994; P8LE: vmrgew 2995; P8LE: xvcvspuxws v2 2996} 2997 2998; Function Attrs: norecurse nounwind readnone 2999define <4 x i32> @spltRegValConvdtoui(double %val) { 3000entry: 3001 %conv = fptoui double %val to i32 3002 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3003 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3004 ret <4 x i32> %splat.splat 3005; P9BE-LABEL: spltRegValConvdtoui 3006; P9LE-LABEL: spltRegValConvdtoui 3007; P8BE-LABEL: spltRegValConvdtoui 3008; P8LE-LABEL: spltRegValConvdtoui 3009; P9BE: xscvdpuxws 3010; P9BE: xxspltw 3011; P9BE: blr 3012; P9LE: xscvdpuxws 3013; P9LE: xxspltw 3014; P9LE: blr 3015; P8BE: xscvdpuxws 3016; P8BE: xxspltw 3017; P8BE: blr 3018; P8LE: xscvdpuxws 3019; P8LE: xxspltw 3020; P8LE: blr 3021} 3022 3023; Function Attrs: norecurse nounwind readonly 3024define <4 x i32> @spltMemValConvdtoui(double* nocapture readonly %ptr) { 3025entry: 3026 %0 = load double, double* %ptr, align 8 3027 %conv = fptoui double %0 to i32 3028 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3029 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3030 ret <4 x i32> %splat.splat 3031; P9BE-LABEL: spltMemValConvdtoui 3032; P9LE-LABEL: spltMemValConvdtoui 3033; P8BE-LABEL: spltMemValConvdtoui 3034; P8LE-LABEL: spltMemValConvdtoui 3035; P9BE: lfd 3036; P9BE: xscvdpuxws 3037; P9BE: xxspltw 3038; P9BE: blr 3039; P9LE: lfd 3040; P9LE: xscvdpuxws 3041; P9LE: xxspltw 3042; P9LE: blr 3043; P8BE: lxsdx 3044; P8BE: xscvdpuxws 3045; P8BE: xxspltw 3046; P8BE: blr 3047; P8LE: lxsdx 3048; P8LE: xscvdpuxws 3049; P8LE: xxspltw 3050; P8LE: blr 3051} 3052; Function Attrs: norecurse nounwind readnone 3053define <2 x i64> @allZeroll() { 3054entry: 3055 ret <2 x i64> zeroinitializer 3056; P9BE-LABEL: allZeroll 3057; P9LE-LABEL: allZeroll 3058; P8BE-LABEL: allZeroll 3059; P8LE-LABEL: allZeroll 3060; P9BE: xxlxor v2, v2, v2 3061; P9BE: blr 3062; P9LE: xxlxor v2, v2, v2 3063; P9LE: blr 3064; P8BE: xxlxor v2, v2, v2 3065; P8BE: blr 3066; P8LE: xxlxor v2, v2, v2 3067; P8LE: blr 3068} 3069 3070; Function Attrs: norecurse nounwind readnone 3071define <2 x i64> @allOnell() { 3072entry: 3073 ret <2 x i64> <i64 -1, i64 -1> 3074; P9BE-LABEL: allOnell 3075; P9LE-LABEL: allOnell 3076; P8BE-LABEL: allOnell 3077; P8LE-LABEL: allOnell 3078; P9BE: xxspltib v2, 255 3079; P9BE: blr 3080; P9LE: xxspltib v2, 255 3081; P9LE: blr 3082; P8BE: vspltisb v2, -1 3083; P8BE: blr 3084; P8LE: vspltisb v2, -1 3085; P8LE: blr 3086} 3087 3088; Function Attrs: norecurse nounwind readnone 3089define <2 x i64> @spltConst1ll() { 3090entry: 3091 ret <2 x i64> <i64 1, i64 1> 3092; P9BE-LABEL: spltConst1ll 3093; P9LE-LABEL: spltConst1ll 3094; P8BE-LABEL: spltConst1ll 3095; P8LE-LABEL: spltConst1ll 3096; P9BE: lxvx 3097; P9BE: blr 3098; P9LE: lxvx 3099; P9LE: blr 3100; P8BE: lxvd2x 3101; P8BE: blr 3102; P8LE: lxvd2x 3103; P8LE: blr 3104} 3105 3106; Function Attrs: norecurse nounwind readnone 3107define <2 x i64> @spltConst16kll() { 3108entry: 3109 ret <2 x i64> <i64 32767, i64 32767> 3110; P9BE-LABEL: spltConst16kll 3111; P9LE-LABEL: spltConst16kll 3112; P8BE-LABEL: spltConst16kll 3113; P8LE-LABEL: spltConst16kll 3114; P9BE: lxvx 3115; P9BE: blr 3116; P9LE: lxvx 3117; P9LE: blr 3118; P8BE: lxvd2x 3119; P8BE: blr 3120; P8LE: lxvd2x 3121; P8LE: blr 3122} 3123 3124; Function Attrs: norecurse nounwind readnone 3125define <2 x i64> @spltConst32kll() { 3126entry: 3127 ret <2 x i64> <i64 65535, i64 65535> 3128; P9BE-LABEL: spltConst32kll 3129; P9LE-LABEL: spltConst32kll 3130; P8BE-LABEL: spltConst32kll 3131; P8LE-LABEL: spltConst32kll 3132; P9BE: lxvx 3133; P9BE: blr 3134; P9LE: lxvx 3135; P9LE: blr 3136; P8BE: lxvd2x 3137; P8BE: blr 3138; P8LE: lxvd2x 3139; P8LE: blr 3140} 3141 3142; Function Attrs: norecurse nounwind readnone 3143define <2 x i64> @fromRegsll(i64 %a, i64 %b) { 3144entry: 3145 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 3146 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 3147 ret <2 x i64> %vecinit1 3148; P9BE-LABEL: fromRegsll 3149; P9LE-LABEL: fromRegsll 3150; P8BE-LABEL: fromRegsll 3151; P8LE-LABEL: fromRegsll 3152; P9BE: mtvsrdd v2, r3, r4 3153; P9BE: blr 3154; P9LE: mtvsrdd v2, r4, r3 3155; P9LE: blr 3156; P8BE-DAG: mtvsrd {{[vsf0-9]+}}, r3 3157; P8BE-DAG: mtvsrd {{[vsf0-9]+}}, r4 3158; P8BE: xxmrghd v2 3159; P8BE: blr 3160; P8LE-DAG: mtvsrd {{[vsf0-9]+}}, r3 3161; P8LE-DAG: mtvsrd {{[vsf0-9]+}}, r4 3162; P8LE: xxmrghd v2 3163; P8LE: blr 3164} 3165 3166; Function Attrs: norecurse nounwind readnone 3167define <2 x i64> @fromDiffConstsll() { 3168entry: 3169 ret <2 x i64> <i64 242, i64 -113> 3170; P9BE-LABEL: fromDiffConstsll 3171; P9LE-LABEL: fromDiffConstsll 3172; P8BE-LABEL: fromDiffConstsll 3173; P8LE-LABEL: fromDiffConstsll 3174; P9BE: lxvx 3175; P9BE: blr 3176; P9LE: lxvx 3177; P9LE: blr 3178; P8BE: lxvd2x 3179; P8BE: blr 3180; P8LE: lxvd2x 3181; P8LE: blr 3182} 3183 3184; Function Attrs: norecurse nounwind readonly 3185define <2 x i64> @fromDiffMemConsAll(i64* nocapture readonly %arr) { 3186entry: 3187 %0 = load i64, i64* %arr, align 8 3188 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3189 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 1 3190 %1 = load i64, i64* %arrayidx1, align 8 3191 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3192 ret <2 x i64> %vecinit2 3193; P9BE-LABEL: fromDiffMemConsAll 3194; P9LE-LABEL: fromDiffMemConsAll 3195; P8BE-LABEL: fromDiffMemConsAll 3196; P8LE-LABEL: fromDiffMemConsAll 3197; P9BE: lxvx v2 3198; P9BE: blr 3199; P9LE: lxvx v2 3200; P9LE: blr 3201; P8BE: lxvd2x v2 3202; P8BE: blr 3203; P8LE: lxvd2x 3204; P8LE: xxswapd v2 3205; P8LE: blr 3206} 3207 3208; Function Attrs: norecurse nounwind readonly 3209define <2 x i64> @fromDiffMemConsDll(i64* nocapture readonly %arr) { 3210entry: 3211 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 3 3212 %0 = load i64, i64* %arrayidx, align 8 3213 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3214 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 2 3215 %1 = load i64, i64* %arrayidx1, align 8 3216 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3217 ret <2 x i64> %vecinit2 3218; P9BE-LABEL: fromDiffMemConsDll 3219; P9LE-LABEL: fromDiffMemConsDll 3220; P8BE-LABEL: fromDiffMemConsDll 3221; P8LE-LABEL: fromDiffMemConsDll 3222; P9BE: lxvx v2 3223; P9BE: blr 3224; P9LE: lxvx 3225; P9LE: xxswapd v2 3226; P9LE: blr 3227; P8BE: lxvd2x 3228; P8BE: xxswapd v2 3229; P8BE-NEXT: blr 3230; P8LE: lxvd2x v2 3231; P8LE-NEXT: blr 3232} 3233 3234; Function Attrs: norecurse nounwind readonly 3235define <2 x i64> @fromDiffMemVarAll(i64* nocapture readonly %arr, i32 signext %elem) { 3236entry: 3237 %idxprom = sext i32 %elem to i64 3238 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 3239 %0 = load i64, i64* %arrayidx, align 8 3240 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3241 %add = add nsw i32 %elem, 1 3242 %idxprom1 = sext i32 %add to i64 3243 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 3244 %1 = load i64, i64* %arrayidx2, align 8 3245 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3246 ret <2 x i64> %vecinit3 3247; P9BE-LABEL: fromDiffMemVarAll 3248; P9LE-LABEL: fromDiffMemVarAll 3249; P8BE-LABEL: fromDiffMemVarAll 3250; P8LE-LABEL: fromDiffMemVarAll 3251; P9BE: sldi 3252; P9BE: lxvx v2 3253; P9BE-NEXT: blr 3254; P9LE: sldi 3255; P9LE: lxvx v2 3256; P9LE-NEXT: blr 3257; P8BE: sldi 3258; P8BE: lxvd2x v2 3259; P8BE-NEXT: blr 3260; P8LE: sldi 3261; P8LE: lxvd2x 3262; P8LE: xxswapd v2 3263; P8LE-NEXT: blr 3264} 3265 3266; Function Attrs: norecurse nounwind readonly 3267define <2 x i64> @fromDiffMemVarDll(i64* nocapture readonly %arr, i32 signext %elem) { 3268entry: 3269 %idxprom = sext i32 %elem to i64 3270 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 3271 %0 = load i64, i64* %arrayidx, align 8 3272 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3273 %sub = add nsw i32 %elem, -1 3274 %idxprom1 = sext i32 %sub to i64 3275 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 3276 %1 = load i64, i64* %arrayidx2, align 8 3277 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3278 ret <2 x i64> %vecinit3 3279; P9BE-LABEL: fromDiffMemVarDll 3280; P9LE-LABEL: fromDiffMemVarDll 3281; P8BE-LABEL: fromDiffMemVarDll 3282; P8LE-LABEL: fromDiffMemVarDll 3283; P9BE: sldi 3284; P9BE: lxvx 3285; P9BE: xxswapd v2 3286; P9BE-NEXT: blr 3287; P9LE: sldi 3288; P9LE: lxvx 3289; P9LE: xxswapd v2 3290; P9LE-NEXT: blr 3291; P8BE: sldi 3292; P8BE: lxvd2x 3293; P8BE: xxswapd v2 3294; P8BE-NEXT: blr 3295; P8LE: sldi 3296; P8LE: lxvd2x v2 3297; P8LE-NEXT: blr 3298} 3299 3300; Function Attrs: norecurse nounwind readonly 3301define <2 x i64> @fromRandMemConsll(i64* nocapture readonly %arr) { 3302entry: 3303 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4 3304 %0 = load i64, i64* %arrayidx, align 8 3305 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3306 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18 3307 %1 = load i64, i64* %arrayidx1, align 8 3308 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3309 ret <2 x i64> %vecinit2 3310; P9BE-LABEL: fromRandMemConsll 3311; P9LE-LABEL: fromRandMemConsll 3312; P8BE-LABEL: fromRandMemConsll 3313; P8LE-LABEL: fromRandMemConsll 3314; P9BE: ld 3315; P9BE: ld 3316; P9BE: mtvsrdd v2 3317; P9BE-NEXT: blr 3318; P9LE: ld 3319; P9LE: ld 3320; P9LE: mtvsrdd v2 3321; P9LE-NEXT: blr 3322; P8BE: ld 3323; P8BE: ld 3324; P8BE-DAG: mtvsrd 3325; P8BE-DAG: mtvsrd 3326; P8BE: xxmrghd v2 3327; P8BE-NEXT: blr 3328; P8LE: ld 3329; P8LE: ld 3330; P8LE-DAG: mtvsrd 3331; P8LE-DAG: mtvsrd 3332; P8LE: xxmrghd v2 3333; P8LE-NEXT: blr 3334} 3335 3336; Function Attrs: norecurse nounwind readonly 3337define <2 x i64> @fromRandMemVarll(i64* nocapture readonly %arr, i32 signext %elem) { 3338entry: 3339 %add = add nsw i32 %elem, 4 3340 %idxprom = sext i32 %add to i64 3341 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 3342 %0 = load i64, i64* %arrayidx, align 8 3343 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3344 %add1 = add nsw i32 %elem, 1 3345 %idxprom2 = sext i32 %add1 to i64 3346 %arrayidx3 = getelementptr inbounds i64, i64* %arr, i64 %idxprom2 3347 %1 = load i64, i64* %arrayidx3, align 8 3348 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3349 ret <2 x i64> %vecinit4 3350; P9BE-LABEL: fromRandMemVarll 3351; P9LE-LABEL: fromRandMemVarll 3352; P8BE-LABEL: fromRandMemVarll 3353; P8LE-LABEL: fromRandMemVarll 3354; P9BE: sldi 3355; P9BE: ld 3356; P9BE: ld 3357; P9BE: mtvsrdd v2 3358; P9BE-NEXT: blr 3359; P9LE: sldi 3360; P9LE: ld 3361; P9LE: ld 3362; P9LE: mtvsrdd v2 3363; P9LE-NEXT: blr 3364; P8BE: sldi 3365; P8BE: ld 3366; P8BE: ld 3367; P8BE: mtvsrd 3368; P8BE: mtvsrd 3369; P8BE: xxmrghd v2 3370; P8BE-NEXT: blr 3371; P8LE: sldi 3372; P8LE: ld 3373; P8LE: ld 3374; P8LE: mtvsrd 3375; P8LE: mtvsrd 3376; P8LE: xxmrghd v2 3377; P8LE-NEXT: blr 3378} 3379 3380; Function Attrs: norecurse nounwind readnone 3381define <2 x i64> @spltRegValll(i64 %val) { 3382entry: 3383 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0 3384 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 3385 ret <2 x i64> %splat.splat 3386; P9BE-LABEL: spltRegValll 3387; P9LE-LABEL: spltRegValll 3388; P8BE-LABEL: spltRegValll 3389; P8LE-LABEL: spltRegValll 3390; P9BE: mtvsrdd v2, r3, r3 3391; P9BE-NEXT: blr 3392; P9LE: mtvsrdd v2, r3, r3 3393; P9LE-NEXT: blr 3394; P8BE: mtvsrd {{[vsf]+}}[[REG1:[0-9]+]], r3 3395; P8BE: xxspltd v2, {{[vsf]+}}[[REG1]], 0 3396; P8BE-NEXT: blr 3397; P8LE: mtvsrd {{[vsf]+}}[[REG1:[0-9]+]], r3 3398; P8LE: xxspltd v2, {{[vsf]+}}[[REG1]], 0 3399; P8LE-NEXT: blr 3400} 3401 3402; Function Attrs: norecurse nounwind readonly 3403define <2 x i64> @spltMemValll(i64* nocapture readonly %ptr) { 3404entry: 3405 %0 = load i64, i64* %ptr, align 8 3406 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 3407 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 3408 ret <2 x i64> %splat.splat 3409; P9BE-LABEL: spltMemValll 3410; P9LE-LABEL: spltMemValll 3411; P8BE-LABEL: spltMemValll 3412; P8LE-LABEL: spltMemValll 3413; P9BE: lxvdsx v2 3414; P9BE-NEXT: blr 3415; P9LE: lxvdsx v2 3416; P9LE-NEXT: blr 3417; P8BE: lxvdsx v2 3418; P8BE-NEXT: blr 3419; P8LE: lxvdsx v2 3420; P8LE-NEXT: blr 3421} 3422 3423; Function Attrs: norecurse nounwind readnone 3424define <2 x i64> @spltCnstConvftoll() { 3425entry: 3426 ret <2 x i64> <i64 4, i64 4> 3427; P9BE-LABEL: spltCnstConvftoll 3428; P9LE-LABEL: spltCnstConvftoll 3429; P8BE-LABEL: spltCnstConvftoll 3430; P8LE-LABEL: spltCnstConvftoll 3431; P9BE: lxvx 3432; P9BE: blr 3433; P9LE: lxvx 3434; P9LE: blr 3435; P8BE: lxvd2x 3436; P8BE: blr 3437; P8LE: lxvd2x 3438; P8LE: blr 3439} 3440 3441; Function Attrs: norecurse nounwind readnone 3442define <2 x i64> @fromRegsConvftoll(float %a, float %b) { 3443entry: 3444 %conv = fptosi float %a to i64 3445 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3446 %conv1 = fptosi float %b to i64 3447 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 3448 ret <2 x i64> %vecinit2 3449; P9BE-LABEL: fromRegsConvftoll 3450; P9LE-LABEL: fromRegsConvftoll 3451; P8BE-LABEL: fromRegsConvftoll 3452; P8LE-LABEL: fromRegsConvftoll 3453; P9BE: xxmrghd 3454; P9BE: xvcvdpsxds v2 3455; P9BE-NEXT: blr 3456; P9LE: xxmrghd 3457; P9LE: xvcvdpsxds v2 3458; P9LE-NEXT: blr 3459; P8BE: xxmrghd 3460; P8BE: xvcvdpsxds v2 3461; P8BE-NEXT: blr 3462; P8LE: xxmrghd 3463; P8LE: xvcvdpsxds v2 3464; P8LE-NEXT: blr 3465} 3466 3467; Function Attrs: norecurse nounwind readnone 3468define <2 x i64> @fromDiffConstsConvftoll() { 3469entry: 3470 ret <2 x i64> <i64 24, i64 234> 3471; P9BE-LABEL: fromDiffConstsConvftoll 3472; P9LE-LABEL: fromDiffConstsConvftoll 3473; P8BE-LABEL: fromDiffConstsConvftoll 3474; P8LE-LABEL: fromDiffConstsConvftoll 3475; P9BE: lxvx v2 3476; P9BE: blr 3477; P9LE: lxvx v2 3478; P9LE: blr 3479; P8BE: lxvd2x v2 3480; P8BE: blr 3481; P8LE: lxvd2x 3482; P8LE: xxswapd v2 3483; P8LE: blr 3484} 3485 3486; Function Attrs: norecurse nounwind readonly 3487define <2 x i64> @fromDiffMemConsAConvftoll(float* nocapture readonly %ptr) { 3488entry: 3489 %0 = load float, float* %ptr, align 4 3490 %conv = fptosi float %0 to i64 3491 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3492 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1 3493 %1 = load float, float* %arrayidx1, align 4 3494 %conv2 = fptosi float %1 to i64 3495 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 3496 ret <2 x i64> %vecinit3 3497; P9BE-LABEL: fromDiffMemConsAConvftoll 3498; P9LE-LABEL: fromDiffMemConsAConvftoll 3499; P8BE-LABEL: fromDiffMemConsAConvftoll 3500; P8LE-LABEL: fromDiffMemConsAConvftoll 3501; P9BE: lfs 3502; P9BE: lfs 3503; P9BE: xxmrghd 3504; P9BE-NEXT: xvcvdpsxds v2 3505; P9BE-NEXT: blr 3506; P9LE: lfs 3507; P9LE: lfs 3508; P9LE: xxmrghd 3509; P9LE-NEXT: xvcvdpsxds v2 3510; P9LE-NEXT: blr 3511; P8BE: lxsspx 3512; P8BE: lxsspx 3513; P8BE: xxmrghd 3514; P8BE-NEXT: xvcvdpsxds v2 3515; P8BE-NEXT: blr 3516; P8LE: lxsspx 3517; P8LE: lxsspx 3518; P8LE: xxmrghd 3519; P8LE-NEXT: xvcvdpsxds v2 3520; P8LE-NEXT: blr 3521} 3522 3523; Function Attrs: norecurse nounwind readonly 3524define <2 x i64> @fromDiffMemConsDConvftoll(float* nocapture readonly %ptr) { 3525entry: 3526 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 3527 %0 = load float, float* %arrayidx, align 4 3528 %conv = fptosi float %0 to i64 3529 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3530 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 3531 %1 = load float, float* %arrayidx1, align 4 3532 %conv2 = fptosi float %1 to i64 3533 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 3534 ret <2 x i64> %vecinit3 3535; P9BE-LABEL: fromDiffMemConsDConvftoll 3536; P9LE-LABEL: fromDiffMemConsDConvftoll 3537; P8BE-LABEL: fromDiffMemConsDConvftoll 3538; P8LE-LABEL: fromDiffMemConsDConvftoll 3539; P9BE: lfs 3540; P9BE: lfs 3541; P9BE: xxmrghd 3542; P9BE-NEXT: xvcvdpsxds v2 3543; P9BE-NEXT: blr 3544; P9LE: lfs 3545; P9LE: lfs 3546; P9LE: xxmrghd 3547; P9LE-NEXT: xvcvdpsxds v2 3548; P9LE-NEXT: blr 3549; P8BE: lxsspx 3550; P8BE: lxsspx 3551; P8BE: xxmrghd 3552; P8BE-NEXT: xvcvdpsxds v2 3553; P8BE-NEXT: blr 3554; P8LE: lxsspx 3555; P8LE: lxsspx 3556; P8LE: xxmrghd 3557; P8LE-NEXT: xvcvdpsxds v2 3558; P8LE-NEXT: blr 3559} 3560 3561; Function Attrs: norecurse nounwind readonly 3562define <2 x i64> @fromDiffMemVarAConvftoll(float* nocapture readonly %arr, i32 signext %elem) { 3563entry: 3564 %idxprom = sext i32 %elem to i64 3565 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 3566 %0 = load float, float* %arrayidx, align 4 3567 %conv = fptosi float %0 to i64 3568 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3569 %add = add nsw i32 %elem, 1 3570 %idxprom1 = sext i32 %add to i64 3571 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 3572 %1 = load float, float* %arrayidx2, align 4 3573 %conv3 = fptosi float %1 to i64 3574 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 3575 ret <2 x i64> %vecinit4 3576; P9BE-LABEL: fromDiffMemVarAConvftoll 3577; P9LE-LABEL: fromDiffMemVarAConvftoll 3578; P8BE-LABEL: fromDiffMemVarAConvftoll 3579; P8LE-LABEL: fromDiffMemVarAConvftoll 3580; P9BE: sldi 3581; P9BE: lfsux 3582; P9BE: lfs 3583; P9BE: xxmrghd 3584; P9BE-NEXT: xvcvdpsxds v2 3585; P9BE-NEXT: blr 3586; P9LE: sldi 3587; P9LE: lfsux 3588; P9LE: lfs 3589; P9LE: xxmrghd 3590; P9LE-NEXT: xvcvdpsxds v2 3591; P9LE-NEXT: blr 3592; P8BE: sldi 3593; P8BE: lfsux 3594; P8BE: lxsspx 3595; P8BE: xxmrghd 3596; P8BE-NEXT: xvcvdpsxds v2 3597; P8BE-NEXT: blr 3598; P8LE: sldi 3599; P8LE: lfsux 3600; P8LE: lxsspx 3601; P8LE: xxmrghd 3602; P8LE-NEXT: xvcvdpsxds v2 3603; P8LE-NEXT: blr 3604} 3605 3606; Function Attrs: norecurse nounwind readonly 3607define <2 x i64> @fromDiffMemVarDConvftoll(float* nocapture readonly %arr, i32 signext %elem) { 3608entry: 3609 %idxprom = sext i32 %elem to i64 3610 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 3611 %0 = load float, float* %arrayidx, align 4 3612 %conv = fptosi float %0 to i64 3613 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3614 %sub = add nsw i32 %elem, -1 3615 %idxprom1 = sext i32 %sub to i64 3616 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 3617 %1 = load float, float* %arrayidx2, align 4 3618 %conv3 = fptosi float %1 to i64 3619 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 3620 ret <2 x i64> %vecinit4 3621; P9BE-LABEL: fromDiffMemVarDConvftoll 3622; P9LE-LABEL: fromDiffMemVarDConvftoll 3623; P8BE-LABEL: fromDiffMemVarDConvftoll 3624; P8LE-LABEL: fromDiffMemVarDConvftoll 3625; P9BE: sldi 3626; P9BE: lfsux 3627; P9BE: lfs 3628; P9BE: xxmrghd 3629; P9BE-NEXT: xvcvdpsxds v2 3630; P9BE-NEXT: blr 3631; P9LE: sldi 3632; P9LE: lfsux 3633; P9LE: lfs 3634; P9LE: xxmrghd 3635; P9LE-NEXT: xvcvdpsxds v2 3636; P9LE-NEXT: blr 3637; P8BE: sldi 3638; P8BE: lfsux 3639; P8BE: lxsspx 3640; P8BE: xxmrghd 3641; P8BE-NEXT: xvcvdpsxds v2 3642; P8BE-NEXT: blr 3643; P8LE: sldi 3644; P8LE: lfsux 3645; P8LE: lxsspx 3646; P8LE: xxmrghd 3647; P8LE-NEXT: xvcvdpsxds v2 3648; P8LE-NEXT: blr 3649} 3650 3651; Function Attrs: norecurse nounwind readnone 3652define <2 x i64> @spltRegValConvftoll(float %val) { 3653entry: 3654 %conv = fptosi float %val to i64 3655 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 3656 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 3657 ret <2 x i64> %splat.splat 3658; P9BE-LABEL: spltRegValConvftoll 3659; P9LE-LABEL: spltRegValConvftoll 3660; P8BE-LABEL: spltRegValConvftoll 3661; P8LE-LABEL: spltRegValConvftoll 3662; P9BE: xscvdpsxds 3663; P9BE-NEXT: xxspltd v2 3664; P9BE-NEXT: blr 3665; P9LE: xscvdpsxds 3666; P9LE-NEXT: xxspltd v2 3667; P9LE-NEXT: blr 3668; P8BE: xscvdpsxds 3669; P8BE-NEXT: xxspltd v2 3670; P8BE-NEXT: blr 3671; P8LE: xscvdpsxds 3672; P8LE-NEXT: xxspltd v2 3673; P8LE-NEXT: blr 3674} 3675 3676; Function Attrs: norecurse nounwind readonly 3677define <2 x i64> @spltMemValConvftoll(float* nocapture readonly %ptr) { 3678entry: 3679 %0 = load float, float* %ptr, align 4 3680 %conv = fptosi float %0 to i64 3681 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 3682 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 3683 ret <2 x i64> %splat.splat 3684; P9BE-LABEL: spltMemValConvftoll 3685; P9LE-LABEL: spltMemValConvftoll 3686; P8BE-LABEL: spltMemValConvftoll 3687; P8LE-LABEL: spltMemValConvftoll 3688; P9BE: lfs 3689; P9BE-NEXT: xscvdpsxds 3690; P9BE-NEXT: xxspltd v2 3691; P9BE-NEXT: blr 3692; P9LE: lfs 3693; P9LE-NEXT: xscvdpsxds 3694; P9LE-NEXT: xxspltd v2 3695; P9LE-NEXT: blr 3696; P8BE: lxsspx 3697; P8BE-NEXT: xscvdpsxds 3698; P8BE-NEXT: xxspltd v2 3699; P8BE-NEXT: blr 3700; P8LE: lxsspx 3701; P8LE-NEXT: xscvdpsxds 3702; P8LE-NEXT: xxspltd v2 3703; P8LE-NEXT: blr 3704} 3705 3706; Function Attrs: norecurse nounwind readnone 3707define <2 x i64> @spltCnstConvdtoll() { 3708entry: 3709 ret <2 x i64> <i64 4, i64 4> 3710; P9BE-LABEL: spltCnstConvdtoll 3711; P9LE-LABEL: spltCnstConvdtoll 3712; P8BE-LABEL: spltCnstConvdtoll 3713; P8LE-LABEL: spltCnstConvdtoll 3714; P9BE: lxvx 3715; P9BE: blr 3716; P9LE: lxvx 3717; P9LE: blr 3718; P8BE: lxvd2x 3719; P8BE: blr 3720; P8LE: lxvd2x 3721; P8LE: blr 3722} 3723 3724; Function Attrs: norecurse nounwind readnone 3725define <2 x i64> @fromRegsConvdtoll(double %a, double %b) { 3726entry: 3727 %conv = fptosi double %a to i64 3728 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3729 %conv1 = fptosi double %b to i64 3730 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 3731 ret <2 x i64> %vecinit2 3732; P9BE-LABEL: fromRegsConvdtoll 3733; P9LE-LABEL: fromRegsConvdtoll 3734; P8BE-LABEL: fromRegsConvdtoll 3735; P8LE-LABEL: fromRegsConvdtoll 3736; P9BE: xxmrghd 3737; P9BE-NEXT: xvcvdpsxds 3738; P9BE-NEXT: blr 3739; P9LE: xxmrghd 3740; P9LE-NEXT: xvcvdpsxds 3741; P9LE-NEXT: blr 3742; P8BE: xxmrghd 3743; P8BE-NEXT: xvcvdpsxds 3744; P8BE-NEXT: blr 3745; P8LE: xxmrghd 3746; P8LE-NEXT: xvcvdpsxds 3747; P8LE-NEXT: blr 3748} 3749 3750; Function Attrs: norecurse nounwind readnone 3751define <2 x i64> @fromDiffConstsConvdtoll() { 3752entry: 3753 ret <2 x i64> <i64 24, i64 234> 3754; P9BE-LABEL: fromDiffConstsConvdtoll 3755; P9LE-LABEL: fromDiffConstsConvdtoll 3756; P8BE-LABEL: fromDiffConstsConvdtoll 3757; P8LE-LABEL: fromDiffConstsConvdtoll 3758; P9BE: lxvx 3759; P9BE: blr 3760; P9LE: lxvx 3761; P9LE: blr 3762; P8BE: lxvd2x 3763; P8BE: blr 3764; P8LE: lxvd2x 3765; P8LE: blr 3766} 3767 3768; Function Attrs: norecurse nounwind readonly 3769define <2 x i64> @fromDiffMemConsAConvdtoll(double* nocapture readonly %ptr) { 3770entry: 3771 %0 = bitcast double* %ptr to <2 x double>* 3772 %1 = load <2 x double>, <2 x double>* %0, align 8 3773 %2 = fptosi <2 x double> %1 to <2 x i64> 3774 ret <2 x i64> %2 3775; P9BE-LABEL: fromDiffMemConsAConvdtoll 3776; P9LE-LABEL: fromDiffMemConsAConvdtoll 3777; P8BE-LABEL: fromDiffMemConsAConvdtoll 3778; P8LE-LABEL: fromDiffMemConsAConvdtoll 3779; P9BE: lxvx 3780; P9BE-NEXT: xvcvdpsxds v2 3781; P9BE-NEXT: blr 3782; P9LE: lxvx 3783; P9LE-NEXT: xvcvdpsxds v2 3784; P9LE-NEXT: blr 3785; P8BE: lxvd2x 3786; P8BE-NEXT: xvcvdpsxds v2 3787; P8BE-NEXT: blr 3788; P8LE: lxvd2x 3789; P8LE: xxswapd 3790; P8LE-NEXT: xvcvdpsxds v2 3791; P8LE-NEXT: blr 3792} 3793 3794; Function Attrs: norecurse nounwind readonly 3795define <2 x i64> @fromDiffMemConsDConvdtoll(double* nocapture readonly %ptr) { 3796entry: 3797 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 3798 %0 = load double, double* %arrayidx, align 8 3799 %conv = fptosi double %0 to i64 3800 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3801 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 3802 %1 = load double, double* %arrayidx1, align 8 3803 %conv2 = fptosi double %1 to i64 3804 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 3805 ret <2 x i64> %vecinit3 3806; P9BE-LABEL: fromDiffMemConsDConvdtoll 3807; P9LE-LABEL: fromDiffMemConsDConvdtoll 3808; P8BE-LABEL: fromDiffMemConsDConvdtoll 3809; P8LE-LABEL: fromDiffMemConsDConvdtoll 3810; P9BE: lxvx 3811; P9BE-NEXT: xxswapd 3812; P9BE-NEXT: xvcvdpsxds v2 3813; P9BE-NEXT: blr 3814; P9LE: lxvx 3815; P9LE-NEXT: xxswapd 3816; P9LE-NEXT: xvcvdpsxds v2 3817; P9LE-NEXT: blr 3818; P8BE: lxvd2x 3819; P8BE-NEXT: xxswapd 3820; P8BE-NEXT: xvcvdpsxds v2 3821; P8BE-NEXT: blr 3822; P8LE: lxvd2x 3823; P8LE-NEXT: xvcvdpsxds v2 3824; P8LE-NEXT: blr 3825} 3826 3827; Function Attrs: norecurse nounwind readonly 3828define <2 x i64> @fromDiffMemVarAConvdtoll(double* nocapture readonly %arr, i32 signext %elem) { 3829entry: 3830 %idxprom = sext i32 %elem to i64 3831 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 3832 %0 = load double, double* %arrayidx, align 8 3833 %conv = fptosi double %0 to i64 3834 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3835 %add = add nsw i32 %elem, 1 3836 %idxprom1 = sext i32 %add to i64 3837 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 3838 %1 = load double, double* %arrayidx2, align 8 3839 %conv3 = fptosi double %1 to i64 3840 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 3841 ret <2 x i64> %vecinit4 3842; P9BE-LABEL: fromDiffMemVarAConvdtoll 3843; P9LE-LABEL: fromDiffMemVarAConvdtoll 3844; P8BE-LABEL: fromDiffMemVarAConvdtoll 3845; P8LE-LABEL: fromDiffMemVarAConvdtoll 3846; P9BE: sldi 3847; P9BE: lxvx 3848; P9BE-NEXT: xvcvdpsxds v2 3849; P9BE-NEXT: blr 3850; P9LE: sldi 3851; P9LE: lxvx 3852; P9LE-NEXT: xvcvdpsxds v2 3853; P9LE-NEXT: blr 3854; P8BE: sldi 3855; P8BE: lxvd2x 3856; P8BE-NEXT: xvcvdpsxds v2 3857; P8BE-NEXT: blr 3858; P8LE: sldi 3859; P8LE: lxvd2x 3860; P8LE-NEXT: xxswapd 3861; P8LE-NEXT: xvcvdpsxds v2 3862; P8LE-NEXT: blr 3863} 3864 3865; Function Attrs: norecurse nounwind readonly 3866define <2 x i64> @fromDiffMemVarDConvdtoll(double* nocapture readonly %arr, i32 signext %elem) { 3867entry: 3868 %idxprom = sext i32 %elem to i64 3869 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 3870 %0 = load double, double* %arrayidx, align 8 3871 %conv = fptosi double %0 to i64 3872 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3873 %sub = add nsw i32 %elem, -1 3874 %idxprom1 = sext i32 %sub to i64 3875 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 3876 %1 = load double, double* %arrayidx2, align 8 3877 %conv3 = fptosi double %1 to i64 3878 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 3879 ret <2 x i64> %vecinit4 3880; P9BE-LABEL: fromDiffMemVarDConvdtoll 3881; P9LE-LABEL: fromDiffMemVarDConvdtoll 3882; P8BE-LABEL: fromDiffMemVarDConvdtoll 3883; P8LE-LABEL: fromDiffMemVarDConvdtoll 3884; P9BE: sldi 3885; P9BE: lxvx 3886; P9BE-NEXT: xxswapd 3887; P9BE-NEXT: xvcvdpsxds v2 3888; P9BE-NEXT: blr 3889; P9LE: sldi 3890; P9LE: lxvx 3891; P9LE-NEXT: xxswapd 3892; P9LE-NEXT: xvcvdpsxds v2 3893; P9LE-NEXT: blr 3894; P8BE: sldi 3895; P8BE: lxvd2x 3896; P8BE-NEXT: xxswapd 3897; P8BE-NEXT: xvcvdpsxds v2 3898; P8BE-NEXT: blr 3899; P8LE: sldi 3900; P8LE: lxvd2x 3901; P8LE-NEXT: xvcvdpsxds v2 3902; P8LE-NEXT: blr 3903} 3904 3905; Function Attrs: norecurse nounwind readnone 3906define <2 x i64> @spltRegValConvdtoll(double %val) { 3907entry: 3908 %conv = fptosi double %val to i64 3909 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 3910 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 3911 ret <2 x i64> %splat.splat 3912; P9BE-LABEL: spltRegValConvdtoll 3913; P9LE-LABEL: spltRegValConvdtoll 3914; P8BE-LABEL: spltRegValConvdtoll 3915; P8LE-LABEL: spltRegValConvdtoll 3916; P9BE: xscvdpsxds 3917; P9BE-NEXT: xxspltd v2 3918; P9BE-NEXT: blr 3919; P9LE: xscvdpsxds 3920; P9LE-NEXT: xxspltd v2 3921; P9LE-NEXT: blr 3922; P8BE: xscvdpsxds 3923; P8BE-NEXT: xxspltd v2 3924; P8BE-NEXT: blr 3925; P8LE: xscvdpsxds 3926; P8LE-NEXT: xxspltd v2 3927; P8LE-NEXT: blr 3928} 3929 3930; Function Attrs: norecurse nounwind readonly 3931define <2 x i64> @spltMemValConvdtoll(double* nocapture readonly %ptr) { 3932entry: 3933 %0 = load double, double* %ptr, align 8 3934 %conv = fptosi double %0 to i64 3935 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 3936 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 3937 ret <2 x i64> %splat.splat 3938; P9BE-LABEL: spltMemValConvdtoll 3939; P9LE-LABEL: spltMemValConvdtoll 3940; P8BE-LABEL: spltMemValConvdtoll 3941; P8LE-LABEL: spltMemValConvdtoll 3942; P9BE: lxvdsx 3943; P9BE-NEXT: xvcvdpsxds 3944; P9BE-NEXT: blr 3945; P9LE: lxvdsx 3946; P9LE-NEXT: xvcvdpsxds 3947; P9LE-NEXT: blr 3948; P8BE: lxvdsx 3949; P8BE-NEXT: xvcvdpsxds 3950; P8BE-NEXT: blr 3951; P8LE: lxvdsx 3952; P8LE-NEXT: xvcvdpsxds 3953; P8LE-NEXT: blr 3954} 3955 3956; Function Attrs: norecurse nounwind readnone 3957define <2 x i64> @allZeroull() { 3958entry: 3959 ret <2 x i64> zeroinitializer 3960; P9BE-LABEL: allZeroull 3961; P9LE-LABEL: allZeroull 3962; P8BE-LABEL: allZeroull 3963; P8LE-LABEL: allZeroull 3964; P9BE: xxlxor v2, v2, v2 3965; P9BE: blr 3966; P9LE: xxlxor v2, v2, v2 3967; P9LE: blr 3968; P8BE: xxlxor v2, v2, v2 3969; P8BE: blr 3970; P8LE: xxlxor v2, v2, v2 3971; P8LE: blr 3972} 3973 3974; Function Attrs: norecurse nounwind readnone 3975define <2 x i64> @allOneull() { 3976entry: 3977 ret <2 x i64> <i64 -1, i64 -1> 3978; P9BE-LABEL: allOneull 3979; P9LE-LABEL: allOneull 3980; P8BE-LABEL: allOneull 3981; P8LE-LABEL: allOneull 3982; P9BE: xxspltib v2, 255 3983; P9BE: blr 3984; P9LE: xxspltib v2, 255 3985; P9LE: blr 3986; P8BE: vspltisb v2, -1 3987; P8BE: blr 3988; P8LE: vspltisb v2, -1 3989; P8LE: blr 3990} 3991 3992; Function Attrs: norecurse nounwind readnone 3993define <2 x i64> @spltConst1ull() { 3994entry: 3995 ret <2 x i64> <i64 1, i64 1> 3996; P9BE-LABEL: spltConst1ull 3997; P9LE-LABEL: spltConst1ull 3998; P8BE-LABEL: spltConst1ull 3999; P8LE-LABEL: spltConst1ull 4000; P9BE: lxvx 4001; P9BE: blr 4002; P9LE: lxvx 4003; P9LE: blr 4004; P8BE: lxvd2x 4005; P8BE: blr 4006; P8LE: lxvd2x 4007; P8LE: blr 4008} 4009 4010; Function Attrs: norecurse nounwind readnone 4011define <2 x i64> @spltConst16kull() { 4012entry: 4013 ret <2 x i64> <i64 32767, i64 32767> 4014; P9BE-LABEL: spltConst16kull 4015; P9LE-LABEL: spltConst16kull 4016; P8BE-LABEL: spltConst16kull 4017; P8LE-LABEL: spltConst16kull 4018; P9BE: lxvx 4019; P9BE: blr 4020; P9LE: lxvx 4021; P9LE: blr 4022; P8BE: lxvd2x 4023; P8BE: blr 4024; P8LE: lxvd2x 4025; P8LE: blr 4026} 4027 4028; Function Attrs: norecurse nounwind readnone 4029define <2 x i64> @spltConst32kull() { 4030entry: 4031 ret <2 x i64> <i64 65535, i64 65535> 4032; P9BE-LABEL: spltConst32kull 4033; P9LE-LABEL: spltConst32kull 4034; P8BE-LABEL: spltConst32kull 4035; P8LE-LABEL: spltConst32kull 4036; P9BE: lxvx 4037; P9BE: blr 4038; P9LE: lxvx 4039; P9LE: blr 4040; P8BE: lxvd2x 4041; P8BE: blr 4042; P8LE: lxvd2x 4043; P8LE: blr 4044} 4045 4046; Function Attrs: norecurse nounwind readnone 4047define <2 x i64> @fromRegsull(i64 %a, i64 %b) { 4048entry: 4049 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 4050 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 4051 ret <2 x i64> %vecinit1 4052; P9BE-LABEL: fromRegsull 4053; P9LE-LABEL: fromRegsull 4054; P8BE-LABEL: fromRegsull 4055; P8LE-LABEL: fromRegsull 4056; P9BE: mtvsrdd v2, r3, r4 4057; P9BE: blr 4058; P9LE: mtvsrdd v2, r4, r3 4059; P9LE: blr 4060; P8BE-DAG: mtvsrd {{[vsf0-9]+}}, r3 4061; P8BE-DAG: mtvsrd {{[vsf0-9]+}}, r4 4062; P8BE: xxmrghd v2 4063; P8BE: blr 4064; P8LE-DAG: mtvsrd {{[vsf0-9]+}}, r3 4065; P8LE-DAG: mtvsrd {{[vsf0-9]+}}, r4 4066; P8LE: xxmrghd v2 4067; P8LE: blr 4068} 4069 4070; Function Attrs: norecurse nounwind readnone 4071define <2 x i64> @fromDiffConstsull() { 4072entry: 4073 ret <2 x i64> <i64 242, i64 -113> 4074; P9BE-LABEL: fromDiffConstsull 4075; P9LE-LABEL: fromDiffConstsull 4076; P8BE-LABEL: fromDiffConstsull 4077; P8LE-LABEL: fromDiffConstsull 4078; P9BE: lxvx 4079; P9BE: blr 4080; P9LE: lxvx 4081; P9LE: blr 4082; P8BE: lxvd2x 4083; P8BE: blr 4084; P8LE: lxvd2x 4085; P8LE: blr 4086} 4087 4088; Function Attrs: norecurse nounwind readonly 4089define <2 x i64> @fromDiffMemConsAull(i64* nocapture readonly %arr) { 4090entry: 4091 %0 = load i64, i64* %arr, align 8 4092 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4093 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 1 4094 %1 = load i64, i64* %arrayidx1, align 8 4095 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4096 ret <2 x i64> %vecinit2 4097; P9BE-LABEL: fromDiffMemConsAull 4098; P9LE-LABEL: fromDiffMemConsAull 4099; P8BE-LABEL: fromDiffMemConsAull 4100; P8LE-LABEL: fromDiffMemConsAull 4101; P9BE: lxvx v2 4102; P9BE: blr 4103; P9LE: lxvx v2 4104; P9LE: blr 4105; P8BE: lxvd2x v2 4106; P8BE: blr 4107; P8LE: lxvd2x 4108; P8LE: xxswapd v2 4109; P8LE: blr 4110} 4111 4112; Function Attrs: norecurse nounwind readonly 4113define <2 x i64> @fromDiffMemConsDull(i64* nocapture readonly %arr) { 4114entry: 4115 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 3 4116 %0 = load i64, i64* %arrayidx, align 8 4117 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4118 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 2 4119 %1 = load i64, i64* %arrayidx1, align 8 4120 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4121 ret <2 x i64> %vecinit2 4122; P9BE-LABEL: fromDiffMemConsDull 4123; P9LE-LABEL: fromDiffMemConsDull 4124; P8BE-LABEL: fromDiffMemConsDull 4125; P8LE-LABEL: fromDiffMemConsDull 4126; P9BE: lxvx v2 4127; P9BE: blr 4128; P9LE: lxvx 4129; P9LE: xxswapd v2 4130; P9LE: blr 4131; P8BE: lxvd2x 4132; P8BE: xxswapd v2 4133; P8BE-NEXT: blr 4134; P8LE: lxvd2x v2 4135; P8LE-NEXT: blr 4136} 4137 4138; Function Attrs: norecurse nounwind readonly 4139define <2 x i64> @fromDiffMemVarAull(i64* nocapture readonly %arr, i32 signext %elem) { 4140entry: 4141 %idxprom = sext i32 %elem to i64 4142 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4143 %0 = load i64, i64* %arrayidx, align 8 4144 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4145 %add = add nsw i32 %elem, 1 4146 %idxprom1 = sext i32 %add to i64 4147 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 4148 %1 = load i64, i64* %arrayidx2, align 8 4149 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4150 ret <2 x i64> %vecinit3 4151; P9BE-LABEL: fromDiffMemVarAull 4152; P9LE-LABEL: fromDiffMemVarAull 4153; P8BE-LABEL: fromDiffMemVarAull 4154; P8LE-LABEL: fromDiffMemVarAull 4155; P9BE: sldi 4156; P9BE: lxvx v2 4157; P9BE-NEXT: blr 4158; P9LE: sldi 4159; P9LE: lxvx v2 4160; P9LE-NEXT: blr 4161; P8BE: sldi 4162; P8BE: lxvd2x v2 4163; P8BE-NEXT: blr 4164; P8LE: sldi 4165; P8LE: lxvd2x 4166; P8LE: xxswapd v2 4167; P8LE-NEXT: blr 4168} 4169 4170; Function Attrs: norecurse nounwind readonly 4171define <2 x i64> @fromDiffMemVarDull(i64* nocapture readonly %arr, i32 signext %elem) { 4172entry: 4173 %idxprom = sext i32 %elem to i64 4174 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4175 %0 = load i64, i64* %arrayidx, align 8 4176 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4177 %sub = add nsw i32 %elem, -1 4178 %idxprom1 = sext i32 %sub to i64 4179 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 4180 %1 = load i64, i64* %arrayidx2, align 8 4181 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4182 ret <2 x i64> %vecinit3 4183; P9BE-LABEL: fromDiffMemVarDull 4184; P9LE-LABEL: fromDiffMemVarDull 4185; P8BE-LABEL: fromDiffMemVarDull 4186; P8LE-LABEL: fromDiffMemVarDull 4187; P9BE: sldi 4188; P9BE: lxvx 4189; P9BE: xxswapd v2 4190; P9BE-NEXT: blr 4191; P9LE: sldi 4192; P9LE: lxvx 4193; P9LE: xxswapd v2 4194; P9LE-NEXT: blr 4195; P8BE: sldi 4196; P8BE: lxvd2x 4197; P8BE: xxswapd v2 4198; P8BE-NEXT: blr 4199; P8LE: sldi 4200; P8LE: lxvd2x v2 4201; P8LE-NEXT: blr 4202} 4203 4204; Function Attrs: norecurse nounwind readonly 4205define <2 x i64> @fromRandMemConsull(i64* nocapture readonly %arr) { 4206entry: 4207 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4 4208 %0 = load i64, i64* %arrayidx, align 8 4209 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4210 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18 4211 %1 = load i64, i64* %arrayidx1, align 8 4212 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4213 ret <2 x i64> %vecinit2 4214; P9BE-LABEL: fromRandMemConsull 4215; P9LE-LABEL: fromRandMemConsull 4216; P8BE-LABEL: fromRandMemConsull 4217; P8LE-LABEL: fromRandMemConsull 4218; P9BE: ld 4219; P9BE: ld 4220; P9BE: mtvsrdd v2 4221; P9BE-NEXT: blr 4222; P9LE: ld 4223; P9LE: ld 4224; P9LE: mtvsrdd v2 4225; P9LE-NEXT: blr 4226; P8BE: ld 4227; P8BE: ld 4228; P8BE-DAG: mtvsrd 4229; P8BE-DAG: mtvsrd 4230; P8BE: xxmrghd v2 4231; P8BE-NEXT: blr 4232; P8LE: ld 4233; P8LE: ld 4234; P8LE-DAG: mtvsrd 4235; P8LE-DAG: mtvsrd 4236; P8LE: xxmrghd v2 4237; P8LE-NEXT: blr 4238} 4239 4240; Function Attrs: norecurse nounwind readonly 4241define <2 x i64> @fromRandMemVarull(i64* nocapture readonly %arr, i32 signext %elem) { 4242entry: 4243 %add = add nsw i32 %elem, 4 4244 %idxprom = sext i32 %add to i64 4245 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4246 %0 = load i64, i64* %arrayidx, align 8 4247 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4248 %add1 = add nsw i32 %elem, 1 4249 %idxprom2 = sext i32 %add1 to i64 4250 %arrayidx3 = getelementptr inbounds i64, i64* %arr, i64 %idxprom2 4251 %1 = load i64, i64* %arrayidx3, align 8 4252 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4253 ret <2 x i64> %vecinit4 4254; P9BE-LABEL: fromRandMemVarull 4255; P9LE-LABEL: fromRandMemVarull 4256; P8BE-LABEL: fromRandMemVarull 4257; P8LE-LABEL: fromRandMemVarull 4258; P9BE: sldi 4259; P9BE: ld 4260; P9BE: ld 4261; P9BE: mtvsrdd v2 4262; P9BE-NEXT: blr 4263; P9LE: sldi 4264; P9LE: ld 4265; P9LE: ld 4266; P9LE: mtvsrdd v2 4267; P9LE-NEXT: blr 4268; P8BE: sldi 4269; P8BE: ld 4270; P8BE: ld 4271; P8BE: mtvsrd 4272; P8BE: mtvsrd 4273; P8BE: xxmrghd v2 4274; P8BE-NEXT: blr 4275; P8LE: sldi 4276; P8LE: ld 4277; P8LE: ld 4278; P8LE: mtvsrd 4279; P8LE: mtvsrd 4280; P8LE: xxmrghd v2 4281; P8LE-NEXT: blr 4282} 4283 4284; Function Attrs: norecurse nounwind readnone 4285define <2 x i64> @spltRegValull(i64 %val) { 4286entry: 4287 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0 4288 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4289 ret <2 x i64> %splat.splat 4290; P9BE-LABEL: spltRegValull 4291; P9LE-LABEL: spltRegValull 4292; P8BE-LABEL: spltRegValull 4293; P8LE-LABEL: spltRegValull 4294; P9BE: mtvsrdd v2, r3, r3 4295; P9BE-NEXT: blr 4296; P9LE: mtvsrdd v2, r3, r3 4297; P9LE-NEXT: blr 4298; P8BE: mtvsrd {{[vsf]+}}[[REG1:[0-9]+]], r3 4299; P8BE: xxspltd v2, {{[vsf]+}}[[REG1]], 0 4300; P8BE-NEXT: blr 4301; P8LE: mtvsrd {{[vsf]+}}[[REG1:[0-9]+]], r3 4302; P8LE: xxspltd v2, {{[vsf]+}}[[REG1]], 0 4303; P8LE-NEXT: blr 4304} 4305 4306; Function Attrs: norecurse nounwind readonly 4307define <2 x i64> @spltMemValull(i64* nocapture readonly %ptr) { 4308entry: 4309 %0 = load i64, i64* %ptr, align 8 4310 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 4311 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4312 ret <2 x i64> %splat.splat 4313; P9BE-LABEL: spltMemValull 4314; P9LE-LABEL: spltMemValull 4315; P8BE-LABEL: spltMemValull 4316; P8LE-LABEL: spltMemValull 4317; P9BE: lxvdsx v2 4318; P9BE-NEXT: blr 4319; P9LE: lxvdsx v2 4320; P9LE-NEXT: blr 4321; P8BE: lxvdsx v2 4322; P8BE-NEXT: blr 4323; P8LE: lxvdsx v2 4324; P8LE-NEXT: blr 4325} 4326 4327; Function Attrs: norecurse nounwind readnone 4328define <2 x i64> @spltCnstConvftoull() { 4329entry: 4330 ret <2 x i64> <i64 4, i64 4> 4331; P9BE-LABEL: spltCnstConvftoull 4332; P9LE-LABEL: spltCnstConvftoull 4333; P8BE-LABEL: spltCnstConvftoull 4334; P8LE-LABEL: spltCnstConvftoull 4335; P9BE: lxvx 4336; P9BE: blr 4337; P9LE: lxvx 4338; P9LE: blr 4339; P8BE: lxvd2x 4340; P8BE: blr 4341; P8LE: lxvd2x 4342; P8LE: blr 4343} 4344 4345; Function Attrs: norecurse nounwind readnone 4346define <2 x i64> @fromRegsConvftoull(float %a, float %b) { 4347entry: 4348 %conv = fptoui float %a to i64 4349 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4350 %conv1 = fptoui float %b to i64 4351 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 4352 ret <2 x i64> %vecinit2 4353; P9BE-LABEL: fromRegsConvftoull 4354; P9LE-LABEL: fromRegsConvftoull 4355; P8BE-LABEL: fromRegsConvftoull 4356; P8LE-LABEL: fromRegsConvftoull 4357; P9BE: xxmrghd 4358; P9BE: xvcvdpuxds v2 4359; P9BE-NEXT: blr 4360; P9LE: xxmrghd 4361; P9LE: xvcvdpuxds v2 4362; P9LE-NEXT: blr 4363; P8BE: xxmrghd 4364; P8BE: xvcvdpuxds v2 4365; P8BE-NEXT: blr 4366; P8LE: xxmrghd 4367; P8LE: xvcvdpuxds v2 4368; P8LE-NEXT: blr 4369} 4370 4371; Function Attrs: norecurse nounwind readnone 4372define <2 x i64> @fromDiffConstsConvftoull() { 4373entry: 4374 ret <2 x i64> <i64 24, i64 234> 4375; P9BE-LABEL: fromDiffConstsConvftoull 4376; P9LE-LABEL: fromDiffConstsConvftoull 4377; P8BE-LABEL: fromDiffConstsConvftoull 4378; P8LE-LABEL: fromDiffConstsConvftoull 4379; P9BE: lxvx v2 4380; P9BE: blr 4381; P9LE: lxvx v2 4382; P9LE: blr 4383; P8BE: lxvd2x v2 4384; P8BE: blr 4385; P8LE: lxvd2x 4386; P8LE: xxswapd v2 4387; P8LE: blr 4388} 4389 4390; Function Attrs: norecurse nounwind readonly 4391define <2 x i64> @fromDiffMemConsAConvftoull(float* nocapture readonly %ptr) { 4392entry: 4393 %0 = load float, float* %ptr, align 4 4394 %conv = fptoui float %0 to i64 4395 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4396 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1 4397 %1 = load float, float* %arrayidx1, align 4 4398 %conv2 = fptoui float %1 to i64 4399 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4400 ret <2 x i64> %vecinit3 4401; P9BE-LABEL: fromDiffMemConsAConvftoull 4402; P9LE-LABEL: fromDiffMemConsAConvftoull 4403; P8BE-LABEL: fromDiffMemConsAConvftoull 4404; P8LE-LABEL: fromDiffMemConsAConvftoull 4405; P9BE: lfs 4406; P9BE: lfs 4407; P9BE: xxmrghd 4408; P9BE-NEXT: xvcvdpuxds v2 4409; P9BE-NEXT: blr 4410; P9LE: lfs 4411; P9LE: lfs 4412; P9LE: xxmrghd 4413; P9LE-NEXT: xvcvdpuxds v2 4414; P9LE-NEXT: blr 4415; P8BE: lxsspx 4416; P8BE: lxsspx 4417; P8BE: xxmrghd 4418; P8BE-NEXT: xvcvdpuxds v2 4419; P8BE-NEXT: blr 4420; P8LE: lxsspx 4421; P8LE: lxsspx 4422; P8LE: xxmrghd 4423; P8LE-NEXT: xvcvdpuxds v2 4424; P8LE-NEXT: blr 4425} 4426 4427; Function Attrs: norecurse nounwind readonly 4428define <2 x i64> @fromDiffMemConsDConvftoull(float* nocapture readonly %ptr) { 4429entry: 4430 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 4431 %0 = load float, float* %arrayidx, align 4 4432 %conv = fptoui float %0 to i64 4433 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4434 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 4435 %1 = load float, float* %arrayidx1, align 4 4436 %conv2 = fptoui float %1 to i64 4437 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4438 ret <2 x i64> %vecinit3 4439; P9BE-LABEL: fromDiffMemConsDConvftoull 4440; P9LE-LABEL: fromDiffMemConsDConvftoull 4441; P8BE-LABEL: fromDiffMemConsDConvftoull 4442; P8LE-LABEL: fromDiffMemConsDConvftoull 4443; P9BE: lfs 4444; P9BE: lfs 4445; P9BE: xxmrghd 4446; P9BE-NEXT: xvcvdpuxds v2 4447; P9BE-NEXT: blr 4448; P9LE: lfs 4449; P9LE: lfs 4450; P9LE: xxmrghd 4451; P9LE-NEXT: xvcvdpuxds v2 4452; P9LE-NEXT: blr 4453; P8BE: lxsspx 4454; P8BE: lxsspx 4455; P8BE: xxmrghd 4456; P8BE-NEXT: xvcvdpuxds v2 4457; P8BE-NEXT: blr 4458; P8LE: lxsspx 4459; P8LE: lxsspx 4460; P8LE: xxmrghd 4461; P8LE-NEXT: xvcvdpuxds v2 4462; P8LE-NEXT: blr 4463} 4464 4465; Function Attrs: norecurse nounwind readonly 4466define <2 x i64> @fromDiffMemVarAConvftoull(float* nocapture readonly %arr, i32 signext %elem) { 4467entry: 4468 %idxprom = sext i32 %elem to i64 4469 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 4470 %0 = load float, float* %arrayidx, align 4 4471 %conv = fptoui float %0 to i64 4472 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4473 %add = add nsw i32 %elem, 1 4474 %idxprom1 = sext i32 %add to i64 4475 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 4476 %1 = load float, float* %arrayidx2, align 4 4477 %conv3 = fptoui float %1 to i64 4478 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4479 ret <2 x i64> %vecinit4 4480; P9BE-LABEL: fromDiffMemVarAConvftoull 4481; P9LE-LABEL: fromDiffMemVarAConvftoull 4482; P8BE-LABEL: fromDiffMemVarAConvftoull 4483; P8LE-LABEL: fromDiffMemVarAConvftoull 4484; P9BE: sldi 4485; P9BE: lfsux 4486; P9BE: lfs 4487; P9BE: xxmrghd 4488; P9BE-NEXT: xvcvdpuxds v2 4489; P9BE-NEXT: blr 4490; P9LE: sldi 4491; P9LE: lfsux 4492; P9LE: lfs 4493; P9LE: xxmrghd 4494; P9LE-NEXT: xvcvdpuxds v2 4495; P9LE-NEXT: blr 4496; P8BE: sldi 4497; P8BE: lfsux 4498; P8BE: lxsspx 4499; P8BE: xxmrghd 4500; P8BE-NEXT: xvcvdpuxds v2 4501; P8BE-NEXT: blr 4502; P8LE: sldi 4503; P8LE: lfsux 4504; P8LE: lxsspx 4505; P8LE: xxmrghd 4506; P8LE-NEXT: xvcvdpuxds v2 4507; P8LE-NEXT: blr 4508} 4509 4510; Function Attrs: norecurse nounwind readonly 4511define <2 x i64> @fromDiffMemVarDConvftoull(float* nocapture readonly %arr, i32 signext %elem) { 4512entry: 4513 %idxprom = sext i32 %elem to i64 4514 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 4515 %0 = load float, float* %arrayidx, align 4 4516 %conv = fptoui float %0 to i64 4517 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4518 %sub = add nsw i32 %elem, -1 4519 %idxprom1 = sext i32 %sub to i64 4520 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 4521 %1 = load float, float* %arrayidx2, align 4 4522 %conv3 = fptoui float %1 to i64 4523 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4524 ret <2 x i64> %vecinit4 4525; P9BE-LABEL: fromDiffMemVarDConvftoull 4526; P9LE-LABEL: fromDiffMemVarDConvftoull 4527; P8BE-LABEL: fromDiffMemVarDConvftoull 4528; P8LE-LABEL: fromDiffMemVarDConvftoull 4529; P9BE: sldi 4530; P9BE: lfsux 4531; P9BE: lfs 4532; P9BE: xxmrghd 4533; P9BE-NEXT: xvcvdpuxds v2 4534; P9BE-NEXT: blr 4535; P9LE: sldi 4536; P9LE: lfsux 4537; P9LE: lfs 4538; P9LE: xxmrghd 4539; P9LE-NEXT: xvcvdpuxds v2 4540; P9LE-NEXT: blr 4541; P8BE: sldi 4542; P8BE: lfsux 4543; P8BE: lxsspx 4544; P8BE: xxmrghd 4545; P8BE-NEXT: xvcvdpuxds v2 4546; P8BE-NEXT: blr 4547; P8LE: sldi 4548; P8LE: lfsux 4549; P8LE: lxsspx 4550; P8LE: xxmrghd 4551; P8LE-NEXT: xvcvdpuxds v2 4552; P8LE-NEXT: blr 4553} 4554 4555; Function Attrs: norecurse nounwind readnone 4556define <2 x i64> @spltRegValConvftoull(float %val) { 4557entry: 4558 %conv = fptoui float %val to i64 4559 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4560 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4561 ret <2 x i64> %splat.splat 4562; P9BE-LABEL: spltRegValConvftoull 4563; P9LE-LABEL: spltRegValConvftoull 4564; P8BE-LABEL: spltRegValConvftoull 4565; P8LE-LABEL: spltRegValConvftoull 4566; P9BE: xscvdpuxds 4567; P9BE-NEXT: xxspltd v2 4568; P9BE-NEXT: blr 4569; P9LE: xscvdpuxds 4570; P9LE-NEXT: xxspltd v2 4571; P9LE-NEXT: blr 4572; P8BE: xscvdpuxds 4573; P8BE-NEXT: xxspltd v2 4574; P8BE-NEXT: blr 4575; P8LE: xscvdpuxds 4576; P8LE-NEXT: xxspltd v2 4577; P8LE-NEXT: blr 4578} 4579 4580; Function Attrs: norecurse nounwind readonly 4581define <2 x i64> @spltMemValConvftoull(float* nocapture readonly %ptr) { 4582entry: 4583 %0 = load float, float* %ptr, align 4 4584 %conv = fptoui float %0 to i64 4585 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4586 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4587 ret <2 x i64> %splat.splat 4588; P9BE-LABEL: spltMemValConvftoull 4589; P9LE-LABEL: spltMemValConvftoull 4590; P8BE-LABEL: spltMemValConvftoull 4591; P8LE-LABEL: spltMemValConvftoull 4592; P9BE: lfs 4593; P9BE-NEXT: xscvdpuxds 4594; P9BE-NEXT: xxspltd v2 4595; P9BE-NEXT: blr 4596; P9LE: lfs 4597; P9LE-NEXT: xscvdpuxds 4598; P9LE-NEXT: xxspltd v2 4599; P9LE-NEXT: blr 4600; P8BE: lxsspx 4601; P8BE-NEXT: xscvdpuxds 4602; P8BE-NEXT: xxspltd v2 4603; P8BE-NEXT: blr 4604; P8LE: lxsspx 4605; P8LE-NEXT: xscvdpuxds 4606; P8LE-NEXT: xxspltd v2 4607; P8LE-NEXT: blr 4608} 4609 4610; Function Attrs: norecurse nounwind readnone 4611define <2 x i64> @spltCnstConvdtoull() { 4612entry: 4613 ret <2 x i64> <i64 4, i64 4> 4614; P9BE-LABEL: spltCnstConvdtoull 4615; P9LE-LABEL: spltCnstConvdtoull 4616; P8BE-LABEL: spltCnstConvdtoull 4617; P8LE-LABEL: spltCnstConvdtoull 4618; P9BE: lxvx 4619; P9BE: blr 4620; P9LE: lxvx 4621; P9LE: blr 4622; P8BE: lxvd2x 4623; P8BE: blr 4624; P8LE: lxvd2x 4625; P8LE: blr 4626} 4627 4628; Function Attrs: norecurse nounwind readnone 4629define <2 x i64> @fromRegsConvdtoull(double %a, double %b) { 4630entry: 4631 %conv = fptoui double %a to i64 4632 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4633 %conv1 = fptoui double %b to i64 4634 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 4635 ret <2 x i64> %vecinit2 4636; P9BE-LABEL: fromRegsConvdtoull 4637; P9LE-LABEL: fromRegsConvdtoull 4638; P8BE-LABEL: fromRegsConvdtoull 4639; P8LE-LABEL: fromRegsConvdtoull 4640; P9BE: xxmrghd 4641; P9BE-NEXT: xvcvdpuxds 4642; P9BE-NEXT: blr 4643; P9LE: xxmrghd 4644; P9LE-NEXT: xvcvdpuxds 4645; P9LE-NEXT: blr 4646; P8BE: xxmrghd 4647; P8BE-NEXT: xvcvdpuxds 4648; P8BE-NEXT: blr 4649; P8LE: xxmrghd 4650; P8LE-NEXT: xvcvdpuxds 4651; P8LE-NEXT: blr 4652} 4653 4654; Function Attrs: norecurse nounwind readnone 4655define <2 x i64> @fromDiffConstsConvdtoull() { 4656entry: 4657 ret <2 x i64> <i64 24, i64 234> 4658; P9BE-LABEL: fromDiffConstsConvdtoull 4659; P9LE-LABEL: fromDiffConstsConvdtoull 4660; P8BE-LABEL: fromDiffConstsConvdtoull 4661; P8LE-LABEL: fromDiffConstsConvdtoull 4662; P9BE: lxvx 4663; P9BE: blr 4664; P9LE: lxvx 4665; P9LE: blr 4666; P8BE: lxvd2x 4667; P8BE: blr 4668; P8LE: lxvd2x 4669; P8LE: blr 4670} 4671 4672; Function Attrs: norecurse nounwind readonly 4673define <2 x i64> @fromDiffMemConsAConvdtoull(double* nocapture readonly %ptr) { 4674entry: 4675 %0 = bitcast double* %ptr to <2 x double>* 4676 %1 = load <2 x double>, <2 x double>* %0, align 8 4677 %2 = fptoui <2 x double> %1 to <2 x i64> 4678 ret <2 x i64> %2 4679; P9BE-LABEL: fromDiffMemConsAConvdtoull 4680; P9LE-LABEL: fromDiffMemConsAConvdtoull 4681; P8BE-LABEL: fromDiffMemConsAConvdtoull 4682; P8LE-LABEL: fromDiffMemConsAConvdtoull 4683; P9BE: lxvx 4684; P9BE-NEXT: xvcvdpuxds v2 4685; P9BE-NEXT: blr 4686; P9LE: lxvx 4687; P9LE-NEXT: xvcvdpuxds v2 4688; P9LE-NEXT: blr 4689; P8BE: lxvd2x 4690; P8BE-NEXT: xvcvdpuxds v2 4691; P8BE-NEXT: blr 4692; P8LE: lxvd2x 4693; P8LE: xxswapd 4694; P8LE-NEXT: xvcvdpuxds v2 4695; P8LE-NEXT: blr 4696} 4697 4698; Function Attrs: norecurse nounwind readonly 4699define <2 x i64> @fromDiffMemConsDConvdtoull(double* nocapture readonly %ptr) { 4700entry: 4701 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 4702 %0 = load double, double* %arrayidx, align 8 4703 %conv = fptoui double %0 to i64 4704 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4705 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 4706 %1 = load double, double* %arrayidx1, align 8 4707 %conv2 = fptoui double %1 to i64 4708 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4709 ret <2 x i64> %vecinit3 4710; P9BE-LABEL: fromDiffMemConsDConvdtoull 4711; P9LE-LABEL: fromDiffMemConsDConvdtoull 4712; P8BE-LABEL: fromDiffMemConsDConvdtoull 4713; P8LE-LABEL: fromDiffMemConsDConvdtoull 4714; P9BE: lxvx 4715; P9BE-NEXT: xxswapd 4716; P9BE-NEXT: xvcvdpuxds v2 4717; P9BE-NEXT: blr 4718; P9LE: lxvx 4719; P9LE-NEXT: xxswapd 4720; P9LE-NEXT: xvcvdpuxds v2 4721; P9LE-NEXT: blr 4722; P8BE: lxvd2x 4723; P8BE-NEXT: xxswapd 4724; P8BE-NEXT: xvcvdpuxds v2 4725; P8BE-NEXT: blr 4726; P8LE: lxvd2x 4727; P8LE-NEXT: xvcvdpuxds v2 4728; P8LE-NEXT: blr 4729} 4730 4731; Function Attrs: norecurse nounwind readonly 4732define <2 x i64> @fromDiffMemVarAConvdtoull(double* nocapture readonly %arr, i32 signext %elem) { 4733entry: 4734 %idxprom = sext i32 %elem to i64 4735 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 4736 %0 = load double, double* %arrayidx, align 8 4737 %conv = fptoui double %0 to i64 4738 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4739 %add = add nsw i32 %elem, 1 4740 %idxprom1 = sext i32 %add to i64 4741 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 4742 %1 = load double, double* %arrayidx2, align 8 4743 %conv3 = fptoui double %1 to i64 4744 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4745 ret <2 x i64> %vecinit4 4746; P9BE-LABEL: fromDiffMemVarAConvdtoull 4747; P9LE-LABEL: fromDiffMemVarAConvdtoull 4748; P8BE-LABEL: fromDiffMemVarAConvdtoull 4749; P8LE-LABEL: fromDiffMemVarAConvdtoull 4750; P9BE: sldi 4751; P9BE: lxvx 4752; P9BE-NEXT: xvcvdpuxds v2 4753; P9BE-NEXT: blr 4754; P9LE: sldi 4755; P9LE: lxvx 4756; P9LE-NEXT: xvcvdpuxds v2 4757; P9LE-NEXT: blr 4758; P8BE: sldi 4759; P8BE: lxvd2x 4760; P8BE-NEXT: xvcvdpuxds v2 4761; P8BE-NEXT: blr 4762; P8LE: sldi 4763; P8LE: lxvd2x 4764; P8LE-NEXT: xxswapd 4765; P8LE-NEXT: xvcvdpuxds v2 4766; P8LE-NEXT: blr 4767} 4768 4769; Function Attrs: norecurse nounwind readonly 4770define <2 x i64> @fromDiffMemVarDConvdtoull(double* nocapture readonly %arr, i32 signext %elem) { 4771entry: 4772 %idxprom = sext i32 %elem to i64 4773 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 4774 %0 = load double, double* %arrayidx, align 8 4775 %conv = fptoui double %0 to i64 4776 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4777 %sub = add nsw i32 %elem, -1 4778 %idxprom1 = sext i32 %sub to i64 4779 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 4780 %1 = load double, double* %arrayidx2, align 8 4781 %conv3 = fptoui double %1 to i64 4782 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4783 ret <2 x i64> %vecinit4 4784; P9BE-LABEL: fromDiffMemVarDConvdtoull 4785; P9LE-LABEL: fromDiffMemVarDConvdtoull 4786; P8BE-LABEL: fromDiffMemVarDConvdtoull 4787; P8LE-LABEL: fromDiffMemVarDConvdtoull 4788; P9BE: sldi 4789; P9BE: lxvx 4790; P9BE-NEXT: xxswapd 4791; P9BE-NEXT: xvcvdpuxds v2 4792; P9BE-NEXT: blr 4793; P9LE: sldi 4794; P9LE: lxvx 4795; P9LE-NEXT: xxswapd 4796; P9LE-NEXT: xvcvdpuxds v2 4797; P9LE-NEXT: blr 4798; P8BE: sldi 4799; P8BE: lxvd2x 4800; P8BE-NEXT: xxswapd 4801; P8BE-NEXT: xvcvdpuxds v2 4802; P8BE-NEXT: blr 4803; P8LE: sldi 4804; P8LE: lxvd2x 4805; P8LE-NEXT: xvcvdpuxds v2 4806; P8LE-NEXT: blr 4807} 4808 4809; Function Attrs: norecurse nounwind readnone 4810define <2 x i64> @spltRegValConvdtoull(double %val) { 4811entry: 4812 %conv = fptoui double %val to i64 4813 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4814 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4815 ret <2 x i64> %splat.splat 4816; P9BE-LABEL: spltRegValConvdtoull 4817; P9LE-LABEL: spltRegValConvdtoull 4818; P8BE-LABEL: spltRegValConvdtoull 4819; P8LE-LABEL: spltRegValConvdtoull 4820; P9BE: xscvdpuxds 4821; P9BE-NEXT: xxspltd v2 4822; P9BE-NEXT: blr 4823; P9LE: xscvdpuxds 4824; P9LE-NEXT: xxspltd v2 4825; P9LE-NEXT: blr 4826; P8BE: xscvdpuxds 4827; P8BE-NEXT: xxspltd v2 4828; P8BE-NEXT: blr 4829; P8LE: xscvdpuxds 4830; P8LE-NEXT: xxspltd v2 4831; P8LE-NEXT: blr 4832} 4833 4834; Function Attrs: norecurse nounwind readonly 4835define <2 x i64> @spltMemValConvdtoull(double* nocapture readonly %ptr) { 4836entry: 4837 %0 = load double, double* %ptr, align 8 4838 %conv = fptoui double %0 to i64 4839 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4840 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4841 ret <2 x i64> %splat.splat 4842; P9BE-LABEL: spltMemValConvdtoull 4843; P9LE-LABEL: spltMemValConvdtoull 4844; P8BE-LABEL: spltMemValConvdtoull 4845; P8LE-LABEL: spltMemValConvdtoull 4846; P9BE: lxvdsx 4847; P9BE-NEXT: xvcvdpuxds 4848; P9BE-NEXT: blr 4849; P9LE: lxvdsx 4850; P9LE-NEXT: xvcvdpuxds 4851; P9LE-NEXT: blr 4852; P8BE: lxvdsx 4853; P8BE-NEXT: xvcvdpuxds 4854; P8BE-NEXT: blr 4855; P8LE: lxvdsx 4856; P8LE-NEXT: xvcvdpuxds 4857; P8LE-NEXT: blr 4858} 4859