1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=powerpc64le-- -verify-machineinstrs | FileCheck %s
3
4define i32 @sub_zext_cmp_mask_same_size_result(i32 %x) {
5; CHECK-LABEL: sub_zext_cmp_mask_same_size_result:
6; CHECK:       # %bb.0:
7; CHECK-NEXT:    clrldi 3, 3, 63
8; CHECK-NEXT:    ori 3, 3, 65508
9; CHECK-NEXT:    oris 3, 3, 65535
10; CHECK-NEXT:    blr
11  %a = and i32 %x, 1
12  %c = icmp eq i32 %a, 0
13  %z = zext i1 %c to i32
14  %r = sub i32 -27, %z
15  ret i32 %r
16}
17
18define i32 @sub_zext_cmp_mask_wider_result(i8 %x) {
19; CHECK-LABEL: sub_zext_cmp_mask_wider_result:
20; CHECK:       # %bb.0:
21; CHECK-NEXT:    clrldi 3, 3, 63
22; CHECK-NEXT:    ori 3, 3, 26
23; CHECK-NEXT:    blr
24  %a = and i8 %x, 1
25  %c = icmp eq i8 %a, 0
26  %z = zext i1 %c to i32
27  %r = sub i32 27, %z
28  ret i32 %r
29}
30
31define i8 @sub_zext_cmp_mask_narrower_result(i32 %x) {
32; CHECK-LABEL: sub_zext_cmp_mask_narrower_result:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    clrldi 3, 3, 63
35; CHECK-NEXT:    ori 3, 3, 46
36; CHECK-NEXT:    blr
37  %a = and i32 %x, 1
38  %c = icmp eq i32 %a, 0
39  %z = zext i1 %c to i8
40  %r = sub i8 47, %z
41  ret i8 %r
42}
43
44define i8 @add_zext_cmp_mask_same_size_result(i8 %x) {
45; CHECK-LABEL: add_zext_cmp_mask_same_size_result:
46; CHECK:       # %bb.0:
47; CHECK-NEXT:    rlwinm 3, 3, 0, 31, 31
48; CHECK-NEXT:    subfic 3, 3, 27
49; CHECK-NEXT:    blr
50  %a = and i8 %x, 1
51  %c = icmp eq i8 %a, 0
52  %z = zext i1 %c to i8
53  %r = add i8 %z, 26
54  ret i8 %r
55}
56
57define i32 @add_zext_cmp_mask_wider_result(i8 %x) {
58; CHECK-LABEL: add_zext_cmp_mask_wider_result:
59; CHECK:       # %bb.0:
60; CHECK-NEXT:    rlwinm 3, 3, 0, 31, 31
61; CHECK-NEXT:    subfic 3, 3, 27
62; CHECK-NEXT:    blr
63  %a = and i8 %x, 1
64  %c = icmp eq i8 %a, 0
65  %z = zext i1 %c to i32
66  %r = add i32 %z, 26
67  ret i32 %r
68}
69
70define i8 @add_zext_cmp_mask_narrower_result(i32 %x) {
71; CHECK-LABEL: add_zext_cmp_mask_narrower_result:
72; CHECK:       # %bb.0:
73; CHECK-NEXT:    rlwinm 3, 3, 0, 31, 31
74; CHECK-NEXT:    subfic 3, 3, 43
75; CHECK-NEXT:    blr
76  %a = and i32 %x, 1
77  %c = icmp eq i32 %a, 0
78  %z = zext i1 %c to i8
79  %r = add i8 %z, 42
80  ret i8 %r
81}
82
83define i32 @low_bit_select_constants_bigger_false_same_size_result(i32 %x) {
84; CHECK-LABEL: low_bit_select_constants_bigger_false_same_size_result:
85; CHECK:       # %bb.0:
86; CHECK-NEXT:    not 3, 3
87; CHECK-NEXT:    clrldi 3, 3, 63
88; CHECK-NEXT:    subfic 3, 3, 43
89; CHECK-NEXT:    blr
90  %a = and i32 %x, 1
91  %c = icmp eq i32 %a, 0
92  %r = select i1 %c, i32 42, i32 43
93  ret i32 %r
94}
95
96define i64 @low_bit_select_constants_bigger_false_wider_result(i32 %x) {
97; CHECK-LABEL: low_bit_select_constants_bigger_false_wider_result:
98; CHECK:       # %bb.0:
99; CHECK-NEXT:    not 3, 3
100; CHECK-NEXT:    clrldi 3, 3, 63
101; CHECK-NEXT:    subfic 3, 3, 27
102; CHECK-NEXT:    blr
103  %a = and i32 %x, 1
104  %c = icmp eq i32 %a, 0
105  %r = select i1 %c, i64 26, i64 27
106  ret i64 %r
107}
108
109define i16 @low_bit_select_constants_bigger_false_narrower_result(i32 %x) {
110; CHECK-LABEL: low_bit_select_constants_bigger_false_narrower_result:
111; CHECK:       # %bb.0:
112; CHECK-NEXT:    nor 3, 3, 3
113; CHECK-NEXT:    clrlwi 3, 3, 31
114; CHECK-NEXT:    subfic 3, 3, 37
115; CHECK-NEXT:    blr
116  %a = and i32 %x, 1
117  %c = icmp eq i32 %a, 0
118  %r = select i1 %c, i16 36, i16 37
119  ret i16 %r
120}
121
122define i8 @low_bit_select_constants_bigger_true_same_size_result(i8 %x) {
123; CHECK-LABEL: low_bit_select_constants_bigger_true_same_size_result:
124; CHECK:       # %bb.0:
125; CHECK-NEXT:    rlwinm 3, 3, 0, 31, 31
126; CHECK-NEXT:    subfic 3, 3, -29
127; CHECK-NEXT:    blr
128  %a = and i8 %x, 1
129  %c = icmp eq i8 %a, 0
130  %r = select i1 %c, i8 227, i8 226
131  ret i8 %r
132}
133
134define i32 @low_bit_select_constants_bigger_true_wider_result(i8 %x) {
135; CHECK-LABEL: low_bit_select_constants_bigger_true_wider_result:
136; CHECK:       # %bb.0:
137; CHECK-NEXT:    clrldi 3, 3, 63
138; CHECK-NEXT:    subfic 3, 3, 227
139; CHECK-NEXT:    blr
140  %a = and i8 %x, 1
141  %c = icmp eq i8 %a, 0
142  %r = select i1 %c, i32 227, i32 226
143  ret i32 %r
144}
145
146define i8 @low_bit_select_constants_bigger_true_narrower_result(i16 %x) {
147; CHECK-LABEL: low_bit_select_constants_bigger_true_narrower_result:
148; CHECK:       # %bb.0:
149; CHECK-NEXT:    rlwinm 3, 3, 0, 31, 31
150; CHECK-NEXT:    subfic 3, 3, 41
151; CHECK-NEXT:    blr
152  %a = and i16 %x, 1
153  %c = icmp eq i16 %a, 0
154  %r = select i1 %c, i8 41, i8 40
155  ret i8 %r
156}
157
158