1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names \
4; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
6; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names \
7; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
8
9; Function Attrs: nofree nounwind writeonly
10define dso_local void @test60(i8* nocapture readnone %vqp, i8* nocapture readnone %vpp, <16 x i8> %vc, i8* nocapture %resp) {
11; CHECK-LABEL: test60:
12; CHECK:       # %bb.0: # %entry
13; CHECK-NEXT:    xvcvspbf16 vs0, v2
14; CHECK-NEXT:    stxv vs0, 0(r7)
15; CHECK-NEXT:    blr
16;
17; CHECK-BE-LABEL: test60:
18; CHECK-BE:       # %bb.0: # %entry
19; CHECK-BE-NEXT:    xvcvspbf16 vs0, v2
20; CHECK-BE-NEXT:    stxv vs0, 0(r7)
21; CHECK-BE-NEXT:    blr
22entry:
23  %0 = tail call <16 x i8> @llvm.ppc.vsx.xvcvspbf16(<16 x i8> %vc)
24  %1 = bitcast i8* %resp to <16 x i8>*
25  store <16 x i8> %0, <16 x i8>* %1, align 16
26  ret void
27}
28; Function Attrs: nounwind readnone
29declare <16 x i8> @llvm.ppc.vsx.xvcvspbf16(<16 x i8>)
30
31; Function Attrs: nofree nounwind writeonly
32define dso_local void @test61(i8* nocapture readnone %vqp, i8* nocapture readnone %vpp, <16 x i8> %vc, i8* nocapture %resp) {
33; CHECK-LABEL: test61:
34; CHECK:       # %bb.0: # %entry
35; CHECK-NEXT:    xvcvbf16spn vs0, v2
36; CHECK-NEXT:    stxv vs0, 0(r7)
37; CHECK-NEXT:    blr
38;
39; CHECK-BE-LABEL: test61:
40; CHECK-BE:       # %bb.0: # %entry
41; CHECK-BE-NEXT:    xvcvbf16spn vs0, v2
42; CHECK-BE-NEXT:    stxv vs0, 0(r7)
43; CHECK-BE-NEXT:    blr
44entry:
45  %0 = tail call <16 x i8> @llvm.ppc.vsx.xvcvbf16spn(<16 x i8> %vc)
46  %1 = bitcast i8* %resp to <16 x i8>*
47  store <16 x i8> %0, <16 x i8>* %1, align 16
48  ret void
49}
50
51; Function Attrs: nounwind readnone
52declare <16 x i8> @llvm.ppc.vsx.xvcvbf16spn(<16 x i8>)
53