1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-64
3; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-32
4
5define zeroext i8 @test1(<16 x i8> %a, i32 signext %index) {
6; CHECK-64-LABEL: test1:
7; CHECK-64:       # %bb.0: # %entry
8; CHECK-64-NEXT:    vextublx 3, 3, 2
9; CHECK-64-NEXT:    clrldi 3, 3, 56
10; CHECK-64-NEXT:    blr
11;
12; CHECK-32-LABEL: test1:
13; CHECK-32:       # %bb.0: # %entry
14; CHECK-32-NEXT:    addi 4, 1, -16
15; CHECK-32-NEXT:    clrlwi 3, 3, 28
16; CHECK-32-NEXT:    stxv 34, -16(1)
17; CHECK-32-NEXT:    lbzx 3, 4, 3
18; CHECK-32-NEXT:    blr
19entry:
20  %vecext = extractelement <16 x i8> %a, i32 %index
21  ret i8 %vecext
22}
23
24define signext i8 @test2(<16 x i8> %a, i32 signext %index) {
25; CHECK-64-LABEL: test2:
26; CHECK-64:       # %bb.0: # %entry
27; CHECK-64-NEXT:    vextublx 3, 3, 2
28; CHECK-64-NEXT:    extsb 3, 3
29; CHECK-64-NEXT:    blr
30;
31; CHECK-32-LABEL: test2:
32; CHECK-32:       # %bb.0: # %entry
33; CHECK-32-NEXT:    addi 4, 1, -16
34; CHECK-32-NEXT:    clrlwi 3, 3, 28
35; CHECK-32-NEXT:    stxv 34, -16(1)
36; CHECK-32-NEXT:    lbzx 3, 4, 3
37; CHECK-32-NEXT:    extsb 3, 3
38; CHECK-32-NEXT:    blr
39entry:
40  %vecext = extractelement <16 x i8> %a, i32 %index
41  ret i8 %vecext
42}
43
44define zeroext i16 @test3(<8 x i16> %a, i32 signext %index) {
45; CHECK-64-LABEL: test3:
46; CHECK-64:       # %bb.0: # %entry
47; CHECK-64-NEXT:    rlwinm 3, 3, 1, 28, 30
48; CHECK-64-NEXT:    vextuhlx 3, 3, 2
49; CHECK-64-NEXT:    clrldi 3, 3, 48
50; CHECK-64-NEXT:    blr
51;
52; CHECK-32-LABEL: test3:
53; CHECK-32:       # %bb.0: # %entry
54; CHECK-32-NEXT:    addi 4, 1, -16
55; CHECK-32-NEXT:    rlwinm 3, 3, 1, 28, 30
56; CHECK-32-NEXT:    stxv 34, -16(1)
57; CHECK-32-NEXT:    lhzx 3, 4, 3
58; CHECK-32-NEXT:    blr
59entry:
60  %vecext = extractelement <8 x i16> %a, i32 %index
61  ret i16 %vecext
62}
63
64define signext i16 @test4(<8 x i16> %a, i32 signext %index) {
65; CHECK-64-LABEL: test4:
66; CHECK-64:       # %bb.0: # %entry
67; CHECK-64-NEXT:    rlwinm 3, 3, 1, 28, 30
68; CHECK-64-NEXT:    vextuhlx 3, 3, 2
69; CHECK-64-NEXT:    extsh 3, 3
70; CHECK-64-NEXT:    blr
71;
72; CHECK-32-LABEL: test4:
73; CHECK-32:       # %bb.0: # %entry
74; CHECK-32-NEXT:    addi 4, 1, -16
75; CHECK-32-NEXT:    rlwinm 3, 3, 1, 28, 30
76; CHECK-32-NEXT:    stxv 34, -16(1)
77; CHECK-32-NEXT:    lhax 3, 4, 3
78; CHECK-32-NEXT:    blr
79entry:
80  %vecext = extractelement <8 x i16> %a, i32 %index
81  ret i16 %vecext
82}
83
84define zeroext i32 @test5(<4 x i32> %a, i32 signext %index) {
85; CHECK-64-LABEL: test5:
86; CHECK-64:       # %bb.0: # %entry
87; CHECK-64-NEXT:    rlwinm 3, 3, 2, 28, 29
88; CHECK-64-NEXT:    vextuwlx 3, 3, 2
89; CHECK-64-NEXT:    blr
90;
91; CHECK-32-LABEL: test5:
92; CHECK-32:       # %bb.0: # %entry
93; CHECK-32-NEXT:    addi 4, 1, -16
94; CHECK-32-NEXT:    rlwinm 3, 3, 2, 28, 29
95; CHECK-32-NEXT:    stxv 34, -16(1)
96; CHECK-32-NEXT:    lwzx 3, 4, 3
97; CHECK-32-NEXT:    blr
98entry:
99  %vecext = extractelement <4 x i32> %a, i32 %index
100  ret i32 %vecext
101}
102
103define signext i32 @test6(<4 x i32> %a, i32 signext %index) {
104; CHECK-64-LABEL: test6:
105; CHECK-64:       # %bb.0: # %entry
106; CHECK-64-NEXT:    rlwinm 3, 3, 2, 28, 29
107; CHECK-64-NEXT:    vextuwlx 3, 3, 2
108; CHECK-64-NEXT:    extsw 3, 3
109; CHECK-64-NEXT:    blr
110;
111; CHECK-32-LABEL: test6:
112; CHECK-32:       # %bb.0: # %entry
113; CHECK-32-NEXT:    addi 4, 1, -16
114; CHECK-32-NEXT:    rlwinm 3, 3, 2, 28, 29
115; CHECK-32-NEXT:    stxv 34, -16(1)
116; CHECK-32-NEXT:    lwzx 3, 4, 3
117; CHECK-32-NEXT:    blr
118entry:
119  %vecext = extractelement <4 x i32> %a, i32 %index
120  ret i32 %vecext
121}
122
123; Test with immediate index
124define zeroext i8 @test7(<16 x i8> %a) {
125; CHECK-64-LABEL: test7:
126; CHECK-64:       # %bb.0: # %entry
127; CHECK-64-NEXT:    li 3, 1
128; CHECK-64-NEXT:    vextublx 3, 3, 2
129; CHECK-64-NEXT:    clrldi 3, 3, 56
130; CHECK-64-NEXT:    blr
131;
132; CHECK-32-LABEL: test7:
133; CHECK-32:       # %bb.0: # %entry
134; CHECK-32-NEXT:    stxv 34, -16(1)
135; CHECK-32-NEXT:    lbz 3, -15(1)
136; CHECK-32-NEXT:    blr
137entry:
138  %vecext = extractelement <16 x i8> %a, i32 1
139  ret i8 %vecext
140}
141
142define zeroext i16 @test8(<8 x i16> %a) {
143; CHECK-64-LABEL: test8:
144; CHECK-64:       # %bb.0: # %entry
145; CHECK-64-NEXT:    li 3, 2
146; CHECK-64-NEXT:    vextuhlx 3, 3, 2
147; CHECK-64-NEXT:    clrldi 3, 3, 48
148; CHECK-64-NEXT:    blr
149;
150; CHECK-32-LABEL: test8:
151; CHECK-32:       # %bb.0: # %entry
152; CHECK-32-NEXT:    stxv 34, -16(1)
153; CHECK-32-NEXT:    lhz 3, -14(1)
154; CHECK-32-NEXT:    blr
155entry:
156  %vecext = extractelement <8 x i16> %a, i32 1
157  ret i16 %vecext
158}
159
160define zeroext i32 @test9(<4 x i32> %a) {
161; CHECK-64-LABEL: test9:
162; CHECK-64:       # %bb.0:
163; CHECK-64-NEXT:    li 3, 12
164; CHECK-64-NEXT:    vextuwlx 3, 3, 2
165; CHECK-64-NEXT:    blr
166;
167; CHECK-32-LABEL: test9:
168; CHECK-32:       # %bb.0:
169; CHECK-32-NEXT:    stxv 34, -16(1)
170; CHECK-32-NEXT:    lwz 3, -4(1)
171; CHECK-32-NEXT:    blr
172  %vecext = extractelement <4 x i32> %a, i32 3
173  ret i32 %vecext
174}
175