1; RUN: llc -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp -mcpu=pwr4 \ 2; RUN: -mattr=-altivec -verify-machineinstrs < %s | \ 3; RUN: FileCheck --check-prefixes=CHECK,32BIT %s 4 5; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \ 6; RUN: -mtriple powerpc-ibm-aix-xcoff < %s | \ 7; RUN: FileCheck --check-prefixes=CHECKASM,ASM32 %s 8 9; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp -mcpu=pwr4 \ 10; RUN: -mattr=-altivec -verify-machineinstrs < %s | \ 11; RUN: FileCheck --check-prefixes=CHECK,64BIT %s 12 13; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \ 14; RUN: -mtriple powerpc64-ibm-aix-xcoff < %s | \ 15; RUN: FileCheck --check-prefixes=CHECKASM,ASM64 %s 16 17%struct.S0 = type {} 18 19%struct.S1 = type { [1 x i8] } 20@gS1 = external global %struct.S1, align 1 21 22define void @call_test_byval_1Byte() { 23entry: 24 %s0 = alloca %struct.S0, align 8 25 %call = call zeroext i8 @test_byval_1Byte(%struct.S0* byval(%struct.S0) align 1 %s0, %struct.S1* byval(%struct.S1) align 1 @gS1) 26 ret void 27} 28 29 30; CHECK-LABEL: name: call_test_byval_1Byte{{.*}} 31 32; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 33; 32BIT-NEXT: renamable $r[[REG:[0-9]+]] = LWZtoc @gS1, $r2 :: (load 4 from got) 34; 32BIT-NEXT: renamable $r3 = LBZ 0, killed renamable $r[[REG]] :: (load 1) 35; 32BIT-NEXT: renamable $r3 = RLWINM killed renamable $r3, 24, 0, 7 36; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_1Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1 37; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 38 39; CHECKASM-LABEL: .call_test_byval_1Byte: 40 41; ASM32: stwu 1, -64(1) 42; ASM32-NEXT: lwz [[REG:[0-9]+]], LC{{[0-9]+}}(2) 43; ASM32-NEXT: lbz 3, 0([[REG]]) 44; ASM32-NEXT: slwi 3, 3, 24 45; ASM32-NEXT: bl .test_byval_1Byte 46; ASM32-NEXT: nop 47; ASM32-NEXT: addi 1, 1, 64 48 49; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 50; 64BIT-NEXT: renamable $x[[REG:[0-9]+]] = LDtoc @gS1, $x2 :: (load 8 from got) 51; 64BIT-NEXT: renamable $x3 = LBZ8 0, killed renamable $x[[REG]] :: (load 1) 52; 64BIT-NEXT: renamable $x3 = RLDICR killed renamable $x3, 56, 7 53; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_1Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 54; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 55 56; ASM64: std 0, 16(1) 57; ASM64-NEXT: stdu 1, -128(1) 58; ASM64-NEXT: ld [[REG:[0-9]+]], LC{{[0-9]+}}(2) 59; ASM64-NEXT: lbz 3, 0([[REG]]) 60; ASM64-NEXT: sldi 3, 3, 56 61; ASM64-NEXT: bl .test_byval_1Byte 62; ASM64-NEXT: nop 63; ASM64-NEXT: addi 1, 1, 128 64 65 66define zeroext i8 @test_byval_1Byte(%struct.S0* byval(%struct.S0) align 1 %s0, %struct.S1* byval(%struct.S1) align 1 %s) { 67entry: 68 %arrayidx = getelementptr inbounds %struct.S1, %struct.S1* %s, i32 0, i32 0, i32 0 69 %0 = load i8, i8* %arrayidx, align 1 70 ret i8 %0 71} 72 73; CHECK-LABEL: name: test_byval_1Byte 74 75; 32BIT: fixedStack: 76; 32BIT-NEXT: - { id: 0, type: default, offset: 24, size: 4, alignment: 8, stack-id: default, 77; 32BIT-NEXT: isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true, 78; 32BIT: - { id: 1, type: default, offset: 24, size: 4, alignment: 8, stack-id: default, 79; 32BIT-NEXT: isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true, 80 81; 32BIT: bb.0.entry: 82; 32BIT-NEXT: liveins: $r3 83; 32BIT: STW killed renamable $r3, 0, %fixed-stack.0 :: (store 4 into %fixed-stack.0, align 8) 84; 32BIT-NEXT: renamable $r3 = LBZ 0, %fixed-stack.0 :: (dereferenceable load 1 85; 32BIT-NEXT: BLR 86 87; 64BIT: fixedStack: 88; 64BIT-NEXT: - { id: 0, type: default, offset: 48, size: 8, alignment: 16, stack-id: default, 89; 64BIT-NEXT: isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true, 90; 64BIT: - { id: 1, type: default, offset: 48, size: 8, alignment: 16, stack-id: default, 91; 64BIT-NEXT: isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true, 92 93; 64BIT: bb.0.entry: 94; 64BIT-NEXT: liveins: $x3 95; 64BIT: STD killed renamable $x3, 0, %fixed-stack.0 :: (store 8 into %fixed-stack.0, align 16) 96; 64BIT-NEXT: renamable $x3 = LBZ8 0, %fixed-stack.0 :: (dereferenceable load 1 97 98; CHECKASM-LABEL: .test_byval_1Byte: 99 100; ASM32: stw 3, 24(1) 101; ASM32-NEXT: lbz 3, 24(1) 102; ASM32-NEXT: blr 103 104; ASM64: std 3, 48(1) 105; ASM64-NEXT: lbz 3, 48(1) 106; ASM64-NEXT: blr 107 108 109@f = common global float 0.000000e+00, align 4 110 111%struct.S2 = type { [2 x i8] } 112 113@gS2 = external global %struct.S2, align 1 114 115define void @call_test_byval_2Byte() { 116entry: 117 %0 = load float, float* @f, align 4 118 %call = call zeroext i8 @test_byval_2Byte(i32 signext 42, float %0, %struct.S2* byval(%struct.S2) align 1 @gS2, float %0, i32 signext 43) 119 ret void 120} 121 122; CHECK-LABEL: name: call_test_byval_2Byte{{.*}} 123 124; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 125; 32BIT: renamable $r[[REG1:[0-9]+]] = LWZtoc @f, $r2 :: (load 4 from got) 126; 32BIT-NEXT: renamable $f1 = LFS 0, killed renamable $r[[REG1]] :: (dereferenceable load 4 from @f) 127; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 128; 32BIT-DAG: $r3 = LI 42 129; 32BIT-DAG: renamable $r[[REG2:[0-9]+]] = LWZtoc @gS2, $r2 :: (load 4 from got) 130; 32BIT-DAG: renamable $r[[REG3:[0-9]+]] = LHZ 0, killed renamable $r[[REG2]] :: (load 2) 131; 32BIT-DAG: renamable $r5 = RLWINM killed renamable $r[[REG3]], 16, 0, 15 132; 32BIT-DAG: $f2 = COPY renamable $f1 133; 32BIT-DAG: $r7 = LI 43 134; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_2Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r5, implicit killed $f2, implicit killed $r7, implicit $r2, implicit-def $r1 135; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 136 137; CHECKASM-LABEL: .call_test_byval_2Byte: 138 139; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 140; ASM32: stwu 1, -64(1) 141; ASM32-DAG: li 3, 42 142; ASM32-DAG: lwz [[REG1:[0-9]+]], LC{{[0-9]+}}(2) 143; ASM32-DAG: lfs 1, 0([[REG1]]) 144; ASM32-DAG: lwz [[REG2:[0-9]+]], LC{{[0-9]+}}(2) 145; ASM32-DAG: lhz [[REG3:[0-9]+]], 0([[REG2]]) 146; ASM32-DAG: slwi 5, [[REG3]], 16 147; ASM32-DAG: fmr 2, 1 148; ASM32-DAG: li 7, 43 149; ASM32-NEXT: bl .test_byval_2Byte 150; ASM32-NEXT: nop 151; ASM32-NEXT: addi 1, 1, 64 152 153; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 154; 64BIT: renamable $x[[REG1:[0-9]+]] = LDtoc @f, $x2 :: (load 8 from got) 155; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x[[REG1]] :: (dereferenceable load 4 from @f) 156; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 157; 64BIT-DAG: $x3 = LI8 42 158; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LDtoc @gS2, $x2 :: (load 8 from got) 159; 64BIT-DAG: renamable $x[[REG3:[0-9]+]] = LHZ8 0, killed renamable $x[[REG2]] :: (load 2) 160; 64BIT-DAG: renamable $x5 = RLDICR killed renamable $x[[REG3]], 48, 15 161; 64BIT-DAG: $f2 = COPY renamable $f1 162; 64BIT-DAG: $x7 = LI8 43 163; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_2Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x5, implicit killed $f2, implicit killed $x7, implicit $x2, implicit-def $r1 164; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 165 166; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 167; ASM64: std 0, 16(1) 168; ASM64-NEXT: stdu 1, -112(1) 169; ASM64-DAG: li 3, 42 170; ASM64-DAG: ld [[REG1:[0-9]+]], LC{{[0-9]+}}(2) 171; ASM64-DAG: lfs 1, 0([[REG1]]) 172; ASM64-DAG: ld [[REG2:[0-9]+]], LC{{[0-9]+}}(2) 173; ASM64-DAG: lhz [[REG3:[0-9]+]], 0([[REG2]]) 174; ASM64-DAG: sldi 5, [[REG3]], 48 175; ASM64-DAG: fmr 2, 1 176; ASM64-DAG: li 7, 43 177; ASM64-NEXT: bl .test_byval_2Byte 178; ASM64-NEXT: nop 179; ASM64-NEXT: addi 1, 1, 112 180 181define zeroext i8 @test_byval_2Byte(i32, float, %struct.S2* byval(%struct.S2) align 1 %s, float, i32) { 182entry: 183 %arrayidx = getelementptr inbounds %struct.S2, %struct.S2* %s, i32 0, i32 0, i32 1 184 %4 = load i8, i8* %arrayidx, align 1 185 ret i8 %4 186} 187 188; CHECK-LABEL: name: test_byval_2Byte 189; 32BIT: fixedStack: 190; 32BIT-NEXT: - { id: 0, type: default, offset: 32, size: 4, alignment: 16, stack-id: default, 191 192; 32BIT: bb.0.entry: 193; 32BIT-NEXT: liveins: $r5 194; 32BIT: STW killed renamable $r5, 0, %fixed-stack.0 :: (store 4 into %fixed-stack.0, align 16) 195; 32BIT-NEXT: renamable $r3 = LBZ 1, %fixed-stack.0 :: (dereferenceable load 1 196 197; 64BIT: fixedStack: 198; 64BIT-NEXT: - { id: 0, type: default, offset: 64, size: 8, alignment: 16, stack-id: default, 199 200; 64BIT: bb.0.entry: 201; 64BIT-NEXT: liveins: $x5 202; 64BIT: STD killed renamable $x5, 0, %fixed-stack.0 :: (store 8 into %fixed-stack.0, align 16) 203; 64BIT-NEXT: renamable $x3 = LBZ8 1, %fixed-stack.0 :: (dereferenceable load 1 204 205; CHECKASM-LABEL: .test_byval_2Byte: 206 207; ASM32: stw 5, 32(1) 208; ASM32-NEXT: lbz 3, 33(1) 209; ASM32-NEXT: blr 210 211; ASM64: std 5, 64(1) 212; ASM64-NEXT: lbz 3, 65(1) 213; ASM64-NEXT: blr 214 215 216%struct.S3 = type <{ i8, i16 }> 217@gS3 = external global %struct.S3, align 1 218 219define void @call_test_byval_3Byte() { 220entry: 221 %call = call zeroext i16 @test_byval_3Byte(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, %struct.S3* byval(%struct.S3) align 1 @gS3, i32 42) 222 ret void 223} 224 225; CHECK-LABEL: name: call_test_byval_3Byte{{.*}} 226 227; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 228; 32BIT: ADJCALLSTACKDOWN 60, 0, implicit-def dead $r1, implicit $r1 229; 32BIT-DAG: $r3 = LI 1 230; 32BIT-DAG: $r4 = LI 2 231; 32BIT-DAG: $r5 = LI 3 232; 32BIT-DAG: $r6 = LI 4 233; 32BIT-DAG: $r7 = LI 5 234; 32BIT-DAG: $r8 = LI 6 235; 32BIT-DAG: $r9 = LI 7 236; 32BIT-DAG: renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS3, $r2 :: (load 4 from got) 237; 32BIT-DAG: renamable $r[[REG1:[0-9]+]] = LHZ 0, killed renamable $r[[REGADDR]] :: (load 2) 238; 32BIT-DAG: renamable $r[[REG2:[0-9]+]] = LBZ 2, renamable $r[[REGADDR]] :: (load 1) 239; 32BIT-DAG: renamable $r10 = RLWINM killed renamable $r[[REG2]], 8, 16, 23 240; 32BIT-DAG: renamable $r10 = RLWIMI killed renamable $r10, killed renamable $r[[REG1]], 16, 0, 15 241; 32BIT-DAG: renamable $r[[REG3:[0-9]+]] = LI 42 242; 32BIT-DAG: STW killed renamable $r[[REG3]], 56, $r1 :: (store 4) 243; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_3Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit $r10, implicit $r2, implicit-def $r1 244; 32BIT-NEXT: ADJCALLSTACKUP 60, 0, implicit-def dead $r1, implicit $r1 245 246; CHECKASM-LABEL: .call_test_byval_3Byte: 247 248; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 249; ASM32: stwu 1, -64(1) 250; ASM32-DAG: li 3, 1 251; ASM32-DAG: li 4, 2 252; ASM32-DAG: li 5, 3 253; ASM32-DAG: li 6, 4 254; ASM32-DAG: li 7, 5 255; ASM32-DAG: li 8, 6 256; ASM32-DAG: li 9, 7 257; ASM32-DAG: lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2) 258; ASM32-DAG: lhz [[REG1:[0-9]+]], 0([[REGADDR]]) 259; ASM32-DAG: lbz [[REG2:[0-9]+]], 2([[REGADDR]]) 260; ASM32-DAG: rlwinm 10, [[REG2]], 8, 16, 23 261; ASM32-DAG: rlwimi 10, [[REG1]], 16, 0, 15 262; ASM32-DAG: li [[REG3:[0-9]+]], 42 263; ASM32-DAG: stw [[REG3]], 56(1) 264; ASM32-NEXT: bl .test_byval_3Byte 265; ASM32-NEXT: nop 266 267; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 268; 64BIT: ADJCALLSTACKDOWN 120, 0, implicit-def dead $r1, implicit $r1 269; 64BIT-DAG: $x3 = LI8 1 270; 64BIT-DAG: $x4 = LI8 2 271; 64BIT-DAG: $x5 = LI8 3 272; 64BIT-DAG: $x6 = LI8 4 273; 64BIT-DAG: $x7 = LI8 5 274; 64BIT-DAG: $x8 = LI8 6 275; 64BIT-DAG: $x9 = LI8 7 276; 64BIT-DAG: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS3, $x2 :: (load 8 from got) 277; 64BIT-DAG: renamable $x[[REG1:[0-9]+]] = LHZ8 0, killed renamable $x[[REGADDR]] :: (load 2) 278; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LBZ8 2, renamable $x[[REGADDR]] :: (load 1) 279; 64BIT-DAG: renamable $x10 = RLDIC killed renamable $x[[REG2]], 40, 16 280; 64BIT-DAG: renamable $x10 = RLDIMI killed renamable $x10, killed renamable $x[[REG1]], 48, 0 281; 64BIT-DAG: $x[[REG3:[0-9]+]] = LI8 42 282; 64BIT-DAG: STD killed renamable $x[[REG3]], 112, $x1 :: (store 8) 283; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_3Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit $x10, implicit $x2, implicit-def $r1 284; 64BIT-NEXT: ADJCALLSTACKUP 120, 0, implicit-def dead $r1, implicit $r1 285 286; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 287; ASM64: stdu 1, -128(1) 288; ASM64-DAG: li 3, 1 289; ASM64-DAG: li 4, 2 290; ASM64-DAG: li 5, 3 291; ASM64-DAG: li 6, 4 292; ASM64-DAG: li 7, 5 293; ASM64-DAG: li 8, 6 294; ASM64-DAG: li 9, 7 295; ASM64-DAG: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2) 296; ASM64-DAG: lhz [[REG1:[0-9]+]], 0([[REGADDR]]) 297; ASM64-DAG: lbz [[REG2:[0-9]+]], 2([[REGADDR]]) 298; ASM64-DAG: rldic 10, [[REG2]], 40, 16 299; ASM64-DAG: rldimi 10, [[REG1]], 48, 0 300; ASM64-DAG: li [[REG3:[0-9]+]], 42 301; ASM64-DAG: std [[REG3]], 112(1) 302; ASM64-NEXT: bl .test_byval_3Byte 303; ASM64-NEXT: nop 304 305 306define zeroext i16 @test_byval_3Byte(i32, i32, i32, i32, i32, i32, i32, %struct.S3* byval(%struct.S3) align 1 %s, i32) { 307entry: 308 %gep = getelementptr inbounds %struct.S3, %struct.S3* %s, i32 0, i32 1 309 %8 = load i16, i16* %gep, align 1 310 ret i16 %8 311} 312 313; CHECK-LABEL: name: test_byval_3Byte 314 315; 32BIT: fixedStack: 316; 32BIT-NEXT: - { id: 0, type: default, offset: 56, size: 4, alignment: 8, stack-id: default, 317; 32BIT: - { id: 1, type: default, offset: 52, size: 4, alignment: 4, stack-id: default, 318 319; 32BIT-LABEL: bb.0.entry: 320; 32BIT-NEXT: liveins: $r10 321; 32BIT: STW killed renamable $r10, 0, %fixed-stack.1 :: (store 4 into %fixed-stack.1) 322; 32BIT-NEXT: renamable $r3 = LHZ 1, %fixed-stack.1 :: (dereferenceable load 2 323 324; 64BIT: fixedStack: 325; 64BIT-NEXT: - { id: 0, type: default, offset: 116, size: 4, alignment: 4, stack-id: default, 326; 64BIT: - { id: 1, type: default, offset: 104, size: 8, alignment: 8, stack-id: default, 327 328; 64BIT-LABEL: bb.0.entry: 329; 64BIT-NEXT: liveins: $x10 330; 64BIT: STD killed renamable $x10, 0, %fixed-stack.1 :: (store 8 into %fixed-stack.1) 331; 64BIT-NEXT: renamable $x3 = LHZ8 1, %fixed-stack.1 :: (dereferenceable load 2 332 333; CHECKASM-LABEL: .test_byval_3Byte: 334 335; ASM32: stw 10, 52(1) 336; ASM32-NEXT: lhz 3, 53(1) 337; ASM32-NEXT: blr 338 339; ASM64: std 10, 104(1) 340; ASM64-NEXT: lhz 3, 105(1) 341; ASM64-NEXT: blr 342 343 344%struct.S4 = type { [4 x i8] } 345%struct.S4A = type { i32 } 346 347@gS4 = external global %struct.S4, align 1 348 349define void @call_test_byval_4Byte() { 350entry: 351 %s0 = alloca %struct.S0, align 8 352 %s4a = alloca %struct.S4A, align 4 353 %call = call signext i32 @test_byval_4Byte(%struct.S4* byval(%struct.S4) align 1 @gS4, %struct.S0* byval(%struct.S0) align 1 %s0, %struct.S4A* byval(%struct.S4A) align 4 %s4a) 354 ret void 355} 356 357; CHECK-LABEL: name: call_test_byval_4Byte{{.*}} 358 359; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 360; 32BIT-NEXT: renamable $r[[REG:[0-9]+]] = LWZtoc @gS4, $r2 :: (load 4 from got) 361; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REG]] :: (load 4) 362; 32BIT-DAG: renamable $r4 = LWZ 0, %stack.1.s4a :: (load 4 from %stack.1.s4a, align 8) 363; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_4Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1 364; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 365 366; CHECKASM-LABEL: .call_test_byval_4Byte: 367 368; ASM32: stwu 1, -80(1) 369; ASM32-NEXT: lwz [[REG:[0-9]+]], LC{{[0-9]+}}(2) 370; ASM32-DAG: lwz 3, 0([[REG]]) 371; ASM32-DAG: lwz 4, 64(1) 372; ASM32-NEXT: bl .test_byval_4Byte 373; ASM32-NEXT: nop 374; ASM32-NEXT: addi 1, 1, 80 375 376; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 377; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS4, $x2 :: (load 8 from got) 378; 64BIT-DAG: renamable $x[[LD1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4) 379; 64BIT-DAG: renamable $x[[LD2:[0-9]+]] = LWZ8 0, %stack.1.s4a :: (load 4 from %stack.1.s4a, align 8) 380; 64BIT-DAG: renamable $x3 = RLDICR killed renamable $x[[LD1]], 32, 31 381; 64BIT-DAG: renamable $x4 = RLDICR killed renamable $x[[LD2]], 32, 31 382; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_4Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x2, implicit-def $r1 383; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 384 385; ASM64: stdu 1, -128(1) 386; ASM64-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2) 387; ASM64-DAG: lwz [[LD1:[0-9]+]], 0([[REGADDR]]) 388; ASM64-DAG: lwz [[LD2:[0-9]+]], 112(1) 389; ASM64-DAG: sldi 3, [[LD1]], 32 390; ASM64-DAG: sldi 4, [[LD2]], 32 391; ASM64-NEXT: bl .test_byval_4Byte 392; ASM64-NEXT: nop 393; ASM64-NEXT: addi 1, 1, 128 394 395 396define signext i32 @test_byval_4Byte(%struct.S4* byval(%struct.S4) align 1 %s, %struct.S0* byval(%struct.S0) align 1, %struct.S4A* byval(%struct.S4A) align 4 %s4a) { 397entry: 398 %arrayidx = getelementptr inbounds %struct.S4, %struct.S4* %s, i32 0, i32 0, i32 3 399 %gep = getelementptr inbounds %struct.S4A, %struct.S4A* %s4a, i32 0, i32 0 400 %1 = load i8, i8* %arrayidx, align 1 401 %2 = load i32, i32* %gep, align 4 402 %conv = zext i8 %1 to i32 403 %add = add nsw i32 %2, %conv 404 ret i32 %add 405} 406 407; CHECK-LABEL: name: test_byval_4Byte 408 409; 32BIT: fixedStack: 410; 32BIT-NEXT: - { id: 0, type: default, offset: 28, size: 4, alignment: 4, stack-id: default, 411; 32BIT-NEXT: isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true, 412; 32BIT: - { id: 1, type: default, offset: 28, size: 4, alignment: 4, stack-id: default, 413; 32BIT-NEXT: isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true, 414; 32BIT: - { id: 2, type: default, offset: 24, size: 4, alignment: 8, stack-id: default, 415; 32BIT-NEXT: isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true, 416 417; 32BIT: bb.0.entry: 418; 32BIT-NEXT: liveins: $r3 419; 32BIT: STW renamable $r3, 0, %fixed-stack.2 :: (store 4 into %fixed-stack.2, align 8) 420; 32BIT-DAG: STW killed renamable $r4, 0, %fixed-stack.0 :: (store 4 into %fixed-stack.0) 421; 32BIT-DAG: renamable $r[[SCRATCH:[0-9]+]] = RLWINM killed renamable $r3, 0, 24, 31 422; 32BIT-DAG: renamable $r3 = nsw ADD4 renamable $r4, killed renamable $r[[SCRATCH]] 423; 32BIT: BLR 424 425; 64BIT: fixedStack: 426; 64BIT-NEXT: - { id: 0, type: default, offset: 56, size: 8, alignment: 8, stack-id: default, 427; 64BIT-NEXT: isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true, 428; 64BIT: - { id: 1, type: default, offset: 56, size: 8, alignment: 8, stack-id: default, 429; 64BIT-NEXT: isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true, 430; 64BIT: - { id: 2, type: default, offset: 48, size: 8, alignment: 16, stack-id: default, 431; 64BIT-NEXT: isImmutable: false, isAliased: true, callee-saved-register: '', callee-saved-restored: true, 432 433; 64BIT: bb.0.entry: 434; 64BIT-NEXT: liveins: $x3 435; 64BIT: STD killed renamable $x3, 0, %fixed-stack.2 :: (store 8 into %fixed-stack.2, align 16) 436; 64BIT-NEXT: STD killed renamable $x4, 0, %fixed-stack.0 :: (store 8 into %fixed-stack.0) 437; 64BIT-DAG: renamable $r[[SCRATCH1:[0-9]+]] = LBZ 3, %fixed-stack.2 :: (dereferenceable load 1 438; 64BIT-DAG: renamable $r[[SCRATCH2:[0-9]+]] = LWZ 0, %fixed-stack.0 :: (dereferenceable load 4 439; 64BIT-NEXT: renamable $r[[SCRATCH3:[0-9]+]] = nsw ADD4 killed renamable $r[[SCRATCH2]], killed renamable $r[[SCRATCH1]] 440; 64BIT-NEXT: renamable $x3 = EXTSW_32_64 killed renamable $r[[SCRATCH3]] 441; 64BIT-NEXT: BLR8 442 443; CHECKASM-LABEL: .test_byval_4Byte: 444 445; ASM32: stw 3, 24(1) 446; ASM32-DAG: stw 4, 28(1) 447; ASM32-DAG: clrlwi [[SCRATCH:[0-9]+]], 3, 24 448; ASM32-DAG: add 3, 4, [[SCRATCH]] 449; ASM32-NEXT: blr 450 451; ASM64: std 3, 48(1) 452; ASM64-NEXT: std 4, 56(1) 453; ASM64-DAG: lbz [[SCRATCH1:[0-9]+]], 51(1) 454; ASM64-DAG: lwz [[SCRATCH2:[0-9]+]], 56(1) 455; ASM64-NEXT: add [[SCRATCH3:[0-9]+]], [[SCRATCH2]], [[SCRATCH1]] 456; ASM64-NEXT: extsw 3, [[SCRATCH3]] 457; ASM64-NEXT: blr 458 459 460%struct.S5 = type { [5 x i8] } 461 462@gS5 = external global %struct.S5, align 1 463 464define void @call_test_byval_5Byte() { 465entry: 466 %call = call zeroext i8 @test_byval_5Byte(%struct.S5* byval(%struct.S5) align 1 @gS5) 467 ret void 468} 469 470declare zeroext i8 @test_byval_5Byte(%struct.S5* byval(%struct.S5) align 1) 471 472; CHECK-LABEL: name: call_test_byval_5Byte{{.*}} 473 474; ASM-LABEL: .call_test_byval_5Byte: 475 476; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 477; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 478; 32BIT-NEXT: renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS5, $r2 :: (load 4 from got) 479; 32BIT-DAG: renamable $r[[REG1:[0-9]+]] = LBZ 4, renamable $r[[REGADDR]] :: (load 1) 480; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load 4) 481; 32BIT-DAG: renamable $r4 = RLWINM killed renamable $r[[REG1]], 24, 0, 7 482; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_5Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1 483; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 484 485; CHECKASM-LABEL: .call_test_byval_5Byte: 486 487; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 488; ASM32: stwu 1, -64(1) 489; ASM32-NEXT: lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2) 490; ASM32-DAG: lbz [[REG1:[0-9]+]], 4([[REGADDR]]) 491; ASM32-DAG: lwz 3, 0([[REGADDR]]) 492; ASM32-DAG: slwi 4, [[REG1]], 24 493; ASM32-NEXT: bl .test_byval_5Byte 494; ASM32-NEXT: nop 495 496; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 497; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 498; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS5, $x2 :: (load 8 from got) 499; 64BIT-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4) 500; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LBZ8 4, renamable $x[[REGADDR]] :: (load 1) 501; 64BIT-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 24, 0, 7 502; 64BIT-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0 503; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_5Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 504; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 505 506; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 507; ASM64: stdu 1, -112(1) 508; ASM64-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2) 509; ASM64-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]]) 510; ASM64-DAG: lbz [[REG2:[0-9]+]], 4([[REGADDR]]) 511; ASM64-DAG: rlwinm 3, [[REG2]], 24, 0, 7 512; ASM64-DAG: rldimi 3, [[REG1]], 32, 0 513; ASM64-NEXT: bl .test_byval_5Byte 514; ASM64-NEXT: nop 515 516 517%struct.S6 = type { [6 x i8] } 518 519@gS6 = external global %struct.S6, align 1 520 521define void @call_test_byval_6Byte() { 522entry: 523 %call = call zeroext i8 @test_byval_6Byte(%struct.S6* byval(%struct.S6) align 1 @gS6) 524 ret void 525} 526 527declare zeroext i8 @test_byval_6Byte(%struct.S6* byval(%struct.S6) align 1) 528 529; CHECK-LABEL: name: call_test_byval_6Byte{{.*}} 530 531; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 532; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 533; 32BIT-NEXT: renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS6, $r2 :: (load 4 from got) 534; 32BIT-DAG: renamable $r[[REG1:[0-9]+]] = LHZ 4, renamable $r[[REGADDR]] :: (load 2) 535; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load 4) 536; 32BIT-DAG: renamable $r4 = RLWINM killed renamable $r[[REG1]], 16, 0, 15 537; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_6Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1 538; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 539 540; CHECKASM-LABEL: .call_test_byval_6Byte: 541 542; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 543; ASM32: stwu 1, -64(1) 544; ASM32-NEXT: lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2) 545; ASM32-DAG: lhz [[REG1:[0-9]+]], 4([[REGADDR]]) 546; ASM32-DAG: lwz 3, 0([[REGADDR]]) 547; ASM32-DAG: slwi 4, [[REG1]], 16 548; ASM32-NEXT: bl .test_byval_6Byte 549; ASM32-NEXT: nop 550 551; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 552; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 553; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS6, $x2 :: (load 8 from got) 554; 64BIT-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4) 555; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2) 556; 64BIT-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 16, 0, 15 557; 64BIT-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0 558; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_6Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 559; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 560 561; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 562; ASM64: stdu 1, -112(1) 563; ASM64-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2) 564; ASM64-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]]) 565; ASM64-DAG: lhz [[REG2:[0-9]+]], 4([[REGADDR]]) 566; ASM64-DAG: rlwinm 3, [[REG2]], 16, 0, 15 567; ASM64-DAG: rldimi 3, [[REG1]], 32, 0 568; ASM64-NEXT: bl .test_byval_6Byte 569; ASM64-NEXT: nop 570 571 572%struct.S7 = type { [7 x i8] } 573 574@gS7 = external global %struct.S7, align 1 575 576define void @call_test_byval_7Byte() { 577entry: 578 %call = call zeroext i8 @test_byval_7Byte(%struct.S7* byval(%struct.S7) align 1 @gS7) 579 ret void 580} 581 582declare zeroext i8 @test_byval_7Byte(%struct.S7* byval(%struct.S7) align 1) 583 584; CHECK-LABEL: name: call_test_byval_7Byte{{.*}} 585 586; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 587; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 588; 32BIT-NEXT: renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS7, $r2 :: (load 4 from got) 589; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load 4) 590; 32BIT-DAG: renamable $r[[REG1:[0-9]+]] = LHZ 4, renamable $r[[REGADDR]] :: (load 2) 591; 32BIT-DAG: renamable $r[[REG2:[0-9]+]] = LBZ 6, renamable $r[[REGADDR]] :: (load 1) 592; 32BIT-DAG: renamable $r4 = RLWINM killed renamable $r[[REG2]], 8, 16, 23 593; 32BIT-DAG: renamable $r4 = RLWIMI killed renamable $r4, killed renamable $r[[REG1]], 16, 0, 15 594; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_7Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1 595; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 596 597; CHECKASM-LABEL: .call_test_byval_7Byte: 598 599; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 600; ASM32: stwu 1, -64(1) 601; ASM32-NEXT: lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2) 602; ASM32-DAG: lwz 3, 0([[REGADDR]]) 603; ASM32-DAG: lhz [[REG1:[0-9]+]], 4([[REGADDR]]) 604; ASM32-DAG: lbz [[REG2:[0-9]+]], 6([[REGADDR]]) 605; ASM32-DAG: rlwinm 4, [[REG2]], 8, 16, 23 606; ASM32-DAG: rlwimi 4, [[REG1]], 16, 0, 15 607; ASM32-NEXT: bl .test_byval_7Byte 608; ASM32-NEXT: nop 609 610; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 611; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 612; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS7, $x2 :: (load 8 from got) 613; 64BIT-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4) 614; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2) 615; 64BIT-DAG: renamable $x[[REG3:[0-9]+]] = LBZ8 6, renamable $x[[REGADDR]] :: (load 1) 616; 64BIT-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG3]], 8, 16, 23 617; 64BIT-DAG: renamable $x3 = RLWIMI8 killed renamable $x3, killed renamable $x[[REG2]], 16, 0, 15 618; 64BIT-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0 619; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_7Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 620; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 621 622; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 623; ASM64: stdu 1, -112(1) 624; ASM64-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2) 625; ASM64-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]]) 626; ASM64-DAG: lhz [[REG2:[0-9]+]], 4([[REGADDR]]) 627; ASM64-DAG: lbz [[REG3:[0-9]+]], 6([[REGADDR]]) 628; ASM64-DAG: rlwinm 3, [[REG3]], 8, 16, 23 629; ASM64-DAG: rlwimi 3, [[REG2]], 16, 0, 15 630; ASM64-DAG: rldimi 3, [[REG1]], 32, 0 631; ASM64-NEXT: bl .test_byval_7Byte 632; ASM64-NEXT: nop 633 634 635%struct.S8 = type { [8 x i8] } 636 637@gS8 = external global %struct.S8, align 1 638 639define void @call_test_byval_8Byte() { 640entry: 641 %call = call zeroext i8 @test_byval_8Byte(%struct.S8* byval(%struct.S8) align 1 @gS8) 642 ret void 643} 644 645declare zeroext i8 @test_byval_8Byte(%struct.S8* byval(%struct.S8) align 1) 646 647; CHECK-LABEL: name: call_test_byval_8Byte{{.*}} 648 649; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 650; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 651; 32BIT-NEXT: renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS8, $r2 :: (load 4 from got) 652; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load 4) 653; 32BIT-DAG: renamable $r4 = LWZ 4, renamable $r[[REGADDR]] :: (load 4) 654; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_8Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1 655; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 656 657; CHECKASM-LABEL: .call_test_byval_8Byte: 658 659; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 660; ASM32: stwu 1, -64(1) 661; ASM32-NEXT: lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2) 662; ASM32-DAG: lwz 3, 0([[REGADDR]]) 663; ASM32-DAG: lwz 4, 4([[REGADDR]]) 664; ASM32-NEXT: bl .test_byval_8Byte 665; ASM32-NEXT: nop 666 667; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 668; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS8, $x2 :: (load 8 from got) 669; 64BIT-NEXT: renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load 8) 670; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_8Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 671; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 672 673; ASM64: stdu 1, -112(1) 674; ASM64-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2) 675; ASM64-NEXT: ld 3, 0([[REGADDR]]) 676; ASM64-NEXT: bl .test_byval_8Byte 677; ASM64-NEXT: nop 678 679 680%struct.S32 = type { [32 x i8] } 681 682@gS32 = external global %struct.S32, align 1 683 684define void @call_test_byval_32Byte() { 685entry: 686 %call = call zeroext i8 @test_byval_32Byte(%struct.S32* byval(%struct.S32) align 1 @gS32) 687 ret void 688} 689 690declare zeroext i8 @test_byval_32Byte(%struct.S32* byval(%struct.S32) align 1 %s) 691 692; CHECK-LABEL: name: call_test_byval_32Byte{{.*}} 693 694; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 695; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 696; 32BIT-NEXT: renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS32, $r2 :: (load 4 from got) 697; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load 4) 698; 32BIT-DAG: renamable $r4 = LWZ 4, renamable $r[[REGADDR]] :: (load 4) 699; 32BIT-DAG: renamable $r5 = LWZ 8, renamable $r[[REGADDR]] :: (load 4) 700; 32BIT-DAG: renamable $r6 = LWZ 12, renamable $r[[REGADDR]] :: (load 4) 701; 32BIT-DAG: renamable $r7 = LWZ 16, renamable $r[[REGADDR]] :: (load 4) 702; 32BIT-DAG: renamable $r8 = LWZ 20, renamable $r[[REGADDR]] :: (load 4) 703; 32BIT-DAG: renamable $r9 = LWZ 24, renamable $r[[REGADDR]] :: (load 4) 704; 32BIT-DAG: renamable $r10 = LWZ 28, renamable $r[[REGADDR]] :: (load 4) 705; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_32Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1 706; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 707 708; CHECKASM-LABEL: .call_test_byval_32Byte: 709 710; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 711; ASM32: stwu 1, -64(1) 712; ASM32-NEXT: lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2) 713; ASM32-DAG: lwz 3, 0([[REGADDR]]) 714; ASM32-DAG: lwz 4, 4([[REGADDR]]) 715; ASM32-DAG: lwz 5, 8([[REGADDR]]) 716; ASM32-DAG: lwz 6, 12([[REGADDR]]) 717; ASM32-DAG: lwz 7, 16([[REGADDR]]) 718; ASM32-DAG: lwz 8, 20([[REGADDR]]) 719; ASM32-DAG: lwz 9, 24([[REGADDR]]) 720; ASM32-DAG: lwz 10, 28([[REGADDR]]) 721; ASM32-NEXT: bl .test_byval_32Byte 722; ASM32-NEXT: nop 723 724; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 725; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 726; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS32, $x2 :: (load 8 from got) 727; 64BIT-DAG: renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load 8) 728; 64BIT-DAG: renamable $x4 = LD 8, renamable $x[[REGADDR]] :: (load 8) 729; 64BIT-DAG: renamable $x5 = LD 16, renamable $x[[REGADDR]] :: (load 8) 730; 64BIT-DAG: renamable $x6 = LD 24, renamable $x[[REGADDR]] :: (load 8) 731; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_32Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x2, implicit-def $r1 732; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 733 734; ASM64: stdu 1, -112(1) 735; ASM64-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2) 736; ASM64-DAG: ld 3, 0([[REGADDR]]) 737; ASM64-DAG: ld 4, 8([[REGADDR]]) 738; ASM64-DAG: ld 5, 16([[REGADDR]]) 739; ASM64-DAG: ld 6, 24([[REGADDR]]) 740; ASM64-NEXT: bl .test_byval_32Byte 741; ASM64-NEXT: nop 742 743 744%struct.S31 = type { [31 x i8] } 745 746@gS31 = external global %struct.S31, align 1 747 748define void @call_test_byval_31Byte() { 749entry: 750 %call = call zeroext i8 @test_byval_31Byte(%struct.S31* byval(%struct.S31) align 1 @gS31) 751 ret void 752} 753 754declare zeroext i8 @test_byval_31Byte(%struct.S31* byval(%struct.S31) align 1) 755 756; CHECK-LABEL: name: call_test_byval_31Byte{{.*}} 757 758; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 759; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 760; 32BIT-NEXT: renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS31, $r2 :: (load 4 from got) 761; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load 4) 762; 32BIT-DAG: renamable $r4 = LWZ 4, renamable $r[[REGADDR]] :: (load 4) 763; 32BIT-DAG: renamable $r5 = LWZ 8, renamable $r[[REGADDR]] :: (load 4) 764; 32BIT-DAG: renamable $r6 = LWZ 12, renamable $r[[REGADDR]] :: (load 4) 765; 32BIT-DAG: renamable $r7 = LWZ 16, renamable $r[[REGADDR]] :: (load 4) 766; 32BIT-DAG: renamable $r8 = LWZ 20, renamable $r[[REGADDR]] :: (load 4) 767; 32BIT-DAG: renamable $r9 = LWZ 24, renamable $r[[REGADDR]] :: (load 4) 768; 32BIT-DAG: renamable $r[[REG:[0-9]+]] = LHZ 28, renamable $r[[REGADDR]] :: (load 2) 769; 32BIT-DAG: renamable $r10 = LBZ 30, renamable $r[[REGADDR]] :: (load 1) 770; 32BIT-DAG: renamable $r10 = RLWINM killed renamable $r10, 8, 16, 23 771; 32BIT-DAG: renamable $r10 = RLWIMI killed renamable $r10, killed renamable $r[[REG]], 16, 0, 15 772; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_31Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1 773; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 774 775; CHECKASM-LABEL: .call_test_byval_31Byte: 776 777; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 778; ASM32: stwu 1, -64(1) 779; ASM32-NEXT: lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2) 780; ASM32-DAG: lwz 3, 0([[REGADDR]]) 781; ASM32-DAG: lwz 4, 4([[REGADDR]]) 782; ASM32-DAG: lwz 5, 8([[REGADDR]]) 783; ASM32-DAG: lwz 6, 12([[REGADDR]]) 784; ASM32-DAG: lwz 7, 16([[REGADDR]]) 785; ASM32-DAG: lwz 8, 20([[REGADDR]]) 786; ASM32-DAG: lwz 9, 24([[REGADDR]]) 787; ASM32-DAG: lbz 10, 30([[REGADDR]]) 788; ASM32-DAG: lhz [[REG:[0-9]+]], 28([[REGADDR]]) 789; ASM32-DAG: rlwinm 10, 10, 8, 16, 23 790; ASM32-DAG: rlwimi 10, [[REG]], 16, 0, 15 791; ASM32-NEXT: bl .test_byval_31Byte 792; ASM32-NEXT: nop 793 794; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 795; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 796; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS31, $x2 :: (load 8 from got) 797; 64BIT-DAG: renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load 8) 798; 64BIT-DAG: renamable $x4 = LD 8, renamable $x[[REGADDR]] :: (load 8) 799; 64BIT-DAG: renamable $x5 = LD 16, renamable $x[[REGADDR]] :: (load 8) 800; 64BIT-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 24, renamable $x[[REGADDR]] :: (load 4) 801; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LHZ8 28, renamable $x[[REGADDR]] :: (load 2) 802; 64BIT-DAG: renamable $x[[REG3:[0-9]+]] = LBZ8 30, renamable $x[[REGADDR]] :: (load 1) 803; 64BIT-DAG: renamable $x6 = RLWINM8 killed renamable $x[[REG3]], 8, 16, 23 804; 64BIT-DAG: renamable $x6 = RLWIMI8 killed renamable $x6, killed renamable $x[[REG2]], 16, 0, 15 805; 64BIT-DAG: renamable $x6 = RLDIMI killed renamable $x6, killed renamable $x[[REG1]], 32, 0 806; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_31Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x2, implicit-def $r1 807; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 808 809; ASM64: stdu 1, -112(1) 810; ASM64-NEXT: ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2) 811; ASM64-DAG: ld 3, 0([[REGADDR]]) 812; ASM64-DAG: ld 4, 8([[REGADDR]]) 813; ASM64-DAG: ld 5, 16([[REGADDR]]) 814; ASM64-DAG: lwz [[REG1:[0-9]+]], 24([[REGADDR]]) 815; ASM64-DAG: lhz [[REG2:[0-9]+]], 28([[REGADDR]]) 816; ASM64-DAG: lbz [[REG3:[0-9]+]], 30([[REGADDR]]) 817; ASM64-DAG: rlwinm 6, [[REG3]], 8, 16, 23 818; ASM64-DAG: rlwimi 6, [[REG2]], 16, 0, 15 819; ASM64-DAG: rldimi 6, [[REG1]], 32, 0 820; ASM64-NEXT: bl .test_byval_31Byte 821; ASM64-NEXT: nop 822 823 824%struct.F = type { float, float, float } 825 826define i32 @call_test_byval_homogeneous_float_struct() { 827entry: 828 %s = alloca %struct.F, align 4 829 %0 = bitcast %struct.F* %s to i8* 830 call void @llvm.memset.p0i8.i32(i8* align 4 %0, i8 0, i32 12, i1 false) 831 %call = call i32 @test_byval_homogeneous_float_struct(%struct.F* byval(%struct.F) align 4 %s) 832 ret i32 %call 833} 834 835declare void @llvm.memset.p0i8.i32(i8* nocapture writeonly, i8, i32, i1 immarg) 836 837declare i32 @test_byval_homogeneous_float_struct(%struct.F* byval(%struct.F) align 4) 838 839; CHECK-LABEL: name: call_test_byval_homogeneous_float_struct{{.*}} 840 841; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1 842; 32BIT-DAG: renamable $r3 = LWZ 0, %stack.0.s :: (load 4 from %stack.0.s, align 8) 843; 32BIT-DAG: renamable $r4 = LWZ 4, %stack.0.s :: (load 4 from %stack.0.s + 4) 844; 32BIT-DAG: renamable $r5 = LWZ 8, %stack.0.s :: (load 4 from %stack.0.s + 8, align 8) 845; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_homogeneous_float_struct>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r2, implicit-def $r1, implicit-def $r3 846; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1 847 848; CHECKASM-LABEL: .call_test_byval_homogeneous_float_struct: 849 850; ASM32: stwu 1, -80(1) 851; ASM32-DAG: lwz 3, 64(1) 852; ASM32-DAG: lwz 4, 68(1) 853; ASM32-DAG: lwz 5, 72(1) 854; ASM32-NEXT: bl .test_byval_homogeneous_float_struct 855; ASM32-NEXT: nop 856 857; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 858; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 859; 64BIT-DAG: renamable $x3 = LD 0, %stack.0.s :: (load 8 from %stack.0.s) 860; 64BIT-DAG: renamable $x4 = LWZ8 8, %stack.0.s :: (load 4 from %stack.0.s + 8, align 8) 861; 64BIT-DAG: renamable $x4 = RLDICR killed renamable $x4, 32, 31 862; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_homogeneous_float_struct>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x2, implicit-def $r1, implicit-def $x3 863; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 864 865; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. 866; ASM64: stdu 1, -128(1) 867; ASM64-DAG: ld 3, 112(1) 868; ASM64-DAG: lwz 4, 120(1) 869; ASM64-DAG: sldi 4, 4, 32 870; ASM64-NEXT: bl .test_byval_homogeneous_float_struct 871; ASM64-NEXT: nop 872