1; RUN: opt < %s -S -nvptx-lower-args | FileCheck %s --check-prefix IR
2; RUN: llc < %s -mcpu=sm_20 | FileCheck %s --check-prefix PTX
3
4target datalayout = "e-i64:64-i128:128-v16:16-v32:32-n16:32:64"
5target triple = "nvptx64-nvidia-cuda"
6
7%class.outer = type <{ %class.inner, i32, [4 x i8] }>
8%class.inner = type { i32*, i32* }
9
10; Check that nvptx-lower-args preserves arg alignment
11define void @load_alignment(%class.outer* nocapture readonly byval(%class.outer) align 8 %arg) {
12entry:
13; IR: load %class.outer, %class.outer addrspace(101)*
14; IR-SAME: align 8
15; PTX: ld.param.u64
16; PTX-NOT: ld.param.u8
17  %arg.idx = getelementptr %class.outer, %class.outer* %arg, i64 0, i32 0, i32 0
18  %arg.idx.val = load i32*, i32** %arg.idx, align 8
19  %arg.idx1 = getelementptr %class.outer, %class.outer* %arg, i64 0, i32 0, i32 1
20  %arg.idx1.val = load i32*, i32** %arg.idx1, align 8
21  %arg.idx2 = getelementptr %class.outer, %class.outer* %arg, i64 0, i32 1
22  %arg.idx2.val = load i32, i32* %arg.idx2, align 8
23  %arg.idx.val.val = load i32, i32* %arg.idx.val, align 4
24  %add.i = add nsw i32 %arg.idx.val.val, %arg.idx2.val
25  store i32 %add.i, i32* %arg.idx1.val, align 4
26
27  ; let the pointer escape so we still create a local copy this test uses to
28  ; check the load alignment.
29  %tmp = call i32* @escape(i32* nonnull %arg.idx2)
30  ret void
31}
32
33; Function Attrs: convergent nounwind
34declare dso_local i32* @escape(i32*) local_unnamed_addr
35