1; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 | FileCheck %s
2
3declare <2 x float> @barv(<2 x float> %input)
4declare [2 x float] @bara([2 x float] %input)
5declare {float, float} @bars({float, float} %input)
6
7define void @foov(<2 x float> %input, <2 x float>* %output) {
8; CHECK-LABEL: @foov
9  %call = tail call <2 x float> @barv(<2 x float> %input)
10; CHECK: .param .align 8 .b8 retval0[8];
11; CHECK: ld.param.v2.f32 {[[ELEMV1:%f[0-9]+]], [[ELEMV2:%f[0-9]+]]}, [retval0+0];
12  store <2 x float> %call, <2 x float>* %output, align 8
13; CHECK: st.v2.f32 [{{%rd[0-9]+}}], {[[ELEMV1]], [[ELEMV2]]}
14  ret void
15}
16
17define void @fooa([2 x float] %input, [2 x float]* %output) {
18; CHECK-LABEL: @fooa
19  %call = tail call [2 x float] @bara([2 x float] %input)
20; CHECK: .param .align 4 .b8 retval0[8];
21; CHECK-DAG: ld.param.f32 [[ELEMA1:%f[0-9]+]], [retval0+0];
22; CHECK-DAG: ld.param.f32 [[ELEMA2:%f[0-9]+]], [retval0+4];
23  store [2 x float] %call, [2 x float]* %output, align 4
24; CHECK: }
25; CHECK-DAG: st.f32 [{{%rd[0-9]+}}], [[ELEMA1]]
26; CHECK-DAG: st.f32 [{{%rd[0-9]+}}+4], [[ELEMA2]]
27  ret void
28; CHECK: ret
29}
30
31define void @foos({float, float} %input, {float, float}* %output) {
32; CHECK-LABEL: @foos
33  %call = tail call {float, float} @bars({float, float} %input)
34; CHECK: .param .align 4 .b8 retval0[8];
35; CHECK-DAG: ld.param.f32 [[ELEMS1:%f[0-9]+]], [retval0+0];
36; CHECK-DAG: ld.param.f32 [[ELEMS2:%f[0-9]+]], [retval0+4];
37  store {float, float} %call, {float, float}* %output, align 4
38; CHECK: }
39; CHECK-DAG: st.f32 [{{%rd[0-9]+}}], [[ELEMS1]]
40; CHECK-DAG: st.f32 [{{%rd[0-9]+}}+4], [[ELEMS2]]
41  ret void
42; CHECK: ret
43}
44