1; RUN: llc < %s -march=mipsel   -mcpu=mips32   -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32
2; RUN: llc < %s -march=mipsel   -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32R2
3; RUN: llc < %s -march=mipsel   -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32R6
4; RUN: llc < %s -march=mips64el -mcpu=mips64   -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64
5; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64R2
6; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64R6
7
8@d2 = external global double
9@d3 = external global double
10
11define i32 @i32_icmp_ne_i32_val(i32 signext %s, i32 signext %f0, i32 signext %f1) nounwind readnone {
12entry:
13; ALL-LABEL: i32_icmp_ne_i32_val:
14
15; 32:            movn $5, $6, $4
16; 32:            move $2, $5
17
18; 32R2:          movn $5, $6, $4
19; 32R2:          move $2, $5
20
21; 32R6-DAG:      seleqz $[[T0:[0-9]+]], $5, $4
22; 32R6-DAG:      selnez $[[T1:[0-9]+]], $6, $4
23; 32R6:          or $2, $[[T1]], $[[T0]]
24
25; 64:            movn $5, $6, $4
26; 64:            move $2, $5
27
28; 64R2:          movn $5, $6, $4
29; 64R2:          move $2, $5
30
31; 64R6-DAG:      seleqz $[[T0:[0-9]+]], $5, $4
32; 64R6-DAG:      selnez $[[T1:[0-9]+]], $6, $4
33; 64R6:          or $2, $[[T1]], $[[T0]]
34
35  %tobool = icmp ne i32 %s, 0
36  %cond = select i1 %tobool, i32 %f1, i32 %f0
37  ret i32 %cond
38}
39
40define i64 @i32_icmp_ne_i64_val(i32 signext %s, i64 %f0, i64 %f1) nounwind readnone {
41entry:
42; ALL-LABEL: i32_icmp_ne_i64_val:
43
44; 32-DAG:        lw $[[F1:[0-9]+]], 16($sp)
45; 32-DAG:        movn $6, $[[F1]], $4
46; 32-DAG:        lw $[[F1H:[0-9]+]], 20($sp)
47; 32:            movn $7, $[[F1H]], $4
48; 32:            move $2, $6
49; 32:            move $3, $7
50
51; 32R2-DAG:      lw $[[F1:[0-9]+]], 16($sp)
52; 32R2-DAG:      movn $6, $[[F1]], $4
53; 32R2-DAG:      lw $[[F1H:[0-9]+]], 20($sp)
54; 32R2:          movn $7, $[[F1H]], $4
55; 32R2:          move $2, $6
56; 32R2:          move $3, $7
57
58; 32R6-DAG:      lw $[[F1:[0-9]+]], 16($sp)
59; 32R6-DAG:      seleqz $[[T0:[0-9]+]], $6, $4
60; 32R6-DAG:      selnez $[[T1:[0-9]+]], $[[F1]], $4
61; 32R6:          or $2, $[[T1]], $[[T0]]
62; 32R6-DAG:      lw $[[F1H:[0-9]+]], 20($sp)
63; 32R6-DAG:      seleqz $[[T0:[0-9]+]], $7, $4
64; 32R6-DAG:      selnez $[[T1:[0-9]+]], $[[F1H]], $4
65; 32R6:          or $3, $[[T1]], $[[T0]]
66
67; 64:            movn $5, $6, $4
68; 64:            move $2, $5
69
70; 64R2:          movn $5, $6, $4
71; 64R2:          move $2, $5
72
73; FIXME: This sll works around an implementation detail in the code generator
74;        (setcc's result is i32 so bits 32-63 are undefined). It's not really
75;        needed.
76; 64R6-DAG:      sll $[[CC:[0-9]+]], $4, 0
77; 64R6-DAG:      seleqz $[[T0:[0-9]+]], $5, $[[CC]]
78; 64R6-DAG:      selnez $[[T1:[0-9]+]], $6, $[[CC]]
79; 64R6:          or $2, $[[T1]], $[[T0]]
80
81  %tobool = icmp ne i32 %s, 0
82  %cond = select i1 %tobool, i64 %f1, i64 %f0
83  ret i64 %cond
84}
85
86define i64 @i64_icmp_ne_i64_val(i64 %s, i64 %f0, i64 %f1) nounwind readnone {
87entry:
88; ALL-LABEL: i64_icmp_ne_i64_val:
89
90; 32-DAG:        or $[[CC:[0-9]+]], $4
91; 32-DAG:        lw $[[F1:[0-9]+]], 16($sp)
92; 32-DAG:        movn $6, $[[F1]], $[[CC]]
93; 32-DAG:        lw $[[F1H:[0-9]+]], 20($sp)
94; 32:            movn $7, $[[F1H]], $[[CC]]
95; 32:            move $2, $6
96; 32:            move $3, $7
97
98; 32R2-DAG:      or $[[CC:[0-9]+]], $4
99; 32R2-DAG:      lw $[[F1:[0-9]+]], 16($sp)
100; 32R2-DAG:      movn $6, $[[F1]], $[[CC]]
101; 32R2-DAG:      lw $[[F1H:[0-9]+]], 20($sp)
102; 32R2:          movn $7, $[[F1H]], $[[CC]]
103; 32R2:          move $2, $6
104; 32R2:          move $3, $7
105
106; 32R6-DAG:      lw $[[F1:[0-9]+]], 16($sp)
107; 32R6-DAG:      or $[[T2:[0-9]+]], $4, $5
108; 32R6-DAG:      seleqz $[[T0:[0-9]+]], $6, $[[T2]]
109; 32R6-DAG:      selnez $[[T1:[0-9]+]], $[[F1]], $[[T2]]
110; 32R6:          or $2, $[[T1]], $[[T0]]
111; 32R6-DAG:      lw $[[F1H:[0-9]+]], 20($sp)
112; 32R6-DAG:      seleqz $[[T0:[0-9]+]], $7, $[[T2]]
113; 32R6-DAG:      selnez $[[T1:[0-9]+]], $[[F1H]], $[[T2]]
114; 32R6:          or $3, $[[T1]], $[[T0]]
115
116; 64:            movn $5, $6, $4
117; 64:            move $2, $5
118
119; 64R2:          movn $5, $6, $4
120; 64R2:          move $2, $5
121
122; 64R6-DAG:      seleqz $[[T0:[0-9]+]], $5, $4
123; 64R6-DAG:      selnez $[[T1:[0-9]+]], $6, $4
124; 64R6:          or $2, $[[T1]], $[[T0]]
125
126  %tobool = icmp ne i64 %s, 0
127  %cond = select i1 %tobool, i64 %f1, i64 %f0
128  ret i64 %cond
129}
130
131define float @i32_icmp_ne_f32_val(i32 signext %s, float %f0, float %f1) nounwind readnone {
132entry:
133; ALL-LABEL: i32_icmp_ne_f32_val:
134
135; 32-DAG:        mtc1 $5, $[[F0:f[0-9]+]]
136; 32-DAG:        mtc1 $6, $[[F1:f0]]
137; 32:            movn.s $[[F1]], $[[F0]], $4
138
139; 32R2-DAG:      mtc1 $5, $[[F0:f[0-9]+]]
140; 32R2-DAG:      mtc1 $6, $[[F1:f0]]
141; 32R2:          movn.s $[[F1]], $[[F0]], $4
142
143; 32R6:          sltu $[[T0:[0-9]+]], $zero, $4
144; 32R6:          negu $[[T0]], $[[T0]]
145; 32R6-DAG:      mtc1 $5, $[[F0:f[0-9]+]]
146; 32R6-DAG:      mtc1 $6, $[[F1:f[0-9]+]]
147; 32R6:          mtc1 $[[T0]], $[[CC:f0]]
148; 32R6:          sel.s $[[CC]], $[[F1]], $[[F0]]
149
150; 64:            movn.s $f14, $f13, $4
151; 64:            mov.s $f0, $f14
152
153; 64R2:          movn.s $f14, $f13, $4
154; 64R2:          mov.s $f0, $f14
155
156; 64R6:          sltu $[[T0:[0-9]+]], $zero, $4
157; 64R6:          mtc1 $[[T0]], $[[CC:f0]]
158; 64R6:          sel.s $[[CC]], $f14, $f13
159
160  %tobool = icmp ne i32 %s, 0
161  %cond = select i1 %tobool, float %f0, float %f1
162  ret float %cond
163}
164
165define double @i32_icmp_ne_f64_val(i32 signext %s, double %f0, double %f1) nounwind readnone {
166entry:
167; ALL-LABEL: i32_icmp_ne_f64_val:
168
169; 32-DAG:        mtc1 $6, $[[F0:f[1-3]*[02468]+]]
170; 32-DAG:        mtc1 $7, $[[F0H:f[1-3]*[13579]+]]
171; 32-DAG:        ldc1 $[[F1:f0]], 16($sp)
172; 32:            movn.d $[[F1]], $[[F0]], $4
173
174; 32R2-DAG:      mtc1 $6, $[[F0:f[0-9]+]]
175; 32R2-DAG:      mthc1 $7, $[[F0]]
176; 32R2-DAG:      ldc1 $[[F1:f0]], 16($sp)
177; 32R2:          movn.d $[[F1]], $[[F0]], $4
178
179; 32R6-DAG:      mtc1 $6, $[[F0:f[0-9]+]]
180; 32R6-DAG:      mthc1 $7, $[[F0]]
181; 32R6-DAG:      sltu $[[T0:[0-9]+]], $zero, $4
182; 32R6-DAG:      mtc1 $[[T0]], $[[CC:f0]]
183; 32R6-DAG:      ldc1 $[[F1:f[0-9]+]], 16($sp)
184; 32R6:          sel.d $[[CC]], $[[F1]], $[[F0]]
185
186; 64:            movn.d $f14, $f13, $4
187; 64:            mov.d $f0, $f14
188
189; 64R2:          movn.d $f14, $f13, $4
190; 64R2:          mov.d $f0, $f14
191
192; 64R6-DAG:      sltu $[[T0:[0-9]+]], $zero, $4
193; 64R6-DAG:      mtc1 $[[T0]], $[[CC:f0]]
194; 64R6:          sel.d $[[CC]], $f14, $f13
195
196  %tobool = icmp ne i32 %s, 0
197  %cond = select i1 %tobool, double %f0, double %f1
198  ret double %cond
199}
200
201define float @f32_fcmp_oeq_f32_val(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
202entry:
203; ALL-LABEL: f32_fcmp_oeq_f32_val:
204
205; 32-DAG:        mtc1 $6, $[[F2:f[0-9]+]]
206; 32-DAG:        mtc1 $7, $[[F3:f[0-9]+]]
207; 32:            c.eq.s $[[F2]], $[[F3]]
208; 32:            movt.s $f14, $f12, $fcc0
209; 32:            mov.s $f0, $f14
210
211; 32R2-DAG:      mtc1 $6, $[[F2:f[0-9]+]]
212; 32R2-DAG:      mtc1 $7, $[[F3:f[0-9]+]]
213; 32R2:          c.eq.s $[[F2]], $[[F3]]
214; 32R2:          movt.s $f14, $f12, $fcc0
215; 32R2:          mov.s $f0, $f14
216
217; 32R6-DAG:      mtc1 $6, $[[F2:f[0-9]+]]
218; 32R6-DAG:      mtc1 $7, $[[F3:f[0-9]+]]
219; 32R6:          cmp.eq.s $[[CC:f0]], $[[F2]], $[[F3]]
220; 32R6:          sel.s $[[CC]], $f14, $f12
221
222; 64:            c.eq.s $f14, $f15
223; 64:            movt.s $f13, $f12, $fcc0
224; 64:            mov.s $f0, $f13
225
226; 64R2:          c.eq.s $f14, $f15
227; 64R2:          movt.s $f13, $f12, $fcc0
228; 64R2:          mov.s $f0, $f13
229
230; 64R6:          cmp.eq.s $[[CC:f0]], $f14, $f15
231; 64R6:          sel.s $[[CC]], $f13, $f12
232
233  %cmp = fcmp oeq float %f2, %f3
234  %cond = select i1 %cmp, float %f0, float %f1
235  ret float %cond
236}
237
238define float @f32_fcmp_olt_f32_val(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
239entry:
240; ALL-LABEL: f32_fcmp_olt_f32_val:
241
242; 32-DAG:        mtc1 $6, $[[F2:f[0-9]+]]
243; 32-DAG:        mtc1 $7, $[[F3:f[0-9]+]]
244; 32:            c.olt.s $[[F2]], $[[F3]]
245; 32:            movt.s $f14, $f12, $fcc0
246; 32:            mov.s $f0, $f14
247
248; 32R2-DAG:      mtc1 $6, $[[F2:f[0-9]+]]
249; 32R2-DAG:      mtc1 $7, $[[F3:f[0-9]+]]
250; 32R2:          c.olt.s $[[F2]], $[[F3]]
251; 32R2:          movt.s $f14, $f12, $fcc0
252; 32R2:          mov.s $f0, $f14
253
254; 32R6-DAG:      mtc1 $6, $[[F2:f[0-9]+]]
255; 32R6-DAG:      mtc1 $7, $[[F3:f[0-9]+]]
256; 32R6:          cmp.lt.s $[[CC:f0]], $[[F2]], $[[F3]]
257; 32R6:          sel.s $[[CC]], $f14, $f12
258
259; 64:            c.olt.s $f14, $f15
260; 64:            movt.s $f13, $f12, $fcc0
261; 64:            mov.s $f0, $f13
262
263; 64R2:          c.olt.s $f14, $f15
264; 64R2:          movt.s $f13, $f12, $fcc0
265; 64R2:          mov.s $f0, $f13
266
267; 64R6:          cmp.lt.s $[[CC:f0]], $f14, $f15
268; 64R6:          sel.s $[[CC]], $f13, $f12
269
270  %cmp = fcmp olt float %f2, %f3
271  %cond = select i1 %cmp, float %f0, float %f1
272  ret float %cond
273}
274
275define float @f32_fcmp_ogt_f32_val(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
276entry:
277; ALL-LABEL: f32_fcmp_ogt_f32_val:
278
279; 32-DAG:        mtc1 $6, $[[F2:f[0-9]+]]
280; 32-DAG:        mtc1 $7, $[[F3:f[0-9]+]]
281; 32:            c.ule.s $[[F2]], $[[F3]]
282; 32:            movf.s $f14, $f12, $fcc0
283; 32:            mov.s $f0, $f14
284
285; 32R2-DAG:      mtc1 $6, $[[F2:f[0-9]+]]
286; 32R2-DAG:      mtc1 $7, $[[F3:f[0-9]+]]
287; 32R2:          c.ule.s $[[F2]], $[[F3]]
288; 32R2:          movf.s $f14, $f12, $fcc0
289; 32R2:          mov.s $f0, $f14
290
291; 32R6-DAG:      mtc1 $6, $[[F2:f[0-9]+]]
292; 32R6-DAG:      mtc1 $7, $[[F3:f[0-9]+]]
293; 32R6:          cmp.lt.s $[[CC:f0]], $[[F3]], $[[F2]]
294; 32R6:          sel.s $[[CC]], $f14, $f12
295
296; 64:            c.ule.s $f14, $f15
297; 64:            movf.s $f13, $f12, $fcc0
298; 64:            mov.s $f0, $f13
299
300; 64R2:          c.ule.s $f14, $f15
301; 64R2:          movf.s $f13, $f12, $fcc0
302; 64R2:          mov.s $f0, $f13
303
304; 64R6:          cmp.lt.s $[[CC:f0]], $f15, $f14
305; 64R6:          sel.s $[[CC]], $f13, $f12
306
307  %cmp = fcmp ogt float %f2, %f3
308  %cond = select i1 %cmp, float %f0, float %f1
309  ret float %cond
310}
311
312define double @f32_fcmp_ogt_f64_val(double %f0, double %f1, float %f2, float %f3) nounwind readnone {
313entry:
314; ALL-LABEL: f32_fcmp_ogt_f64_val:
315
316; 32-DAG:        lwc1 $[[F2:f[0-9]+]], 16($sp)
317; 32-DAG:        lwc1 $[[F3:f[0-9]+]], 20($sp)
318; 32:            c.ule.s $[[F2]], $[[F3]]
319; 32:            movf.d $f14, $f12, $fcc0
320; 32:            mov.d $f0, $f14
321
322; 32R2-DAG:      lwc1 $[[F2:f[0-9]+]], 16($sp)
323; 32R2-DAG:      lwc1 $[[F3:f[0-9]+]], 20($sp)
324; 32R2:          c.ule.s $[[F2]], $[[F3]]
325; 32R2:          movf.d $f14, $f12, $fcc0
326; 32R2:          mov.d $f0, $f14
327
328; 32R6-DAG:      lwc1 $[[F2:f[0-9]+]], 16($sp)
329; 32R6-DAG:      lwc1 $[[F3:f[0-9]+]], 20($sp)
330; 32R6:          cmp.lt.s $[[CC:f0]], $[[F3]], $[[F2]]
331; 32R6:          sel.d $[[CC]], $f14, $f12
332
333; 64:            c.ule.s $f14, $f15
334; 64:            movf.d $f13, $f12, $fcc0
335; 64:            mov.d $f0, $f13
336
337; 64R2:          c.ule.s $f14, $f15
338; 64R2:          movf.d $f13, $f12, $fcc0
339; 64R2:          mov.d $f0, $f13
340
341; 64R6:          cmp.lt.s $[[CC:f0]], $f15, $f14
342; 64R6:          sel.d $[[CC]], $f13, $f12
343
344  %cmp = fcmp ogt float %f2, %f3
345  %cond = select i1 %cmp, double %f0, double %f1
346  ret double %cond
347}
348
349define double @f64_fcmp_oeq_f64_val(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
350entry:
351; ALL-LABEL: f64_fcmp_oeq_f64_val:
352
353; 32-DAG:        ldc1 $[[F2:f[0-9]+]], 16($sp)
354; 32-DAG:        ldc1 $[[F3:f[0-9]+]], 24($sp)
355; 32:            c.eq.d $[[F2]], $[[F3]]
356; 32:            movt.d $f14, $f12, $fcc0
357; 32:            mov.d $f0, $f14
358
359; 32R2-DAG:      ldc1 $[[F2:f[0-9]+]], 16($sp)
360; 32R2-DAG:      ldc1 $[[F3:f[0-9]+]], 24($sp)
361; 32R2:          c.eq.d $[[F2]], $[[F3]]
362; 32R2:          movt.d $f14, $f12, $fcc0
363; 32R2:          mov.d $f0, $f14
364
365; 32R6-DAG:      ldc1 $[[F2:f[0-9]+]], 16($sp)
366; 32R6-DAG:      ldc1 $[[F3:f[0-9]+]], 24($sp)
367; 32R6:          cmp.eq.d $[[CC:f0]], $[[F2]], $[[F3]]
368; 32R6:          sel.d $[[CC]], $f14, $f12
369
370; 64:            c.eq.d $f14, $f15
371; 64:            movt.d $f13, $f12, $fcc0
372; 64:            mov.d $f0, $f13
373
374; 64R2:          c.eq.d $f14, $f15
375; 64R2:          movt.d $f13, $f12, $fcc0
376; 64R2:          mov.d $f0, $f13
377
378; 64R6:          cmp.eq.d $[[CC:f0]], $f14, $f15
379; 64R6:          sel.d $[[CC]], $f13, $f12
380
381  %cmp = fcmp oeq double %f2, %f3
382  %cond = select i1 %cmp, double %f0, double %f1
383  ret double %cond
384}
385
386define double @f64_fcmp_olt_f64_val(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
387entry:
388; ALL-LABEL: f64_fcmp_olt_f64_val:
389
390; 32-DAG:        ldc1 $[[F2:f[0-9]+]], 16($sp)
391; 32-DAG:        ldc1 $[[F3:f[0-9]+]], 24($sp)
392; 32:            c.olt.d $[[F2]], $[[F3]]
393; 32:            movt.d $f14, $f12, $fcc0
394; 32:            mov.d $f0, $f14
395
396; 32R2-DAG:      ldc1 $[[F2:f[0-9]+]], 16($sp)
397; 32R2-DAG:      ldc1 $[[F3:f[0-9]+]], 24($sp)
398; 32R2:          c.olt.d $[[F2]], $[[F3]]
399; 32R2:          movt.d $f14, $f12, $fcc0
400; 32R2:          mov.d $f0, $f14
401
402; 32R6-DAG:      ldc1 $[[F2:f[0-9]+]], 16($sp)
403; 32R6-DAG:      ldc1 $[[F3:f[0-9]+]], 24($sp)
404; 32R6:          cmp.lt.d $[[CC:f0]], $[[F2]], $[[F3]]
405; 32R6:          sel.d $[[CC]], $f14, $f12
406
407; 64:            c.olt.d $f14, $f15
408; 64:            movt.d $f13, $f12, $fcc0
409; 64:            mov.d $f0, $f13
410
411; 64R2:          c.olt.d $f14, $f15
412; 64R2:          movt.d $f13, $f12, $fcc0
413; 64R2:          mov.d $f0, $f13
414
415; 64R6:          cmp.lt.d $[[CC:f0]], $f14, $f15
416; 64R6:          sel.d $[[CC]], $f13, $f12
417
418  %cmp = fcmp olt double %f2, %f3
419  %cond = select i1 %cmp, double %f0, double %f1
420  ret double %cond
421}
422
423define double @f64_fcmp_ogt_f64_val(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
424entry:
425; ALL-LABEL: f64_fcmp_ogt_f64_val:
426
427; 32-DAG:        ldc1 $[[F2:f[0-9]+]], 16($sp)
428; 32-DAG:        ldc1 $[[F3:f[0-9]+]], 24($sp)
429; 32:            c.ule.d $[[F2]], $[[F3]]
430; 32:            movf.d $f14, $f12, $fcc0
431; 32:            mov.d $f0, $f14
432
433; 32R2-DAG:      ldc1 $[[F2:f[0-9]+]], 16($sp)
434; 32R2-DAG:      ldc1 $[[F3:f[0-9]+]], 24($sp)
435; 32R2:          c.ule.d $[[F2]], $[[F3]]
436; 32R2:          movf.d $f14, $f12, $fcc0
437; 32R2:          mov.d $f0, $f14
438
439; 32R6-DAG:      ldc1 $[[F2:f[0-9]+]], 16($sp)
440; 32R6-DAG:      ldc1 $[[F3:f[0-9]+]], 24($sp)
441; 32R6:          cmp.lt.d $[[CC:f0]], $[[F3]], $[[F2]]
442; 32R6:          sel.d $[[CC]], $f14, $f12
443
444; 64:            c.ule.d $f14, $f15
445; 64:            movf.d $f13, $f12, $fcc0
446; 64:            mov.d $f0, $f13
447
448; 64R2:          c.ule.d $f14, $f15
449; 64R2:          movf.d $f13, $f12, $fcc0
450; 64R2:          mov.d $f0, $f13
451
452; 64R6:          cmp.lt.d $[[CC:f0]], $f15, $f14
453; 64R6:          sel.d $[[CC]], $f13, $f12
454
455  %cmp = fcmp ogt double %f2, %f3
456  %cond = select i1 %cmp, double %f0, double %f1
457  ret double %cond
458}
459
460define float @f64_fcmp_ogt_f32_val(float %f0, float %f1, double %f2, double %f3) nounwind readnone {
461entry:
462; ALL-LABEL: f64_fcmp_ogt_f32_val:
463
464; 32-DAG:        mtc1 $6, $[[F2:f[1-3]*[02468]+]]
465; 32-DAG:        mtc1 $7, $[[F2H:f[1-3]*[13579]+]]
466; 32-DAG:        ldc1 $[[F3:f[0-9]+]], 16($sp)
467; 32:            c.ule.d $[[F2]], $[[F3]]
468; 32:            movf.s $f14, $f12, $fcc0
469; 32:            mov.s $f0, $f14
470
471; 32R2-DAG:      mtc1 $6, $[[F2:f[0-9]+]]
472; 32R2-DAG:      mthc1 $7, $[[F2]]
473; 32R2-DAG:      ldc1 $[[F3:f[0-9]+]], 16($sp)
474; 32R2:          c.ule.d $[[F2]], $[[F3]]
475; 32R2:          movf.s $f14, $f12, $fcc0
476; 32R2:          mov.s $f0, $f14
477
478; 32R6-DAG:      mtc1 $6, $[[F2:f[0-9]+]]
479; 32R6-DAG:      mthc1 $7, $[[F2]]
480; 32R6-DAG:      ldc1 $[[F3:f[0-9]+]], 16($sp)
481; 32R6:          cmp.lt.d $[[CC:f0]], $[[F3]], $[[F2]]
482; 32R6:          sel.s $[[CC]], $f14, $f12
483
484; 64:            c.ule.d $f14, $f15
485; 64:            movf.s $f13, $f12, $fcc0
486; 64:            mov.s $f0, $f13
487
488; 64R2:          c.ule.d $f14, $f15
489; 64R2:          movf.s $f13, $f12, $fcc0
490; 64R2:          mov.s $f0, $f13
491
492; 64R6:          cmp.lt.d $[[CC:f0]], $f15, $f14
493; 64R6:          sel.s $[[CC]], $f13, $f12
494
495  %cmp = fcmp ogt double %f2, %f3
496  %cond = select i1 %cmp, float %f0, float %f1
497  ret float %cond
498}
499
500define i32 @f32_fcmp_oeq_i32_val(i32 signext %f0, i32 signext %f1, float %f2, float %f3) nounwind readnone {
501entry:
502; ALL-LABEL: f32_fcmp_oeq_i32_val:
503
504; 32-DAG:        mtc1 $6, $[[F2:f[0-9]+]]
505; 32-DAG:        mtc1 $7, $[[F3:f[0-9]+]]
506; 32:            c.eq.s $[[F2]], $[[F3]]
507; 32:            movt $5, $4, $fcc0
508; 32:            move $2, $5
509
510; 32R2-DAG:      mtc1 $6, $[[F2:f[0-9]+]]
511; 32R2-DAG:      mtc1 $7, $[[F3:f[0-9]+]]
512; 32R2:          c.eq.s $[[F2]], $[[F3]]
513; 32R2:          movt $5, $4, $fcc0
514; 32R2:          move $2, $5
515
516; 32R6-DAG:      mtc1 $6, $[[F2:f[0-9]+]]
517; 32R6-DAG:      mtc1 $7, $[[F3:f[0-9]+]]
518; 32R6:          cmp.eq.s $[[CC:f[0-9]+]], $[[F2]], $[[F3]]
519; 32R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
520; 32R6:          andi $[[CCGPR]], $[[CCGPR]], 1
521; 32R6:          seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
522; 32R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
523; 32R6:          or $2, $[[NE]], $[[EQ]]
524
525; 64:            c.eq.s $f14, $f15
526; 64:            movt $5, $4, $fcc0
527; 64:            move $2, $5
528
529; 64R2:          c.eq.s $f14, $f15
530; 64R2:          movt $5, $4, $fcc0
531; 64R2:          move $2, $5
532
533; 64R6:          cmp.eq.s $[[CC:f[0-9]+]], $f14, $f15
534; 64R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
535; 64R6:          andi $[[CCGPR]], $[[CCGPR]], 1
536; 64R6:          seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
537; 64R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
538; 64R6:          or $2, $[[NE]], $[[EQ]]
539
540  %cmp = fcmp oeq float %f2, %f3
541  %cond = select i1 %cmp, i32 %f0, i32 %f1
542  ret i32 %cond
543}
544
545define i32 @f32_fcmp_olt_i32_val(i32 signext %f0, i32 signext %f1, float %f2, float %f3) nounwind readnone {
546entry:
547; ALL-LABEL: f32_fcmp_olt_i32_val:
548
549; 32-DAG:        mtc1 $6, $[[F2:f[0-9]+]]
550; 32-DAG:        mtc1 $7, $[[F3:f[0-9]+]]
551; 32:            c.olt.s $[[F2]], $[[F3]]
552; 32:            movt $5, $4, $fcc0
553; 32:            move $2, $5
554
555; 32R2-DAG:      mtc1 $6, $[[F2:f[0-9]+]]
556; 32R2-DAG:      mtc1 $7, $[[F3:f[0-9]+]]
557; 32R2:          c.olt.s $[[F2]], $[[F3]]
558; 32R2:          movt $5, $4, $fcc0
559; 32R2:          move $2, $5
560
561; 32R6-DAG:      mtc1 $6, $[[F2:f[0-9]+]]
562; 32R6-DAG:      mtc1 $7, $[[F3:f[0-9]+]]
563; 32R6:          cmp.lt.s $[[CC:f[0-9]+]], $[[F2]], $[[F3]]
564; 32R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
565; 32R6:          andi $[[CCGPR]], $[[CCGPR]], 1
566; 32R6:          seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
567; 32R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
568; 32R6:          or $2, $[[NE]], $[[EQ]]
569
570; 64:            c.olt.s $f14, $f15
571; 64:            movt $5, $4, $fcc0
572; 64:            move $2, $5
573
574; 64R2:          c.olt.s $f14, $f15
575; 64R2:          movt $5, $4, $fcc0
576; 64R2:          move $2, $5
577
578; 64R6:          cmp.lt.s $[[CC:f[0-9]+]], $f14, $f15
579; 64R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
580; 64R6:          andi $[[CCGPR]], $[[CCGPR]], 1
581; 64R6:          seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
582; 64R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
583; 64R6:          or $2, $[[NE]], $[[EQ]]
584  %cmp = fcmp olt float %f2, %f3
585  %cond = select i1 %cmp, i32 %f0, i32 %f1
586  ret i32 %cond
587}
588
589define i32 @f32_fcmp_ogt_i32_val(i32 signext %f0, i32 signext %f1, float %f2, float %f3) nounwind readnone {
590entry:
591; ALL-LABEL: f32_fcmp_ogt_i32_val:
592
593; 32-DAG:        mtc1 $6, $[[F2:f[0-9]+]]
594; 32-DAG:        mtc1 $7, $[[F3:f[0-9]+]]
595; 32:            c.ule.s $[[F2]], $[[F3]]
596; 32:            movf $5, $4, $fcc0
597; 32:            move $2, $5
598
599; 32R2-DAG:      mtc1 $6, $[[F2:f[0-9]+]]
600; 32R2-DAG:      mtc1 $7, $[[F3:f[0-9]+]]
601; 32R2:          c.ule.s $[[F2]], $[[F3]]
602; 32R2:          movf $5, $4, $fcc0
603; 32R2:          move $2, $5
604
605; 32R6-DAG:      mtc1 $6, $[[F2:f[0-9]+]]
606; 32R6-DAG:      mtc1 $7, $[[F3:f[0-9]+]]
607; 32R6:          cmp.lt.s $[[CC:f[0-9]+]], $[[F3]], $[[F2]]
608; 32R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
609; 32R6:          andi $[[CCGPR]], $[[CCGPR]], 1
610; 32R6:          seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
611; 32R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
612; 32R6:          or $2, $[[NE]], $[[EQ]]
613
614; 64:            c.ule.s $f14, $f15
615; 64:            movf $5, $4, $fcc0
616; 64:            move $2, $5
617
618; 64R2:          c.ule.s $f14, $f15
619; 64R2:          movf $5, $4, $fcc0
620; 64R2:          move $2, $5
621
622; 64R6:          cmp.lt.s $[[CC:f[0-9]+]], $f15, $f14
623; 64R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
624; 64R6:          andi $[[CCGPR]], $[[CCGPR]], 1
625; 64R6:          seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
626; 64R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
627; 64R6:          or $2, $[[NE]], $[[EQ]]
628
629  %cmp = fcmp ogt float %f2, %f3
630  %cond = select i1 %cmp, i32 %f0, i32 %f1
631  ret i32 %cond
632}
633
634define i32 @f64_fcmp_oeq_i32_val(i32 signext %f0, i32 signext %f1) nounwind readonly {
635entry:
636; ALL-LABEL: f64_fcmp_oeq_i32_val:
637
638; 32-DAG:        addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
639; 32-DAG:        addu $[[GOT:[0-9]+]], $[[T0]], $25
640; 32-DAG:        lw $[[D2:[0-9]+]], %got(d2)($1)
641; 32-DAG:        ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
642; 32-DAG:        lw $[[D3:[0-9]+]], %got(d3)($1)
643; 32-DAG:        ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
644; 32:            c.eq.d $[[TMP]], $[[TMP1]]
645; 32:            movt $5, $4, $fcc0
646; 32:            move $2, $5
647
648; 32R2-DAG:      addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
649; 32R2-DAG:      addu $[[GOT:[0-9]+]], $[[T0]], $25
650; 32R2-DAG:      lw $[[D2:[0-9]+]], %got(d2)($1)
651; 32R2-DAG:      ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
652; 32R2-DAG:      lw $[[D3:[0-9]+]], %got(d3)($1)
653; 32R2-DAG:      ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
654; 32R2:          c.eq.d $[[TMP]], $[[TMP1]]
655; 32R2:          movt $5, $4, $fcc0
656; 32R2:          move $2, $5
657
658; 32R6-DAG:      addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
659; 32R6-DAG:      addu $[[GOT:[0-9]+]], $[[T0]], $25
660; 32R6-DAG:      lw $[[D2:[0-9]+]], %got(d2)($1)
661; 32R6-DAG:      ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
662; 32R6-DAG:      lw $[[D3:[0-9]+]], %got(d3)($1)
663; 32R6-DAG:      ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
664; 32R6:          cmp.eq.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
665; 32R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
666; 32R6:          andi $[[CCGPR]], $[[CCGPR]], 1
667; 32R6:          seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
668; 32R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
669; 32R6:          or $2, $[[NE]], $[[EQ]]
670
671; 64-DAG:        daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
672; 64-DAG:        daddu $[[GOT:[0-9]+]], $[[T0]], $25
673; 64-DAG:        ld $[[D2:[0-9]+]], %got_disp(d2)($1)
674; 64-DAG:        ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
675; 64-DAG:        ld $[[D3:[0-9]+]], %got_disp(d3)($1)
676; 64-DAG:        ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
677; 64:            c.eq.d $[[TMP]], $[[TMP1]]
678; 64:            movt $5, $4, $fcc0
679; 64:            move $2, $5
680
681; 64R2-DAG:      daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
682; 64R2-DAG:      daddu $[[GOT:[0-9]+]], $[[T0]], $25
683; 64R2-DAG:      ld $[[D2:[0-9]+]], %got_disp(d2)($1)
684; 64R2-DAG:      ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
685; 64R2-DAG:      ld $[[D3:[0-9]+]], %got_disp(d3)($1)
686; 64R2-DAG:      ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
687; 64R2:          c.eq.d $[[TMP]], $[[TMP1]]
688; 64R2:          movt $5, $4, $fcc0
689; 64R2:          move $2, $5
690
691; 64R6-DAG:      daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_oeq_i32_val)))
692; 64R6-DAG:      daddu $[[GOT:[0-9]+]], $[[T0]], $25
693; 64R6-DAG:      ld $[[D2:[0-9]+]], %got_disp(d2)($1)
694; 64R6-DAG:      ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
695; 64R6-DAG:      ld $[[D3:[0-9]+]], %got_disp(d3)($1)
696; 64R6-DAG:      ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
697; 64R6:          cmp.eq.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
698; 64R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
699; 64R6:          andi $[[CCGPR]], $[[CCGPR]], 1
700; 64R6:          seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
701; 64R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
702; 64R6:          or $2, $[[NE]], $[[EQ]]
703
704  %tmp = load double, double* @d2, align 8
705  %tmp1 = load double, double* @d3, align 8
706  %cmp = fcmp oeq double %tmp, %tmp1
707  %cond = select i1 %cmp, i32 %f0, i32 %f1
708  ret i32 %cond
709}
710
711define i32 @f64_fcmp_olt_i32_val(i32 signext %f0, i32 signext %f1) nounwind readonly {
712entry:
713; ALL-LABEL: f64_fcmp_olt_i32_val:
714
715; 32-DAG:        addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
716; 32-DAG:        addu $[[GOT:[0-9]+]], $[[T0]], $25
717; 32-DAG:        lw $[[D2:[0-9]+]], %got(d2)($1)
718; 32-DAG:        ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
719; 32-DAG:        lw $[[D3:[0-9]+]], %got(d3)($1)
720; 32-DAG:        ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
721; 32:            c.olt.d $[[TMP]], $[[TMP1]]
722; 32:            movt $5, $4, $fcc0
723; 32:            move $2, $5
724
725; 32R2-DAG:      addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
726; 32R2-DAG:      addu $[[GOT:[0-9]+]], $[[T0]], $25
727; 32R2-DAG:      lw $[[D2:[0-9]+]], %got(d2)($1)
728; 32R2-DAG:      ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
729; 32R2-DAG:      lw $[[D3:[0-9]+]], %got(d3)($1)
730; 32R2-DAG:      ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
731; 32R2:          c.olt.d $[[TMP]], $[[TMP1]]
732; 32R2:          movt $5, $4, $fcc0
733; 32R2:          move $2, $5
734
735; 32R6-DAG:      addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
736; 32R6-DAG:      addu $[[GOT:[0-9]+]], $[[T0]], $25
737; 32R6-DAG:      lw $[[D2:[0-9]+]], %got(d2)($1)
738; 32R6-DAG:      ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
739; 32R6-DAG:      lw $[[D3:[0-9]+]], %got(d3)($1)
740; 32R6-DAG:      ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
741; 32R6:          cmp.lt.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
742; 32R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
743; 32R6:          andi $[[CCGPR]], $[[CCGPR]], 1
744; 32R6:          seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
745; 32R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
746; 32R6:          or $2, $[[NE]], $[[EQ]]
747
748; 64-DAG:        daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
749; 64-DAG:        daddu $[[GOT:[0-9]+]], $[[T0]], $25
750; 64-DAG:        ld $[[D2:[0-9]+]], %got_disp(d2)($1)
751; 64-DAG:        ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
752; 64-DAG:        ld $[[D3:[0-9]+]], %got_disp(d3)($1)
753; 64-DAG:        ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
754; 64:            c.olt.d $[[TMP]], $[[TMP1]]
755; 64:            movt $5, $4, $fcc0
756; 64:            move $2, $5
757
758; 64R2-DAG:      daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
759; 64R2-DAG:      daddu $[[GOT:[0-9]+]], $[[T0]], $25
760; 64R2-DAG:      ld $[[D2:[0-9]+]], %got_disp(d2)($1)
761; 64R2-DAG:      ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
762; 64R2-DAG:      ld $[[D3:[0-9]+]], %got_disp(d3)($1)
763; 64R2-DAG:      ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
764; 64R2:          c.olt.d $[[TMP]], $[[TMP1]]
765; 64R2:          movt $5, $4, $fcc0
766; 64R2:          move $2, $5
767
768; 64R6-DAG:      daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_olt_i32_val)))
769; 64R6-DAG:      daddu $[[GOT:[0-9]+]], $[[T0]], $25
770; 64R6-DAG:      ld $[[D2:[0-9]+]], %got_disp(d2)($1)
771; 64R6-DAG:      ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
772; 64R6-DAG:      ld $[[D3:[0-9]+]], %got_disp(d3)($1)
773; 64R6-DAG:      ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
774; 64R6:          cmp.lt.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
775; 64R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
776; 64R6:          andi $[[CCGPR]], $[[CCGPR]], 1
777; 64R6:          seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
778; 64R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
779; 64R6:          or $2, $[[NE]], $[[EQ]]
780
781  %tmp = load double, double* @d2, align 8
782  %tmp1 = load double, double* @d3, align 8
783  %cmp = fcmp olt double %tmp, %tmp1
784  %cond = select i1 %cmp, i32 %f0, i32 %f1
785  ret i32 %cond
786}
787
788define i32 @f64_fcmp_ogt_i32_val(i32 signext %f0, i32 signext %f1) nounwind readonly {
789entry:
790; ALL-LABEL: f64_fcmp_ogt_i32_val:
791
792; 32-DAG:        addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
793; 32-DAG:        addu $[[GOT:[0-9]+]], $[[T0]], $25
794; 32-DAG:        lw $[[D2:[0-9]+]], %got(d2)($1)
795; 32-DAG:        ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
796; 32-DAG:        lw $[[D3:[0-9]+]], %got(d3)($1)
797; 32-DAG:        ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
798; 32:            c.ule.d $[[TMP]], $[[TMP1]]
799; 32:            movf $5, $4, $fcc0
800; 32:            move $2, $5
801
802; 32R2-DAG:      addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
803; 32R2-DAG:      addu $[[GOT:[0-9]+]], $[[T0]], $25
804; 32R2-DAG:      lw $[[D2:[0-9]+]], %got(d2)($1)
805; 32R2-DAG:      ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
806; 32R2-DAG:      lw $[[D3:[0-9]+]], %got(d3)($1)
807; 32R2-DAG:      ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
808; 32R2:          c.ule.d $[[TMP]], $[[TMP1]]
809; 32R2:          movf $5, $4, $fcc0
810; 32R2:          move $2, $5
811
812; 32R6-DAG:      addiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(_gp_disp)
813; 32R6-DAG:      addu $[[GOT:[0-9]+]], $[[T0]], $25
814; 32R6-DAG:      lw $[[D2:[0-9]+]], %got(d2)($1)
815; 32R6-DAG:      ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
816; 32R6-DAG:      lw $[[D3:[0-9]+]], %got(d3)($1)
817; 32R6-DAG:      ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
818; 32R6:          cmp.lt.d $[[CC:f[0-9]+]], $[[TMP1]], $[[TMP]]
819; 32R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
820; 32R6:          andi $[[CCGPR]], $[[CCGPR]], 1
821; 32R6:          seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
822; 32R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
823; 32R6:          or $2, $[[NE]], $[[EQ]]
824
825; 64-DAG:        daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
826; 64-DAG:        daddu $[[GOT:[0-9]+]], $[[T0]], $25
827; 64-DAG:        ld $[[D2:[0-9]+]], %got_disp(d2)($1)
828; 64-DAG:        ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
829; 64-DAG:        ld $[[D3:[0-9]+]], %got_disp(d3)($1)
830; 64-DAG:        ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
831; 64:            c.ule.d $[[TMP]], $[[TMP1]]
832; 64:            movf $5, $4, $fcc0
833; 64:            move $2, $5
834
835; 64R2-DAG:      daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
836; 64R2-DAG:      daddu $[[GOT:[0-9]+]], $[[T0]], $25
837; 64R2-DAG:      ld $[[D2:[0-9]+]], %got_disp(d2)($1)
838; 64R2-DAG:      ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
839; 64R2-DAG:      ld $[[D3:[0-9]+]], %got_disp(d3)($1)
840; 64R2-DAG:      ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
841; 64R2:          c.ule.d $[[TMP]], $[[TMP1]]
842; 64R2:          movf $5, $4, $fcc0
843; 64R2:          move $2, $5
844
845; 64R6-DAG:      daddiu $[[T0:[0-9]+]], ${{[0-9]+}}, %lo(%neg(%gp_rel(f64_fcmp_ogt_i32_val)))
846; 64R6-DAG:      daddu $[[GOT:[0-9]+]], $[[T0]], $25
847; 64R6-DAG:      ld $[[D2:[0-9]+]], %got_disp(d2)($1)
848; 64R6-DAG:      ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
849; 64R6-DAG:      ld $[[D3:[0-9]+]], %got_disp(d3)($1)
850; 64R6-DAG:      ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
851; 64R6:          cmp.lt.d $[[CC:f[0-9]+]], $[[TMP1]], $[[TMP]]
852; 64R6:          mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
853; 64R6:          andi $[[CCGPR]], $[[CCGPR]], 1
854; 64R6:          seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
855; 64R6:          selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
856; 64R6:          or $2, $[[NE]], $[[EQ]]
857
858  %tmp = load double, double* @d2, align 8
859  %tmp1 = load double, double* @d3, align 8
860  %cmp = fcmp ogt double %tmp, %tmp1
861  %cond = select i1 %cmp, i32 %f0, i32 %f1
862  ret i32 %cond
863}
864