1; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 2 3declare <4 x float> @llvm.mips.fmax.w(<4 x float>, <4 x float>) nounwind 4declare <2 x double> @llvm.mips.fmax.d(<2 x double>, <2 x double>) nounwind 5declare <4 x float> @llvm.mips.fmin.w(<4 x float>, <4 x float>) nounwind 6declare <2 x double> @llvm.mips.fmin.d(<2 x double>, <2 x double>) nounwind 7 8define void @false_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 9 ; CHECK: false_v4f32: 10 11 %1 = load <4 x float>* %a 12 %2 = load <4 x float>* %b 13 %3 = fcmp false <4 x float> %1, %2 14 %4 = sext <4 x i1> %3 to <4 x i32> 15 store <4 x i32> %4, <4 x i32>* %c 16 ret void 17 18 ; (setcc $a, $b, SETFALSE) is always folded, so we won't get fcaf: 19 ; CHECK-DAG: ldi.b [[R1:\$w[0-9]+]], 0 20 ; CHECK-DAG: st.w [[R1]], 0($4) 21 ; CHECK: .size false_v4f32 22} 23 24define void @false_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 25 ; CHECK: false_v2f64: 26 27 %1 = load <2 x double>* %a 28 %2 = load <2 x double>* %b 29 %3 = fcmp false <2 x double> %1, %2 30 %4 = sext <2 x i1> %3 to <2 x i64> 31 store <2 x i64> %4, <2 x i64>* %c 32 ret void 33 34 ; FIXME: This code is correct, but poor. Ideally it would be similar to 35 ; the code in @false_v4f32 36 ; CHECK-DAG: ldi.b [[R1:\$w[0-9]+]], 0 37 ; CHECK-DAG: slli.d [[R3:\$w[0-9]+]], [[R1]], 63 38 ; CHECK-DAG: srai.d [[R4:\$w[0-9]+]], [[R3]], 63 39 ; CHECK-DAG: st.d [[R4]], 0($4) 40 ; CHECK: .size false_v2f64 41} 42 43define void @oeq_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 44 ; CHECK: oeq_v4f32: 45 46 %1 = load <4 x float>* %a 47 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 48 %2 = load <4 x float>* %b 49 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 50 %3 = fcmp oeq <4 x float> %1, %2 51 %4 = sext <4 x i1> %3 to <4 x i32> 52 ; CHECK-DAG: fceq.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 53 store <4 x i32> %4, <4 x i32>* %c 54 ; CHECK-DAG: st.w [[R3]], 0($4) 55 56 ret void 57 ; CHECK: .size oeq_v4f32 58} 59 60define void @oeq_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 61 ; CHECK: oeq_v2f64: 62 63 %1 = load <2 x double>* %a 64 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 65 %2 = load <2 x double>* %b 66 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 67 %3 = fcmp oeq <2 x double> %1, %2 68 %4 = sext <2 x i1> %3 to <2 x i64> 69 ; CHECK-DAG: fceq.d [[R3:\$w[0-9]+]], [[R1]], [[R2]] 70 store <2 x i64> %4, <2 x i64>* %c 71 ; CHECK-DAG: st.d [[R3]], 0($4) 72 73 ret void 74 ; CHECK: .size oeq_v2f64 75} 76 77define void @oge_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 78 ; CHECK: oge_v4f32: 79 80 %1 = load <4 x float>* %a 81 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 82 %2 = load <4 x float>* %b 83 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 84 %3 = fcmp oge <4 x float> %1, %2 85 %4 = sext <4 x i1> %3 to <4 x i32> 86 ; CHECK-DAG: fcle.w [[R3:\$w[0-9]+]], [[R2]], [[R1]] 87 store <4 x i32> %4, <4 x i32>* %c 88 ; CHECK-DAG: st.w [[R3]], 0($4) 89 90 ret void 91 ; CHECK: .size oge_v4f32 92} 93 94define void @oge_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 95 ; CHECK: oge_v2f64: 96 97 %1 = load <2 x double>* %a 98 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 99 %2 = load <2 x double>* %b 100 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 101 %3 = fcmp oge <2 x double> %1, %2 102 %4 = sext <2 x i1> %3 to <2 x i64> 103 ; CHECK-DAG: fcle.d [[R3:\$w[0-9]+]], [[R2]], [[R1]] 104 store <2 x i64> %4, <2 x i64>* %c 105 ; CHECK-DAG: st.d [[R3]], 0($4) 106 107 ret void 108 ; CHECK: .size oge_v2f64 109} 110 111define void @ogt_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 112 ; CHECK: ogt_v4f32: 113 114 %1 = load <4 x float>* %a 115 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 116 %2 = load <4 x float>* %b 117 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 118 %3 = fcmp ogt <4 x float> %1, %2 119 %4 = sext <4 x i1> %3 to <4 x i32> 120 ; CHECK-DAG: fclt.w [[R3:\$w[0-9]+]], [[R2]], [[R1]] 121 store <4 x i32> %4, <4 x i32>* %c 122 ; CHECK-DAG: st.w [[R3]], 0($4) 123 124 ret void 125 ; CHECK: .size ogt_v4f32 126} 127 128define void @ogt_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 129 ; CHECK: ogt_v2f64: 130 131 %1 = load <2 x double>* %a 132 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 133 %2 = load <2 x double>* %b 134 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 135 %3 = fcmp ogt <2 x double> %1, %2 136 %4 = sext <2 x i1> %3 to <2 x i64> 137 ; CHECK-DAG: fclt.d [[R3:\$w[0-9]+]], [[R2]], [[R1]] 138 store <2 x i64> %4, <2 x i64>* %c 139 ; CHECK-DAG: st.d [[R3]], 0($4) 140 141 ret void 142 ; CHECK: .size ogt_v2f64 143} 144 145define void @ole_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 146 ; CHECK: ole_v4f32: 147 148 %1 = load <4 x float>* %a 149 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 150 %2 = load <4 x float>* %b 151 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 152 %3 = fcmp ole <4 x float> %1, %2 153 %4 = sext <4 x i1> %3 to <4 x i32> 154 ; CHECK-DAG: fcle.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 155 store <4 x i32> %4, <4 x i32>* %c 156 ; CHECK-DAG: st.w [[R3]], 0($4) 157 158 ret void 159 ; CHECK: .size ole_v4f32 160} 161 162define void @ole_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 163 ; CHECK: ole_v2f64: 164 165 %1 = load <2 x double>* %a 166 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 167 %2 = load <2 x double>* %b 168 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 169 %3 = fcmp ole <2 x double> %1, %2 170 %4 = sext <2 x i1> %3 to <2 x i64> 171 ; CHECK-DAG: fcle.d [[R3:\$w[0-9]+]], [[R1]], [[R2]] 172 store <2 x i64> %4, <2 x i64>* %c 173 ; CHECK-DAG: st.d [[R3]], 0($4) 174 175 ret void 176 ; CHECK: .size ole_v2f64 177} 178 179define void @olt_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 180 ; CHECK: olt_v4f32: 181 182 %1 = load <4 x float>* %a 183 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 184 %2 = load <4 x float>* %b 185 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 186 %3 = fcmp olt <4 x float> %1, %2 187 %4 = sext <4 x i1> %3 to <4 x i32> 188 ; CHECK-DAG: fclt.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 189 store <4 x i32> %4, <4 x i32>* %c 190 ; CHECK-DAG: st.w [[R3]], 0($4) 191 192 ret void 193 ; CHECK: .size olt_v4f32 194} 195 196define void @olt_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 197 ; CHECK: olt_v2f64: 198 199 %1 = load <2 x double>* %a 200 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 201 %2 = load <2 x double>* %b 202 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 203 %3 = fcmp olt <2 x double> %1, %2 204 %4 = sext <2 x i1> %3 to <2 x i64> 205 ; CHECK-DAG: fclt.d [[R3:\$w[0-9]+]], [[R1]], [[R2]] 206 store <2 x i64> %4, <2 x i64>* %c 207 ; CHECK-DAG: st.d [[R3]], 0($4) 208 209 ret void 210 ; CHECK: .size olt_v2f64 211} 212 213define void @one_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 214 ; CHECK: one_v4f32: 215 216 %1 = load <4 x float>* %a 217 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 218 %2 = load <4 x float>* %b 219 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 220 %3 = fcmp one <4 x float> %1, %2 221 %4 = sext <4 x i1> %3 to <4 x i32> 222 ; CHECK-DAG: fcne.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 223 store <4 x i32> %4, <4 x i32>* %c 224 ; CHECK-DAG: st.w [[R3]], 0($4) 225 226 ret void 227 ; CHECK: .size one_v4f32 228} 229 230define void @one_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 231 ; CHECK: one_v2f64: 232 233 %1 = load <2 x double>* %a 234 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 235 %2 = load <2 x double>* %b 236 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 237 %3 = fcmp one <2 x double> %1, %2 238 %4 = sext <2 x i1> %3 to <2 x i64> 239 ; CHECK-DAG: fcne.d [[R3:\$w[0-9]+]], [[R1]], [[R2]] 240 store <2 x i64> %4, <2 x i64>* %c 241 ; CHECK-DAG: st.d [[R3]], 0($4) 242 243 ret void 244 ; CHECK: .size one_v2f64 245} 246 247define void @ord_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 248 ; CHECK: ord_v4f32: 249 250 %1 = load <4 x float>* %a 251 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 252 %2 = load <4 x float>* %b 253 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 254 %3 = fcmp ord <4 x float> %1, %2 255 %4 = sext <4 x i1> %3 to <4 x i32> 256 ; CHECK-DAG: fcor.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 257 store <4 x i32> %4, <4 x i32>* %c 258 ; CHECK-DAG: st.w [[R3]], 0($4) 259 260 ret void 261 ; CHECK: .size ord_v4f32 262} 263 264define void @ord_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 265 ; CHECK: ord_v2f64: 266 267 %1 = load <2 x double>* %a 268 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 269 %2 = load <2 x double>* %b 270 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 271 %3 = fcmp ord <2 x double> %1, %2 272 %4 = sext <2 x i1> %3 to <2 x i64> 273 ; CHECK-DAG: fcor.d [[R3:\$w[0-9]+]], [[R1]], [[R2]] 274 store <2 x i64> %4, <2 x i64>* %c 275 ; CHECK-DAG: st.d [[R3]], 0($4) 276 277 ret void 278 ; CHECK: .size ord_v2f64 279} 280 281define void @ueq_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 282 ; CHECK: ueq_v4f32: 283 284 %1 = load <4 x float>* %a 285 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 286 %2 = load <4 x float>* %b 287 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 288 %3 = fcmp ueq <4 x float> %1, %2 289 %4 = sext <4 x i1> %3 to <4 x i32> 290 ; CHECK-DAG: fcueq.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 291 store <4 x i32> %4, <4 x i32>* %c 292 ; CHECK-DAG: st.w [[R3]], 0($4) 293 294 ret void 295 ; CHECK: .size ueq_v4f32 296} 297 298define void @ueq_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 299 ; CHECK: ueq_v2f64: 300 301 %1 = load <2 x double>* %a 302 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 303 %2 = load <2 x double>* %b 304 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 305 %3 = fcmp ueq <2 x double> %1, %2 306 %4 = sext <2 x i1> %3 to <2 x i64> 307 ; CHECK-DAG: fcueq.d [[R3:\$w[0-9]+]], [[R1]], [[R2]] 308 store <2 x i64> %4, <2 x i64>* %c 309 ; CHECK-DAG: st.d [[R3]], 0($4) 310 311 ret void 312 ; CHECK: .size ueq_v2f64 313} 314 315define void @uge_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 316 ; CHECK: uge_v4f32: 317 318 %1 = load <4 x float>* %a 319 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 320 %2 = load <4 x float>* %b 321 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 322 %3 = fcmp uge <4 x float> %1, %2 323 %4 = sext <4 x i1> %3 to <4 x i32> 324 ; CHECK-DAG: fcule.w [[R3:\$w[0-9]+]], [[R2]], [[R1]] 325 store <4 x i32> %4, <4 x i32>* %c 326 ; CHECK-DAG: st.w [[R3]], 0($4) 327 328 ret void 329 ; CHECK: .size uge_v4f32 330} 331 332define void @uge_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 333 ; CHECK: uge_v2f64: 334 335 %1 = load <2 x double>* %a 336 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 337 %2 = load <2 x double>* %b 338 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 339 %3 = fcmp uge <2 x double> %1, %2 340 %4 = sext <2 x i1> %3 to <2 x i64> 341 ; CHECK-DAG: fcule.d [[R3:\$w[0-9]+]], [[R2]], [[R1]] 342 store <2 x i64> %4, <2 x i64>* %c 343 ; CHECK-DAG: st.d [[R3]], 0($4) 344 345 ret void 346 ; CHECK: .size uge_v2f64 347} 348 349define void @ugt_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 350 ; CHECK: ugt_v4f32: 351 352 %1 = load <4 x float>* %a 353 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 354 %2 = load <4 x float>* %b 355 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 356 %3 = fcmp ugt <4 x float> %1, %2 357 %4 = sext <4 x i1> %3 to <4 x i32> 358 ; CHECK-DAG: fcult.w [[R3:\$w[0-9]+]], [[R2]], [[R1]] 359 store <4 x i32> %4, <4 x i32>* %c 360 ; CHECK-DAG: st.w [[R3]], 0($4) 361 362 ret void 363 ; CHECK: .size ugt_v4f32 364} 365 366define void @ugt_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 367 ; CHECK: ugt_v2f64: 368 369 %1 = load <2 x double>* %a 370 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 371 %2 = load <2 x double>* %b 372 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 373 %3 = fcmp ugt <2 x double> %1, %2 374 %4 = sext <2 x i1> %3 to <2 x i64> 375 ; CHECK-DAG: fcult.d [[R3:\$w[0-9]+]], [[R2]], [[R1]] 376 store <2 x i64> %4, <2 x i64>* %c 377 ; CHECK-DAG: st.d [[R3]], 0($4) 378 379 ret void 380 ; CHECK: .size ugt_v2f64 381} 382 383define void @ule_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 384 ; CHECK: ule_v4f32: 385 386 %1 = load <4 x float>* %a 387 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 388 %2 = load <4 x float>* %b 389 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 390 %3 = fcmp ule <4 x float> %1, %2 391 %4 = sext <4 x i1> %3 to <4 x i32> 392 ; CHECK-DAG: fcule.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 393 store <4 x i32> %4, <4 x i32>* %c 394 ; CHECK-DAG: st.w [[R3]], 0($4) 395 396 ret void 397 ; CHECK: .size ule_v4f32 398} 399 400define void @ule_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 401 ; CHECK: ule_v2f64: 402 403 %1 = load <2 x double>* %a 404 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 405 %2 = load <2 x double>* %b 406 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 407 %3 = fcmp ule <2 x double> %1, %2 408 %4 = sext <2 x i1> %3 to <2 x i64> 409 ; CHECK-DAG: fcule.d [[R3:\$w[0-9]+]], [[R1]], [[R2]] 410 store <2 x i64> %4, <2 x i64>* %c 411 ; CHECK-DAG: st.d [[R3]], 0($4) 412 413 ret void 414 ; CHECK: .size ule_v2f64 415} 416 417define void @ult_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 418 ; CHECK: ult_v4f32: 419 420 %1 = load <4 x float>* %a 421 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 422 %2 = load <4 x float>* %b 423 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 424 %3 = fcmp ult <4 x float> %1, %2 425 %4 = sext <4 x i1> %3 to <4 x i32> 426 ; CHECK-DAG: fcult.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 427 store <4 x i32> %4, <4 x i32>* %c 428 ; CHECK-DAG: st.w [[R3]], 0($4) 429 430 ret void 431 ; CHECK: .size ult_v4f32 432} 433 434define void @ult_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 435 ; CHECK: ult_v2f64: 436 437 %1 = load <2 x double>* %a 438 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 439 %2 = load <2 x double>* %b 440 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 441 %3 = fcmp ult <2 x double> %1, %2 442 %4 = sext <2 x i1> %3 to <2 x i64> 443 ; CHECK-DAG: fcult.d [[R3:\$w[0-9]+]], [[R1]], [[R2]] 444 store <2 x i64> %4, <2 x i64>* %c 445 ; CHECK-DAG: st.d [[R3]], 0($4) 446 447 ret void 448 ; CHECK: .size ult_v2f64 449} 450 451define void @uno_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 452 ; CHECK: uno_v4f32: 453 454 %1 = load <4 x float>* %a 455 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 456 %2 = load <4 x float>* %b 457 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 458 %3 = fcmp uno <4 x float> %1, %2 459 %4 = sext <4 x i1> %3 to <4 x i32> 460 ; CHECK-DAG: fcun.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 461 store <4 x i32> %4, <4 x i32>* %c 462 ; CHECK-DAG: st.w [[R3]], 0($4) 463 464 ret void 465 ; CHECK: .size uno_v4f32 466} 467 468define void @uno_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 469 ; CHECK: uno_v2f64: 470 471 %1 = load <2 x double>* %a 472 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 473 %2 = load <2 x double>* %b 474 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 475 %3 = fcmp uno <2 x double> %1, %2 476 %4 = sext <2 x i1> %3 to <2 x i64> 477 ; CHECK-DAG: fcun.d [[R3:\$w[0-9]+]], [[R1]], [[R2]] 478 store <2 x i64> %4, <2 x i64>* %c 479 ; CHECK-DAG: st.d [[R3]], 0($4) 480 481 ret void 482 ; CHECK: .size uno_v2f64 483} 484 485define void @true_v4f32(<4 x i32>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 486 ; CHECK: true_v4f32: 487 488 %1 = load <4 x float>* %a 489 %2 = load <4 x float>* %b 490 %3 = fcmp true <4 x float> %1, %2 491 %4 = sext <4 x i1> %3 to <4 x i32> 492 store <4 x i32> %4, <4 x i32>* %c 493 ret void 494 495 ; (setcc $a, $b, SETTRUE) is always folded, so we won't get fcaf: 496 ; CHECK-DAG: ldi.b [[R1:\$w[0-9]+]], -1 497 ; CHECK-DAG: st.w [[R1]], 0($4) 498 ; CHECK: .size true_v4f32 499} 500 501define void @true_v2f64(<2 x i64>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 502 ; CHECK: true_v2f64: 503 504 %1 = load <2 x double>* %a 505 %2 = load <2 x double>* %b 506 %3 = fcmp true <2 x double> %1, %2 507 %4 = sext <2 x i1> %3 to <2 x i64> 508 store <2 x i64> %4, <2 x i64>* %c 509 ret void 510 511 ; FIXME: This code is correct, but poor. Ideally it would be similar to 512 ; the code in @true_v4f32 513 ; CHECK-DAG: ldi.d [[R1:\$w[0-9]+]], 1 514 ; CHECK-DAG: slli.d [[R3:\$w[0-9]+]], [[R1]], 63 515 ; CHECK-DAG: srai.d [[R4:\$w[0-9]+]], [[R3]], 63 516 ; CHECK-DAG: st.d [[R4]], 0($4) 517 ; CHECK: .size true_v2f64 518} 519 520define void @bsel_v4f32(<4 x float>* %d, <4 x float>* %a, <4 x float>* %b, 521 <4 x float>* %c) nounwind { 522 ; CHECK: bsel_v4f32: 523 524 %1 = load <4 x float>* %a 525 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 526 %2 = load <4 x float>* %b 527 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 528 %3 = load <4 x float>* %c 529 ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7) 530 %4 = fcmp ogt <4 x float> %1, %2 531 ; CHECK-DAG: fclt.w [[R4:\$w[0-9]+]], [[R2]], [[R1]] 532 %5 = select <4 x i1> %4, <4 x float> %1, <4 x float> %3 533 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]] 534 store <4 x float> %5, <4 x float>* %d 535 ; CHECK-DAG: st.w [[R4]], 0($4) 536 537 ret void 538 ; CHECK: .size bsel_v4f32 539} 540 541define void @bsel_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b, 542 <2 x double>* %c) nounwind { 543 ; CHECK: bsel_v2f64: 544 545 %1 = load <2 x double>* %a 546 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 547 %2 = load <2 x double>* %b 548 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 549 %3 = load <2 x double>* %c 550 ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7) 551 %4 = fcmp ogt <2 x double> %1, %2 552 ; CHECK-DAG: fclt.d [[R4:\$w[0-9]+]], [[R2]], [[R1]] 553 %5 = select <2 x i1> %4, <2 x double> %1, <2 x double> %3 554 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3]] 555 store <2 x double> %5, <2 x double>* %d 556 ; CHECK-DAG: st.d [[R4]], 0($4) 557 558 ret void 559 ; CHECK: .size bsel_v2f64 560} 561 562define void @bseli_v4f32(<4 x float>* %d, <4 x float>* %a, <4 x float>* %b, 563 <4 x float>* %c) nounwind { 564 ; CHECK: bseli_v4f32: 565 566 %1 = load <4 x float>* %a 567 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 568 %2 = load <4 x float>* %b 569 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 570 %3 = fcmp ogt <4 x float> %1, %2 571 ; CHECK-DAG: fclt.w [[R4:\$w[0-9]+]], [[R2]], [[R1]] 572 %4 = select <4 x i1> %3, <4 x float> %1, <4 x float> zeroinitializer 573 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3:\$w[0-9]+]] 574 store <4 x float> %4, <4 x float>* %d 575 ; CHECK-DAG: st.w [[R4]], 0($4) 576 577 ret void 578 ; CHECK: .size bseli_v4f32 579} 580 581define void @bseli_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b, 582 <2 x double>* %c) nounwind { 583 ; CHECK: bseli_v2f64: 584 585 %1 = load <2 x double>* %a 586 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 587 %2 = load <2 x double>* %b 588 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 589 %3 = fcmp ogt <2 x double> %1, %2 590 ; CHECK-DAG: fclt.d [[R4:\$w[0-9]+]], [[R2]], [[R1]] 591 %4 = select <2 x i1> %3, <2 x double> %1, <2 x double> zeroinitializer 592 ; CHECK-DAG: bsel.v [[R4]], [[R1]], [[R3:\$w[0-9]+]] 593 store <2 x double> %4, <2 x double>* %d 594 ; CHECK-DAG: st.d [[R4]], 0($4) 595 596 ret void 597 ; CHECK: .size bseli_v2f64 598} 599 600define void @max_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 601 ; CHECK: max_v4f32: 602 603 %1 = load <4 x float>* %a 604 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 605 %2 = load <4 x float>* %b 606 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 607 %3 = tail call <4 x float> @llvm.mips.fmax.w(<4 x float> %1, <4 x float> %2) 608 ; CHECK-DAG: fmax.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 609 store <4 x float> %3, <4 x float>* %c 610 ; CHECK-DAG: st.w [[R3]], 0($4) 611 612 ret void 613 ; CHECK: .size max_v4f32 614} 615 616define void @max_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 617 ; CHECK: max_v2f64: 618 619 %1 = load <2 x double>* %a 620 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 621 %2 = load <2 x double>* %b 622 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 623 %3 = tail call <2 x double> @llvm.mips.fmax.d(<2 x double> %1, <2 x double> %2) 624 ; CHECK-DAG: fmax.d [[R3:\$w[0-9]+]], [[R1]], [[R2]] 625 store <2 x double> %3, <2 x double>* %c 626 ; CHECK-DAG: st.d [[R3]], 0($4) 627 628 ret void 629 ; CHECK: .size max_v2f64 630} 631 632define void @min_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 633 ; CHECK: min_v4f32: 634 635 %1 = load <4 x float>* %a 636 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 637 %2 = load <4 x float>* %b 638 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 639 %3 = tail call <4 x float> @llvm.mips.fmin.w(<4 x float> %1, <4 x float> %2) 640 ; CHECK-DAG: fmin.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 641 store <4 x float> %3, <4 x float>* %c 642 ; CHECK-DAG: st.w [[R3]], 0($4) 643 644 ret void 645 ; CHECK: .size min_v4f32 646} 647 648define void @min_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 649 ; CHECK: min_v2f64: 650 651 %1 = load <2 x double>* %a 652 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 653 %2 = load <2 x double>* %b 654 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 655 %3 = tail call <2 x double> @llvm.mips.fmin.d(<2 x double> %1, <2 x double> %2) 656 ; CHECK-DAG: fmin.d [[R3:\$w[0-9]+]], [[R1]], [[R2]] 657 store <2 x double> %3, <2 x double>* %c 658 ; CHECK-DAG: st.d [[R3]], 0($4) 659 660 ret void 661 ; CHECK: .size min_v2f64 662} 663