1; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s
2
3@v4f32 = global <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>
4@v2f64 = global <2 x double> <double 0.0, double 0.0>
5
6define void @const_v4f32() nounwind {
7  ; MIPS32: const_v4f32:
8
9  store volatile <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>, <4 x float>*@v4f32
10  ; MIPS32: ld.w  [[R1:\$w[0-9]+]], %lo(
11
12  store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float>*@v4f32
13  ; MIPS32: ld.w  [[R1:\$w[0-9]+]], %lo(
14
15  store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 31.0>, <4 x float>*@v4f32
16  ; MIPS32: ld.w  [[R1:\$w[0-9]+]], %lo(
17
18  store volatile <4 x float> <float 65537.0, float 65537.0, float 65537.0, float 65537.0>, <4 x float>*@v4f32
19  ; MIPS32: ld.w  [[R1:\$w[0-9]+]], %lo(
20
21  store volatile <4 x float> <float 1.0, float 2.0, float 1.0, float 2.0>, <4 x float>*@v4f32
22  ; MIPS32: ld.w  [[R1:\$w[0-9]+]], %lo(
23
24  store volatile <4 x float> <float 3.0, float 4.0, float 5.0, float 6.0>, <4 x float>*@v4f32
25  ; MIPS32: ld.w  [[R1:\$w[0-9]+]], %lo(
26
27  ret void
28  ; MIPS32: .size const_v4f32
29}
30
31define void @const_v2f64() nounwind {
32  ; MIPS32: const_v2f64:
33
34  store volatile <2 x double> <double 0.0, double 0.0>, <2 x double>*@v2f64
35  ; MIPS32: ld.d  [[R1:\$w[0-9]+]], %lo(
36
37  store volatile <2 x double> <double 72340172838076673.0, double 72340172838076673.0>, <2 x double>*@v2f64
38  ; MIPS32: ld.d  [[R1:\$w[0-9]+]], %lo(
39
40  store volatile <2 x double> <double 281479271743489.0, double 281479271743489.0>, <2 x double>*@v2f64
41  ; MIPS32: ld.d  [[R1:\$w[0-9]+]], %lo(
42
43  store volatile <2 x double> <double 4294967297.0, double 4294967297.0>, <2 x double>*@v2f64
44  ; MIPS32: ld.d  [[R1:\$w[0-9]+]], %lo(
45
46  store volatile <2 x double> <double 1.0, double 1.0>, <2 x double>*@v2f64
47  ; MIPS32: ld.d  [[R1:\$w[0-9]+]], %lo(
48
49  store volatile <2 x double> <double 1.0, double 31.0>, <2 x double>*@v2f64
50  ; MIPS32: ld.d  [[R1:\$w[0-9]+]], %lo(
51
52  store volatile <2 x double> <double 3.0, double 4.0>, <2 x double>*@v2f64
53  ; MIPS32: ld.d  [[R1:\$w[0-9]+]], %lo(
54
55  ret void
56  ; MIPS32: .size const_v2f64
57}
58
59define float @extract_v4f32() nounwind {
60  ; MIPS32: extract_v4f32:
61
62  %1 = load <4 x float>* @v4f32
63  ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
64
65  %2 = fadd <4 x float> %1, %1
66  ; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
67
68  %3 = extractelement <4 x float> %2, i32 1
69  ; Element 1 can be obtained by splatting it across the vector and extracting
70  ; $w0:sub_lo
71  ; MIPS32-DAG: splati.w $w0, [[R1]][1]
72
73  ret float %3
74  ; MIPS32: .size extract_v4f32
75}
76
77define float @extract_v4f32_elt0() nounwind {
78  ; MIPS32: extract_v4f32_elt0:
79
80  %1 = load <4 x float>* @v4f32
81  ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
82
83  %2 = fadd <4 x float> %1, %1
84  ; MIPS32-DAG: fadd.w $w0, [[R1]], [[R1]]
85
86  %3 = extractelement <4 x float> %2, i32 0
87  ; Element 0 can be obtained by extracting $w0:sub_lo ($f0)
88  ; MIPS32-NOT: copy_u.w
89  ; MIPS32-NOT: mtc1
90
91  ret float %3
92  ; MIPS32: .size extract_v4f32_elt0
93}
94
95define double @extract_v2f64() nounwind {
96  ; MIPS32: extract_v2f64:
97
98  %1 = load <2 x double>* @v2f64
99  ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
100
101  %2 = fadd <2 x double> %1, %1
102  ; MIPS32-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
103
104  %3 = extractelement <2 x double> %2, i32 1
105  ; Element 1 can be obtained by splatting it across the vector and extracting
106  ; $w0:sub_64
107  ; MIPS32-DAG: splati.d $w0, [[R1]][1]
108  ; MIPS32-NOT: copy_u.w
109  ; MIPS32-NOT: mtc1
110  ; MIPS32-NOT: mthc1
111  ; MIPS32-NOT: sll
112  ; MIPS32-NOT: sra
113
114  ret double %3
115  ; MIPS32: .size extract_v2f64
116}
117
118define double @extract_v2f64_elt0() nounwind {
119  ; MIPS32: extract_v2f64_elt0:
120
121  %1 = load <2 x double>* @v2f64
122  ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
123
124  %2 = fadd <2 x double> %1, %1
125  ; MIPS32-DAG: fadd.d $w0, [[R1]], [[R1]]
126
127  %3 = extractelement <2 x double> %2, i32 0
128  ; Element 0 can be obtained by extracting $w0:sub_64 ($f0)
129  ; MIPS32-NOT: copy_u.w
130  ; MIPS32-NOT: mtc1
131  ; MIPS32-NOT: mthc1
132  ; MIPS32-NOT: sll
133  ; MIPS32-NOT: sra
134
135  ret double %3
136  ; MIPS32: .size extract_v2f64_elt0
137}
138
139define void @insert_v4f32(float %a) nounwind {
140  ; MIPS32: insert_v4f32:
141
142  %1 = load <4 x float>* @v4f32
143  ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
144
145  %2 = insertelement <4 x float> %1, float %a, i32 1
146  ; float argument passed in $f12
147  ; MIPS32-DAG: insve.w [[R1]][1], $w12[0]
148
149  store <4 x float> %2, <4 x float>* @v4f32
150  ; MIPS32-DAG: st.w [[R1]]
151
152  ret void
153  ; MIPS32: .size insert_v4f32
154}
155
156define void @insert_v2f64(double %a) nounwind {
157  ; MIPS32: insert_v2f64:
158
159  %1 = load <2 x double>* @v2f64
160  ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
161
162  %2 = insertelement <2 x double> %1, double %a, i32 1
163  ; double argument passed in $f12
164  ; MIPS32-DAG: insve.d [[R1]][1], $w12[0]
165
166  store <2 x double> %2, <2 x double>* @v2f64
167  ; MIPS32-DAG: st.d [[R1]]
168
169  ret void
170  ; MIPS32: .size insert_v2f64
171}
172