1; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s
2; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s
3
4@v4f32 = global <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>
5@v2f64 = global <2 x double> <double 0.0, double 0.0>
6@f32 = global float 0.0
7@f64 = global double 0.0
8
9define void @const_v4f32() nounwind {
10  ; MIPS32: const_v4f32:
11
12  store volatile <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>, <4 x float>*@v4f32
13  ; MIPS32: ldi.b  [[R1:\$w[0-9]+]], 0
14
15  store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float>*@v4f32
16  ; MIPS32: lui     [[R1:\$[0-9]+]], 16256
17  ; MIPS32: fill.w  [[R2:\$w[0-9]+]], [[R1]]
18
19  store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 31.0>, <4 x float>*@v4f32
20  ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
21  ; MIPS32: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
22
23  store volatile <4 x float> <float 65537.0, float 65537.0, float 65537.0, float 65537.0>, <4 x float>*@v4f32
24  ; MIPS32: lui     [[R1:\$[0-9]+]], 18304
25  ; MIPS32: ori     [[R2:\$[0-9]+]], [[R1]], 128
26  ; MIPS32: fill.w  [[R3:\$w[0-9]+]], [[R2]]
27
28  store volatile <4 x float> <float 1.0, float 2.0, float 1.0, float 2.0>, <4 x float>*@v4f32
29  ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
30  ; MIPS32: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
31
32  store volatile <4 x float> <float 3.0, float 4.0, float 5.0, float 6.0>, <4 x float>*@v4f32
33  ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
34  ; MIPS32: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
35
36  ret void
37  ; MIPS32: .size const_v4f32
38}
39
40define void @const_v2f64() nounwind {
41  ; MIPS32: const_v2f64:
42
43  store volatile <2 x double> <double 0.0, double 0.0>, <2 x double>*@v2f64
44  ; MIPS32: ldi.b  [[R1:\$w[0-9]+]], 0
45
46  store volatile <2 x double> <double 72340172838076673.0, double 72340172838076673.0>, <2 x double>*@v2f64
47  ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
48  ; MIPS32: ld.d  [[R1:\$w[0-9]+]], 0([[G_PTR]])
49
50  store volatile <2 x double> <double 281479271743489.0, double 281479271743489.0>, <2 x double>*@v2f64
51  ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
52  ; MIPS32: ld.d  [[R1:\$w[0-9]+]], 0([[G_PTR]])
53
54  store volatile <2 x double> <double 4294967297.0, double 4294967297.0>, <2 x double>*@v2f64
55  ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
56  ; MIPS32: ld.d  [[R1:\$w[0-9]+]], 0([[G_PTR]])
57
58  store volatile <2 x double> <double 1.0, double 1.0>, <2 x double>*@v2f64
59  ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
60  ; MIPS32: ld.d  [[R1:\$w[0-9]+]], 0([[G_PTR]])
61
62  store volatile <2 x double> <double 1.0, double 31.0>, <2 x double>*@v2f64
63  ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
64  ; MIPS32: ld.d  [[R1:\$w[0-9]+]], 0([[G_PTR]])
65
66  store volatile <2 x double> <double 3.0, double 4.0>, <2 x double>*@v2f64
67  ; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
68  ; MIPS32: ld.d  [[R1:\$w[0-9]+]], 0([[G_PTR]])
69
70  ret void
71  ; MIPS32: .size const_v2f64
72}
73
74define void @nonconst_v4f32() nounwind {
75  ; MIPS32: nonconst_v4f32:
76
77  %1 = load float *@f32
78  %2 = insertelement <4 x float> undef, float %1, i32 0
79  %3 = insertelement <4 x float> %2, float %1, i32 1
80  %4 = insertelement <4 x float> %3, float %1, i32 2
81  %5 = insertelement <4 x float> %4, float %1, i32 3
82  store volatile <4 x float> %5, <4 x float>*@v4f32
83  ; MIPS32: lwc1 $f[[R1:[0-9]+]], 0(
84  ; MIPS32: splati.w [[R2:\$w[0-9]+]], $w[[R1]]
85
86  ret void
87  ; MIPS32: .size nonconst_v4f32
88}
89
90define void @nonconst_v2f64() nounwind {
91  ; MIPS32: nonconst_v2f64:
92
93  %1 = load double *@f64
94  %2 = insertelement <2 x double> undef, double %1, i32 0
95  %3 = insertelement <2 x double> %2, double %1, i32 1
96  store volatile <2 x double> %3, <2 x double>*@v2f64
97  ; MIPS32: ldc1 $f[[R1:[0-9]+]], 0(
98  ; MIPS32: splati.d [[R2:\$w[0-9]+]], $w[[R1]]
99
100  ret void
101  ; MIPS32: .size nonconst_v2f64
102}
103
104define float @extract_v4f32() nounwind {
105  ; MIPS32: extract_v4f32:
106
107  %1 = load <4 x float>* @v4f32
108  ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
109
110  %2 = fadd <4 x float> %1, %1
111  ; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
112
113  %3 = extractelement <4 x float> %2, i32 1
114  ; Element 1 can be obtained by splatting it across the vector and extracting
115  ; $w0:sub_lo
116  ; MIPS32-DAG: splati.w $w0, [[R1]][1]
117
118  ret float %3
119  ; MIPS32: .size extract_v4f32
120}
121
122define float @extract_v4f32_elt0() nounwind {
123  ; MIPS32: extract_v4f32_elt0:
124
125  %1 = load <4 x float>* @v4f32
126  ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
127
128  %2 = fadd <4 x float> %1, %1
129  ; MIPS32-DAG: fadd.w $w0, [[R1]], [[R1]]
130
131  %3 = extractelement <4 x float> %2, i32 0
132  ; Element 0 can be obtained by extracting $w0:sub_lo ($f0)
133  ; MIPS32-NOT: copy_u.w
134  ; MIPS32-NOT: mtc1
135
136  ret float %3
137  ; MIPS32: .size extract_v4f32_elt0
138}
139
140define float @extract_v4f32_elt2() nounwind {
141  ; MIPS32: extract_v4f32_elt2:
142
143  %1 = load <4 x float>* @v4f32
144  ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
145
146  %2 = fadd <4 x float> %1, %1
147  ; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
148
149  %3 = extractelement <4 x float> %2, i32 2
150  ; Element 2 can be obtained by splatting it across the vector and extracting
151  ; $w0:sub_lo
152  ; MIPS32-DAG: splati.w $w0, [[R1]][2]
153
154  ret float %3
155  ; MIPS32: .size extract_v4f32_elt2
156}
157
158define double @extract_v2f64() nounwind {
159  ; MIPS32: extract_v2f64:
160
161  %1 = load <2 x double>* @v2f64
162  ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
163
164  %2 = fadd <2 x double> %1, %1
165  ; MIPS32-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
166
167  %3 = extractelement <2 x double> %2, i32 1
168  ; Element 1 can be obtained by splatting it across the vector and extracting
169  ; $w0:sub_64
170  ; MIPS32-DAG: splati.d $w0, [[R1]][1]
171  ; MIPS32-NOT: copy_u.w
172  ; MIPS32-NOT: mtc1
173  ; MIPS32-NOT: mthc1
174  ; MIPS32-NOT: sll
175  ; MIPS32-NOT: sra
176
177  ret double %3
178  ; MIPS32: .size extract_v2f64
179}
180
181define double @extract_v2f64_elt0() nounwind {
182  ; MIPS32: extract_v2f64_elt0:
183
184  %1 = load <2 x double>* @v2f64
185  ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
186
187  %2 = fadd <2 x double> %1, %1
188  ; MIPS32-DAG: fadd.d $w0, [[R1]], [[R1]]
189
190  %3 = extractelement <2 x double> %2, i32 0
191  ; Element 0 can be obtained by extracting $w0:sub_64 ($f0)
192  ; MIPS32-NOT: copy_u.w
193  ; MIPS32-NOT: mtc1
194  ; MIPS32-NOT: mthc1
195  ; MIPS32-NOT: sll
196  ; MIPS32-NOT: sra
197
198  ret double %3
199  ; MIPS32: .size extract_v2f64_elt0
200}
201
202define void @insert_v4f32(float %a) nounwind {
203  ; MIPS32: insert_v4f32:
204
205  %1 = load <4 x float>* @v4f32
206  ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
207
208  %2 = insertelement <4 x float> %1, float %a, i32 1
209  ; float argument passed in $f12
210  ; MIPS32-DAG: insve.w [[R1]][1], $w12[0]
211
212  store <4 x float> %2, <4 x float>* @v4f32
213  ; MIPS32-DAG: st.w [[R1]]
214
215  ret void
216  ; MIPS32: .size insert_v4f32
217}
218
219define void @insert_v2f64(double %a) nounwind {
220  ; MIPS32: insert_v2f64:
221
222  %1 = load <2 x double>* @v2f64
223  ; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
224
225  %2 = insertelement <2 x double> %1, double %a, i32 1
226  ; double argument passed in $f12
227  ; MIPS32-DAG: insve.d [[R1]][1], $w12[0]
228
229  store <2 x double> %2, <2 x double>* @v2f64
230  ; MIPS32-DAG: st.d [[R1]]
231
232  ret void
233  ; MIPS32: .size insert_v2f64
234}
235