1; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL %s 2; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL %s 3 4@v4f32 = global <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0> 5@v2f64 = global <2 x double> <double 0.0, double 0.0> 6@i32 = global i32 0 7@f32 = global float 0.0 8@f64 = global double 0.0 9 10define void @const_v4f32() nounwind { 11 ; ALL-LABEL: const_v4f32: 12 13 store volatile <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>, <4 x float>*@v4f32 14 ; ALL: ldi.b [[R1:\$w[0-9]+]], 0 15 16 store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float>*@v4f32 17 ; ALL: lui [[R1:\$[0-9]+]], 16256 18 ; ALL: fill.w [[R2:\$w[0-9]+]], [[R1]] 19 20 store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 31.0>, <4 x float>*@v4f32 21 ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ 22 ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) 23 24 store volatile <4 x float> <float 65537.0, float 65537.0, float 65537.0, float 65537.0>, <4 x float>*@v4f32 25 ; ALL: lui [[R1:\$[0-9]+]], 18304 26 ; ALL: ori [[R2:\$[0-9]+]], [[R1]], 128 27 ; ALL: fill.w [[R3:\$w[0-9]+]], [[R2]] 28 29 store volatile <4 x float> <float 1.0, float 2.0, float 1.0, float 2.0>, <4 x float>*@v4f32 30 ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ 31 ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) 32 33 store volatile <4 x float> <float 3.0, float 4.0, float 5.0, float 6.0>, <4 x float>*@v4f32 34 ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ 35 ; ALL: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]]) 36 37 ret void 38} 39 40define void @const_v2f64() nounwind { 41 ; ALL-LABEL: const_v2f64: 42 43 store volatile <2 x double> <double 0.0, double 0.0>, <2 x double>*@v2f64 44 ; ALL: ldi.b [[R1:\$w[0-9]+]], 0 45 46 store volatile <2 x double> <double 72340172838076673.0, double 72340172838076673.0>, <2 x double>*@v2f64 47 ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ 48 ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) 49 50 store volatile <2 x double> <double 281479271743489.0, double 281479271743489.0>, <2 x double>*@v2f64 51 ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ 52 ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) 53 54 store volatile <2 x double> <double 4294967297.0, double 4294967297.0>, <2 x double>*@v2f64 55 ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ 56 ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) 57 58 store volatile <2 x double> <double 1.0, double 1.0>, <2 x double>*@v2f64 59 ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ 60 ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) 61 62 store volatile <2 x double> <double 1.0, double 31.0>, <2 x double>*@v2f64 63 ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ 64 ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) 65 66 store volatile <2 x double> <double 3.0, double 4.0>, <2 x double>*@v2f64 67 ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ 68 ; ALL: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]]) 69 70 ret void 71} 72 73define void @nonconst_v4f32() nounwind { 74 ; ALL-LABEL: nonconst_v4f32: 75 76 %1 = load float , float *@f32 77 %2 = insertelement <4 x float> undef, float %1, i32 0 78 %3 = insertelement <4 x float> %2, float %1, i32 1 79 %4 = insertelement <4 x float> %3, float %1, i32 2 80 %5 = insertelement <4 x float> %4, float %1, i32 3 81 store volatile <4 x float> %5, <4 x float>*@v4f32 82 ; ALL: lwc1 $f[[R1:[0-9]+]], 0( 83 ; ALL: splati.w [[R2:\$w[0-9]+]], $w[[R1]] 84 85 ret void 86} 87 88define void @nonconst_v2f64() nounwind { 89 ; ALL-LABEL: nonconst_v2f64: 90 91 %1 = load double , double *@f64 92 %2 = insertelement <2 x double> undef, double %1, i32 0 93 %3 = insertelement <2 x double> %2, double %1, i32 1 94 store volatile <2 x double> %3, <2 x double>*@v2f64 95 ; ALL: ldc1 $f[[R1:[0-9]+]], 0( 96 ; ALL: splati.d [[R2:\$w[0-9]+]], $w[[R1]] 97 98 ret void 99} 100 101define float @extract_v4f32() nounwind { 102 ; ALL-LABEL: extract_v4f32: 103 104 %1 = load <4 x float>, <4 x float>* @v4f32 105 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 106 107 %2 = fadd <4 x float> %1, %1 108 ; ALL-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] 109 110 %3 = extractelement <4 x float> %2, i32 1 111 ; Element 1 can be obtained by splatting it across the vector and extracting 112 ; $w0:sub_lo 113 ; ALL-DAG: splati.w $w0, [[R1]][1] 114 115 ret float %3 116} 117 118define float @extract_v4f32_elt0() nounwind { 119 ; ALL-LABEL: extract_v4f32_elt0: 120 121 %1 = load <4 x float>, <4 x float>* @v4f32 122 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 123 124 %2 = fadd <4 x float> %1, %1 125 ; ALL-DAG: fadd.w $w0, [[R1]], [[R1]] 126 127 %3 = extractelement <4 x float> %2, i32 0 128 ; Element 0 can be obtained by extracting $w0:sub_lo ($f0) 129 ; ALL-NOT: copy_u.w 130 ; ALL-NOT: mtc1 131 132 ret float %3 133} 134 135define float @extract_v4f32_elt2() nounwind { 136 ; ALL-LABEL: extract_v4f32_elt2: 137 138 %1 = load <4 x float>, <4 x float>* @v4f32 139 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 140 141 %2 = fadd <4 x float> %1, %1 142 ; ALL-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] 143 144 %3 = extractelement <4 x float> %2, i32 2 145 ; Element 2 can be obtained by splatting it across the vector and extracting 146 ; $w0:sub_lo 147 ; ALL-DAG: splati.w $w0, [[R1]][2] 148 149 ret float %3 150} 151 152define float @extract_v4f32_vidx() nounwind { 153 ; ALL-LABEL: extract_v4f32_vidx: 154 155 %1 = load <4 x float>, <4 x float>* @v4f32 156 ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)( 157 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]]) 158 159 %2 = fadd <4 x float> %1, %1 160 ; ALL-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] 161 162 %3 = load i32, i32* @i32 163 ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 164 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 165 166 %4 = extractelement <4 x float> %2, i32 %3 167 ; ALL-DAG: splat.w $w0, [[R1]]{{\[}}[[IDX]]] 168 169 ret float %4 170} 171 172define double @extract_v2f64() nounwind { 173 ; ALL-LABEL: extract_v2f64: 174 175 %1 = load <2 x double>, <2 x double>* @v2f64 176 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 177 178 %2 = fadd <2 x double> %1, %1 179 ; ALL-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] 180 181 %3 = extractelement <2 x double> %2, i32 1 182 ; Element 1 can be obtained by splatting it across the vector and extracting 183 ; $w0:sub_64 184 ; ALL-DAG: splati.d $w0, [[R1]][1] 185 ; ALL-NOT: copy_u.w 186 ; ALL-NOT: mtc1 187 ; ALL-NOT: mthc1 188 ; ALL-NOT: sll 189 ; ALL-NOT: sra 190 191 ret double %3 192} 193 194define double @extract_v2f64_elt0() nounwind { 195 ; ALL-LABEL: extract_v2f64_elt0: 196 197 %1 = load <2 x double>, <2 x double>* @v2f64 198 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 199 200 %2 = fadd <2 x double> %1, %1 201 ; ALL-DAG: fadd.d $w0, [[R1]], [[R1]] 202 203 %3 = extractelement <2 x double> %2, i32 0 204 ; Element 0 can be obtained by extracting $w0:sub_64 ($f0) 205 ; ALL-NOT: copy_u.w 206 ; ALL-NOT: mtc1 207 ; ALL-NOT: mthc1 208 ; ALL-NOT: sll 209 ; ALL-NOT: sra 210 211 ret double %3 212} 213 214define double @extract_v2f64_vidx() nounwind { 215 ; ALL-LABEL: extract_v2f64_vidx: 216 217 %1 = load <2 x double>, <2 x double>* @v2f64 218 ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)( 219 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]]) 220 221 %2 = fadd <2 x double> %1, %1 222 ; ALL-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] 223 224 %3 = load i32, i32* @i32 225 ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 226 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 227 228 %4 = extractelement <2 x double> %2, i32 %3 229 ; ALL-DAG: splat.d $w0, [[R1]]{{\[}}[[IDX]]] 230 231 ret double %4 232} 233 234define void @insert_v4f32(float %a) nounwind { 235 ; ALL-LABEL: insert_v4f32: 236 237 %1 = load <4 x float>, <4 x float>* @v4f32 238 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 239 240 %2 = insertelement <4 x float> %1, float %a, i32 1 241 ; float argument passed in $f12 242 ; ALL-DAG: insve.w [[R1]][1], $w12[0] 243 244 store <4 x float> %2, <4 x float>* @v4f32 245 ; ALL-DAG: st.w [[R1]] 246 247 ret void 248} 249 250define void @insert_v2f64(double %a) nounwind { 251 ; ALL-LABEL: insert_v2f64: 252 253 %1 = load <2 x double>, <2 x double>* @v2f64 254 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 255 256 %2 = insertelement <2 x double> %1, double %a, i32 1 257 ; double argument passed in $f12 258 ; ALL-DAG: insve.d [[R1]][1], $w12[0] 259 260 store <2 x double> %2, <2 x double>* @v2f64 261 ; ALL-DAG: st.d [[R1]] 262 263 ret void 264} 265 266define void @insert_v4f32_vidx(float %a) nounwind { 267 ; ALL-LABEL: insert_v4f32_vidx: 268 269 %1 = load <4 x float>, <4 x float>* @v4f32 270 ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)( 271 ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]]) 272 273 %2 = load i32, i32* @i32 274 ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 275 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 276 277 %3 = insertelement <4 x float> %1, float %a, i32 %2 278 ; float argument passed in $f12 279 ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2 280 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]] 281 ; ALL-DAG: insve.w [[R1]][0], $w12[0] 282 ; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] 283 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] 284 285 store <4 x float> %3, <4 x float>* @v4f32 286 ; ALL-DAG: st.w [[R1]] 287 288 ret void 289} 290 291define void @insert_v2f64_vidx(double %a) nounwind { 292 ; ALL-LABEL: insert_v2f64_vidx: 293 294 %1 = load <2 x double>, <2 x double>* @v2f64 295 ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)( 296 ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]]) 297 298 %2 = load i32, i32* @i32 299 ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)( 300 ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]]) 301 302 %3 = insertelement <2 x double> %1, double %a, i32 %2 303 ; double argument passed in $f12 304 ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 3 305 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]] 306 ; ALL-DAG: insve.d [[R1]][0], $w12[0] 307 ; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]] 308 ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]] 309 310 store <2 x double> %3, <2 x double>* @v2f64 311 ; ALL-DAG: st.d [[R1]] 312 313 ret void 314} 315