1; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 2 3define void @add_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 4 ; CHECK: add_v4f32: 5 6 %1 = load <4 x float>* %a 7 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 8 %2 = load <4 x float>* %b 9 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 10 %3 = fadd <4 x float> %1, %2 11 ; CHECK-DAG: fadd.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 12 store <4 x float> %3, <4 x float>* %c 13 ; CHECK-DAG: st.w [[R3]], 0($4) 14 15 ret void 16 ; CHECK: .size add_v4f32 17} 18 19define void @add_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 20 ; CHECK: add_v2f64: 21 22 %1 = load <2 x double>* %a 23 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 24 %2 = load <2 x double>* %b 25 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 26 %3 = fadd <2 x double> %1, %2 27 ; CHECK-DAG: fadd.d [[R3:\$w[0-9]+]], [[R1]], [[R2]] 28 store <2 x double> %3, <2 x double>* %c 29 ; CHECK-DAG: st.d [[R3]], 0($4) 30 31 ret void 32 ; CHECK: .size add_v2f64 33} 34 35define void @sub_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 36 ; CHECK: sub_v4f32: 37 38 %1 = load <4 x float>* %a 39 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 40 %2 = load <4 x float>* %b 41 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 42 %3 = fsub <4 x float> %1, %2 43 ; CHECK-DAG: fsub.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 44 store <4 x float> %3, <4 x float>* %c 45 ; CHECK-DAG: st.w [[R3]], 0($4) 46 47 ret void 48 ; CHECK: .size sub_v4f32 49} 50 51define void @sub_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 52 ; CHECK: sub_v2f64: 53 54 %1 = load <2 x double>* %a 55 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 56 %2 = load <2 x double>* %b 57 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 58 %3 = fsub <2 x double> %1, %2 59 ; CHECK-DAG: fsub.d [[R3:\$w[0-9]+]], [[R1]], [[R2]] 60 store <2 x double> %3, <2 x double>* %c 61 ; CHECK-DAG: st.d [[R3]], 0($4) 62 63 ret void 64 ; CHECK: .size sub_v2f64 65} 66 67define void @mul_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 68 ; CHECK: mul_v4f32: 69 70 %1 = load <4 x float>* %a 71 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 72 %2 = load <4 x float>* %b 73 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 74 %3 = fmul <4 x float> %1, %2 75 ; CHECK-DAG: fmul.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 76 store <4 x float> %3, <4 x float>* %c 77 ; CHECK-DAG: st.w [[R3]], 0($4) 78 79 ret void 80 ; CHECK: .size mul_v4f32 81} 82 83define void @mul_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 84 ; CHECK: mul_v2f64: 85 86 %1 = load <2 x double>* %a 87 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 88 %2 = load <2 x double>* %b 89 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 90 %3 = fmul <2 x double> %1, %2 91 ; CHECK-DAG: fmul.d [[R3:\$w[0-9]+]], [[R1]], [[R2]] 92 store <2 x double> %3, <2 x double>* %c 93 ; CHECK-DAG: st.d [[R3]], 0($4) 94 95 ret void 96 ; CHECK: .size mul_v2f64 97} 98 99define void @fma_v4f32(<4 x float>* %d, <4 x float>* %a, <4 x float>* %b, 100 <4 x float>* %c) nounwind { 101 ; CHECK: fma_v4f32: 102 103 %1 = load <4 x float>* %a 104 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 105 %2 = load <4 x float>* %b 106 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 107 %3 = load <4 x float>* %c 108 ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7) 109 %4 = tail call <4 x float> @llvm.fma.v4f32 (<4 x float> %1, <4 x float> %2, 110 <4 x float> %3) 111 ; CHECK-DAG: fmadd.w [[R1]], [[R2]], [[R3]] 112 store <4 x float> %4, <4 x float>* %d 113 ; CHECK-DAG: st.w [[R1]], 0($4) 114 115 ret void 116 ; CHECK: .size fma_v4f32 117} 118 119define void @fma_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b, 120 <2 x double>* %c) nounwind { 121 ; CHECK: fma_v2f64: 122 123 %1 = load <2 x double>* %a 124 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 125 %2 = load <2 x double>* %b 126 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 127 %3 = load <2 x double>* %c 128 ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7) 129 %4 = tail call <2 x double> @llvm.fma.v2f64 (<2 x double> %1, <2 x double> %2, 130 <2 x double> %3) 131 ; CHECK-DAG: fmadd.d [[R1]], [[R2]], [[R3]] 132 store <2 x double> %4, <2 x double>* %d 133 ; CHECK-DAG: st.d [[R1]], 0($4) 134 135 ret void 136 ; CHECK: .size fma_v2f64 137} 138 139define void @fmsub_v4f32(<4 x float>* %d, <4 x float>* %a, <4 x float>* %b, 140 <4 x float>* %c) nounwind { 141 ; CHECK: fmsub_v4f32: 142 143 %1 = load <4 x float>* %a 144 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 145 %2 = load <4 x float>* %b 146 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 147 %3 = load <4 x float>* %c 148 ; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7) 149 %4 = fmul <4 x float> %2, %3 150 %5 = fsub <4 x float> %1, %4 151 ; CHECK-DAG: fmsub.w [[R1]], [[R2]], [[R3]] 152 store <4 x float> %5, <4 x float>* %d 153 ; CHECK-DAG: st.w [[R1]], 0($4) 154 155 ret void 156 ; CHECK: .size fmsub_v4f32 157} 158 159define void @fmsub_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b, 160 <2 x double>* %c) nounwind { 161 ; CHECK: fmsub_v2f64: 162 163 %1 = load <2 x double>* %a 164 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 165 %2 = load <2 x double>* %b 166 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 167 %3 = load <2 x double>* %c 168 ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7) 169 %4 = fmul <2 x double> %2, %3 170 %5 = fsub <2 x double> %1, %4 171 ; CHECK-DAG: fmsub.d [[R1]], [[R2]], [[R3]] 172 store <2 x double> %5, <2 x double>* %d 173 ; CHECK-DAG: st.d [[R1]], 0($4) 174 175 ret void 176 ; CHECK: .size fmsub_v2f64 177} 178 179define void @fdiv_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind { 180 ; CHECK: fdiv_v4f32: 181 182 %1 = load <4 x float>* %a 183 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 184 %2 = load <4 x float>* %b 185 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) 186 %3 = fdiv <4 x float> %1, %2 187 ; CHECK-DAG: fdiv.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 188 store <4 x float> %3, <4 x float>* %c 189 ; CHECK-DAG: st.w [[R3]], 0($4) 190 191 ret void 192 ; CHECK: .size fdiv_v4f32 193} 194 195define void @fdiv_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind { 196 ; CHECK: fdiv_v2f64: 197 198 %1 = load <2 x double>* %a 199 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 200 %2 = load <2 x double>* %b 201 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) 202 %3 = fdiv <2 x double> %1, %2 203 ; CHECK-DAG: fdiv.d [[R3:\$w[0-9]+]], [[R1]], [[R2]] 204 store <2 x double> %3, <2 x double>* %c 205 ; CHECK-DAG: st.d [[R3]], 0($4) 206 207 ret void 208 ; CHECK: .size fdiv_v2f64 209} 210 211define void @fabs_v4f32(<4 x float>* %c, <4 x float>* %a) nounwind { 212 ; CHECK: fabs_v4f32: 213 214 %1 = load <4 x float>* %a 215 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 216 %2 = tail call <4 x float> @llvm.fabs.v4f32 (<4 x float> %1) 217 ; CHECK-DAG: fmax_a.w [[R3:\$w[0-9]+]], [[R1]], [[R1]] 218 store <4 x float> %2, <4 x float>* %c 219 ; CHECK-DAG: st.w [[R3]], 0($4) 220 221 ret void 222 ; CHECK: .size fabs_v4f32 223} 224 225define void @fabs_v2f64(<2 x double>* %c, <2 x double>* %a) nounwind { 226 ; CHECK: fabs_v2f64: 227 228 %1 = load <2 x double>* %a 229 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 230 %2 = tail call <2 x double> @llvm.fabs.v2f64 (<2 x double> %1) 231 ; CHECK-DAG: fmax_a.d [[R3:\$w[0-9]+]], [[R1]], [[R1]] 232 store <2 x double> %2, <2 x double>* %c 233 ; CHECK-DAG: st.d [[R3]], 0($4) 234 235 ret void 236 ; CHECK: .size fabs_v2f64 237} 238 239define void @fsqrt_v4f32(<4 x float>* %c, <4 x float>* %a) nounwind { 240 ; CHECK: fsqrt_v4f32: 241 242 %1 = load <4 x float>* %a 243 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 244 %2 = tail call <4 x float> @llvm.sqrt.v4f32 (<4 x float> %1) 245 ; CHECK-DAG: fsqrt.w [[R3:\$w[0-9]+]], [[R1]] 246 store <4 x float> %2, <4 x float>* %c 247 ; CHECK-DAG: st.w [[R3]], 0($4) 248 249 ret void 250 ; CHECK: .size fsqrt_v4f32 251} 252 253define void @fsqrt_v2f64(<2 x double>* %c, <2 x double>* %a) nounwind { 254 ; CHECK: fsqrt_v2f64: 255 256 %1 = load <2 x double>* %a 257 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 258 %2 = tail call <2 x double> @llvm.sqrt.v2f64 (<2 x double> %1) 259 ; CHECK-DAG: fsqrt.d [[R3:\$w[0-9]+]], [[R1]] 260 store <2 x double> %2, <2 x double>* %c 261 ; CHECK-DAG: st.d [[R3]], 0($4) 262 263 ret void 264 ; CHECK: .size fsqrt_v2f64 265} 266 267define void @ffint_u_v4f32(<4 x float>* %c, <4 x i32>* %a) nounwind { 268 ; CHECK: ffint_u_v4f32: 269 270 %1 = load <4 x i32>* %a 271 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 272 %2 = uitofp <4 x i32> %1 to <4 x float> 273 ; CHECK-DAG: ffint_u.w [[R3:\$w[0-9]+]], [[R1]] 274 store <4 x float> %2, <4 x float>* %c 275 ; CHECK-DAG: st.w [[R3]], 0($4) 276 277 ret void 278 ; CHECK: .size ffint_u_v4f32 279} 280 281define void @ffint_u_v2f64(<2 x double>* %c, <2 x i64>* %a) nounwind { 282 ; CHECK: ffint_u_v2f64: 283 284 %1 = load <2 x i64>* %a 285 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 286 %2 = uitofp <2 x i64> %1 to <2 x double> 287 ; CHECK-DAG: ffint_u.d [[R3:\$w[0-9]+]], [[R1]] 288 store <2 x double> %2, <2 x double>* %c 289 ; CHECK-DAG: st.d [[R3]], 0($4) 290 291 ret void 292 ; CHECK: .size ffint_u_v2f64 293} 294 295define void @ffint_s_v4f32(<4 x float>* %c, <4 x i32>* %a) nounwind { 296 ; CHECK: ffint_s_v4f32: 297 298 %1 = load <4 x i32>* %a 299 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 300 %2 = sitofp <4 x i32> %1 to <4 x float> 301 ; CHECK-DAG: ffint_s.w [[R3:\$w[0-9]+]], [[R1]] 302 store <4 x float> %2, <4 x float>* %c 303 ; CHECK-DAG: st.w [[R3]], 0($4) 304 305 ret void 306 ; CHECK: .size ffint_s_v4f32 307} 308 309define void @ffint_s_v2f64(<2 x double>* %c, <2 x i64>* %a) nounwind { 310 ; CHECK: ffint_s_v2f64: 311 312 %1 = load <2 x i64>* %a 313 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 314 %2 = sitofp <2 x i64> %1 to <2 x double> 315 ; CHECK-DAG: ffint_s.d [[R3:\$w[0-9]+]], [[R1]] 316 store <2 x double> %2, <2 x double>* %c 317 ; CHECK-DAG: st.d [[R3]], 0($4) 318 319 ret void 320 ; CHECK: .size ffint_s_v2f64 321} 322 323define void @ftrunc_u_v4f32(<4 x i32>* %c, <4 x float>* %a) nounwind { 324 ; CHECK: ftrunc_u_v4f32: 325 326 %1 = load <4 x float>* %a 327 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 328 %2 = fptoui <4 x float> %1 to <4 x i32> 329 ; CHECK-DAG: ftrunc_u.w [[R3:\$w[0-9]+]], [[R1]] 330 store <4 x i32> %2, <4 x i32>* %c 331 ; CHECK-DAG: st.w [[R3]], 0($4) 332 333 ret void 334 ; CHECK: .size ftrunc_u_v4f32 335} 336 337define void @ftrunc_u_v2f64(<2 x i64>* %c, <2 x double>* %a) nounwind { 338 ; CHECK: ftrunc_u_v2f64: 339 340 %1 = load <2 x double>* %a 341 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 342 %2 = fptoui <2 x double> %1 to <2 x i64> 343 ; CHECK-DAG: ftrunc_u.d [[R3:\$w[0-9]+]], [[R1]] 344 store <2 x i64> %2, <2 x i64>* %c 345 ; CHECK-DAG: st.d [[R3]], 0($4) 346 347 ret void 348 ; CHECK: .size ftrunc_u_v2f64 349} 350 351define void @ftrunc_s_v4f32(<4 x i32>* %c, <4 x float>* %a) nounwind { 352 ; CHECK: ftrunc_s_v4f32: 353 354 %1 = load <4 x float>* %a 355 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) 356 %2 = fptosi <4 x float> %1 to <4 x i32> 357 ; CHECK-DAG: ftrunc_s.w [[R3:\$w[0-9]+]], [[R1]] 358 store <4 x i32> %2, <4 x i32>* %c 359 ; CHECK-DAG: st.w [[R3]], 0($4) 360 361 ret void 362 ; CHECK: .size ftrunc_s_v4f32 363} 364 365define void @ftrunc_s_v2f64(<2 x i64>* %c, <2 x double>* %a) nounwind { 366 ; CHECK: ftrunc_s_v2f64: 367 368 %1 = load <2 x double>* %a 369 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) 370 %2 = fptosi <2 x double> %1 to <2 x i64> 371 ; CHECK-DAG: ftrunc_s.d [[R3:\$w[0-9]+]], [[R1]] 372 store <2 x i64> %2, <2 x i64>* %c 373 ; CHECK-DAG: st.d [[R3]], 0($4) 374 375 ret void 376 ; CHECK: .size ftrunc_s_v2f64 377} 378 379declare <4 x float> @llvm.fabs.v4f32(<4 x float> %Val) 380declare <2 x double> @llvm.fabs.v2f64(<2 x double> %Val) 381declare <4 x float> @llvm.fma.v4f32(<4 x float> %a, <4 x float> %b, 382 <4 x float> %c) 383declare <2 x double> @llvm.fma.v2f64(<2 x double> %a, <2 x double> %b, 384 <2 x double> %c) 385declare <4 x float> @llvm.sqrt.v4f32(<4 x float> %Val) 386declare <2 x double> @llvm.sqrt.v2f64(<2 x double> %Val) 387