1; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
2; RUN:    -check-prefix=ALL -check-prefix=M2 -check-prefix=M2-M3
3; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
4; RUN:    -check-prefix=ALL -check-prefix=CMOV \
5; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R1
6; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
7; RUN:    -check-prefix=ALL -check-prefix=CMOV \
8; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
9; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
10; RUN:    -check-prefix=ALL -check-prefix=CMOV \
11; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
12; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
13; RUN:    -check-prefix=ALL -check-prefix=CMOV \
14; RUN:    -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
15; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
16; RUN:    -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32
17; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
18; RUN:    -check-prefix=ALL -check-prefix=M3 -check-prefix=M2-M3
19; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
20; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
21; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
22; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
23; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
24; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
25; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
26; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
27; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
28; RUN:    -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
29; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
30; RUN:    -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
31
32define double @tst_select_i1_double(i1 signext %s, double %x, double %y) {
33entry:
34  ; ALL-LABEL: tst_select_i1_double:
35
36  ; M2:         andi    $[[T0:[0-9]+]], $4, 1
37  ; M2:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
38  ; M2:         nop
39  ; M2:         ldc1    $f0, 16($sp)
40  ; M2:         jr      $ra
41  ; M2:         nop
42  ; M2:         $[[BB0]]:
43  ; M2:         mtc1    $7, $f0
44  ; M2:         jr      $ra
45  ; M2:         mtc1    $6, $f1
46
47  ; CMOV-32:      mtc1    $7, $[[F0:f[0-9]+]]
48  ; CMOV-32R1:    mtc1    $6, $f{{[0-9]+}}
49  ; CMOV-32R2-R5: mthc1   $6, $[[F0]]
50  ; CMOV-32:      andi    $[[T0:[0-9]+]], $4, 1
51  ; CMOV-32:      ldc1    $f0, 16($sp)
52  ; CMOV-32:      movn.d  $f0, $[[F0]], $[[T0]]
53
54  ; SEL-32:     mtc1    $7, $[[F0:f[0-9]+]]
55  ; SEL-32:     mthc1   $6, $[[F0]]
56  ; SEL-32:     ldc1    $[[F1:f[0-9]+]], 16($sp)
57  ; SEL-32:     mtc1    $4, $f0
58  ; SEL-32:     sel.d   $f0, $[[F1]], $[[F0]]
59
60  ; M3:         andi    $[[T0:[0-9]+]], $4, 1
61  ; M3:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
62  ; M3:         nop
63  ; M3:         mov.d   $f13, $f14
64  ; M3:         $[[BB0]]:
65  ; M3:         jr      $ra
66  ; M3:         mov.d   $f0, $f13
67
68  ; CMOV-64:    andi    $[[T0:[0-9]+]], $4, 1
69  ; CMOV-64:    movn.d  $f14, $f13, $[[T0]]
70  ; CMOV-64:    mov.d   $f0, $f14
71
72  ; SEL-64:     mtc1    $4, $f0
73  ; SEL-64:     sel.d   $f0, $f14, $f13
74  %r = select i1 %s, double %x, double %y
75  ret double %r
76}
77
78define double @tst_select_i1_double_reordered(double %x, double %y,
79                                              i1 signext %s) {
80entry:
81  ; ALL-LABEL: tst_select_i1_double_reordered:
82
83  ; M2:         lw      $[[T0:[0-9]+]], 16($sp)
84  ; M2:         andi    $[[T1:[0-9]+]], $[[T0]], 1
85  ; M2:         bnez    $[[T1]], $[[BB0:BB[0-9_]+]]
86  ; M2:         nop
87  ; M2:         mov.d   $f12, $f14
88  ; M2:         $[[BB0]]:
89  ; M2:         jr      $ra
90  ; M2:         mov.d   $f0, $f12
91
92  ; CMOV-32:    lw      $[[T0:[0-9]+]], 16($sp)
93  ; CMOV-32:    andi    $[[T1:[0-9]+]], $[[T0]], 1
94  ; CMOV-32:    movn.d  $f14, $f12, $[[T1]]
95  ; CMOV-32:    mov.d   $f0, $f14
96
97  ; SEL-32:     lw      $[[T0:[0-9]+]], 16($sp)
98  ; SEL-32:     mtc1    $[[T0]], $f0
99  ; SEL-32:     sel.d   $f0, $f14, $f12
100
101  ; M3:         andi    $[[T0:[0-9]+]], $6, 1
102  ; M3:         bnez    $[[T0]], $[[BB0:BB[0-9_]+]]
103  ; M3:         nop
104  ; M3:         mov.d   $f12, $f13
105  ; M3:         $[[BB0]]:
106  ; M3:         jr      $ra
107  ; M3:         mov.d   $f0, $f12
108
109  ; CMOV-64:    andi    $[[T0:[0-9]+]], $6, 1
110  ; CMOV-64:    movn.d  $f13, $f12, $[[T0]]
111  ; CMOV-64:    mov.d   $f0, $f13
112
113  ; SEL-64:     mtc1    $6, $f0
114  ; SEL-64:     sel.d   $f0, $f13, $f12
115  %r = select i1 %s, double %x, double %y
116  ret double %r
117}
118
119define double @tst_select_fcmp_olt_double(double %x, double %y) {
120entry:
121  ; ALL-LABEL: tst_select_fcmp_olt_double:
122
123  ; M2:         c.olt.d   $f12, $f14
124  ; M3:         c.olt.d   $f12, $f13
125  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
126  ; M2-M3:      nop
127  ; M2:         mov.d     $f12, $f14
128  ; M3:         mov.d     $f12, $f13
129  ; M2-M3:      $[[BB0]]:
130  ; M2-M3:      jr        $ra
131  ; M2-M3:      mov.d     $f0, $f12
132
133  ; CMOV-32:    c.olt.d   $f12, $f14
134  ; CMOV-32:    movt.d    $f14, $f12, $fcc0
135  ; CMOV-32:    mov.d     $f0, $f14
136
137  ; SEL-32:     cmp.lt.d  $f0, $f12, $f14
138  ; SEL-32:     sel.d     $f0, $f14, $f12
139
140  ; CMOV-64:    c.olt.d   $f12, $f13
141  ; CMOV-64:    movt.d    $f13, $f12, $fcc0
142  ; CMOV-64:    mov.d     $f0, $f13
143
144  ; SEL-64:     cmp.lt.d  $f0, $f12, $f13
145  ; SEL-64:     sel.d     $f0, $f13, $f12
146  %s = fcmp olt double %x, %y
147  %r = select i1 %s, double %x, double %y
148  ret double %r
149}
150
151define double @tst_select_fcmp_ole_double(double %x, double %y) {
152entry:
153  ; ALL-LABEL: tst_select_fcmp_ole_double:
154
155  ; M2:         c.ole.d   $f12, $f14
156  ; M3:         c.ole.d   $f12, $f13
157  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
158  ; M2-M3:      nop
159  ; M2:         mov.d     $f12, $f14
160  ; M3:         mov.d     $f12, $f13
161  ; M2-M3:      $[[BB0]]:
162  ; M2-M3:      jr        $ra
163  ; M2-M3:      mov.d     $f0, $f12
164
165  ; CMOV-32:    c.ole.d   $f12, $f14
166  ; CMOV-32:    movt.d    $f14, $f12, $fcc0
167  ; CMOV-32:    mov.d     $f0, $f14
168
169  ; SEL-32:     cmp.le.d  $f0, $f12, $f14
170  ; SEL-32:     sel.d     $f0, $f14, $f12
171
172  ; CMOV-64:    c.ole.d   $f12, $f13
173  ; CMOV-64:    movt.d    $f13, $f12, $fcc0
174  ; CMOV-64:    mov.d     $f0, $f13
175
176  ; SEL-64:     cmp.le.d  $f0, $f12, $f13
177  ; SEL-64:     sel.d     $f0, $f13, $f12
178  %s = fcmp ole double %x, %y
179  %r = select i1 %s, double %x, double %y
180  ret double %r
181}
182
183define double @tst_select_fcmp_ogt_double(double %x, double %y) {
184entry:
185  ; ALL-LABEL: tst_select_fcmp_ogt_double:
186
187  ; M2:         c.ule.d   $f12, $f14
188  ; M3:         c.ule.d   $f12, $f13
189  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
190  ; M2-M3:      nop
191  ; M2:         mov.d     $f12, $f14
192  ; M3:         mov.d     $f12, $f13
193  ; M2-M3:      $[[BB0]]:
194  ; M2-M3:      jr        $ra
195  ; M2-M3:      mov.d     $f0, $f12
196
197  ; CMOV-32:    c.ule.d   $f12, $f14
198  ; CMOV-32:    movf.d    $f14, $f12, $fcc0
199  ; CMOV-32:    mov.d     $f0, $f14
200
201  ; SEL-32:     cmp.lt.d  $f0, $f14, $f12
202  ; SEL-32:     sel.d     $f0, $f14, $f12
203
204  ; CMOV-64:    c.ule.d   $f12, $f13
205  ; CMOV-64:    movf.d    $f13, $f12, $fcc0
206  ; CMOV-64:    mov.d     $f0, $f13
207
208  ; SEL-64:     cmp.lt.d  $f0, $f13, $f12
209  ; SEL-64:     sel.d     $f0, $f13, $f12
210  %s = fcmp ogt double %x, %y
211  %r = select i1 %s, double %x, double %y
212  ret double %r
213}
214
215define double @tst_select_fcmp_oge_double(double %x, double %y) {
216entry:
217  ; ALL-LABEL: tst_select_fcmp_oge_double:
218
219  ; M2:         c.ult.d   $f12, $f14
220  ; M3:         c.ult.d   $f12, $f13
221  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
222  ; M2-M3:      nop
223  ; M2:         mov.d     $f12, $f14
224  ; M3:         mov.d     $f12, $f13
225  ; M2-M3:      $[[BB0]]:
226  ; M2-M3:      jr        $ra
227  ; M2-M3:      mov.d     $f0, $f12
228
229  ; CMOV-32:    c.ult.d   $f12, $f14
230  ; CMOV-32:    movf.d    $f14, $f12, $fcc0
231  ; CMOV-32:    mov.d     $f0, $f14
232
233  ; SEL-32:     cmp.le.d  $f0, $f14, $f12
234  ; SEL-32:     sel.d     $f0, $f14, $f12
235
236  ; CMOV-64:    c.ult.d   $f12, $f13
237  ; CMOV-64:    movf.d    $f13, $f12, $fcc0
238  ; CMOV-64:    mov.d     $f0, $f13
239
240  ; SEL-64:     cmp.le.d  $f0, $f13, $f12
241  ; SEL-64:     sel.d     $f0, $f13, $f12
242  %s = fcmp oge double %x, %y
243  %r = select i1 %s, double %x, double %y
244  ret double %r
245}
246
247define double @tst_select_fcmp_oeq_double(double %x, double %y) {
248entry:
249  ; ALL-LABEL: tst_select_fcmp_oeq_double:
250
251  ; M2:         c.eq.d    $f12, $f14
252  ; M3:         c.eq.d    $f12, $f13
253  ; M2-M3:      bc1t      $[[BB0:BB[0-9_]+]]
254  ; M2-M3:      nop
255  ; M2:         mov.d     $f12, $f14
256  ; M3:         mov.d     $f12, $f13
257  ; M2-M3:      $[[BB0]]:
258  ; M2-M3:      jr        $ra
259  ; M2-M3:      mov.d     $f0, $f12
260
261  ; CMOV-32:    c.eq.d    $f12, $f14
262  ; CMOV-32:    movt.d    $f14, $f12, $fcc0
263  ; CMOV-32:    mov.d     $f0, $f14
264
265  ; SEL-32:     cmp.eq.d  $f0, $f12, $f14
266  ; SEL-32:     sel.d     $f0, $f14, $f12
267
268  ; CMOV-64:    c.eq.d    $f12, $f13
269  ; CMOV-64:    movt.d    $f13, $f12, $fcc0
270  ; CMOV-64:    mov.d     $f0, $f13
271
272  ; SEL-64:     cmp.eq.d  $f0, $f12, $f13
273  ; SEL-64:     sel.d     $f0, $f13, $f12
274  %s = fcmp oeq double %x, %y
275  %r = select i1 %s, double %x, double %y
276  ret double %r
277}
278
279define double @tst_select_fcmp_one_double(double %x, double %y) {
280entry:
281  ; ALL-LABEL: tst_select_fcmp_one_double:
282
283  ; M2:         c.ueq.d   $f12, $f14
284  ; M3:         c.ueq.d   $f12, $f13
285  ; M2-M3:      bc1f      $[[BB0:BB[0-9_]+]]
286  ; M2-M3:      nop
287  ; M2:         mov.d     $f12, $f14
288  ; M3:         mov.d     $f12, $f13
289  ; M2-M3:      $[[BB0]]:
290  ; M2-M3:      jr        $ra
291  ; M2-M3:      mov.d     $f0, $f12
292
293  ; CMOV-32:    c.ueq.d   $f12, $f14
294  ; CMOV-32:    movf.d    $f14, $f12, $fcc0
295  ; CMOV-32:    mov.d     $f0, $f14
296
297  ; SEL-32:     cmp.ueq.d $f0, $f12, $f14
298  ; SEL-32:     mfc1      $[[T0:[0-9]+]], $f0
299  ; SEL-32:     not       $[[T0]], $[[T0]]
300  ; SEL-32:     mtc1      $[[T0:[0-9]+]], $f0
301  ; SEL-32:     sel.d     $f0, $f14, $f12
302
303  ; CMOV-64:    c.ueq.d   $f12, $f13
304  ; CMOV-64:    movf.d    $f13, $f12, $fcc0
305  ; CMOV-64:    mov.d     $f0, $f13
306
307  ; SEL-64:     cmp.ueq.d $f0, $f12, $f13
308  ; SEL-64:     mfc1      $[[T0:[0-9]+]], $f0
309  ; SEL-64:     not       $[[T0]], $[[T0]]
310  ; SEL-64:     mtc1      $[[T0:[0-9]+]], $f0
311  ; SEL-64:     sel.d     $f0, $f13, $f12
312  %s = fcmp one double %x, %y
313  %r = select i1 %s, double %x, double %y
314  ret double %r
315}
316