1; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ 2; RUN: -check-prefixes=ALL,NOT-R6,NOT-R2-R6,GP32 3; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ 4; RUN: -check-prefixes=ALL,NOT-R6,NOT-R2-R6,GP32 5; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ 6; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP32 7; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ 8; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP32 9; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ 10; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP32 11; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ 12; RUN: -check-prefixes=ALL,R6,GP32 13 14; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ 15; RUN: -check-prefixes=ALL,NOT-R6,NOT-R2-R6,GP64-NOT-R6 16; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ 17; RUN: -check-prefixes=ALL,NOT-R6,NOT-R2-R6,GP64-NOT-R6 18; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ 19; RUN: -check-prefixes=ALL,NOT-R6,NOT-R2-R6,GP64-NOT-R6 20; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ 21; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP64-NOT-R6 22; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ 23; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP64-NOT-R6 24; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ 25; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP64-NOT-R6 26; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ 27; RUN: -check-prefixes=ALL,R6,64R6 28 29; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ 30; RUN: -check-prefixes=ALL,MMR3,MM32 31; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ 32; RUN: -check-prefixes=ALL,MMR6,MM32 33; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | FileCheck %s \ 34; RUN: -check-prefixes=ALL,MMR6,MM64 35 36define signext i1 @sdiv_i1(i1 signext %a, i1 signext %b) { 37entry: 38; ALL-LABEL: sdiv_i1: 39 40 ; NOT-R6: div $zero, $4, $5 41 ; NOT-R6: teq $5, $zero, 7 42 ; NOT-R6: mflo $[[T0:[0-9]+]] 43 ; FIXME: The andi/negu instructions are redundant since div is signed. 44 ; NOT-R6: andi $[[T0]], $[[T0]], 1 45 ; NOT-R6: negu $2, $[[T0]] 46 47 ; R6: div $[[T0:[0-9]+]], $4, $5 48 ; R6: teq $5, $zero, 7 49 ; FIXME: The andi/negu instructions are redundant since div is signed. 50 ; R6: andi $[[T0]], $[[T0]], 1 51 ; R6: negu $2, $[[T0]] 52 53 ; MMR3: div $zero, $4, $5 54 ; MMR3: teq $5, $zero, 7 55 ; MMR3: mflo $[[T0:[0-9]+]] 56 ; MMR3: andi16 $[[T0]], $[[T0]], 1 57 ; MMR3: li16 $[[T1:[0-9]+]], 0 58 ; MMR3: subu16 $2, $[[T1]], $[[T0]] 59 60 ; MMR6: div $[[T0:[0-9]+]], $4, $5 61 ; MMR6: teq $5, $zero, 7 62 ; MMR6: andi16 $[[T0]], $[[T0]], 1 63 ; MMR6: li16 $[[T1:[0-9]+]], 0 64 ; MMR6: subu16 $2, $[[T1]], $[[T0]] 65 66 %r = sdiv i1 %a, %b 67 ret i1 %r 68} 69 70define signext i8 @sdiv_i8(i8 signext %a, i8 signext %b) { 71entry: 72; ALL-LABEL: sdiv_i8: 73 74 ; NOT-R2-R6: div $zero, $4, $5 75 ; NOT-R2-R6: teq $5, $zero, 7 76 ; NOT-R2-R6: mflo $[[T0:[0-9]+]] 77 ; FIXME: The sll/sra instructions are redundant since div is signed. 78 ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 24 79 ; NOT-R2-R6: sra $2, $[[T1]], 24 80 81 ; R2-R5: div $zero, $4, $5 82 ; R2-R5: teq $5, $zero, 7 83 ; R2-R5: mflo $[[T0:[0-9]+]] 84 ; FIXME: This instruction is redundant. 85 ; R2-R5: seb $2, $[[T0]] 86 87 ; R6: div $[[T0:[0-9]+]], $4, $5 88 ; R6: teq $5, $zero, 7 89 ; FIXME: This instruction is redundant. 90 ; R6: seb $2, $[[T0]] 91 92 ; MMR3: div $zero, $4, $5 93 ; MMR3: teq $5, $zero, 7 94 ; MMR3: mflo $[[T0:[0-9]+]] 95 ; MMR3: seb $2, $[[T0]] 96 97 ; MMR6: div $[[T0:[0-9]+]], $4, $5 98 ; MMR6: teq $5, $zero, 7 99 ; MMR6: seb $2, $[[T0]] 100 101 %r = sdiv i8 %a, %b 102 ret i8 %r 103} 104 105define signext i16 @sdiv_i16(i16 signext %a, i16 signext %b) { 106entry: 107; ALL-LABEL: sdiv_i16: 108 109 ; NOT-R2-R6: div $zero, $4, $5 110 ; NOT-R2-R6: teq $5, $zero, 7 111 ; NOT-R2-R6: mflo $[[T0:[0-9]+]] 112 ; FIXME: The sll/sra instructions are redundant since div is signed. 113 ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 16 114 ; NOT-R2-R6: sra $2, $[[T1]], 16 115 116 ; R2-R5: div $zero, $4, $5 117 ; R2-R5: teq $5, $zero, 7 118 ; R2-R5: mflo $[[T0:[0-9]+]] 119 ; FIXME: This is instruction is redundant since div is signed. 120 ; R2-R5: seh $2, $[[T0]] 121 122 ; R6: div $[[T0:[0-9]+]], $4, $5 123 ; R6: teq $5, $zero, 7 124 ; FIXME: This is instruction is redundant since div is signed. 125 ; R6: seh $2, $[[T0]] 126 127 ; MMR3: div $zero, $4, $5 128 ; MMR3: teq $5, $zero, 7 129 ; MMR3: mflo $[[T0:[0-9]+]] 130 ; MMR3: seh $2, $[[T0]] 131 132 ; MMR6: div $[[T0:[0-9]+]], $4, $5 133 ; MMR6: teq $5, $zero, 7 134 ; MMR6: seh $2, $[[T0]] 135 136 %r = sdiv i16 %a, %b 137 ret i16 %r 138} 139 140define signext i32 @sdiv_i32(i32 signext %a, i32 signext %b) { 141entry: 142; ALL-LABEL: sdiv_i32: 143 144 ; NOT-R6: div $zero, $4, $5 145 ; NOT-R6: teq $5, $zero, 7 146 ; NOT-R6: mflo $2 147 148 ; R6: div $2, $4, $5 149 ; R6: teq $5, $zero, 7 150 151 ; MMR3: div $zero, $4, $5 152 ; MMR3: teq $5, $zero, 7 153 ; MMR3: mflo $2 154 155 ; MMR6: div $2, $4, $5 156 ; MMR6: teq $5, $zero, 7 157 158 %r = sdiv i32 %a, %b 159 ret i32 %r 160} 161 162define signext i64 @sdiv_i64(i64 signext %a, i64 signext %b) { 163entry: 164; ALL-LABEL: sdiv_i64: 165 166 ; GP32: lw $25, %call16(__divdi3)($gp) 167 168 ; GP64-NOT-R6: ddiv $zero, $4, $5 169 ; GP64-NOT-R6: teq $5, $zero, 7 170 ; GP64-NOT-R6: mflo $2 171 172 ; 64R6: ddiv $2, $4, $5 173 ; 64R6: teq $5, $zero, 7 174 175 ; MM32: lw $25, %call16(__divdi3)($2) 176 177 ; MM64: ddiv $2, $4, $5 178 ; MM64: teq $5, $zero, 7 179 180 %r = sdiv i64 %a, %b 181 ret i64 %r 182} 183 184define signext i128 @sdiv_i128(i128 signext %a, i128 signext %b) { 185entry: 186 ; ALL-LABEL: sdiv_i128: 187 188 ; GP32: lw $25, %call16(__divti3)($gp) 189 190 ; GP64-NOT-R6: ld $25, %call16(__divti3)($gp) 191 ; 64R6: ld $25, %call16(__divti3)($gp) 192 193 ; MM32: lw $25, %call16(__divti3)($16) 194 195 ; MM64: ld $25, %call16(__divti3)($2) 196 197 %r = sdiv i128 %a, %b 198 ret i128 %r 199} 200