1; Positive test for inline register constraints
2;
3; RUN: llc -march=mipsel < %s  | FileCheck %s -check-prefix=LITTLE
4; RUN: llc -march=mips < %s  | FileCheck %s -check-prefix=BIG
5
6%union.u_tag = type { i64 }
7%struct.anon = type { i32, i32 }
8@uval = common global %union.u_tag zeroinitializer, align 8
9define i32 @main() nounwind {
10entry:
11
12; X with -3
13;LITTLE:	#APP
14;LITTLE:	addi ${{[0-9]+}},${{[0-9]+}},0xfffffffffffffffd
15;LITTLE:	#NO_APP
16  tail call i32 asm sideeffect "addi $0,$1,${2:X}", "=r,r,I"(i32 7, i32 -3) nounwind
17
18; x with -3
19;LITTLE:	#APP
20;LITTLE:	addi ${{[0-9]+}},${{[0-9]+}},0xfffd
21;LITTLE:	#NO_APP
22  tail call i32 asm sideeffect "addi $0,$1,${2:x}", "=r,r,I"(i32 7, i32 -3) nounwind
23
24; d with -3
25;LITTLE:	#APP
26;LITTLE:	addi ${{[0-9]+}},${{[0-9]+}},-3
27;LITTLE:	#NO_APP
28  tail call i32 asm sideeffect "addi $0,$1,${2:d}", "=r,r,I"(i32 7, i32 -3) nounwind
29
30; m with -3
31;LITTLE:	#APP
32;LITTLE:	addi ${{[0-9]+}},${{[0-9]+}},-4
33;LITTLE:	#NO_APP
34  tail call i32 asm sideeffect "addi $0,$1,${2:m}", "=r,r,I"(i32 7, i32 -3) nounwind
35
36; z with -3
37;LITTLE:	#APP
38;LITTLE:	addi ${{[0-9]+}},${{[0-9]+}},-3
39;LITTLE:	#NO_APP
40  tail call i32 asm sideeffect "addi $0,$1,${2:z}", "=r,r,I"(i32 7, i32 -3) nounwind
41
42; z with 0
43;LITTLE:	#APP
44;LITTLE:	addi ${{[0-9]+}},${{[0-9]+}},$0
45;LITTLE:	#NO_APP
46  tail call i32 asm sideeffect "addi $0,$1,${2:z}", "=r,r,I"(i32 7, i32 0) nounwind
47
48; a long long in 32 bit mode (use to assert)
49;LITTLE:	#APP
50;LITTLE:	addi ${{[0-9]+}},${{[0-9]+}},3
51;LITTLE:	#NO_APP
52  tail call i64 asm sideeffect "addi $0,$1,$2 \0A\09", "=r,r,X"(i64 1229801703532086340, i64 3) nounwind
53
54; D, in little endian the source reg will be 4 bytes into the long long
55;LITTLE:    lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
56;LITTLE:    lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
57;LITTLE-NEXT: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
58;LITTLE:	#APP
59;LITTLE:    or	${{[0-9]+}},$[[FIRST]],${{[0-9]+}}
60;LITTLE:    #NO_APP
61
62; D, in big endian the source reg will also be 4 bytes into the long long
63;BIG:       #APP
64;BIG:       #APP
65;BIG:       #APP
66;BIG:       #APP
67;BIG:       #APP
68;BIG:       #APP
69;BIG:       #APP
70;BIG:       lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
71;BIG:       lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
72;BIG-NEXT:  lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
73;BIG:       #APP
74;BIG:       or	${{[0-9]+}},$[[SECOND]],${{[0-9]+}}
75;BIG:       #NO_APP
76  %7 = load i64* getelementptr inbounds (%union.u_tag* @uval, i32 0, i32 0), align 8
77  %trunc1 = trunc i64 %7 to i32
78  tail call i32 asm sideeffect "or $0,${1:D},$2", "=r,r,r"(i64 %7, i32 %trunc1) nounwind
79
80; L, in little endian the source reg will be 4 bytes into the long long
81;LITTLE:	#APP
82;LITTLE:	     or	${{[0-9]+}},$[[SECOND]],${{[0-9]+}}
83;LITTLE:	#NO_APP
84; L, in big endian the source reg will be 0 bytes into the long long
85;BIG:	#APP
86;BIG:	     or	${{[0-9]+}},$[[FIRST]],${{[0-9]+}}
87;BIG:	#NO_APP
88  tail call i32 asm sideeffect "or $0,${1:L},$2", "=r,r,r"(i64 %7, i32 %trunc1) nounwind
89
90  ret i32 0
91}
92
93