1; RUN: llc -march=mipsel < %s | FileCheck %s
2; RUN: llc -march=mips64el < %s | FileCheck %s -check-prefixes=CHECK,CHECK64
3
4; CHECK-LABEL: mul5_32:
5; CHECK: sll $[[R0:[0-9]+]], $4, 2
6; CHECK: addu ${{[0-9]+}}, $[[R0]], $4
7
8define i32 @mul5_32(i32 signext %a) {
9entry:
10  %mul = mul nsw i32 %a, 5
11  ret i32 %mul
12}
13
14; CHECK-LABEL:     mul27_32:
15; CHECK-DAG: sll $[[R0:[0-9]+]], $4, 2
16; CHECK-DAG: addu $[[R1:[0-9]+]], $[[R0]], $4
17; CHECK-DAG: sll $[[R2:[0-9]+]], $4, 5
18; CHECK:     subu ${{[0-9]+}}, $[[R2]], $[[R1]]
19
20define i32 @mul27_32(i32 signext %a) {
21entry:
22  %mul = mul nsw i32 %a, 27
23  ret i32 %mul
24}
25
26; CHECK-LABEL:     muln2147483643_32:
27; CHECK-DAG: sll $[[R0:[0-9]+]], $4, 2
28; CHECK-DAG: addu $[[R1:[0-9]+]], $[[R0]], $4
29; CHECK-DAG: sll $[[R2:[0-9]+]], $4, 31
30; CHECK:     addu ${{[0-9]+}}, $[[R2]], $[[R1]]
31
32define i32 @muln2147483643_32(i32 signext %a) {
33entry:
34  %mul = mul nsw i32 %a, -2147483643
35  ret i32 %mul
36}
37
38; CHECK64-LABEL:     muln9223372036854775805_64:
39; CHECK64-DAG: dsll $[[R0:[0-9]+]], $4, 1
40; CHECK64-DAG: daddu $[[R1:[0-9]+]], $[[R0]], $4
41; CHECK64-DAG: dsll $[[R2:[0-9]+]], $4, 63
42; CHECK64:     daddu ${{[0-9]+}}, $[[R2]], $[[R1]]
43
44define i64 @muln9223372036854775805_64(i64 signext %a) {
45entry:
46  %mul = mul nsw i64 %a, -9223372036854775805
47  ret i64 %mul
48}
49
50; CHECK64-LABEL:     muln170141183460469231731687303715884105725_128:
51; CHECK64-DAG: dsrl $[[R0:[0-9]+]], $4, 63
52; CHECK64-DAG: dsll $[[R1:[0-9]+]], $5, 1
53; CHECK64-DAG: or $[[R2:[0-9]+]], $[[R1]], $[[R0]]
54; CHECK64-DAG: daddu $[[R3:[0-9]+]], $[[R2]], $5
55; CHECK64-DAG: dsll $[[R4:[0-9]+]], $4, 1
56; CHECK64-DAG: daddu $[[R5:[0-9]+]], $[[R4]], $4
57; CHECK64-DAG: sltu $[[R6:[0-9]+]], $[[R5]], $[[R4]]
58; CHECK64-DAG: dsll $[[R7:[0-9]+]], $[[R6]], 32
59; CHECK64-DAG: dsrl $[[R8:[0-9]+]], $[[R7]], 32
60; CHECK64-DAG: daddu $[[R9:[0-9]+]], $[[R3]], $[[R8]]
61; CHECK64-DAG: dsll $[[R10:[0-9]+]], $4, 63
62; CHECK64:     daddu ${{[0-9]+}}, $[[R10]], $[[R9]]
63
64define i128 @muln170141183460469231731687303715884105725_128(i128 signext %a) {
65entry:
66  %mul = mul nsw i128 %a, -170141183460469231731687303715884105725
67  ret i128 %mul
68}
69
70; CHECK64-LABEL:     mul170141183460469231731687303715884105723_128:
71; CHECK64-DAG: dsrl $[[R0:[0-9]+]], $4, 62
72; CHECK64-DAG: dsll $[[R1:[0-9]+]], $5, 2
73; CHECK64-DAG: or $[[R2:[0-9]+]], $[[R1]], $[[R0]]
74; CHECK64-DAG: daddu $[[R3:[0-9]+]], $[[R2]], $5
75; CHECK64-DAG: dsll $[[R4:[0-9]+]], $4, 2
76; CHECK64-DAG: daddu $[[R5:[0-9]+]], $[[R4]], $4
77; CHECK64-DAG: sltu $[[R6:[0-9]+]], $[[R5]], $[[R4]]
78; CHECK64-DAG: dsll $[[R7:[0-9]+]], $[[R6]], 32
79; CHECK64-DAG: dsrl $[[R8:[0-9]+]], $[[R7]], 32
80; CHECK64-DAG: daddu $[[R9:[0-9]+]], $[[R3]], $[[R8]]
81; CHECK64-DAG: dsll $[[R10:[0-9]+]], $4, 63
82; CHECK64-DAG: dsubu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
83; CHECK64-DAG: sltu $[[R12:[0-9]+]], $zero, $[[R5]]
84; CHECK64-DAG: dsll $[[R13:[0-9]+]], $[[R12]], 32
85; CHECK64-DAG: dsrl $[[R14:[0-9]+]], $[[R13]], 32
86; CHECK64-DAG: dsubu $[[R15:[0-9]+]], $[[R11]], $[[R14]]
87; CHECK64:     dnegu ${{[0-9]+}}, $[[R5]]
88
89define i128 @mul170141183460469231731687303715884105723_128(i128 signext %a) {
90entry:
91  %mul = mul nsw i128 %a, 170141183460469231731687303715884105723
92  ret i128 %mul
93}
94