1; RUN: llc < %s -march=mips -mcpu=mips32 -disable-mips-delay-filler | FileCheck %s --check-prefixes=ALL,MIPS32,MIPS32EB 2; RUN: llc < %s -march=mips64 -relocation-model=pic -mcpu=mips64 -disable-mips-delay-filler | FileCheck %s --check-prefixes=ALL,MIPS64,MIPS64EB 3; RUN: llc < %s -march=mips -mcpu=mips32r5 -mattr=+fp64,+msa -disable-mips-delay-filler | FileCheck %s --check-prefixes=ALL,MIPS32R5,MIPS32R5EB 4; RUN: llc < %s -march=mips64 -relocation-model=pic -mcpu=mips64r5 -mattr=+fp64,+msa -disable-mips-delay-filler | FileCheck %s --check-prefixes=ALL,MIPS64R5 5; RUN: llc < %s -march=mipsel -mcpu=mips32 -disable-mips-delay-filler | FileCheck %s --check-prefixes=ALL,MIPS32,MIPS32EL 6; RUN: llc < %s -march=mips64el -relocation-model=pic -mcpu=mips64 -disable-mips-delay-filler | FileCheck %s --check-prefixes=ALL,MIPS64,MIPS64EL 7; RUN: llc < %s -march=mipsel -mcpu=mips32r5 -mattr=+fp64,+msa -disable-mips-delay-filler | FileCheck %s --check-prefixes=ALL,MIPS32R5,MIPS32R5EL 8; RUN: llc < %s -march=mips64el -relocation-model=pic -mcpu=mips64r5 -mattr=+fp64,+msa -disable-mips-delay-filler | FileCheck %s --check-prefixes=ALL,MIPS64R5 9 10 11 12; Test that vector types are passed through the integer register set whether or 13; not MSA is enabled. This is a ABI requirement for MIPS. For GCC compatibility 14; we need to handle any power of 2 number of elements. We will test this 15; exhaustively for combinations up to MSA register (128 bits) size. 16 17; First set of tests are for argument passing. 18 19define <2 x i8> @i8_2(<2 x i8> %a, <2 x i8> %b) { 20; ALL-LABEL: i8_2: 21; MIPS32EB-DAG: srl ${{[0-9]+}}, $5, 24 22; MIPS32EB-DAG: srl ${{[0-9]+}}, $4, 24 23; MIPS32EB-DAG: srl ${{[0-9]+}}, $5, 16 24; MIPS32EB-DAG: srl ${{[0-9]+}}, $4, 16 25 26; MIPS32EL: addu $1, $4, $5 27 28; MIPS32R5-DAG: sw $4 29; MIPS32R5-DAG: sw $5 30 31; MIPS64EB-DAG: dsrl ${{[0-9]+}}, $5, 56 32; MIPS64EB-DAG: dsrl ${{[0-9]+}}, $4, 56 33; MIPS64EB-DAG: dsrl ${{[0-9]+}}, $5, 48 34; MIPS64EB-DAG: dsrl ${{[0-9]+}}, $4, 48 35 36; MIPS64EL-DAG: sll ${{[0-9]+}}, $4, 0 37; MIPS64EL-DAG: sll ${{[0-9]+}}, $5, 0 38 39; MIPS64R5-DAG: sd $4 40; MIPS64R5-DAG: sd $5 41 42 %1 = add <2 x i8> %a, %b 43 ret <2 x i8> %1 44} 45 46; Test that vector spilled to the outgoing argument area have the expected 47; offset from $sp. 48 49define <2 x i8> @i8x2_7(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d, 50 <2 x i8> %e, <2 x i8> %f, <2 x i8> %g) { 51entry: 52 53; MIPS32EB-DAG: srl ${{[0-9]+}}, $4, 24 54; MIPS32EB-DAG: srl ${{[0-9]+}}, $5, 24 55; MIPS32EB-DAG: srl ${{[0-9]+}}, $6, 24 56; MIPS32EB-DAG: srl ${{[0-9]+}}, $7, 24 57 58; MIPS32EL-DAG: andi ${{[0-9]+}}, $4, 65280 59; MIPS32EL-DAG: andi ${{[0-9]+}}, $5, 65280 60; MIPS32EL-DAG: andi ${{[0-9]+}}, $6, 65280 61; MIPS32EL-DAG: andi ${{[0-9]+}}, $7, 65280 62 63; MIPS32-DAG: lbu ${{[0-9]+}}, 16($sp) 64; MIPS32-DAG; lbu ${{[0-9]+}}, 17($sp) 65; MIPS32-DAG: lbu ${{[0-9]+}}, 20($sp) 66; MIPS32-DAG: lbu ${{[0-9]+}}, 21($sp) 67; MIPS32-DAG: lbu ${{[0-9]+}}, 24($sp) 68; MIPS32-DAG: lbu ${{[0-9]+}}, 25($sp) 69 70; MIPS32R5-DAG: sw $4, {{[0-9]+}}($sp) 71; MIPS32R5-DAG: sw $5, {{[0-9]+}}($sp) 72; MIPS32R5-DAG: sw $6, {{[0-9]+}}($sp) 73; MIPS32R5-DAG: sw $7, {{[0-9]+}}($sp) 74 75; MIPS32R5-DAG: lbu ${{[0-9]+}}, 40($sp) 76; MIPS32R5-DAG: lbu ${{[0-9]+}}, 41($sp) 77; MIPS32R5-DAG: lbu ${{[0-9]+}}, 42($sp) 78; MIPS32R5-DAG: lbu ${{[0-9]+}}, 43($sp) 79; MIPS32R5-DAG: lbu ${{[0-9]+}}, 44($sp) 80; MIPS32R5-DAG: lbu ${{[0-9]+}}, 45($sp) 81; MIPS32R5-DAG: lbu ${{[0-9]+}}, 46($sp) 82; MIPS32R5-DAG: lbu ${{[0-9]+}}, 47($sp) 83; MIPS32R5-DAG: lbu ${{[0-9]+}}, 48($sp) 84; MIPS32R5-DAG: lbu ${{[0-9]+}}, 49($sp) 85; MIPS32R5-DAG: lbu ${{[0-9]+}}, 50($sp) 86; MIPS32R5-DAG: lbu ${{[0-9]+}}, 51($sp) 87 88; MIPS64EB-DAG: dsrl ${{[0-9]+}}, $4, 48 89; MIPS64EB-DAG: dsrl ${{[0-9]+}}, $5, 48 90; MIPS64EB-DAG: dsrl ${{[0-9]+}}, $6, 48 91; MIPS64EB-DAG: dsrl ${{[0-9]+}}, $7, 48 92; MIPS64EB-DAG: dsrl ${{[0-9]+}}, $8, 48 93; MIPS64EB-DAG: dsrl ${{[0-9]+}}, $9, 48 94; MIPS64EB-DAG: dsrl ${{[0-9]+}}, $10, 48 95 96; MIPS64R5-DAG: sd $4, {{[0-9]+}}($sp) 97; MIPS64R5-DAG: sd $5, {{[0-9]+}}($sp) 98; MIPS64R5-DAG: sd $6, {{[0-9]+}}($sp) 99; MIPS64R5-DAG: sd $7, {{[0-9]+}}($sp) 100; MIPS64R5-DAG: sd $8, {{[0-9]+}}($sp) 101; MIPS64R5-DAG: sd $9, {{[0-9]+}}($sp) 102; MIPS64R5-DAG: sd $10, {{[0-9]+}}($sp) 103 104 %0 = add <2 x i8> %a, %b 105 %1 = add <2 x i8> %0, %c 106 %2 = add <2 x i8> %1, %d 107 %3 = add <2 x i8> %2, %e 108 %4 = add <2 x i8> %3, %f 109 %5 = add <2 x i8> %4, %g 110 ret <2 x i8> %5 111} 112 113define <4 x i8> @i8_4(<4 x i8> %a, <4 x i8> %b) { 114; ALL-LABEL: i8_4: 115; MIPS32-DAG: srl ${{[0-9]+}}, $5, 24 116; MIPS32-DAG: srl ${{[0-9]+}}, $4, 24 117; MIPS32-DAG: srl ${{[0-9]+}}, $5, 16 118; MIPS32-DAG: srl ${{[0-9]+}}, $4, 16 119; MIPS32-DAG: srl ${{[0-9]+}}, $5, 8 120; MIPS32-DAG: srl ${{[0-9]+}}, $4, 8 121 122; MIPS32R5-DAG: sw $4 123; MIPS32R5-DAG: sw $5 124 125; MIPS64-DAG: sll ${{[0-9]+}}, $4, 0 126; MIPS64-DAG: sll ${{[0-9]+}}, $5, 0 127 128; MIPS64R5-DAG: sll ${{[0-9]+}}, $4, 0 129; MIPS64R5-DAG: sll ${{[0-9]+}}, $5, 0 130 131 %1 = add <4 x i8> %a, %b 132 ret <4 x i8> %1 133} 134 135define <8 x i8> @i8_8(<8 x i8> %a, <8 x i8> %b) { 136; ALL-LABEL: i8_8: 137; MIPS32-NOT: lw 138; MIPS32-DAG: srl ${{[0-9]+}}, $7, 24 139; MIPS32-DAG: srl ${{[0-9]+}}, $6, 24 140; MIPS32-DAG: srl ${{[0-9]+}}, $7, 16 141; MIPS32-DAG: srl ${{[0-9]+}}, $6, 16 142; MIPS32-DAG: srl ${{[0-9]+}}, $7, 8 143; MIPS32-DAG: srl ${{[0-9]+}}, $6, 8 144; MIPS32-DAG: srl ${{[0-9]+}}, $5, 24 145; MIPS32-DAG: srl ${{[0-9]+}}, $4, 24 146; MIPS32-DAG: srl ${{[0-9]+}}, $5, 16 147; MIPS32-DAG: srl ${{[0-9]+}}, $4, 16 148; MIPS32-DAG: srl ${{[0-9]+}}, $5, 8 149; MIPS32-DAG: srl ${{[0-9]+}}, $4, 8 150 151; MIPS32R5-DAG: sw $4 152; MIPS32R5-DAG: sw $5 153; MIPS32R5-DAG: sw $6 154; MIPS32R5-DAG: sw $7 155 156; MIPS64-DAG: dsrl ${{[0-9]+}}, $5, 56 157; MIPS64-DAG: dsrl ${{[0-9]+}}, $4, 56 158; MIPS64-DAG: dsrl ${{[0-9]+}}, $5, 48 159; MIPS64-DAG: dsrl ${{[0-9]+}}, $4, 48 160; MIPS64-DAG: dsrl ${{[0-9]+}}, $5, 40 161; MIPS64-DAG: dsrl ${{[0-9]+}}, $4, 40 162; MIPS64-DAG: dsrl ${{[0-9]+}}, $5, 32 163; MIPS64-DAG: dsrl ${{[0-9]+}}, $4, 32 164; MIPS64-DAG: sll $[[R0:[0-9]+]], $4, 0 165; MIPS64-DAG: sll $[[R1:[0-9]+]], $5, 0 166; MIPS64-DAG: srl ${{[0-9]+}}, $[[R1]], 24 167; MIPS64-DAG: srl ${{[0-9]+}}, $[[R0]], 24 168; MIPS64-DAG: srl ${{[0-9]+}}, $[[R1]], 16 169; MIPS64-DAG: srl ${{[0-9]+}}, $[[R0]], 16 170; MIPS64-DAG: srl ${{[0-9]+}}, $[[R1]], 8 171; MIPS64-DAG: srl ${{[0-9]+}}, $[[R0]], 8 172 173; MIPS64R5-DAG: sd $4 174; MIPS64R5-DAG: sd $5 175 176 %1 = add <8 x i8> %a, %b 177 ret <8 x i8> %1 178} 179 180define <16 x i8> @i8_16(<16 x i8> %a, <16 x i8> %b) { 181; ALL-LABEL: i8_16: 182; MIPS32-DAG: lw ${{[0-9]+}}, 16($sp) 183; MIPS32-DAG: lw ${{[0-9]+}}, 20($sp) 184; MIPS32-DAG: lw ${{[0-9]+}}, 24($sp) 185; MIPS32-DAG: lw ${{[0-9]+}}, 28($sp) 186; MIPS32-DAG: srl ${{[0-9]+}}, $7, 24 187; MIPS32-DAG: srl ${{[0-9]+}}, $6, 24 188; MIPS32-DAG: srl ${{[0-9]+}}, $7, 16 189; MIPS32-DAG: srl ${{[0-9]+}}, $6, 16 190; MIPS32-DAG: srl ${{[0-9]+}}, $7, 8 191; MIPS32-DAG: srl ${{[0-9]+}}, $6, 8 192; MIPS32-DAG: srl ${{[0-9]+}}, $5, 24 193; MIPS32-DAG: srl ${{[0-9]+}}, $4, 24 194; MIPS32-DAG: srl ${{[0-9]+}}, $5, 16 195; MIPS32-DAG: srl ${{[0-9]+}}, $4, 16 196; MIPS32-DAG: srl ${{[0-9]+}}, $5, 8 197; MIPS32-DAG: srl ${{[0-9]+}}, $4, 8 198 199; MIPS32R5-DAG: lw ${{[0-9]+}}, 16($sp) 200; MIPS32R5-DAG: lw ${{[0-9]+}}, 20($sp) 201; MIPS32R5-DAG: lw ${{[0-9]+}}, 24($sp) 202; MIPS32R5-DAG: lw ${{[0-9]+}}, 28($sp) 203; MIPS32R5-DAG: insert.w $w[[W0:[0-9]+]][0], $4 204; MIPS32R5-DAG: insert.w $w[[W0]][1], $5 205; MIPS32R5-DAG: insert.w $w[[W0]][2], $6 206; MIPS32R5-DAG: insert.w $w[[W0]][3], $7 207 208; MIPS64-DAG: dsrl ${{[0-9]+}}, $7, 56 209; MIPS64-DAG: dsrl ${{[0-9]+}}, $6, 56 210; MIPS64-DAG: dsrl ${{[0-9]+}}, $7, 48 211; MIPS64-DAG: dsrl ${{[0-9]+}}, $6, 48 212; MIPS64-DAG: dsrl ${{[0-9]+}}, $7, 40 213; MIPS64-DAG: dsrl ${{[0-9]+}}, $6, 40 214; MIPS64-DAG: dsrl ${{[0-9]+}}, $7, 32 215; MIPS64-DAG: dsrl ${{[0-9]+}}, $6, 32 216; MIPS64-DAG: dsrl ${{[0-9]+}}, $5, 56 217; MIPS64-DAG: dsrl ${{[0-9]+}}, $4, 56 218; MIPS64-DAG: dsrl ${{[0-9]+}}, $5, 48 219; MIPS64-DAG: dsrl ${{[0-9]+}}, $4, 48 220; MIPS64-DAG: dsrl ${{[0-9]+}}, $5, 32 221; MIPS64-DAG: dsrl ${{[0-9]+}}, $4, 32 222 223; MIPS64R5-DAG: insert.d $w[[W0:[0-9]+]][{{[0-9]}}], $4 224; MIPS64R5-DAG: insert.d $w[[W0]][{{[0-9]}}], $5 225; MIPS64R5-DAG: insert.d $w[[W1:[0-9]+]][{{[0-9]}}], $6 226; MIPS64R5-DAG: insert.d $w[[W1]][{{[0-9]}}], $7 227 228 %1 = add <16 x i8> %a, %b 229 230 ret <16 x i8> %1 231} 232 233define <2 x i16> @i16_2(<2 x i16> %a, <2 x i16> %b) { 234; ALL-LABEL: i16_2: 235; MIPS32: addu $[[R0:[0-9]+]], $4, $5 236; MIPS32: andi $[[R1:[0-9]+]], $[[R0]], 65535 237; MIPS32: srl $[[R2:[0-9]+]], $5, 16 238; MIPS32: srl $[[R3:[0-9]+]], $4, 16 239; MIPS32: addu $[[R4:[0-9]+]], $[[R3]], $[[R2]] 240; MIPS32: sll $2, $[[R4]], 16 241 242; MIPS32R5-DAG: sw $4 243; MIPS32R5-DAG: sw $5 244 245; MIPS64-DAG: sll ${{[0-9]+}}, $5, 0 246; MIPS64-DAG: sll ${{[0-9]+}}, $4, 0 247 248; MIPS64R5-DAG: sll ${{[0-9]+}}, $4, 0 249; MIPS64R5-DAG: sll ${{[0-9]+}}, $5, 0 250 251 %1 = add <2 x i16> %a, %b 252 ret <2 x i16> %1 253} 254 255define <4 x i16> @i16_4(<4 x i16> %a, <4 x i16> %b) { 256; ALL-LABEL: i16_4: 257; MIPS32-DAG: srl ${{[0-9]+}}, $7, 16 258; MIPS32-DAG: srl ${{[0-9]+}}, $6, 16 259; MIPS32-DAG: srl ${{[0-9]+}}, $5, 16 260; MIPS32-DAG: srl ${{[0-9]+}}, $4, 16 261 262; MIPS32R5-DAG: sw $4 263; MIPS32R5-DAG: sw $5 264; MIPS32R5-DAG: sw $6 265; MIPS32R5-DAG: sw $7 266 267; MIPS64-DAG: dsrl ${{[0-9]+}}, $4, 48 268; MIPS64-DAG: dsrl ${{[0-9]+}}, $5, 48 269; MIPS64-DAG: dsrl ${{[0-9]+}}, $4, 32 270; MIPS64-DAG: dsrl ${{[0-9]+}}, $5, 32 271 272; MIPS64R5-DAG: sd $4 273; MIPS64R5-DAG: sd $5 274 275 %1 = add <4 x i16> %a, %b 276 ret <4 x i16> %1 277} 278 279define <8 x i16> @i16_8(<8 x i16> %a, <8 x i16> %b) { 280; ALL-LABEL: i16_8: 281; MIPS32-DAG: lw ${{[0-9]+}}, 16($sp) 282; MIPS32-DAG: lw ${{[0-9]+}}, 20($sp) 283; MIPS32-DAG: lw ${{[0-9]+}}, 24($sp) 284; MIPS32-DAG: lw ${{[0-9]+}}, 28($sp) 285; MIPS32-DAG: srl ${{[0-9]+}}, $7, 16 286; MIPS32-DAG: srl ${{[0-9]+}}, $6, 16 287; MIPS32-DAG: srl ${{[0-9]+}}, $5, 16 288; MIPS32-DAG: srl ${{[0-9]+}}, $4, 16 289 290; MIPS32R5-DAG: lw ${{[0-9]+}}, 16($sp) 291; MIPS32R5-DAG: lw ${{[0-9]+}}, 20($sp) 292; MIPS32R5-DAG: lw ${{[0-9]+}}, 24($sp) 293; MIPS32R5-DAG: lw ${{[0-9]+}}, 28($sp) 294; MIPS32R5-DAG: insert.w $w[[W0:[0-9]+]][0], $4 295; MIPS32R5-DAG: insert.w $w[[W0]][1], $5 296; MIPS32R5-DAG: insert.w $w[[W0]][2], $6 297; MIPS32R5-DAG: insert.w $w[[W0]][3], $7 298 299; MIPS64-DAG: dsrl ${{[0-9]+}}, $6, 48 300; MIPS64-DAG: dsrl ${{[0-9]+}}, $7, 48 301; MIPS64-DAG: dsrl ${{[0-9]+}}, $6, 32 302; MIPS64-DAG: dsrl ${{[0-9]+}}, $7, 32 303; MIPS64-DAG: dsrl ${{[0-9]+}}, $4, 48 304; MIPS64-DAG: dsrl ${{[0-9]+}}, $5, 48 305; MIPS64-DAG: dsrl ${{[0-9]+}}, $4, 32 306; MIPS64-DAG: dsrl ${{[0-9]+}}, $5, 32 307 308; MIPS64R5-DAG: insert.d $w[[W0:[0-9]+]][{{[0-9]}}], $4 309; MIPS64R5-DAG: insert.d $w[[W0]][{{[0-9]}}], $5 310; MIPS64R5-DAG: insert.d $w[[W1:[0-9]+]][{{[0-9]}}], $6 311; MIPS64R5-DAG: insert.d $w[[W1]][{{[0-9]}}], $7 312 313 %1 = add <8 x i16> %a, %b 314 ret <8 x i16> %1 315} 316 317define <2 x i32> @i32_2(<2 x i32> %a, <2 x i32> %b) { 318; ALL-LABEL: i32_2: 319; MIPS32-DAG: addu $2, $4, $6 320; MIPS32-DAG: addu $3, $5, $7 321 322; MIPS32R5-DAG: sw $4 323; MIPS32R5-DAG: sw $5 324; MIPS32R5-DAG: sw $6 325; MIPS32R5-DAG: sw $7 326 327; MIPS64-DAG: sll ${{[0-9]+}}, $4, 0 328; MIPS64-DAG: sll ${{[0-9]+}}, $5, 0 329 330; MIPS64R5-DAG: sd $4 331; MIPS64R5-DAG: sd $5 332 333 %1 = add <2 x i32> %a, %b 334 335 ret <2 x i32> %1 336} 337 338define <4 x i32> @i32_4(<4 x i32> %a, <4 x i32> %b) { 339; ALL-LABEL: i32_4: 340; MIPS32-DAG: lw ${{[0-9]+}}, 16($sp) 341; MIPS32-DAG: lw ${{[0-9]+}}, 20($sp) 342; MIPS32-DAG: lw ${{[0-9]+}}, 24($sp) 343; MIPS32-DAG: lw ${{[0-9]+}}, 28($sp) 344; MIPS32-DAG: addu $2 345; MIPS32-DAG: addu $3 346; MIPS32-DAG: addu $4 347; MIPS32-DAG: addu $5 348 349; MIPS32R5-DAG: lw ${{[0-9]+}}, 16($sp) 350; MIPS32R5-DAG: lw ${{[0-9]+}}, 20($sp) 351; MIPS32R5-DAG: lw ${{[0-9]+}}, 24($sp) 352; MIPS32R5-DAG: lw ${{[0-9]+}}, 28($sp) 353; MIPS32R5-DAG: insert.w $w[[W0:[0-9]+]][0], $4 354; MIPS32R5-DAG: insert.w $w[[W0]][1], $5 355; MIPS32R5-DAG: insert.w $w[[W0]][2], $6 356; MIPS32R5-DAG: insert.w $w[[W0]][3], $7 357 358; MIPS64-DAG: sll ${{[0-9]+}}, $4, 0 359; MIPS64-DAG: sll ${{[0-9]+}}, $5, 0 360; MIPS64-DAG: sll ${{[0-9]+}}, $6, 0 361; MIPS64-DAG: sll ${{[0-9]+}}, $7, 0 362; MIPS64-DAG: dsrl ${{[0-9]+}}, $4, 32 363; MIPS64-DAG: dsrl ${{[0-9]+}}, $5, 32 364; MIPS64-DAG: dsrl ${{[0-9]+}}, $6, 32 365; MIPS64-DAG: dsrl ${{[0-9]+}}, $7, 32 366 %1 = add <4 x i32> %a, %b 367 ret <4 x i32> %1 368} 369 370define <2 x i64> @i64_2(<2 x i64> %a, <2 x i64> %b) { 371; ALL-LABEL: i64_2: 372; MIPS32-DAG: lw ${{[0-9]+}}, 16($sp) 373; MIPS32-DAG: lw ${{[0-9]+}}, 20($sp) 374; MIPS32-DAG: lw ${{[0-9]+}}, 24($sp) 375; MIPS32-DAG: lw ${{[0-9]+}}, 28($sp) 376; MIPS32-DAG: addu $2 377; MIPS32-DAG: addu $3 378; MIPS32-DAG: addu $4 379; MIPS32-DAG: addu $5 380 381; MIPS32R5-DAG: lw ${{[0-9]+}}, 16($sp) 382; MIPS32R5-DAG: lw ${{[0-9]+}}, 20($sp) 383; MIPS32R5-DAG: lw ${{[0-9]+}}, 24($sp) 384; MIPS32R5-DAG: lw ${{[0-9]+}}, 28($sp) 385; MIPS32R5-DAG: insert.w $w[[W0:[0-9]+]][0], $4 386; MIPS32R5-DAG: insert.w $w[[W0]][1], $5 387; MIPS32R5-DAG: insert.w $w[[W0]][2], $6 388; MIPS32R5-DAG: insert.w $w[[W0]][3], $7 389 390; MIPS64-DAG: daddu $2, $4, $6 391; MIPS64-DAG: daddu $3, $5, $7 392 393; MIPS64R5-DAG: insert.d $w[[W0:[0-9]+]][{{[0-9]}}], $4 394; MIPS64R5-DAG: insert.d $w[[W0]][{{[0-9]}}], $5 395; MIPS64R5-DAG: insert.d $w[[W1:[0-9]+]][{{[0-9]}}], $6 396; MIPS64R5-DAG: insert.d $w[[W1]][{{[0-9]}}], $7 397 398 %1 = add <2 x i64> %a, %b 399 ret <2 x i64> %1 400} 401 402; The MIPS vector ABI treats vectors of floats differently to vectors of 403; integers. 404 405; For arguments floating pointer vectors are bitcasted to integer vectors whose 406; elements are of GPR width and where the element count is deduced from 407; the length of the floating point vector divided by the size of the GPRs. 408 409; For returns, integer vectors are passed via the GPR register set, but 410; floating point vectors are returned via a hidden sret pointer. 411 412; For testing purposes we skip returning values here and test them below 413; instead. 414@float_res_v2f32 = external global <2 x float> 415 416define void @float_2(<2 x float> %a, <2 x float> %b) { 417; ALL-LABEL: float_2: 418; MIPS32: mtc1 $7, $f[[F0:[0-9]+]] 419; MIPS32: mtc1 $5, $f[[F1:[0-9]+]] 420; MIPS32: add.s $f[[F2:[0-9]+]], $f[[F1]], $f[[F0]] 421; MIPS32: swc1 $f[[F2]] 422; MIPS32: mtc1 $6, $f[[F3:[0-9]+]] 423; MIPS32: mtc1 $4, $f[[F4:[0-9]+]] 424; MIPS32: add.s $f[[F5:[0-9]+]], $f[[F4]], $f[[F3]] 425; MIPS32: swc1 $f[[F5]] 426 427; MIPS32R5-DAG: sw $4 428; MIPS32R5-DAG: sw $5 429; MIPS32R5-DAG: sw $6 430; MIPS32R5-DAG: sw $7 431 432; MIPS64-DAG: sll $[[R0:[0-9]+]], $4, 0 433; MIPS64-DAG: sll $[[R1:[0-9]+]], $5, 0 434; MIPS64-DAG: mtc1 $[[R0]], $f{{[0-9]+}} 435; MIPS64-DAG: mtc1 $[[R1]], $f{{[0-9]+}} 436; MIPS64-DAG: dsrl $[[R2:[0-9]+]], $4, 32 437; MIPS64-DAG: dsrl $[[R3:[0-9]+]], $5, 32 438; MIPS64-DAG: sll $[[R4:[0-9]+]], $[[R2]], 0 439; MIPS64-DAG: sll $[[R5:[0-9]+]], $[[R3]], 0 440; MIPS64-DAG: mtc1 $[[R4]], $f{{[0-9]+}} 441; MIPS64-DAG: mtc1 $[[R5]], $f{{[0-9]+}} 442 443; MIPS64R5-DAG: sd $4 444; MIPS64R5-DAG: sd $5 445 446 %1 = fadd <2 x float> %a, %b 447 store <2 x float> %1, <2 x float> * @float_res_v2f32 448 ret void 449} 450 451@float_res_v4f32 = external global <4 x float> 452 453; For MSA this case is suboptimal, the 4 loads can be combined into a single 454; ld.w. 455 456define void @float_4(<4 x float> %a, <4 x float> %b) { 457; ALL-LABEL: float_4: 458; MIPS32-DAG: mtc1 $4 459; MIPS32-DAG: mtc1 $5 460; MIPS32-DAG: mtc1 $6 461; MIPS32-DAG: mtc1 $7 462; MIPS32-DAG: lwc1 463; MIPS32-DAG: lwc1 464; MIPS32-DAG: lwc1 465; MIPS32-DAG: lwc1 466 467; MIPS32R5-DAG: lw $[[R1:[0-9]+]], 16($sp) 468; MIPS32R5-DAG: insert.w $w[[W0:[0-9]+]][0], $[[R1]] 469; MIPS32R5-DAG: lw $[[R2:[0-9]+]], 20($sp) 470; MIPS32R5-DAG: insert.w $w[[W0]][1], $[[R2]] 471; MIPS32R5-DAG: lw $[[R3:[0-9]+]], 24($sp) 472; MIPS32R5-DAG: insert.w $w[[W0]][2], $[[R3]] 473; MIPS32R5-DAG: lw $[[R4:[0-9]+]], 28($sp) 474; MIPS32R5-DAG: insert.w $w[[W0]][3], $[[R4]] 475 476; MIPS32R5-DAG: insert.w $w[[W1:[0-9]+]][0], $4 477; MIPS32R5-DAG: insert.w $w[[W1]][1], $5 478; MIPS32R5-DAG: insert.w $w[[W1]][2], $6 479; MIPS32R5-DAG: insert.w $w[[W1]][3], $7 480 481; MIPS64-DAG: sll $[[R0:[0-9]+]], $4, 0 482; MIPS64-DAG: sll $[[R1:[0-9]+]], $5, 0 483; MIPS64-DAG: mtc1 $[[R0]], $f{{[0-9]+}} 484; MIPS64-DAG: mtc1 $[[R1]], $f{{[0-9]+}} 485; MIPS64-DAG: dsrl $[[R2:[0-9]+]], $4, 32 486; MIPS64-DAG: dsrl $[[R3:[0-9]+]], $5, 32 487; MIPS64-DAG: sll $[[R4:[0-9]+]], $[[R2]], 0 488; MIPS64-DAG: sll $[[R5:[0-9]+]], $[[R3]], 0 489; MIPS64-DAG: mtc1 $[[R4]], $f{{[0-9]+}} 490; MIPS64-DAG: mtc1 $[[R5]], $f{{[0-9]+}} 491; MIPS64-DAG: sll $[[R6:[0-9]+]], $6, 0 492; MIPS64-DAG: sll $[[R7:[0-9]+]], $7, 0 493; MIPS64-DAG: mtc1 $[[R6]], $f{{[0-9]+}} 494; MIPS64-DAG: mtc1 $[[R7]], $f{{[0-9]+}} 495; MIPS64-DAG: dsrl $[[R8:[0-9]+]], $6, 32 496; MIPS64-DAG: dsrl $[[R9:[0-9]+]], $7, 32 497; MIPS64-DAG: sll $[[R10:[0-9]+]], $[[R8]], 0 498; MIPS64-DAG: sll $[[R11:[0-9]+]], $[[R9]], 0 499; MIPS64-DAG: mtc1 $[[R10]], $f{{[0-9]+}} 500; MIPS64-DAG: mtc1 $[[R11]], $f{{[0-9]+}} 501 502; MIPS64R5-DAG: insert.d $w[[W0:[0-9]+]][{{[0-9]}}], $4 503; MIPS64R5-DAG: insert.d $w[[W0]][{{[0-9]}}], $5 504; MIPS64R5-DAG: insert.d $w[[W1:[0-9]+]][{{[0-9]}}], $6 505; MIPS64R5-DAG: insert.d $w[[W1]][{{[0-9]}}], $7 506 507 %1 = fadd <4 x float> %a, %b 508 store <4 x float> %1, <4 x float> * @float_res_v4f32 509 ret void 510} 511 512@double_v2f64 = external global <2 x double> 513 514define void @double_2(<2 x double> %a, <2 x double> %b) { 515; ALL-LABEL: double_2: 516; MIPS32-DAG: sw $7 517; MIPS32-DAG: sw $6 518; MIPS32-DAG: ldc1 519; MIPS32-DAG: ldc1 520; MIPS32: add.d 521; MIPS32-DAG: sw $5 522; MIPS32-DAG: sw $4 523; MIPS32-DAG: ldc1 524; MIPS32-DAG: ldc1 525; MIPS32: add.d 526 527; MIPS32R5-DAG: lw $[[R1:[0-9]+]], 16($sp) 528; MIPS32R5-DAG: insert.w $w[[W0:[0-9]+]][0], $[[R1]] 529; MIPS32R5-DAG: lw $[[R2:[0-9]+]], 20($sp) 530; MIPS32R5-DAG: insert.w $w[[W0]][1], $[[R2]] 531; MIPS32R5-DAG: lw $[[R3:[0-9]+]], 24($sp) 532; MIPS32R5-DAG: insert.w $w[[W0]][2], $[[R3]] 533; MIPS32R5-DAG: lw $[[R4:[0-9]+]], 28($sp) 534; MIPS32R5-DAG: insert.w $w[[W0]][3], $[[R4]] 535 536; MIPS32R5-DAG: insert.w $w[[W1:[0-9]+]][0], $4 537; MIPS32R5-DAG: insert.w $w[[W1]][1], $5 538; MIPS32R5-DAG: insert.w $w[[W1]][2], $6 539; MIPS32R5-DAG: insert.w $w[[W1]][3], $7 540 541; MIPS64-DAG: dmtc1 $6, $f[[R0:[0-9]+]] 542; MIPS64-DAG: dmtc1 $4, $f[[R1:[0-9]+]] 543; MIPS64-DAG: add.d $f[[R2:[0-9]+]], $f[[R1]], $f[[R0]] 544; MIPS64-DAG: dmtc1 $7, $f[[R3:[0-9]+]] 545; MIPS64-DAG: dmtc1 $5, $f[[R4:[0-9]+]] 546; MIPS64-DAG: add.d $f[[R5:[0-9]+]], $f[[R4]], $f[[R3]] 547 548; MIPS64R5-DAG: insert.d $w[[W0:[0-9]+]][{{[0-9]}}], $4 549; MIPS64R5-DAG: insert.d $w[[W0]][{{[0-9]}}], $5 550; MIPS64R5-DAG: insert.d $w[[W1:[0-9]+]][{{[0-9]}}], $6 551; MIPS64R5-DAG: insert.d $w[[W1]][{{[0-9]}}], $7 552 553 %1 = fadd <2 x double> %a, %b 554 store <2 x double> %1, <2 x double> * @double_v2f64 555 ret void 556} 557 558; Return value testing. 559; Integer vectors are returned in $2, $3, $4, $5 for O32, $2, $3 for N32/N64 560; Floating point vectors are returned through a hidden sret pointer. 561 562@gv2i8 = global <2 x i8> <i8 1, i8 2> 563@gv4i8 = global <4 x i8> <i8 0, i8 1, i8 2, i8 3> 564@gv8i8 = global <8 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7> 565@gv16i8 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15> 566 567@gv2i16 = global <2 x i16> <i16 1, i16 2> 568@gv4i16 = global <4 x i16> <i16 0, i16 1, i16 2, i16 3> 569@gv8i16 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7> 570 571@gv2i32 = global <2 x i32> <i32 0, i32 1> 572@gv4i32 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3> 573 574@gv2i64 = global <2 x i64> <i64 0, i64 1> 575 576define <2 x i8> @ret_2_i8() { 577; ALL-LABEL: ret_2_i8: 578; MIPS32-DAG: lhu $2 579; MIPS32R5-DAG: lhu $2 580 581; FIXME: why is this lh instead of lhu on mips64? 582 583; MIPS64-DAG: lh $2 584; MIPS64-DAG: lh $2 585 %1 = load <2 x i8>, <2 x i8> * @gv2i8 586 ret <2 x i8> %1 587} 588 589define <4 x i8> @ret_4_i8() { 590; ALL-LABEL: ret_4_i8: 591; MIPS32-DAG: lw $2 592; MIPS32R5-DAG: lw $2 593 594; MIPS64-DAG: lw $2 595; MIPS64R5-DAG: lw $2 596 597 %1 = load <4 x i8>, <4 x i8> * @gv4i8 598 ret <4 x i8> %1 599} 600 601define <8 x i8> @ret_8_i8() { 602; ALL-LABEL: ret_8_i8: 603; MIPS32-DAG: lw $2 604; MIPS32-DAG: lw $3 605 606; MIPS32R5: copy_s.w $2, $w[[W0:[0-9]+]] 607; MIPS32R5: copy_s.w $3, $w[[W0]] 608 609; MIPS64-DAG: ld $2 610; MIPS64R5-DAG: ld $2 611 %1 = load <8 x i8>, <8 x i8> * @gv8i8 612 ret <8 x i8> %1 613} 614 615define <16 x i8> @ret_16_i8() { 616; ALL-LABEL: ret_16_i8: 617; MIPS32-DAG: lw $2 618; MIPS32-DAG: lw $3 619; MIPS32-DAG: lw $4 620; MIPS32-DAG: lw $5 621 622; MIPS32R5-DAG: copy_s.w $2, $w[[W0:[0-9]+]][0] 623; MIPS32R5-DAG: copy_s.w $3, $w[[W0]][1] 624; MIPS32R5-DAG: copy_s.w $4, $w[[W0]][2] 625; MIPS32R5-DAG: copy_s.w $5, $w[[W0]][3] 626 627; MIPS64-DAG: ld $2 628; MIPS64-DAG: ld $3 629 630; MIPS64R5-DAG: copy_s.d $2 631; MIPS64R5-DAG: copy_s.d $3 632 633 %1 = load <16 x i8>, <16 x i8> * @gv16i8 634 ret <16 x i8> %1 635} 636 637define <2 x i16> @ret_2_i16() { 638; ALL-LABEL: ret_2_i16: 639; MIPS32-DAG: lw $2 640 641; MIPS32R5-DAG: lw $2 642 643; MIPS64-DAG: lw $2 644 645; MIPS64R5-DAG: lw $2 646 %1 = load <2 x i16>, <2 x i16> * @gv2i16 647 ret <2 x i16> %1 648} 649 650define <4 x i16> @ret_4_i16() { 651; ALL-LABEL: ret_4_i16: 652; MIPS32-DAG: lw $2 653; MIPS32-DAG: lw $3 654 655; MIPS32R5-DAG: copy_s.w $2, $w[[W0:[0-9]+]] 656; MIPS32R5-DAG: copy_s.w $3, $w[[W0]] 657 658; MIPS64-DAG: ld $2 659; MIPS64R5-DAG: ld $2 660 %1 = load <4 x i16>, <4 x i16> * @gv4i16 661 ret <4 x i16> %1 662} 663 664define <8 x i16> @ret_8_i16() { 665; ALL-LABEL: ret_8_i16: 666; MIPS32-DAG: lw $2 667; MIPS32-DAG: lw $3 668; MIPS32-DAG: lw $4 669; MIPS32-DAG: lw $5 670 671; MIPS32R5-DAG: copy_s.w $2, $w[[W0:[0-9]+]][0] 672; MIPS32R5-DAG: copy_s.w $3, $w[[W0]][1] 673; MIPS32R5-DAG: copy_s.w $4, $w[[W0]][2] 674; MIPS32R5-DAG: copy_s.w $5, $w[[W0]][3] 675 676; MIPS64-DAG: ld $2 677; MIPS64-DAG: ld $3 678 679; MIPS64R5-DAG: copy_s.d $2 680; MIPS64R5-DAG: copy_s.d $3 681 682 %1 = load <8 x i16>, <8 x i16> * @gv8i16 683 ret <8 x i16> %1 684} 685 686define <2 x i32> @ret_2_i32() { 687; ALL-LABEL: ret_2_i32: 688; MIPS32-DAG: lw $2 689; MIPS32-DAG: lw $3 690 691; MIPS32R5-DAG: copy_s.w $2, $w[[W0:[0-9]+]] 692; MIPS32R5-DAG: copy_s.w $3, $w[[W0]] 693 694; MIPS64-DAG: ld $2 695; MIPS64R5-DAG: ld $2 696 697 %1 = load <2 x i32>, <2 x i32> * @gv2i32 698 ret <2 x i32> %1 699} 700 701define <4 x i32> @ret_4_i32() { 702; ALL-LABEL: ret_4_i32: 703; MIPS32-DAG: lw $2 704; MIPS32-DAG: lw $3 705; MIPS32-DAG: lw $4 706; MIPS32-DAG: lw $5 707 708; MIPS32R5-DAG: copy_s.w $2, $w[[W0:[0-9]+]][0] 709; MIPS32R5-DAG: copy_s.w $3, $w[[W0]][1] 710; MIPS32R5-DAG: copy_s.w $4, $w[[W0]][2] 711; MIPS32R5-DAG: copy_s.w $5, $w[[W0]][3] 712 713; MIPS64-DAG: ld $2 714; MIPS64-DAG: ld $3 715 716; MIPS64R5-DAG: copy_s.d $2, $w[[W0:[0-9]+]] 717; MIPS64R5-DAG: copy_s.d $3, $w[[W0]] 718 719 %1 = load <4 x i32>, <4 x i32> * @gv4i32 720 ret <4 x i32> %1 721} 722 723define <2 x i64> @ret_2_i64() { 724; ALL-LABEL: ret_2_i64: 725; MIPS32-DAG: lw $2 726; MIPS32-DAG: lw $3 727; MIPS32-DAG: lw $4 728; MIPS32-DAG: lw $5 729 730; MIPS32R5-DAG: copy_s.w $2, $w[[W0:[0-9]+]][0] 731; MIPS32R5-DAG: copy_s.w $3, $w[[W0]][1] 732; MIPS32R5-DAG: copy_s.w $4, $w[[W0]][2] 733; MIPS32R5-DAG: copy_s.w $5, $w[[W0]][3] 734 735; MIPS64-DAG: ld $2 736; MIPS64-DAG: ld $3 737 738; MIPS64R5-DAG: copy_s.d $2, $w[[W0:[0-9]+]] 739; MIPS64R5-DAG: copy_s.d $3, $w[[W0]] 740 741 %1 = load <2 x i64>, <2 x i64> * @gv2i64 742 ret <2 x i64> %1 743} 744 745@gv2f32 = global <2 x float> <float 0.0, float 0.0> 746@gv4f32 = global <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0> 747 748define <2 x float> @ret_float_2() { 749entry: 750; ALL-LABEL: ret_float_2: 751 752; MIPS32-DAG: swc1 $f{{[0-9]+}}, 0($4) 753; MIPS32-DAG: swc1 $f{{[0-9]+}}, 4($4) 754 755; MIPS32R5-DAG: swc1 $f{{[0-9]+}}, 0($4) 756; MIPS32R5-DAG: swc1 $f{{[0-9]+}}, 4($4) 757 758; MIPS64: ld $2 759 760; MIPS64R5: ld $2 761 762 %0 = load <2 x float>, <2 x float> * @gv2f32 763 ret <2 x float> %0 764} 765 766define <4 x float> @ret_float_4() { 767entry: 768; ALL-LABEL: ret_float_4: 769 770; MIPS32-DAG: swc1 $f{{[0-9]+}}, 0($4) 771; MIPS32-DAG: swc1 $f{{[0-9]+}}, 4($4) 772; MIPS32-DAG: swc1 $f{{[0-9]+}}, 8($4) 773; MIPS32-DAG: swc1 $f{{[0-9]+}}, 12($4) 774 775; MIPS32R5: st.w $w{{[0-9]+}}, 0($4) 776 777; MIPS64-DAG: ld $2 778; MIPS64-DAG: ld $3 779 780; MIPS64R5-DAG: copy_s.d $2, $w{{[0-9]+}}[0] 781; MIPS64R5-DAG: copy_s.d $3, $w{{[0-9]+}}[1] 782 783 %0 = load <4 x float>, <4 x float> * @gv4f32 784 ret <4 x float> %0 785} 786 787@gv2f64 = global <2 x double> <double 0.0, double 0.0> 788 789define <2 x double> @ret_double_2() { 790entry: 791; ALL-LABEL: ret_double_2: 792 793; MIPS32-DAG: sdc1 $f{{[0-9]+}}, 8($4) 794; MIPS32-DAG: sdc1 $f{{[0-9]+}}, 0($4) 795 796; MIPS32R5: st.d $w{{[0-9]+}}, 0($4) 797 798; MIPS64-DAG: ld $2 799; MIPS64-DAG: ld $2 800 801; MIPS64R5-DAG: copy_s.d $2, $w{{[0-9]+}}[0] 802; MIPS64R5-DAG: copy_s.d $3, $w{{[0-9]+}}[1] 803 804 %0 = load <2 x double>, <2 x double> * @gv2f64 805 ret <2 x double> %0 806} 807 808; Test argument lowering and call result lowering. 809 810define void @call_i8_2() { 811entry: 812; ALL-LABEL: call_i8_2: 813; MIPS32EB-DAG: addiu $4 814; MIPS32EB-DAG: addiu $5 815; MIPS32-NOT: addiu $6 816; MIPS32-NOT: addiu $7 817 818; MIPS32R5-DAG: lhu $4, {{[0-9]+}}($sp) 819; MIPS32R5-DAG: lhu $5, {{[0-9]+}}($sp) 820 821; MIPS32R5: jal 822; MIPS32R5: sw $2, {{[0-9]+}}($sp) 823 824; MIPS32R5-DAG: sb ${{[0-9]+}}, 1(${{[0-9]+}}) 825; MIPS32R5-DAG; sb ${{[0-9]+}}, %lo(gv2i8)(${{[0-9]+}}) 826 827; MIPS64EB: daddiu $4, $zero, 1543 828; MIPS64EB: daddiu $5, $zero, 3080 829 830; MIPS64EL: daddiu $4, $zero, 1798 831; MIPS64EL; daddiu $5, $zero, 2060 832 833; MIPS64R5-DAG: lh $4 834; MIPS64R5-DAG: lh $5 835 836; MIPS32: jal i8_2 837; MIPS64: jalr $25 838 839; MIPS32EB-DAG: srl $[[R0:[0-9]+]], $2, 16 840; MIPS32EB-DAG: sb $[[R0]] 841; MIPS32EB-DAG: srl $[[R1:[0-9]+]], $2, 24 842; MIPS32EB-DAG: sb $[[R1]] 843 844; MIPS32EL: sb $2 845; MIPS32EL: srl $[[R0:[0-9]+]], $2, 8 846; MIPS32EL: sb $[[R0]] 847 848; MIPS64EB: dsrl $[[R4:[0-9]+]], $2, 48 849; MIPS64EB: sb $[[R4]] 850; MIPS64EB: dsrl $[[R5:[0-9]+]], $2, 56 851; MIPS64EB: sb $[[R5]] 852 853; MIPS64EL: sll $[[R6:[0-9]+]], $2, 0 854; MIPS64EL: sb $[[R6]] 855; MIPS64EL: srl $[[R7:[0-9]+]], $[[R6]], 8 856; MIPS64EL: sb $[[R7]] 857 858; MIPS64R5: sd $2 859 860 %0 = call <2 x i8> @i8_2(<2 x i8> <i8 6, i8 7>, <2 x i8> <i8 12, i8 8>) 861 store <2 x i8> %0, <2 x i8> * @gv2i8 862 ret void 863} 864 865define void @call_i8_4() { 866entry: 867; ALL-LABEL: call_i8_4: 868; MIPS32: ori $4 869; MIPS32: ori $5 870; MIPS32-NOT: ori $6 871; MIPS32-NOT: ori $7 872 873; MIPS32R5-DAG: lw $4, {{[0-9]+}}($sp) 874; MIPS32R5-DAG: lw $5, {{[0-9]+}}($sp) 875 876; MIPS64: ori $4 877; MIPS64: ori $5 878 879; MIPS64R5: lw $4 880; MIPS64R5: lw $5 881 882; MIPS32: jal i8_4 883; MIPS64: jalr $25 884 885; MIPS32: sw $2 886 887; MIPS32R5-DAG: sw $2 888 889; MIPS64: sw $2 890; MIPS64R5: sw $2 891 892 %0 = call <4 x i8> @i8_4(<4 x i8> <i8 6, i8 7, i8 9, i8 10>, <4 x i8> <i8 12, i8 8, i8 9, i8 10>) 893 store <4 x i8> %0, <4 x i8> * @gv4i8 894 ret void 895} 896 897define void @call_i8_8() { 898entry: 899; ALL-LABEL: call_i8_8: 900 901; MIPS32: ori $6 902; MIPS32: ori $4 903; MIPS32: move $5 904; MIPS32: move $7 905 906; MIPS32R5-DAG: ori $6 907; MIPS32R5-DAG: ori $4 908; MIPS32R5-DAG: move $5 909; MIPS32R5-DAG: move $7 910 911; MIPS64EB: daddiu $4, ${{[0-9]+}}, 2314 912; MIPS64EB: daddiu $5, ${{[0-9]+}}, 2314 913 914; MIPS64EL: daddiu $4, ${{[0-9]+}}, 1798 915; MIPS64EL: daddiu $5, ${{[0-9]+}}, 2060 916 917; MIPS32: jal i8_8 918; MIPS64: jalr $25 919 920; MIPS32-DAG: sw $2 921; MIPS32-DAG: sw $3 922 923; MIPS32R5-DAG: sw $2 924; MIPS32R5-DAG: sw $3 925 926; MIPS64: sd $2 927; MIPS64R5: sd $2 928 929 %0 = call <8 x i8> @i8_8(<8 x i8> <i8 6, i8 7, i8 9, i8 10, i8 6, i8 7, i8 9, i8 10>, <8 x i8> <i8 12, i8 8, i8 9, i8 10, i8 6, i8 7, i8 9, i8 10>) 930 store <8 x i8> %0, <8 x i8> * @gv8i8 931 ret void 932} 933 934define void @calli8_16() { 935entry: 936; ALL-LABEL: calli8_16: 937; MIPS32-DAG: sw ${{[0-9]+}}, 28($sp) 938; MIPS32-DAG: sw ${{[0-9]+}}, 24($sp) 939; MIPS32-DAG: sw ${{[0-9]+}}, 20($sp) 940; MIPS32-DAG: sw ${{[0-9]+}}, 16($sp) 941 942; MIPS32: ori $4, ${{[0-9]+}}, {{[0-9]+}} 943; MIPS32: ori $7, ${{[0-9]+}}, {{[0-9]+}} 944; MIPS32: move $5, ${{[0-9]+}} 945; MIPS32: move $6, ${{[0-9]+}} 946 947; MIPS32R5-DAG: copy_s.w $4, $w{{[0-9]+}} 948; MIPS32R5-DAG: copy_s.w $5, $w{{[0-9]+}} 949; MIPS32R5-DAG: copy_s.w $6, $w{{[0-9]+}} 950; MIPS32R5-DAG: copy_s.w $7, $w{{[0-9]+}} 951 952; MIPS32R5-DAG: sw ${{[0-9]+}}, 28($sp) 953; MIPS32R5-DAG: sw ${{[0-9]+}}, 24($sp) 954; MIPS32R5-DAG: sw ${{[0-9]+}}, 20($sp) 955; MIPS32R5-DAG: sw ${{[0-9]+}}, 16($sp) 956 957; MIPS64-DAG: daddiu $4 958; MIPS64-DAG: daddiu $5 959; MIPS64-DAG: daddiu $6 960; MIPS64-DAG: daddiu $7 961 962; MIPS64R5-DAG: copy_s.d $4 963; MIPS64R5-DAG: copy_s.d $5 964; MIPS64R5-DAG: copy_s.d $6 965; MIPS64R5-DAG: copy_s.d $7 966 967; MIPS32: jal i8_16 968; MIPS64: jalr $25 969 970; MIPS32-DAG: sw $5, 12(${{[0-9]+}}) 971; MIPS32-DAG: sw $4, 8(${{[0-9]+}}) 972; MIPS32-DAG: sw $3, 4(${{[0-9]+}}) 973; MIPS32-DAG: sw $2, %lo(gv16i8)(${{[0-9]+}}) 974 975; MIPS32R5-DAG: insert.w $w[[W0:[0-9]+]][0], $2 976; MIPS32R5-DAG: insert.w $w[[W0]][1], $3 977; MIPS32R5-DAG: insert.w $w[[W0]][2], $4 978; MIPS32R5-DAG: insert.w $w[[W0]][3], $5 979; MIPS32R5-DAG: st.w $w[[W0]] 980 981; MIPS64-DAG: sd $3 982; MIPS64-DAG: sd $2 983 984; MIPS64R5-DAG: insert.d $w[[W0:[0-9]+]][0], $2 985; MIPS64R5-DAG: insert.d $w[[W0:[0-9]+]][1], $3 986 987 %0 = call <16 x i8> @i8_16(<16 x i8> <i8 6, i8 7,i8 6, i8 7,i8 6, i8 7,i8 6, i8 7,i8 6, i8 7,i8 6, i8 7, i8 6, i8 7, i8 9, i8 10>, <16 x i8> <i8 7, i8 9,i8 7, i8 9,i8 7, i8 9,i8 7, i8 9,i8 7, i8 9,i8 7, i8 9,i8 12, i8 8, i8 9, i8 10>) 988 store <16 x i8> %0, <16 x i8> * @gv16i8 989 ret void 990} 991 992define void @calli16_2() { 993entry: 994; ALL-LABEL: calli16_2: 995 996; MIPS32-DAG: ori $4 997; MIPS32-DAG: ori $5 998 999; MIPS32R5-DAG: lw $4 1000; MIPS32R5-DAG: lw $5 1001 1002; MIPS64: ori $4 1003; MIPS64: ori $5 1004 1005; MIPS64R5-DAG: lw $4 1006; MIPS64R5-DAG: lw $5 1007 1008; MIPS32: jal i16_2 1009; MIPS64: jalr $25 1010 1011; MIPS32: sw $2, %lo(gv2i16) 1012 1013; MIPS32R5: sw $2, %lo(gv2i16) 1014 1015; MIPS64: sw $2 1016 1017; MIPS64R6: sw $2 1018 1019 %0 = call <2 x i16> @i16_2(<2 x i16> <i16 6, i16 7>, <2 x i16> <i16 12, i16 8>) 1020 store <2 x i16> %0, <2 x i16> * @gv2i16 1021 ret void 1022} 1023 1024define void @calli16_4() { 1025entry: 1026; ALL-LABEL: calli16_4: 1027; MIPS32-DAG: ori $4 1028; MIPS32-DAG: ori $5 1029; MIPS32-DAG: ori $6 1030; MIPS32-DAG: move $7 1031 1032; MIPS32R5-DAG: ori $4 1033; MIPS32R5-DAG: ori $5 1034; MIPS32R5-DAG: ori $6 1035; MIPS32R5-DAG: move $7 1036 1037; MIPS64-DAG: daddiu $4 1038; MIPS64-DAG: daddiu $5 1039 1040; MIPS64R5-DAG: ld $4 1041; MIPS64R5-DAG: ld $5 1042 1043; MIPS32: jal i16_4 1044; MIPS64: jalr $25 1045 1046; MIPS32-DAG: sw $3, 4(${{[0-9]+}}) 1047; MIPS32-DAG: sw $2, %lo(gv4i16)(${{[0-9]+}}) 1048 1049; MIPS32R5-DAG: sw $3, 4(${{[0-9]+}}) 1050; MIPS32R5-DAG: sw $2, %lo(gv4i16)(${{[0-9]+}}) 1051 1052; MIPS64: sd $2 1053; MIPS64R5: sd $2 1054 1055 %0 = call <4 x i16> @i16_4(<4 x i16> <i16 6, i16 7, i16 9, i16 10>, <4 x i16> <i16 12, i16 8, i16 9, i16 10>) 1056 store <4 x i16> %0, <4 x i16> * @gv4i16 1057 ret void 1058} 1059 1060define void @calli16_8() { 1061entry: 1062; ALL-LABEL: calli16_8: 1063 1064; MIPS32-DAG: sw ${{[0-9]+}}, 28($sp) 1065; MIPS32-DAG: sw ${{[0-9]+}}, 24($sp) 1066; MIPS32-DAG: sw ${{[0-9]+}}, 20($sp) 1067; MIPS32-DAG: sw ${{[0-9]+}}, 16($sp) 1068 1069; MIPS32-DAG: ori $4, ${{[0-9]+}}, {{[0-9]+}} 1070; MIPS32-DAG: ori $5, ${{[0-9]+}}, {{[0-9]+}} 1071; MIPS32-DAG: move $6, ${{[0-9]+}} 1072; MIPS32-DAG: move $7, ${{[0-9]+}} 1073 1074; MIPS32R5-DAG: copy_s.w $4, $w{{[0-9]+}} 1075; MIPS32R5-DAG: copy_s.w $5, $w{{[0-9]+}} 1076; MIPS32R5-DAG: copy_s.w $6, $w{{[0-9]+}} 1077; MIPS32R5-DAG: copy_s.w $7, $w{{[0-9]+}} 1078 1079; MIPS32R5-DAG: sw ${{[0-9]+}}, 28($sp) 1080; MIPS32R5-DAG: sw ${{[0-9]+}}, 24($sp) 1081; MIPS32R5-DAG: sw ${{[0-9]+}}, 20($sp) 1082; MIPS32R5-DAG: sw ${{[0-9]+}}, 16($sp) 1083 1084; MIPS64-DAG: daddiu $4 1085; MIPS64-DAG: daddiu $7 1086; MIPS64-DAG: move $5 1087; MIPS64-DAG: move $6 1088 1089; MIPS64R5-DAG: copy_s.d $4, $w[[W0:[0-9]+]][0] 1090; MIPS64R5-DAG: copy_s.d $5, $w[[W0]][1] 1091; MIPS64R5-DAG: copy_s.d $6, $w[[W1:[0-9]+]][0] 1092; MIPS64R5-DAG: copy_s.d $7, $w[[W1]][1] 1093 1094; MIPS32: jal i16_8 1095; MIPS64: jalr $25 1096 1097; MIPS32-DAG: sw $5, 12(${{[0-9]+}}) 1098; MIPS32-DAG: sw $4, 8(${{[0-9]+}}) 1099; MIPS32-DAG: sw $3, 4(${{[0-9]+}}) 1100; MIPS32-DAG: sw $2, %lo(gv8i16)(${{[0-9]+}}) 1101 1102; MIPS32R5-DAG: insert.w $w[[W0:[0-9]+]][0], $2 1103; MIPS32R5-DAG: insert.w $w[[W0]][1], $3 1104; MIPS32R5-DAG: insert.w $w[[W0]][2], $4 1105; MIPS32R5-DAG: insert.w $w[[W0]][3], $5 1106; MIPS32R5-DAG: st.w $w[[W0]] 1107 1108; MIPS64: sd $3 1109; MIPS64: sd $2 1110 1111; MIPS64R5-DAG: insert.d $w[[W2:[0-9]+]][0], $2 1112; MIPS64R5-DAG: insert.d $w[[W2]][1], $3 1113 1114 %0 = call <8 x i16> @i16_8(<8 x i16> <i16 6, i16 7, i16 9, i16 10, i16 6, i16 7, i16 9, i16 10>, <8 x i16> <i16 6, i16 7, i16 9, i16 10, i16 12, i16 8, i16 9, i16 10>) 1115 store <8 x i16> %0, <8 x i16> * @gv8i16 1116 ret void 1117} 1118 1119define void @calli32_2() { 1120entry: 1121; ALL-LABEL: calli32_2: 1122 1123; MIPS32-DAG: addiu $4 1124; MIPS32-DAG: addiu $5 1125; MIPS32-DAG: addiu $6 1126; MIPS32-DAG: addiu $7 1127 1128; MIPS32R5-DAG: addiu $4 1129; MIPS32R5-DAG: addiu $5 1130; MIPS32R5-DAG: addiu $6 1131; MIPS32R5-DAG: addiu $7 1132 1133; MIPS64: daddiu $4 1134; MIPS64: daddiu $5 1135 1136; MIPS64R5-DAG: ld $4 1137; MIPS64R5-DAG: ld $5 1138 1139; MIPS32: jal i32_2 1140; MIPS64: jalr $25 1141 1142; MIPS32-DAG: sw $2, %lo(gv2i32)(${{[0-9]+}}) 1143; MIPS32-DAG: sw $3, 4(${{[0-9]+}}) 1144 1145; MIPS32R5-DAG: sw $2, %lo(gv2i32)(${{[0-9]+}}) 1146; MIPS32R5-DAG: sw $3, 4(${{[0-9]+}}) 1147 1148; MIPS64: sd $2 1149 1150; MIPS64R5: sd $2 1151 1152 %0 = call <2 x i32> @i32_2(<2 x i32> <i32 6, i32 7>, <2 x i32> <i32 12, i32 8>) 1153 store <2 x i32> %0, <2 x i32> * @gv2i32 1154 ret void 1155} 1156 1157define void @calli32_4() { 1158entry: 1159; ALL-LABEL: calli32_4: 1160 1161; MIPS32-DAG: sw ${{[0-9]+}}, 28($sp) 1162; MIPS32-DAG: sw ${{[0-9]+}}, 24($sp) 1163; MIPS32-DAG: sw ${{[0-9]+}}, 20($sp) 1164; MIPS32-DAG: sw ${{[0-9]+}}, 16($sp) 1165 1166; MIPS32-DAG: addiu $4 1167; MIPS32-DAG: addiu $5 1168; MIPS32-DAG: addiu $6 1169; MIPS32-DAG: addiu $7 1170 1171; MIPS32R5-DAG: sw ${{[0-9]+}}, 28($sp) 1172; MIPS32R5-DAG: sw ${{[0-9]+}}, 24($sp) 1173; MIPS32R5-DAG: sw ${{[0-9]+}}, 20($sp) 1174; MIPS32R5-DAG: sw ${{[0-9]+}}, 16($sp) 1175 1176; MIPS32R5-DAG: addiu $4 1177; MIPS32R5-DAG: addiu $5 1178; MIPS32R5-DAG: addiu $6 1179; MIPS32R5-DAG: addiu $7 1180 1181; MIPS64-DAG: daddiu $4 1182; MIPS64-DAG: daddiu $6 1183; MIPS64-DAG: daddiu $5 1184; MIPS64-DAG: move $7 1185 1186; MIPS64R5-DAG: copy_s.d $4, $w[[W0:[0-9]+]][0] 1187; MIPS64R5-DAG: copy_s.d $5, $w[[W0]][1] 1188; MIPS64R5-DAG: copy_s.d $6, $w[[W1:[0-9]+]][0] 1189; MIPS64R5-DAG: copy_s.d $7, $w[[W1]][1] 1190 1191; MIPS32: jal i32_4 1192; MIPS64: jalr $25 1193 1194; MIPS32-DAG: sw $5, 12(${{[0-9]+}}) 1195; MIPS32-DAG: sw $4, 8(${{[0-9]+}}) 1196; MIPS32-DAG: sw $3, 4(${{[0-9]+}}) 1197; MIPS32-DAG: sw $2, %lo(gv4i32)(${{[0-9]+}}) 1198 1199; MIPS32R5-DAG: insert.w $w[[W0:[0-9]+]][0], $2 1200; MIPS32R5-DAG: insert.w $w[[W0]][1], $3 1201; MIPS32R5-DAG: insert.w $w[[W0]][2], $4 1202; MIPS32R5-DAG: insert.w $w[[W0]][3], $5 1203; MIPS32R5-DAG: st.w $w[[W0]] 1204 1205; MIPS64-DAG: sd $2 1206; MIPS64-DAG: sd $3 1207 1208; MIPS64R5-DAG: insert.d $w[[W0:[0-9]+]][0], $2 1209; MIPS64R6-DAG: insert.d $w[[W0:[0-9]+]][1], $3 1210 1211 %0 = call <4 x i32> @i32_4(<4 x i32> <i32 6, i32 7, i32 9, i32 10>, <4 x i32> <i32 12, i32 8, i32 9, i32 10>) 1212 store <4 x i32> %0, <4 x i32> * @gv4i32 1213 ret void 1214} 1215 1216define void @calli64_2() { 1217entry: 1218; ALL-LABEL: calli64_2: 1219 1220; MIPS32-DAG: sw ${{[0-9a-z]+}}, 28($sp) 1221; MIPS32-DAG: sw ${{[0-9a-z]+}}, 24($sp) 1222; MIPS32-DAG: sw ${{[0-9a-z]+}}, 20($sp) 1223; MIPS32-DAG: sw ${{[0-9a-z]+}}, 16($sp) 1224 1225; MIPS32-DAG: addiu $4 1226; MIPS32-DAG: addiu $5 1227; MIPS32-DAG: addiu $6 1228; MIPS32-DAG: addiu $7 1229 1230; MIPS32R5-DAG: copy_s.w $4, $w{{[0-9]+}} 1231; MIPS32R5-DAG: copy_s.w $5, $w{{[0-9]+}} 1232; MIPS32R5-DAG: copy_s.w $6, $w{{[0-9]+}} 1233; MIPS32R5-DAG: copy_s.w $7, $w{{[0-9]+}} 1234 1235; MIPS32R5-DAG: sw ${{[0-9]+}}, 28($sp) 1236; MIPS32R5-DAG: sw ${{[0-9]+}}, 24($sp) 1237; MIPS32R5-DAG: sw ${{[0-9]+}}, 20($sp) 1238; MIPS32R5-DAG: sw ${{[0-9]+}}, 16($sp) 1239 1240; MIPS64: daddiu $4 1241; MIPS64: daddiu $5 1242; MIPS64: daddiu $6 1243; MIPS64: daddiu $7 1244 1245; MIPS64R5: daddiu $4 1246; MIPS64R5: daddiu $5 1247; MIPS64R5: daddiu $6 1248; MIPS64R5: daddiu $7 1249 1250; MIPS32: jal i64_2 1251; MIPS64: jalr $25 1252 1253; MIPS32-DAG: sw $5, 12(${{[0-9]+}}) 1254; MIPS32-DAG: sw $4, 8(${{[0-9]+}}) 1255; MIPS32-DAG: sw $3, 4(${{[0-9]+}}) 1256; MIPS32-DAG: sw $2, %lo(gv2i64)(${{[0-9]+}}) 1257 1258; MIPS32R5-DAG: insert.w $w[[W0:[0-9]+]][0], $2 1259; MIPS32R5-DAG: insert.w $w[[W0]][1], $3 1260; MIPS32R5-DAG: insert.w $w[[W0]][2], $4 1261; MIPS32R5-DAG: insert.w $w[[W0]][3], $5 1262; MIPS32R5-DAG: st.w $w[[W0]] 1263 1264; MIPS64-DAG: sd $3 1265; MIPS64-DAG: sd $2 1266 1267; MIPS64R5-DAG: insert.d $w[[W0:[0-9]+]][0], $2 1268; MIPS64R6-DAG: insert.d $w[[W0:[0-9]+]][1], $3 1269 1270 %0 = call <2 x i64> @i64_2(<2 x i64> <i64 6, i64 7>, <2 x i64> <i64 12, i64 8>) 1271 store <2 x i64> %0, <2 x i64> * @gv2i64 1272 ret void 1273} 1274 1275declare <2 x float> @float2_extern(<2 x float>, <2 x float>) 1276declare <4 x float> @float4_extern(<4 x float>, <4 x float>) 1277declare <2 x double> @double2_extern(<2 x double>, <2 x double>) 1278 1279define void @callfloat_2() { 1280entry: 1281; ALL-LABEL: callfloat_2: 1282 1283; MIPS32-DAG: addiu $4, $sp, 24 1284; MIPS32-DAG: addiu $6, $zero, 0 1285; MIPS32-DAG: lui $7 1286 1287; MIPS32R5-DAG: addiu $4, $sp, 24 1288; MIPS32R5-DAG: addiu $6, $zero, 0 1289; MIPS32R5-DAG: lui $7 1290 1291; MIPS64: dsll $4 1292; MIPS64: dsll $5 1293 1294; MIPS64R5-DAG: copy_s.d $4, $w{{[0-9]+}} 1295; MIPS64R5-DAG: copy_s.d $5, $w{{[0-9]+}} 1296 1297; MIPS32: jal float2_extern 1298; MIPS64: jalr $25 1299 1300; MIPS32-DAG: lwc1 $f[[F0:[0-9]+]], 24($sp) 1301; MIPS32-DAG: lwc1 $f[[F1:[0-9]+]], 28($sp) 1302 1303; MIPS32-DAG: swc1 $f[[F1]], 4(${{[0-9]+}}) 1304; MIPS32-DAG: swc1 $f[[F0]], %lo(gv2f32)(${{[0-9]+}}) 1305 1306; MIPS32R5-DAG: lwc1 $f[[F0:[0-9]+]], 24($sp) 1307; MIPS32R5-DAG: lwc1 $f[[F1:[0-9]+]], 28($sp) 1308 1309; MIPS32R5-DAG: swc1 $f[[F1]], 4(${{[0-9]+}}) 1310; MIPS32R5-DAG: swc1 $f[[F0]], %lo(gv2f32)(${{[0-9]+}}) 1311 1312; MIPS64: sd $2 1313 1314; MIPS64R5: sd $2 1315 1316 %0 = call <2 x float> @float2_extern(<2 x float> <float 0.0, float -1.0>, <2 x float> <float 12.0, float 14.0>) 1317 store <2 x float> %0, <2 x float> * @gv2f32 1318 ret void 1319} 1320 1321define void @callfloat_4() { 1322entry: 1323; ALL-LABEL: callfloat_4: 1324 1325; MIPS32: sw ${{[0-9]+}}, 36($sp) 1326; MIPS32: sw ${{[0-9]+}}, 32($sp) 1327; MIPS32: sw ${{[0-9]+}}, 28($sp) 1328; MIPS32: sw ${{[0-9]+}}, 24($sp) 1329; MIPS32: sw ${{[0-9]+}}, 20($sp) 1330; MIPS32: sw ${{[0-9]+}}, 16($sp) 1331; MIPS32: addiu $4, $sp, 48 1332; MIPS32: addiu $6, $zero, 0 1333; MIPS32: lui $7 1334 1335; MIPS32R5: copy_s.w $6, $w{{[0-9]+}} 1336; MIPS32R5: copy_s.w $7, $w{{[0-9]+}} 1337; MIPS32R5: sw ${{[0-9]+}}, 36($sp) 1338; MIPS32R5: sw ${{[0-9]+}}, 32($sp) 1339; MIPS32R5: sw ${{[0-9]+}}, 28($sp) 1340; MIPS32R5: sw ${{[0-9]+}}, 24($sp) 1341; MIPS32R5: sw ${{[0-9]+}}, 20($sp) 1342; MIPS32R5: sw ${{[0-9]+}}, 16($sp) 1343; MIPS32R5: addiu $4, $sp, 48 1344 1345; MIPS64-DAG: dsll $4 1346; MIPS64-DAG: dsll $5 1347; MIPS64-DAG: dsll $6 1348; MIPS64-DAG: dsll $7 1349 1350; MIPS64R5-DAG: copy_s.d $4, $w{{[0-9]+}} 1351; MIPS64R5-DAG: copy_s.d $5, $w{{[0-9]+}} 1352; MIPS64R5-DAG: copy_s.d $6, $w{{[0-9]+}} 1353; MIPS64R5-DAG: copy_s.d $7, $w{{[0-9]+}} 1354 1355; MIPS64: jalr $25 1356; MIPS32: jal 1357 1358; MIPS32-DAG: lwc1 $f{{[0-9]+}}, 48($sp) 1359; MIPS32-DAG: lwc1 $f{{[0-9]+}}, 52($sp) 1360; MIPS32-DAG: lwc1 $f{{[0-9]+}}, 56($sp) 1361; MIPS32-DAG: lwc1 $f{{[0-9]+}}, 60($sp) 1362 1363; MIPS32R5: ld.w $w{{[0-9]+}}, 48($sp) 1364 1365; MIPS64-DAG: $2 1366; MIPS64-DAG: $3 1367 1368; MIPS64R5-DAG: insert.d $w[[W0:[0-9]+]][0], $2 1369; MIPS64R5-DAG: insert.d $w[[W0:[0-9]+]][1], $3 1370 1371 %0 = call <4 x float> @float4_extern(<4 x float> <float 0.0, float -1.0, float 2.0, float 4.0>, <4 x float> <float 12.0, float 14.0, float 15.0, float 16.0>) 1372 store <4 x float> %0, <4 x float> * @gv4f32 1373 ret void 1374} 1375 1376define void @calldouble_2() { 1377entry: 1378; ALL-LABEL: calldouble_2: 1379 1380; MIPS32-DAG: sw ${{[0-9a-z]+}}, 36($sp) 1381; MIPS32-DAG: sw ${{[0-9a-z]+}}, 32($sp) 1382; MIPS32-DAG: sw ${{[0-9a-z]+}}, 28($sp) 1383; MIPS32-DAG: sw ${{[0-9a-z]+}}, 24($sp) 1384; MIPS32-DAG: sw ${{[0-9a-z]+}}, 20($sp) 1385; MIPS32-DAG: sw ${{[0-9a-z]+}}, 16($sp) 1386 1387; MIPS32-DAG: addiu $4, $sp, [[R0:[0-9]+]] 1388; MIPS32-DAG: addiu $6, $zero, 0 1389; MIPS32-DAG: addiu $7, $zero, 0 1390 1391; MIPS32R5-DAG: copy_s.w $4, $w{{[0-9]+}} 1392; MIPS32R5-DAG: copy_s.w $5, $w{{[0-9]+}} 1393; MIPS32R5-DAG: copy_s.w $6, $w{{[0-9]+}} 1394; MIPS32R5-DAG: copy_s.w $7, $w{{[0-9]+}} 1395 1396; MIPS32R5-DAG: sw ${{[0-9]+}}, 36($sp) 1397; MIPS32R5-DAG: sw ${{[0-9]+}}, 32($sp) 1398; MIPS32R5-DAG: sw ${{[0-9]+}}, 28($sp) 1399; MIPS32R5-DAG: sw ${{[0-9]+}}, 24($sp) 1400; MIPS32R5-DAG: sw ${{[0-9]+}}, 20($sp) 1401; MIPS32R5-DAG: sw ${{[0-9]+}}, 16($sp) 1402 1403; MIPS64-DAG: dsll $5 1404; MIPS64-DAG: dsll $6 1405; MIPS64-DAG: dsll $7 1406; MIPS64-DAG: daddiu $4 1407 1408; MIPS64R5-DAG: copy_s.d $4, $w{{[0-9]+}} 1409; MIPS64R5-DAG: copy_s.d $5, $w{{[0-9]+}} 1410; MIPS64R5-DAG: copy_s.d $6, $w{{[0-9]+}} 1411; MIPS64R5-DAG: copy_s.d $7, $w{{[0-9]+}} 1412 1413; MIPS32: jal double2_extern 1414; MIPS64: jalr $25 1415 1416; MIPS32-DAG: ldc1 $f[[F0:[0-9]+]], 48($sp) 1417; MIPS32-DAG: ldc1 $f[[F1:[0-9]+]], 56($sp) 1418 1419; MIPS32-DAG: sdc1 $f[[F1]], 8(${{[0-9]+}}) 1420; MIPS32-DAG: sdc1 $f[[F0]], %lo(gv2f64)(${{[0-9]+}}) 1421 1422; MIPS32R5: ld.d $w[[W0:[0-9]+]], 48($sp) 1423; MIPS32R5: st.d $w[[W0]], 0(${{[0-9]+}}) 1424 1425; MIPS64-DAG: sd $2 1426; MIPS64-DAG: sd $3 1427 1428; MIPS64R5-DAG: insert.d $w[[W0:[0-9]+]][0], $2 1429; MIPS64R5-DAG: insert.d $w[[W0:[0-9]+]][1], $3 1430 1431 %0 = call <2 x double> @double2_extern(<2 x double> <double 0.0, double -1.0>, <2 x double> <double 12.0, double 14.0>) 1432 store <2 x double> %0, <2 x double> * @gv2f64 1433 ret void 1434} 1435 1436; The mixed tests show that due to alignment requirements, $5 is not used 1437; in argument passing. 1438 1439define float @mixed_i8(<2 x float> %a, i8 %b, <2 x float> %c) { 1440entry: 1441; ALL-LABEL: mixed_i8: 1442 1443; MIPS32-DAG: mtc1 $5, $f{{[0-9]+}} 1444; MIPS32: andi $[[R7:[0-9]+]], $6, 255 1445; MIPS32: mtc1 $[[R7]], $f[[F0:[0-9]+]] 1446; MIPS32: cvt.s.w $f{{[0-9]+}}, $f[[F0]] 1447 1448; MIPS32-DAG: mtc1 $4, $f{{[0-9]+}} 1449; MIPS32-DAG: lwc1 $f{{[0-9]+}}, 16($sp) 1450; MIPS32-DAG: lwc1 $f{{[0-9]+}}, 20($sp) 1451; MIPS32-DAG: add.s $f0, $f{{[0-9]+}}, $f{{[0-9]+}} 1452 1453; MIPS32R5: andi $[[R0:[0-9]+]], $6, 255 1454; MIPS32R5: sw $[[R0]], {{[0-9]+}}($sp) 1455; MIPS32R5: sw $[[R0]], {{[0-9]+}}($sp) 1456; MIPS32R5-DAG: sw $5, {{[0-9]+}}($sp) 1457; MIPS32R5-DAG: sw $4, {{[0-9]+}}($sp) 1458 1459; MIPS64EB-DAG: sll $[[R0:[0-9]+]], $4, 0 1460; MIPS64EB-DAG: mtc1 $[[R0]], $f{{[0-9]+}} 1461; MIPS64EB: sll $[[R6:[0-9]+]], $5, 0 1462; MIPS64EB: andi $[[R7:[0-9]+]], $[[R6]], 255 1463; MIPS64EB: mtc1 $[[R7]], $f[[F0:[0-9]+]] 1464; MIPS64EB: cvt.s.w $f{{[0-9]+}}, $f[[F0]] 1465 1466; MIPS64EB-DAG: dsrl $[[R1:[0-9]+]], $4, 32 1467; MIPS64EB-DAG: sll $[[R2:[0-9]+]], $[[R1]], 0 1468; MIPS64EB-DAG: mtc1 $[[R2:[0-9]+]], $f{{[0-9]+}} 1469 1470; MIPS64EB-DAG: sll $[[R3:[0-9]+]], $6, 0 1471; MIPS64EB-DAG: mtc1 $[[R3]], $f{{[0-9]+}} 1472; MIPS64EB-DAG: dsrl $[[R4:[0-9]+]], $6, 32 1473; MIPS64EB-DAG: sll $[[R5:[0-9]+]], $[[R4]], 0 1474; MIPS64EB-DAG: mtc1 $[[R5:[0-9]+]], $f{{[0-9]+}} 1475 1476; MIPS64EL-DAG: dsrl $[[R1:[0-9]+]], $4, 32 1477; MIPS64EL-DAG: sll $[[R2:[0-9]+]], $[[R1]], 0 1478; MIPS64EL-DAG: mtc1 $[[R2:[0-9]+]], $f{{[0-9]+}} 1479 1480; MIPS64EL: sll $[[R6:[0-9]+]], $5, 0 1481; MIPS64EL: andi $[[R7:[0-9]+]], $[[R6]], 255 1482; MIPS64EL: mtc1 $[[R7]], $f[[F0:[0-9]+]] 1483; MIPS64EL: cvt.s.w $f{{[0-9]+}}, $f[[F0]] 1484 1485; MIPS64EL-DAG: dsrl $[[R4:[0-9]+]], $6, 32 1486; MIPS64EL-DAG: sll $[[R5:[0-9]+]], $[[R4]], 0 1487; MIPS64EL-DAG: mtc1 $[[R5:[0-9]+]], $f{{[0-9]+}} 1488 1489; MIPS64EL-DAG: sll $[[R0:[0-9]+]], $4, 0 1490; MIPS64EL-DAG: mtc1 $[[R0]], $f{{[0-9]+}} 1491; MIPS64EL-DAG: sll $[[R3:[0-9]+]], $6, 0 1492; MIPS64EL-DAG: mtc1 $[[R3]], $f{{[0-9]+}} 1493 1494; MIPS64R5: sll $[[R0:[0-9]+]], $5, 0 1495; MIPS64R5: andi $[[R1:[0-9]+]], $[[R0]], 255 1496; MIPS64R5: sd $4, {{[0-9]+}}($sp) 1497; MIPS64R5: sd $6, {{[0-9]+}}($sp) 1498 1499 %0 = zext i8 %b to i32 1500 %1 = uitofp i32 %0 to float 1501 %2 = insertelement <2 x float> undef, float %1, i32 0 1502 %3 = insertelement <2 x float> %2, float %1, i32 1 1503 %4 = fadd <2 x float> %3, %a 1504 %5 = fadd <2 x float> %4, %c 1505 %6 = extractelement <2 x float> %5, i32 0 1506 %7 = extractelement <2 x float> %5, i32 1 1507 %8 = fadd float %6, %7 1508 ret float %8 1509} 1510 1511define <4 x float> @mixed_32(<4 x float> %a, i32 %b) { 1512entry: 1513; ALL-LABEL: mixed_32: 1514 1515; MIPS32-DAG: mtc1 $6, $f{{[0-9]+}} 1516; MIPS32-DAG: mtc1 $7, $f{{[0-9]+}} 1517; MIPS32-DAG: lwc1 $f{{[0-9]+}}, 28($sp) 1518; MIPS32-DAG: lwc1 $f{{[0-9]+}}, 24($sp) 1519; MIPS32-DAG: swc1 $f{{[0-9]+}}, 0($4) 1520; MIPS32-DAG: swc1 $f{{[0-9]+}}, 4($4) 1521; MIPS32-DAG: swc1 $f{{[0-9]+}}, 8($4) 1522; MIPS32-DAG: swc1 $f{{[0-9]+}}, 12($4) 1523 1524; MIPS32R5: insert.w $w[[W0:[0-9]+]][0], $6 1525; MIPS32R5: insert.w $w[[W0:[0-9]+]][1], $7 1526; MIPS32R5: lw $[[R0:[0-9]+]], 16($sp) 1527; MIPS32R5: insert.w $w[[W0:[0-9]+]][2], $[[R0]] 1528; MIPS32R5: lw $[[R1:[0-9]+]], 20($sp) 1529; MIPS32R5: insert.w $w[[W0:[0-9]+]][3], $[[R1]] 1530; MIPS32R5: lw $[[R0:[0-9]+]], 24($sp) 1531 1532; MIPS64-DAG: sll ${{[0-9]+}}, $6, 0 1533; MIPS64-DAG: dsrl $[[R0:[0-9]+]], $4, 32 1534; MIPS64-DAG: sll $[[R1:[0-9]+]], $[[R0]], 0 1535; MIPS64-DAG: mtc1 $[[R1]], $f{{[0-9]+}} 1536; MIPS64-DAG: sll $[[R2:[0-9]+]], $4, 0 1537; MIPS64-DAG: dsrl $[[R3:[0-9]+]], $5, 32 1538; MIPS64-DAG: sll $[[R4:[0-9]+]], $[[R3]], 0 1539; MIPS64-DAG: mtc1 $[[R4]], $f{{[0-9]+}} 1540; MIPS64-DAG: mtc1 $[[R2]], $f{{[0-9]+}} 1541; MIPS64-DAG: sll $[[R6:[0-9]+]], $5, 0 1542; MIPS64-DAG: mtc1 $[[R6:[0-9]+]], $f{{[0-9]+}} 1543 1544; MIPS64R5: insert.d $w[[W0:[0-9]+]][0], $4 1545; MIPS64R5: insert.d $w[[W0]][1], $5 1546; MIPS64R5: sll $[[R0:[0-9]+]], $6, 0 1547; MIPS64R5: fill.w $w{{[0-9]+}}, $[[R0]] 1548 1549 %0 = uitofp i32 %b to float 1550 %1 = insertelement <4 x float> undef, float %0, i32 0 1551 %2 = insertelement <4 x float> %1, float %0, i32 1 1552 %3 = insertelement <4 x float> %2, float %0, i32 2 1553 %4 = insertelement <4 x float> %3, float %0, i32 3 1554 %5 = fadd <4 x float> %4, %a 1555 ret <4 x float> %5 1556} 1557 1558 1559; This test is slightly more fragile than I'd like as the offset into the 1560; outgoing arguments area is dependant on the size of the stack frame for 1561; this function. 1562 1563define <4 x float> @cast(<4 x i32> %a) { 1564entry: 1565; ALL-LABEL: cast: 1566 1567; MIPS32: addiu $sp, $sp, -32 1568; MIPS32-DAG: sw $6, {{[0-9]+}}($sp) 1569; MIPS32-DAG: sw $7, {{[0-9]+}}($sp) 1570; MIPS32-DAG: lw ${{[0-9]+}}, 48($sp) 1571; MIPS32-DAG: lw ${{[0-9]+}}, 52($sp) 1572 1573; MIPS32R5-DAG: insert.w $w0[0], $6 1574; MIPS32R5-DAG: insert.w $w0[1], $7 1575; MIPS32R5-DAG: lw $[[R0:[0-9]+]], 16($sp) 1576; MIPS32R5-DAG: insert.w $w0[2], $[[R0]] 1577; MIPS32R5-DAG: lw $[[R1:[0-9]+]], 20($sp) 1578; MIPS32R5-DAG: insert.w $w0[3], $[[R1]] 1579 1580; MIPS64-DAG: sll ${{[0-9]+}}, $4, 0 1581; MIPS64-DAG: dsrl ${{[0-9]+}}, $4, 32 1582; MIPS64-DAG: sll ${{[0-9]+}}, $5, 0 1583; MIPS64-DAG: dsrl ${{[0-9]+}}, $5, 32 1584 1585; MIPS64R5-DAG: insert.d $w0[0], $4 1586; MIPS64R5-DAG: insert.d $w0[1], $5 1587 1588 %0 = uitofp <4 x i32> %a to <4 x float> 1589 ret <4 x float> %0 1590} 1591 1592define <4 x float> @select(<4 x i32> %cond, <4 x float> %arg1, <4 x float> %arg2) { 1593entry: 1594; ALL-LABEL: select: 1595 1596; MIPS32-DAG: andi ${{[0-9]+}}, $7, 1 1597; MIPS32-DAG: andi ${{[0-9]+}}, $6, 1 1598; MIPS32-DAG: lw $[[R0:[0-9]+]], 16($sp) 1599; MIPS32-DAG: andi ${{[0-9]+}}, $[[R0]], 1 1600; MIPS32-DAG: lw $[[R1:[0-9]+]], 20($sp) 1601; MIPS32-DAG: andi ${{[0-9]+}}, $[[R0]], 1 1602 1603; MIPS32R5-DAG: insert.w $w[[W0:[0-9]+]][0], $6 1604; MIPS32R5-DAG: insert.w $w[[W0]][1], $7 1605; MIPS32R5-DAG: lw $[[R0:[0-9]+]], 16($sp) 1606; MIPS32R5-DAG: lw $[[R1:[0-9]+]], 20($sp) 1607; MIPS32R5-DAG: insert.w $w[[W0]][2], $[[R0]] 1608; MIPS32R5-DAG: insert.w $w[[W0]][3], $[[R1]] 1609; MIPS32R5-DAG: slli.w $w{{[0-9]}}, $w[[W0]] 1610 1611; MIPS64-DAG: sll $[[R0:[0-9]+]], $6, 0 1612; MIPS64-DAG: mtc1 $[[R0]], $f{{[0-9]+}} 1613; MIPS64-DAG: dsrl $[[R1:[0-9]+]], $6, 32 1614; MIPS64-DAG: sll $[[R2:[0-9]+]], $[[R1]], 0 1615; MIPS64-DAG: mtc1 $[[R2]], $f{{[0-9]+}} 1616 1617; MIPS64-DAG: sll $[[R3:[0-9]+]], $7, 0 1618; MIPS64-DAG: mtc1 $[[R3]], $f{{[0-9]+}} 1619; MIPS64-DAG: dsrl $[[R4:[0-9]+]], $7, 32 1620; MIPS64-DAG: sll $[[R5:[0-9]+]], $[[R4]], 0 1621; MIPS64-DAG: mtc1 $[[R5]], $f{{[0-9]+}} 1622 1623; MIPS64-DAG: sll $[[R6:[0-9]+]], $8, 0 1624; MIPS64-DAG: mtc1 $[[R6]], $f{{[0-9]+}} 1625; MIPS64-DAG: dsrl $[[R7:[0-9]+]], $8, 32 1626; MIPS64-DAG: sll $[[R8:[0-9]+]], $[[R7]], 0 1627; MIPS64-DAG: mtc1 $[[R8]], $f{{[0-9]+}} 1628 1629; MIPS64-DAG: sll $[[R9:[0-9]+]], $9, 0 1630; MIPS64-DAG: mtc1 $[[R9]], $f{{[0-9]+}} 1631; MIPS64-DAG: dsrl $[[R10:[0-9]+]], $9, 32 1632; MIPS64-DAG: sll $[[R11:[0-9]+]], $[[R10]], 0 1633; MIPS64-DAG: mtc1 $[[R11]], $f{{[0-9]+}} 1634 1635; MIPS64-DAG: sll $[[R12:[0-9]+]], $4, 0 1636; MIPS64-DAG: andi ${{[0-9]+}}, $[[R12]], 1 1637; MIPS64-DAG: dsrl $[[R13:[0-9]+]], $4, 32 1638; MIPS64-DAG: sll $[[R14:[0-9]+]], $[[R13]], 0 1639; MIPS64-DAG: andi ${{[0-9]+}}, $[[R14]], 1 1640 1641; MIPS64-DAG: sll $[[R15:[0-9]+]], $5, 0 1642; MIPS64-DAG: andi ${{[0-9]+}}, $[[R15]], 1 1643; MIPS64-DAG: dsrl $[[R16:[0-9]+]], $5, 32 1644; MIPS64-DAG: sll $[[R17:[0-9]+]], $[[R16]], 0 1645; MIPS64-DAG: andi ${{[0-9]+}}, $[[R17]], 1 1646 1647; MIPS64R5-DAG: insert.d $w{{[0-9]+}}[0], $8 1648; MIPS64R5-DAG: insert.d $w{{[0-9]+}}[1], $9 1649; MIPS64R5-DAG: insert.d $w{{[0-9]+}}[0], $6 1650; MIPS64R5-DAG: insert.d $w{{[0-9]+}}[1], $7 1651; MIPS64R5-DAG: insert.d $w{{[0-9]+}}[0], $4 1652; MIPS64R5-DAG: insert.d $w{{[0-9]+}}[1], $5 1653 1654 %cond.t = trunc <4 x i32> %cond to <4 x i1> 1655 %res = select <4 x i1> %cond.t, <4 x float> %arg1, <4 x float> %arg2 1656 ret <4 x float> %res 1657} 1658