1; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32   < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=NO-SEB-SEH  -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
2; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
3; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=MIPSR6
4; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips4    < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=NO-SEB-SEH  -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
5; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64   < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=NO-SEB-SEH  -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
6; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
7; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=MIPSR6
8; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 -mattr=micromips < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=MICROMIPS
9
10; Keep one big-endian check so that we don't reduce testing, but don't add more
11; since endianness doesn't affect the body of the atomic operations.
12; RUN: llc -march=mips   --disable-machine-licm -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EB -check-prefix=NOT-MICROMIPS
13
14@x = common global i32 0, align 4
15
16define i32 @AtomicLoadAdd32(i32 signext %incr) nounwind {
17entry:
18  %0 = atomicrmw add i32* @x, i32 %incr monotonic
19  ret i32 %0
20
21; ALL-LABEL: AtomicLoadAdd32:
22
23; MIPS32-ANY:    lw      $[[R0:[0-9]+]], %got(x)
24; MIPS64-ANY:    ld      $[[R0:[0-9]+]], %got_disp(x)(
25
26; ALL:       $[[BB0:[A-Z_0-9]+]]:
27; ALL:           ll      $[[R1:[0-9]+]], 0($[[R0]])
28; ALL:           addu    $[[R2:[0-9]+]], $[[R1]], $4
29; ALL:           sc      $[[R2]], 0($[[R0]])
30; NOT-MICROMIPS: beqz    $[[R2]], $[[BB0]]
31; MICROMIPS:     beqzc   $[[R2]], $[[BB0]]
32; MIPSR6:        beqzc   $[[R2]], $[[BB0]]
33}
34
35define i32 @AtomicLoadNand32(i32 signext %incr) nounwind {
36entry:
37  %0 = atomicrmw nand i32* @x, i32 %incr monotonic
38  ret i32 %0
39
40; ALL-LABEL: AtomicLoadNand32:
41
42; MIPS32-ANY:    lw      $[[R0:[0-9]+]], %got(x)
43; MIPS64-ANY:    ld      $[[R0:[0-9]+]], %got_disp(x)(
44
45; ALL:       $[[BB0:[A-Z_0-9]+]]:
46; ALL:           ll      $[[R1:[0-9]+]], 0($[[R0]])
47; ALL:           and     $[[R3:[0-9]+]], $[[R1]], $4
48; ALL:           nor     $[[R2:[0-9]+]], $zero, $[[R3]]
49; ALL:           sc      $[[R2]], 0($[[R0]])
50; NOT-MICROMIPS: beqz    $[[R2]], $[[BB0]]
51; MICROMIPS:     beqzc   $[[R2]], $[[BB0]]
52; MIPSR6:        beqzc   $[[R2]], $[[BB0]]
53}
54
55define i32 @AtomicSwap32(i32 signext %newval) nounwind {
56entry:
57  %newval.addr = alloca i32, align 4
58  store i32 %newval, i32* %newval.addr, align 4
59  %tmp = load i32, i32* %newval.addr, align 4
60  %0 = atomicrmw xchg i32* @x, i32 %tmp monotonic
61  ret i32 %0
62
63; ALL-LABEL: AtomicSwap32:
64
65; MIPS32-ANY:    lw      $[[R0:[0-9]+]], %got(x)
66; MIPS64-ANY:    ld      $[[R0:[0-9]+]], %got_disp(x)
67
68; ALL:       $[[BB0:[A-Z_0-9]+]]:
69; ALL:           ll      ${{[0-9]+}}, 0($[[R0]])
70; ALL:           sc      $[[R2:[0-9]+]], 0($[[R0]])
71; NOT-MICROMIPS: beqz    $[[R2]], $[[BB0]]
72; MICROMIPS:     beqzc   $[[R2]], $[[BB0]]
73; MIPSR6:        beqzc   $[[R2]], $[[BB0]]
74}
75
76define i32 @AtomicCmpSwap32(i32 signext %oldval, i32 signext %newval) nounwind {
77entry:
78  %newval.addr = alloca i32, align 4
79  store i32 %newval, i32* %newval.addr, align 4
80  %tmp = load i32, i32* %newval.addr, align 4
81  %0 = cmpxchg i32* @x, i32 %oldval, i32 %tmp monotonic monotonic
82  %1 = extractvalue { i32, i1 } %0, 0
83  ret i32 %1
84
85; ALL-LABEL: AtomicCmpSwap32:
86
87; MIPS32-ANY:    lw      $[[R0:[0-9]+]], %got(x)
88; MIPS64-ANY:    ld      $[[R0:[0-9]+]], %got_disp(x)(
89
90; ALL:       $[[BB0:[A-Z_0-9]+]]:
91; ALL:           ll      $2, 0($[[R0]])
92; NOT-MICROMIPS: bne     $2, $4, $[[BB1:[A-Z_0-9]+]]
93; MICROMIPS:     bne     $2, $4, $[[BB1:[A-Z_0-9]+]]
94; MIPSR6:        bnec    $2, $4, $[[BB1:[A-Z_0-9]+]]
95; ALL:           sc      $[[R2:[0-9]+]], 0($[[R0]])
96; NOT-MICROMIPS: beqz    $[[R2]], $[[BB0]]
97; MICROMIPS:     beqzc   $[[R2]], $[[BB0]]
98; MIPSR6:        beqzc   $[[R2]], $[[BB0]]
99; ALL:       $[[BB1]]:
100}
101
102
103
104@y = common global i8 0, align 1
105
106define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind {
107entry:
108  %0 = atomicrmw add i8* @y, i8 %incr monotonic
109  ret i8 %0
110
111; ALL-LABEL: AtomicLoadAdd8:
112
113; MIPS32-ANY:    lw      $[[R0:[0-9]+]], %got(y)
114; MIPS64-ANY:    ld      $[[R0:[0-9]+]], %got_disp(y)(
115
116; ALL:           addiu   $[[R1:[0-9]+]], $zero, -4
117; ALL:           and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
118; ALL:           andi    $[[R3:[0-9]+]], $[[R0]], 3
119; CHECK-EB:      xori    $[[R4:[0-9]+]], $[[R3]], 3
120; CHECK-EB:      sll     $[[R5:[0-9]+]], $[[R4]], 3
121; CHECK-EL:      sll     $[[R5:[0-9]+]], $[[R3]], 3
122; ALL:           ori     $[[R6:[0-9]+]], $zero, 255
123; ALL:           sllv    $[[R7:[0-9]+]], $[[R6]], $[[R5]]
124; ALL:           nor     $[[R8:[0-9]+]], $zero, $[[R7]]
125; ALL:           sllv    $[[R9:[0-9]+]], $4, $[[R5]]
126
127; ALL:       $[[BB0:[A-Z_0-9]+]]:
128; ALL:           ll      $[[R10:[0-9]+]], 0($[[R2]])
129; ALL:           addu    $[[R11:[0-9]+]], $[[R10]], $[[R9]]
130; ALL:           and     $[[R12:[0-9]+]], $[[R11]], $[[R7]]
131; ALL:           and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
132; ALL:           or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
133; ALL:           sc      $[[R14]], 0($[[R2]])
134; NOT-MICROMIPS: beqz    $[[R14]], $[[BB0]]
135; MICROMIPS:     beqzc   $[[R14]], $[[BB0]]
136; MIPSR6:        beqzc   $[[R14]], $[[BB0]]
137
138; ALL:           and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
139; ALL:           srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
140
141; NO-SEB-SEH:    sll     $[[R17:[0-9]+]], $[[R16]], 24
142; NO-SEB-SEH:    sra     $2, $[[R17]], 24
143
144; HAS-SEB-SEH:   seb     $2, $[[R16]]
145}
146
147define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind {
148entry:
149  %0 = atomicrmw sub i8* @y, i8 %incr monotonic
150  ret i8 %0
151
152; ALL-LABEL: AtomicLoadSub8:
153
154; MIPS32-ANY: lw      $[[R0:[0-9]+]], %got(y)
155; MIPS64-ANY: ld      $[[R0:[0-9]+]], %got_disp(y)(
156
157; ALL:        addiu   $[[R1:[0-9]+]], $zero, -4
158; ALL:        and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
159; ALL:        andi    $[[R3:[0-9]+]], $[[R0]], 3
160; CHECK-EL:   sll     $[[R5:[0-9]+]], $[[R3]], 3
161; CHECK-EB:   xori    $[[R4:[0-9]+]], $[[R3]], 3
162; CHECK-EB:   sll     $[[R5:[0-9]+]], $[[R4]], 3
163; ALL:        ori     $[[R6:[0-9]+]], $zero, 255
164; ALL:        sllv    $[[R7:[0-9]+]], $[[R6]], $[[R5]]
165; ALL:        nor     $[[R8:[0-9]+]], $zero, $[[R7]]
166; ALL:        sllv    $[[R9:[0-9]+]], $4, $[[R5]]
167
168; ALL:    $[[BB0:[A-Z_0-9]+]]:
169; ALL:        ll      $[[R10:[0-9]+]], 0($[[R2]])
170; ALL:        subu    $[[R11:[0-9]+]], $[[R10]], $[[R9]]
171; ALL:        and     $[[R12:[0-9]+]], $[[R11]], $[[R7]]
172; ALL:        and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
173; ALL:        or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
174; ALL:        sc      $[[R14]], 0($[[R2]])
175; NOT-MICROMIPS: beqz    $[[R14]], $[[BB0]]
176; MICROMIPS:  beqzc   $[[R14]], $[[BB0]]
177; MIPSR6:     beqzc   $[[R14]], $[[BB0]]
178
179; ALL:        and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
180; ALL:        srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
181
182; NO-SEB-SEH: sll     $[[R17:[0-9]+]], $[[R16]], 24
183; NO-SEB-SEH: sra     $2, $[[R17]], 24
184
185; HAS-SEB-SEH:seb     $2, $[[R16]]
186}
187
188define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind {
189entry:
190  %0 = atomicrmw nand i8* @y, i8 %incr monotonic
191  ret i8 %0
192
193; ALL-LABEL: AtomicLoadNand8:
194
195; MIPS32-ANY:    lw      $[[R0:[0-9]+]], %got(y)
196; MIPS64-ANY:    ld      $[[R0:[0-9]+]], %got_disp(y)(
197
198; ALL:           addiu   $[[R1:[0-9]+]], $zero, -4
199; ALL:           and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
200; ALL:           andi    $[[R3:[0-9]+]], $[[R0]], 3
201; CHECK-EL:      sll     $[[R5:[0-9]+]], $[[R3]], 3
202; CHECK-EB:      xori    $[[R4:[0-9]+]], $[[R3]], 3
203; CHECK-EB:      sll     $[[R5:[0-9]+]], $[[R4]], 3
204; ALL:           ori     $[[R6:[0-9]+]], $zero, 255
205; ALL:           sllv    $[[R7:[0-9]+]], $[[R6]], $[[R5]]
206; ALL:           nor     $[[R8:[0-9]+]], $zero, $[[R7]]
207; ALL:           sllv    $[[R9:[0-9]+]], $4, $[[R5]]
208
209; ALL:       $[[BB0:[A-Z_0-9]+]]:
210; ALL:           ll      $[[R10:[0-9]+]], 0($[[R2]])
211; ALL:           and     $[[R18:[0-9]+]], $[[R10]], $[[R9]]
212; ALL:           nor     $[[R11:[0-9]+]], $zero, $[[R18]]
213; ALL:           and     $[[R12:[0-9]+]], $[[R11]], $[[R7]]
214; ALL:           and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
215; ALL:           or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
216; ALL:           sc      $[[R14]], 0($[[R2]])
217; NOT-MICROMIPS: beqz    $[[R14]], $[[BB0]]
218; MICROMIPS:     beqzc   $[[R14]], $[[BB0]]
219; MIPSR6:        beqzc   $[[R14]], $[[BB0]]
220
221; ALL:           and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
222; ALL:           srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
223
224; NO-SEB-SEH:    sll     $[[R17:[0-9]+]], $[[R16]], 24
225; NO-SEB-SEH:    sra     $2, $[[R17]], 24
226
227; HAS-SEB-SEH:   seb     $2, $[[R16]]
228}
229
230define signext i8 @AtomicSwap8(i8 signext %newval) nounwind {
231entry:
232  %0 = atomicrmw xchg i8* @y, i8 %newval monotonic
233  ret i8 %0
234
235; ALL-LABEL: AtomicSwap8:
236
237; MIPS32-ANY:    lw      $[[R0:[0-9]+]], %got(y)
238; MIPS64-ANY:    ld      $[[R0:[0-9]+]], %got_disp(y)(
239
240; ALL:           addiu   $[[R1:[0-9]+]], $zero, -4
241; ALL:           and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
242; ALL:           andi    $[[R3:[0-9]+]], $[[R0]], 3
243; CHECK-EL:      sll     $[[R5:[0-9]+]], $[[R3]], 3
244; CHECK-EB:      xori    $[[R4:[0-9]+]], $[[R3]], 3
245; CHECK-EB:      sll     $[[R5:[0-9]+]], $[[R4]], 3
246; ALL:           ori     $[[R6:[0-9]+]], $zero, 255
247; ALL:           sllv    $[[R7:[0-9]+]], $[[R6]], $[[R5]]
248; ALL:           nor     $[[R8:[0-9]+]], $zero, $[[R7]]
249; ALL:           sllv    $[[R9:[0-9]+]], $4, $[[R5]]
250
251; ALL:       $[[BB0:[A-Z_0-9]+]]:
252; ALL:           ll      $[[R10:[0-9]+]], 0($[[R2]])
253; ALL:           and     $[[R18:[0-9]+]], $[[R9]], $[[R7]]
254; ALL:           and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
255; ALL:           or      $[[R14:[0-9]+]], $[[R13]], $[[R18]]
256; ALL:           sc      $[[R14]], 0($[[R2]])
257; NOT-MICROMIPS: beqz    $[[R14]], $[[BB0]]
258; MICROMIPS:     beqzc   $[[R14]], $[[BB0]]
259; MIPSR6:        beqzc   $[[R14]], $[[BB0]]
260
261; ALL:           and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
262; ALL:           srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
263
264; NO-SEB-SEH:    sll     $[[R17:[0-9]+]], $[[R16]], 24
265; NO-SEB-SEH:    sra     $2, $[[R17]], 24
266
267; HAS-SEB-SEH:   seb     $2, $[[R16]]
268
269}
270
271define signext i8 @AtomicCmpSwap8(i8 signext %oldval, i8 signext %newval) nounwind {
272entry:
273  %pair0 = cmpxchg i8* @y, i8 %oldval, i8 %newval monotonic monotonic
274  %0 = extractvalue { i8, i1 } %pair0, 0
275  ret i8 %0
276
277; ALL-LABEL: AtomicCmpSwap8:
278
279; MIPS32-ANY:    lw      $[[R0:[0-9]+]], %got(y)
280; MIPS64-ANY:    ld      $[[R0:[0-9]+]], %got_disp(y)(
281
282; ALL:           addiu   $[[R1:[0-9]+]], $zero, -4
283; ALL:           and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
284; ALL:           andi    $[[R3:[0-9]+]], $[[R0]], 3
285; CHECK-EL:      sll     $[[R5:[0-9]+]], $[[R3]], 3
286; CHECK-EB:      xori    $[[R4:[0-9]+]], $[[R3]], 3
287; CHECK-EB:      sll     $[[R5:[0-9]+]], $[[R4]], 3
288; ALL:           ori     $[[R6:[0-9]+]], $zero, 255
289; ALL:           sllv    $[[R7:[0-9]+]], $[[R6]], $[[R5]]
290; ALL:           nor     $[[R8:[0-9]+]], $zero, $[[R7]]
291; ALL:           andi    $[[R9:[0-9]+]], $4, 255
292; ALL:           sllv    $[[R10:[0-9]+]], $[[R9]], $[[R5]]
293; ALL:           andi    $[[R11:[0-9]+]], $5, 255
294; ALL:           sllv    $[[R12:[0-9]+]], $[[R11]], $[[R5]]
295
296; ALL:       $[[BB0:[A-Z_0-9]+]]:
297; ALL:           ll      $[[R13:[0-9]+]], 0($[[R2]])
298; ALL:           and     $[[R14:[0-9]+]], $[[R13]], $[[R7]]
299; NOT-MICROMIPS: bne     $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]]
300; MICROMIPS:     bne     $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]]
301; MIPSR6:        bnec    $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]]
302
303; ALL:           and     $[[R15:[0-9]+]], $[[R13]], $[[R8]]
304; ALL:           or      $[[R16:[0-9]+]], $[[R15]], $[[R12]]
305; ALL:           sc      $[[R16]], 0($[[R2]])
306; NOT-MICROMIPS: beqz    $[[R16]], $[[BB0]]
307; MICROMIPS:     beqzc   $[[R16]], $[[BB0]]
308; MIPSR6:        beqzc   $[[R16]], $[[BB0]]
309
310; ALL:       $[[BB1]]:
311; ALL:           srlv    $[[R17:[0-9]+]], $[[R14]], $[[R5]]
312
313; NO-SEB-SEH:    sll     $[[R18:[0-9]+]], $[[R17]], 24
314; NO-SEB-SEH:    sra     $2, $[[R18]], 24
315
316; HAS-SEB-SEH:   seb     $2, $[[R17]]
317}
318
319define i1 @AtomicCmpSwapRes8(i8* %ptr, i8 signext %oldval, i8 signext %newval) nounwind {
320entry:
321  %0 = cmpxchg i8* %ptr, i8 %oldval, i8 %newval monotonic monotonic
322  %1 = extractvalue { i8, i1 } %0, 1
323  ret i1 %1
324; ALL-LABEL: AtomicCmpSwapRes8
325
326; ALL:           addiu   $[[R1:[0-9]+]], $zero, -4
327; ALL:           and     $[[R2:[0-9]+]], $4, $[[R1]]
328; ALL:           andi    $[[R3:[0-9]+]], $4, 3
329; CHECK-EL:      sll     $[[R5:[0-9]+]], $[[R3]], 3
330; CHECK-EB:      xori    $[[R4:[0-9]+]], $[[R3]], 3
331; CHECK-EB:      sll     $[[R5:[0-9]+]], $[[R4]], 3
332; ALL:           ori     $[[R6:[0-9]+]], $zero, 255
333; ALL:           sllv    $[[R7:[0-9]+]], $[[R6]], $[[R5]]
334; ALL:           nor     $[[R8:[0-9]+]], $zero, $[[R7]]
335; ALL:           andi    $[[R9:[0-9]+]], $5, 255
336; ALL:           sllv    $[[R10:[0-9]+]], $[[R9]], $[[R5]]
337; ALL:           andi    $[[R11:[0-9]+]], $6, 255
338; ALL:           sllv    $[[R12:[0-9]+]], $[[R11]], $[[R5]]
339
340; ALL:       $[[BB0:[A-Z_0-9]+]]:
341; ALL:           ll      $[[R13:[0-9]+]], 0($[[R2]])
342; ALL:           and     $[[R14:[0-9]+]], $[[R13]], $[[R7]]
343; NOT-MICROMIPS: bne     $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]]
344; MICROMIPS:     bne     $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]]
345; MIPSR6:        bnec    $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]]
346
347; ALL:           and     $[[R15:[0-9]+]], $[[R13]], $[[R8]]
348; ALL:           or      $[[R16:[0-9]+]], $[[R15]], $[[R12]]
349; ALL:           sc      $[[R16]], 0($[[R2]])
350; NOT-MICROMIPS: beqz    $[[R16]], $[[BB0]]
351; MICROMIPS:     beqzc   $[[R16]], $[[BB0]]
352; MIPSR6:        beqzc   $[[R16]], $[[BB0]]
353
354; ALL:       $[[BB1]]:
355; ALL:           srlv    $[[R17:[0-9]+]], $[[R14]], $[[R5]]
356
357; NO-SEB-SEH:    sll     $[[R18:[0-9]+]], $[[R17]], 24
358; NO-SEB-SEH:    sra     $[[R19:[0-9]+]], $[[R18]], 24
359
360; FIXME: -march=mips produces a redundant sign extension here...
361; NO-SEB-SEH:    sll     $[[R20:[0-9]+]], $5, 24
362; NO-SEB-SEH:    sra     $[[R20]], $[[R20]], 24
363
364; HAS-SEB-SEH:   seb     $[[R19:[0-9]+]], $[[R17]]
365
366; FIXME: ...Leading to this split check.
367; NO-SEB-SEH:    xor     $[[R21:[0-9]+]], $[[R19]], $[[R20]]
368; HAS-SEB-SEH:   xor     $[[R21:[0-9]+]], $[[R19]], $5
369
370; ALL: sltiu   $2, $[[R21]], 1
371}
372
373; Check one i16 so that we cover the seh sign extend
374@z = common global i16 0, align 1
375
376define signext i16 @AtomicLoadAdd16(i16 signext %incr) nounwind {
377entry:
378  %0 = atomicrmw add i16* @z, i16 %incr monotonic
379  ret i16 %0
380
381; ALL-LABEL: AtomicLoadAdd16:
382
383; MIPS32-ANY:    lw      $[[R0:[0-9]+]], %got(z)
384; MIPS64-ANY:    ld      $[[R0:[0-9]+]], %got_disp(z)(
385
386; ALL:           addiu   $[[R1:[0-9]+]], $zero, -4
387; ALL:           and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
388; ALL:           andi    $[[R3:[0-9]+]], $[[R0]], 3
389; CHECK-EB:      xori    $[[R4:[0-9]+]], $[[R3]], 2
390; CHECK-EB:      sll     $[[R5:[0-9]+]], $[[R4]], 3
391; CHECK-EL:      sll     $[[R5:[0-9]+]], $[[R3]], 3
392; ALL:           ori     $[[R6:[0-9]+]], $zero, 65535
393; ALL:           sllv    $[[R7:[0-9]+]], $[[R6]], $[[R5]]
394; ALL:           nor     $[[R8:[0-9]+]], $zero, $[[R7]]
395; ALL:           sllv    $[[R9:[0-9]+]], $4, $[[R5]]
396
397; ALL:       $[[BB0:[A-Z_0-9]+]]:
398; ALL:           ll      $[[R10:[0-9]+]], 0($[[R2]])
399; ALL:           addu    $[[R11:[0-9]+]], $[[R10]], $[[R9]]
400; ALL:           and     $[[R12:[0-9]+]], $[[R11]], $[[R7]]
401; ALL:           and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
402; ALL:           or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
403; ALL:           sc      $[[R14]], 0($[[R2]])
404; NOT-MICROMIPS: beqz    $[[R14]], $[[BB0]]
405; MICROMIPS:     beqzc   $[[R14]], $[[BB0]]
406; MIPSR6:        beqzc   $[[R14]], $[[BB0]]
407
408; ALL:           and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
409; ALL:           srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
410
411; NO-SEB-SEH:    sll     $[[R17:[0-9]+]], $[[R16]], 16
412; NO-SEB-SEH:    sra     $2, $[[R17]], 16
413
414; MIPS32R2:      seh     $2, $[[R16]]
415}
416
417; Test that the i16 return value from cmpxchg is recognised as signed,
418; so that setCC doesn't end up comparing an unsigned value to a signed
419; value.
420; The rest of the functions here are testing the atomic expansion, so
421; we just match the end of the function.
422define {i16, i1} @foo(i16* %addr, i16 %l, i16 %r, i16 %new) {
423  %desired = add i16 %l, %r
424  %res = cmpxchg i16* %addr, i16 %desired, i16 %new seq_cst seq_cst
425  ret {i16, i1} %res
426
427; ALL-LABEL: foo
428; MIPSR6:        addu    $[[R2:[0-9]+]], $[[R1:[0-9]+]], $[[R0:[0-9]+]]
429; NOT-MICROMIPS: addu    $[[R2:[0-9]+]], $[[R1:[0-9]+]], $[[R0:[0-9]+]]
430; MICROMIPS:     addu16  $[[R2:[0-9]+]], $[[R1:[0-9]+]], $[[R0:[0-9]+]]
431
432; ALL:           sync
433
434; ALL:           andi    $[[R3:[0-9]+]], $[[R2]], 65535
435; ALL:       $[[BB0:[A-Z_0-9]+]]:
436; ALL:           ll      $[[R4:[0-9]+]], 0($[[R5:[0-9]+]])
437; ALL:           and     $[[R6:[0-9]+]], $[[R4]], $
438; ALL:           and     $[[R7:[0-9]+]], $[[R4]], $
439; ALL:           or      $[[R8:[0-9]+]], $[[R7]], $
440; ALL:           sc      $[[R8]], 0($[[R5]])
441; NOT-MICROMIPS: beqz    $[[R8]], $[[BB0]]
442; MICROMIPS:     beqzc   $[[R8]], $[[BB0]]
443; MIPSR6:        beqzc   $[[R8]], $[[BB0]]
444
445; ALL:           srlv    $[[R9:[0-9]+]], $[[R6]], $
446
447; NO-SEB-SEH:    sll     $[[R10:[0-9]+]], $[[R9]], 16
448; NO-SEB-SEH:    sra     $[[R11:[0-9]+]], $[[R10]], 16
449
450; NO-SEB-SEH:    sll     $[[R12:[0-9]+]], $[[R2]], 16
451; NO-SEB-SEH:    sra     $[[R13:[0-9]+]], $[[R12]], 16
452
453; HAS-SEB-SEH:   seh     $[[R11:[0-9]+]], $[[R9]]
454; HAS-SEB-SEH:   seh     $[[R13:[0-9]+]], $[[R2]]
455
456; ALL:           xor     $[[R12:[0-9]+]], $[[R11]], $[[R13]]
457; ALL:           sltiu   $3, $[[R12]], 1
458; ALL:           sync
459}
460
461@countsint = common global i32 0, align 4
462
463define i32 @CheckSync(i32 signext %v) nounwind noinline {
464entry:
465  %0 = atomicrmw add i32* @countsint, i32 %v seq_cst
466  ret i32 %0
467
468; ALL-LABEL: CheckSync:
469
470; ALL:           sync
471; ALL:           ll
472; ALL:           sc
473; ALL:           beq
474; ALL:           sync
475}
476
477; make sure that this assertion in
478; TwoAddressInstructionPass::TryInstructionTransform does not fail:
479;
480; line 1203: assert(TargetRegisterInfo::isVirtualRegister(regB) &&
481;
482; it failed when MipsDAGToDAGISel::ReplaceUsesWithZeroReg replaced an
483; operand of an atomic instruction with register $zero.
484@a = external global i32
485
486define i32 @zeroreg() nounwind {
487entry:
488  %pair0 = cmpxchg i32* @a, i32 1, i32 0 seq_cst seq_cst
489  %0 = extractvalue { i32, i1 } %pair0, 0
490  %1 = icmp eq i32 %0, 1
491  %conv = zext i1 %1 to i32
492  ret i32 %conv
493}
494
495; Check that MIPS32R6 has the correct offset range.
496; FIXME: At the moment, we don't seem to do addr+offset for any atomic load/store.
497define i32 @AtomicLoadAdd32_OffGt9Bit(i32 signext %incr) nounwind {
498entry:
499  %0 = atomicrmw add i32* getelementptr(i32, i32* @x, i32 256), i32 %incr monotonic
500  ret i32 %0
501
502; ALL-LABEL: AtomicLoadAdd32_OffGt9Bit:
503
504; MIPS32-ANY:    lw      $[[R0:[0-9]+]], %got(x)
505; MIPS64-ANY:    ld      $[[R0:[0-9]+]], %got_disp(x)(
506
507; ALL:           addiu   $[[PTR:[0-9]+]], $[[R0]], 1024
508; ALL:       $[[BB0:[A-Z_0-9]+]]:
509; ALL:           ll      $[[R1:[0-9]+]], 0($[[PTR]])
510; ALL:           addu    $[[R2:[0-9]+]], $[[R1]], $4
511; ALL:           sc      $[[R2]], 0($[[PTR]])
512; NOT-MICROMIPS: beqz    $[[R2]], $[[BB0]]
513; MICROMIPS:     beqzc   $[[R2]], $[[BB0]]
514; MIPSR6:        beqzc   $[[R2]], $[[BB0]]
515}
516