1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=msp430-- < %s | FileCheck %s
3
4; Check the following conversion in TargetLowering::SimplifySetCC
5; (X & 8) != 0  -->  (X & 8) >> 3
6define i16 @testSimplifySetCC_0(i16 %x) {
7; CHECK-LABEL: testSimplifySetCC_0:
8; CHECK:       ; %bb.0: ; %entry
9; CHECK-NEXT:    bit #32, r12
10; CHECK-NEXT:    mov r2, r12
11; CHECK-NEXT:    and #1, r12
12; CHECK-NEXT:    ret
13entry:
14  %and = and i16 %x, 32
15  %cmp = icmp ne i16 %and, 0
16  %conv = zext i1 %cmp to i16
17  ret i16 %conv
18}
19
20; Check the following conversion in TargetLowering::SimplifySetCC
21; (X & 8) == 8  -->  (X & 8) >> 3
22define i16 @testSimplifySetCC_1(i16 %x) {
23; CHECK-LABEL: testSimplifySetCC_1:
24; CHECK:       ; %bb.0: ; %entry
25; CHECK-NEXT:    bit #32, r12
26; CHECK-NEXT:    mov r2, r12
27; CHECK-NEXT:    and #1, r12
28; CHECK-NEXT:    ret
29entry:
30  %and = and i16 %x, 32
31  %cmp = icmp eq i16 %and, 32
32  %conv = zext i1 %cmp to i16
33  ret i16 %conv
34}
35
36; Check the following conversion in DAGCombiner::SimplifySelectCC
37; (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
38define i16 @testSimplifySelectCC_0(i16 %x, i16 %a) {
39; CHECK-LABEL: testSimplifySelectCC_0:
40; CHECK:       ; %bb.0: ; %entry
41; CHECK-NEXT:    mov r12, r14
42; CHECK-NEXT:    clr r12
43; CHECK-NEXT:    bit #2048, r14
44; CHECK-NEXT:    jeq .LBB2_2
45; CHECK-NEXT:  ; %bb.1: ; %entry
46; CHECK-NEXT:    mov r13, r12
47; CHECK-NEXT:  .LBB2_2: ; %entry
48; CHECK-NEXT:    ret
49entry:
50  %and = and i16 %x, 2048
51  %cmp = icmp eq i16 %and, 0
52  %cond = select i1 %cmp, i16 0, i16 %a
53  ret i16 %cond
54}
55
56; Check the following conversion in DAGCombiner foldExtendedSignBitTest
57; sext i1 (setgt iN X, -1) --> sra (not X), (N - 1)
58define i16 @testExtendSignBit_0(i16 %x) {
59; CHECK-LABEL: testExtendSignBit_0:
60; CHECK:       ; %bb.0: ; %entry
61; CHECK-NEXT:    inv r12
62; CHECK-NEXT:    swpb r12
63; CHECK-NEXT:    sxt r12
64; CHECK-NEXT:    rra r12
65; CHECK-NEXT:    rra r12
66; CHECK-NEXT:    rra r12
67; CHECK-NEXT:    rra r12
68; CHECK-NEXT:    rra r12
69; CHECK-NEXT:    rra r12
70; CHECK-NEXT:    rra r12
71; CHECK-NEXT:    ret
72entry:
73  %cmp = icmp sgt i16 %x, -1
74  %cond = sext i1 %cmp to i16
75  ret i16 %cond
76}
77
78; Check the following conversion in DAGCombiner foldExtendedSignBitTest
79; zext i1 (setgt iN X, -1) --> srl (not X), (N - 1)
80define i16 @testExtendSignBit_1(i16 %x) {
81; CHECK-LABEL: testExtendSignBit_1:
82; CHECK:       ; %bb.0: ; %entry
83; CHECK-NEXT:    inv r12
84; CHECK-NEXT:    swpb r12
85; CHECK-NEXT:    mov.b r12, r12
86; CHECK-NEXT:    clrc
87; CHECK-NEXT:    rrc r12
88; CHECK-NEXT:    rra r12
89; CHECK-NEXT:    rra r12
90; CHECK-NEXT:    rra r12
91; CHECK-NEXT:    rra r12
92; CHECK-NEXT:    rra r12
93; CHECK-NEXT:    rra r12
94; CHECK-NEXT:    ret
95entry:
96  %cmp = icmp sgt i16 %x, -1
97  %cond = zext i1 %cmp to i16
98  ret i16 %cond
99}
100
101; Check the following conversion in DAGCombiner::foldSelectCCToShiftAnd
102; select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
103define i16 @testShiftAnd_0(i16 %x, i16 %a) {
104; CHECK-LABEL: testShiftAnd_0:
105; CHECK:       ; %bb.0: ; %entry
106; CHECK-NEXT:    swpb r12
107; CHECK-NEXT:    sxt r12
108; CHECK-NEXT:    rra r12
109; CHECK-NEXT:    rra r12
110; CHECK-NEXT:    rra r12
111; CHECK-NEXT:    rra r12
112; CHECK-NEXT:    rra r12
113; CHECK-NEXT:    rra r12
114; CHECK-NEXT:    rra r12
115; CHECK-NEXT:    and r13, r12
116; CHECK-NEXT:    ret
117entry:
118  %cmp = icmp slt i16 %x, 0
119  %cond = select i1 %cmp, i16 %a, i16 0
120  ret i16 %cond
121}
122
123; Check the following conversion in DAGCombiner::foldSelectCCToShiftAnd
124; select_cc setlt X, 0, A, 0 -> "and (srl X, C2), A" iff A is a single-bit
125define i16 @testShiftAnd_1(i16 %x) {
126; CHECK-LABEL: testShiftAnd_1:
127; CHECK:       ; %bb.0: ; %entry
128; CHECK-NEXT:    swpb r12
129; CHECK-NEXT:    mov.b r12, r12
130; CHECK-NEXT:    clrc
131; CHECK-NEXT:    rrc r12
132; CHECK-NEXT:    rra r12
133; CHECK-NEXT:    rra r12
134; CHECK-NEXT:    rra r12
135; CHECK-NEXT:    rra r12
136; CHECK-NEXT:    rra r12
137; CHECK-NEXT:    and #2, r12
138; CHECK-NEXT:    ret
139entry:
140  %cmp = icmp slt i16 %x, 0
141  %cond = select i1 %cmp, i16 2, i16 0
142  ret i16 %cond
143}
144
145; Check the following conversion in DAGCombiner::SimplifySelectCC
146; select C, 16, 0 -> shl C, 4
147define i16 @testSimplifySelectCC_1(i16 %a, i16 %b) {
148; CHECK-LABEL: testSimplifySelectCC_1:
149; CHECK:       ; %bb.0: ; %entry
150; CHECK-NEXT:    mov r12, r14
151; CHECK-NEXT:    mov #1, r12
152; CHECK-NEXT:    cmp r14, r13
153; CHECK-NEXT:    jl .LBB7_2
154; CHECK-NEXT:  ; %bb.1: ; %entry
155; CHECK-NEXT:    clr r12
156; CHECK-NEXT:  .LBB7_2: ; %entry
157; CHECK-NEXT:    add r12, r12
158; CHECK-NEXT:    add r12, r12
159; CHECK-NEXT:    add r12, r12
160; CHECK-NEXT:    add r12, r12
161; CHECK-NEXT:    add r12, r12
162; CHECK-NEXT:    ret
163entry:
164  %cmp = icmp sgt i16 %a, %b
165  %cond = select i1 %cmp, i16 32, i16 0
166  ret i16 %cond
167}
168