1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=msp430-- -msp430-no-legal-immediate=true < %s | FileCheck %s
3
4; Test case for the following transformation in TargetLowering::SimplifySetCC
5; (X & -256) == 256 -> (X >> 8) == 1
6define i16 @testSimplifySetCC_2(i16 %x) {
7; CHECK-LABEL: testSimplifySetCC_2:
8; CHECK:       ; %bb.0: ; %entry
9; CHECK-NEXT:    clrc
10; CHECK-NEXT:    rrc r12
11; CHECK-NEXT:    rra r12
12; CHECK-NEXT:    rra r12
13; CHECK-NEXT:    rra r12
14; CHECK-NEXT:    rra r12
15; CHECK-NEXT:    rra r12
16; CHECK-NEXT:    cmp #1, r12
17; CHECK-NEXT:    mov r2, r12
18; CHECK-NEXT:    rra r12
19; CHECK-NEXT:    and #1, r12
20; CHECK-NEXT:    ret
21entry:
22  %and = and i16 %x, -64
23  %cmp = icmp eq i16 %and, 64
24  %conv = zext i1 %cmp to i16
25  ret i16 %conv
26}
27
28; Test case for the following transformation in TargetLowering::SimplifySetCC
29; X >  0x0ffffffff -> (X >> 32) >= 1
30define i16 @testSimplifySetCC_3(i16 %x) {
31; CHECK-LABEL: testSimplifySetCC_3:
32; CHECK:       ; %bb.0: ; %entry
33; CHECK-NEXT:    clrc
34; CHECK-NEXT:    rrc r12
35; CHECK-NEXT:    rra r12
36; CHECK-NEXT:    rra r12
37; CHECK-NEXT:    rra r12
38; CHECK-NEXT:    rra r12
39; CHECK-NEXT:    rra r12
40; CHECK-NEXT:    tst r12
41; CHECK-NEXT:    mov r2, r13
42; CHECK-NEXT:    rra r13
43; CHECK-NEXT:    mov #1, r12
44; CHECK-NEXT:    bic r13, r12
45; CHECK-NEXT:    ret
46entry:
47  %cmp = icmp ugt i16 %x, 63
48  %conv = zext i1 %cmp to i16
49  ret i16 %conv
50}
51
52; Test case for the following transformation in TargetLowering::SimplifySetCC
53; X <  0x100000000 -> (X >> 32) <  1
54define i16 @testSimplifySetCC_4(i16 %x) {
55; CHECK-LABEL: testSimplifySetCC_4:
56; CHECK:       ; %bb.0: ; %entry
57; CHECK-NEXT:    clrc
58; CHECK-NEXT:    rrc r12
59; CHECK-NEXT:    rra r12
60; CHECK-NEXT:    rra r12
61; CHECK-NEXT:    rra r12
62; CHECK-NEXT:    rra r12
63; CHECK-NEXT:    rra r12
64; CHECK-NEXT:    tst r12
65; CHECK-NEXT:    mov r2, r12
66; CHECK-NEXT:    rra r12
67; CHECK-NEXT:    and #1, r12
68; CHECK-NEXT:    ret
69entry:
70  %cmp = icmp ult i16 %x, 64
71  %conv = zext i1 %cmp to i16
72  ret i16 %conv
73}
74