1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -run-pass=none -o - %s | FileCheck %s
3--- |
4  ; ModuleID = 'test/CodeGen/AMDGPU/memcpy-scoped-aa.ll'
5  source_filename = "test/CodeGen/AMDGPU/memcpy-scoped-aa.ll"
6  target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7"
7  target triple = "amdgcn-amd-amdhsa"
8
9  define i32 @test_memcpy(i32 addrspace(1)* nocapture %p, i32 addrspace(1)* nocapture readonly %q) #0 {
10    %p0 = bitcast i32 addrspace(1)* %p to i8 addrspace(1)*
11    %add.ptr = getelementptr inbounds i32, i32 addrspace(1)* %p, i64 4
12    %p1 = bitcast i32 addrspace(1)* %add.ptr to i8 addrspace(1)*
13    tail call void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* noundef nonnull align 4 dereferenceable(16) %p0, i8 addrspace(1)* noundef nonnull align 4 dereferenceable(16) %p1, i64 16, i1 false), !alias.scope !0, !noalias !3
14    %1 = bitcast i32 addrspace(1)* %q to <2 x i32> addrspace(1)*
15    %2 = load <2 x i32>, <2 x i32> addrspace(1)* %1, align 4, !alias.scope !3, !noalias !0
16    %v01 = extractelement <2 x i32> %2, i32 0
17    %v12 = extractelement <2 x i32> %2, i32 1
18    %add = add i32 %v01, %v12
19    ret i32 %add
20  }
21
22  define i32 @test_memcpy_inline(i32 addrspace(1)* nocapture %p, i32 addrspace(1)* nocapture readonly %q) #0 {
23    %p0 = bitcast i32 addrspace(1)* %p to i8 addrspace(1)*
24    %add.ptr = getelementptr inbounds i32, i32 addrspace(1)* %p, i64 4
25    %p1 = bitcast i32 addrspace(1)* %add.ptr to i8 addrspace(1)*
26    tail call void @llvm.memcpy.inline.p1i8.p1i8.i64(i8 addrspace(1)* noundef nonnull align 4 dereferenceable(16) %p0, i8 addrspace(1)* noundef nonnull align 4 dereferenceable(16) %p1, i64 16, i1 false), !alias.scope !0, !noalias !3
27    %1 = bitcast i32 addrspace(1)* %q to <2 x i32> addrspace(1)*
28    %2 = load <2 x i32>, <2 x i32> addrspace(1)* %1, align 4, !alias.scope !3, !noalias !0
29    %v01 = extractelement <2 x i32> %2, i32 0
30    %v12 = extractelement <2 x i32> %2, i32 1
31    %add = add i32 %v01, %v12
32    ret i32 %add
33  }
34
35  ; Function Attrs: argmemonly nofree nounwind willreturn
36  declare void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* noalias nocapture writeonly, i8 addrspace(1)* noalias nocapture readonly, i64, i1 immarg) #1
37
38  ; Function Attrs: argmemonly nofree nounwind willreturn
39  declare void @llvm.memcpy.inline.p1i8.p1i8.i64(i8 addrspace(1)* noalias nocapture writeonly, i8 addrspace(1)* noalias nocapture readonly, i64 immarg, i1 immarg) #1
40
41  ; Function Attrs: convergent nounwind willreturn
42  declare { i1, i32 } @llvm.amdgcn.if.i32(i1) #2
43
44  ; Function Attrs: convergent nounwind willreturn
45  declare { i1, i32 } @llvm.amdgcn.else.i32.i32(i32) #2
46
47  ; Function Attrs: convergent nounwind readnone willreturn
48  declare i32 @llvm.amdgcn.if.break.i32(i1, i32) #3
49
50  ; Function Attrs: convergent nounwind willreturn
51  declare i1 @llvm.amdgcn.loop.i32(i32) #2
52
53  ; Function Attrs: convergent nounwind willreturn
54  declare void @llvm.amdgcn.end.cf.i32(i32) #2
55
56  attributes #0 = { "target-cpu"="gfx1010" }
57  attributes #1 = { argmemonly nofree nounwind willreturn "target-cpu"="gfx1010" }
58  attributes #2 = { convergent nounwind willreturn }
59  attributes #3 = { convergent nounwind readnone willreturn }
60
61  !0 = !{!1}
62  !1 = distinct !{!1, !2, !"bax: %p"}
63  !2 = distinct !{!2, !"bax"}
64  !3 = !{!4}
65  !4 = distinct !{!4, !2, !"bax: %q"}
66
67...
68---
69name:            test_memcpy
70machineMetadataNodes:
71  - '!9 = distinct !{!9, !7, !"Dst"}'
72  - '!6 = distinct !{!6, !7, !"Src"}'
73  - '!11 = !{!4, !6}'
74  - '!5 = !{!1, !6}'
75  - '!8 = !{!4, !9}'
76  - '!10 = !{!1, !9}'
77  - '!7 = distinct !{!7, !"MemcpyLoweringDomain"}'
78body:             |
79  bb.0 (%ir-block.0):
80    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
81
82    ; CHECK-LABEL: name: test_memcpy
83    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr30_sgpr31
84    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3
85    ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
86    ; CHECK: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1
87    ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
88    ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY1]], %subreg.sub1
89    ; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY3]], %subreg.sub1
90    ; CHECK: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]]
91    ; CHECK: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 [[COPY5]], 16, 0, implicit $exec :: (load (s128) from %ir.p1, align 4, !alias.scope !5, !noalias !8, addrspace 1)
92    ; CHECK: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]]
93    ; CHECK: GLOBAL_STORE_DWORDX4 [[COPY6]], killed [[GLOBAL_LOAD_DWORDX4_]], 0, 0, implicit $exec :: (store (s128) into %ir.p0, align 4, !alias.scope !10, !noalias !11, addrspace 1)
94    ; CHECK: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]]
95    ; CHECK: [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2 killed [[COPY7]], 0, 0, implicit $exec :: (load (s64) from %ir.1, align 4, !alias.scope !3, !noalias !0, addrspace 1)
96    ; CHECK: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_]].sub0
97    ; CHECK: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_]].sub1
98    ; CHECK: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[COPY8]], killed [[COPY9]], 0, implicit $exec
99    ; CHECK: [[COPY10:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
100    ; CHECK: $vgpr0 = COPY [[V_ADD_U32_e64_]]
101    ; CHECK: [[COPY11:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY10]]
102    ; CHECK: S_SETPC_B64_return [[COPY11]], implicit $vgpr0
103    %4:sreg_64 = COPY $sgpr30_sgpr31
104    %3:vgpr_32 = COPY $vgpr3
105    %2:vgpr_32 = COPY $vgpr2
106    %1:vgpr_32 = COPY $vgpr1
107    %0:vgpr_32 = COPY $vgpr0
108    %17:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
109    %18:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
110    %9:vreg_64 = COPY %18
111    %8:vreg_128 = GLOBAL_LOAD_DWORDX4 %9, 16, 0, implicit $exec :: (load (s128) from %ir.p1, align 4, !alias.scope !5, !noalias !8, addrspace 1)
112    %10:vreg_64 = COPY %18
113    GLOBAL_STORE_DWORDX4 %10, killed %8, 0, 0, implicit $exec :: (store (s128) into %ir.p0, align 4, !alias.scope !10, !noalias !11, addrspace 1)
114    %12:vreg_64 = COPY %17
115    %11:vreg_64 = GLOBAL_LOAD_DWORDX2 killed %12, 0, 0, implicit $exec :: (load (s64) from %ir.1, align 4, !alias.scope !3, !noalias !0, addrspace 1)
116    %13:vgpr_32 = COPY %11.sub0
117    %14:vgpr_32 = COPY %11.sub1
118    %15:vgpr_32 = V_ADD_U32_e64 killed %13, killed %14, 0, implicit $exec
119    %5:ccr_sgpr_64 = COPY %4
120    $vgpr0 = COPY %15
121    %16:ccr_sgpr_64 = COPY %5
122    S_SETPC_B64_return %16, implicit $vgpr0
123
124...
125---
126name:            test_memcpy_inline
127machineMetadataNodes:
128  - '!6 = distinct !{!6, !7, !"Src"}'
129  - '!7 = distinct !{!7, !"MemcpyLoweringDomain"}'
130  - '!9 = distinct !{!9, !7, !"Dst"}'
131  - '!11 = !{!4, !6}'
132  - '!5 = !{!1, !6}'
133  - '!8 = !{!4, !9}'
134  - '!10 = !{!1, !9}'
135body:             |
136  bb.0 (%ir-block.0):
137    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
138
139    ; CHECK-LABEL: name: test_memcpy_inline
140    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr30_sgpr31
141    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3
142    ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
143    ; CHECK: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1
144    ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
145    ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY1]], %subreg.sub1
146    ; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY3]], %subreg.sub1
147    ; CHECK: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]]
148    ; CHECK: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 [[COPY5]], 16, 0, implicit $exec :: (load (s128) from %ir.p1, align 4, !alias.scope !5, !noalias !8, addrspace 1)
149    ; CHECK: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]]
150    ; CHECK: GLOBAL_STORE_DWORDX4 [[COPY6]], killed [[GLOBAL_LOAD_DWORDX4_]], 0, 0, implicit $exec :: (store (s128) into %ir.p0, align 4, !alias.scope !10, !noalias !11, addrspace 1)
151    ; CHECK: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]]
152    ; CHECK: [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2 killed [[COPY7]], 0, 0, implicit $exec :: (load (s64) from %ir.1, align 4, !alias.scope !3, !noalias !0, addrspace 1)
153    ; CHECK: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_]].sub0
154    ; CHECK: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[GLOBAL_LOAD_DWORDX2_]].sub1
155    ; CHECK: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[COPY8]], killed [[COPY9]], 0, implicit $exec
156    ; CHECK: [[COPY10:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
157    ; CHECK: $vgpr0 = COPY [[V_ADD_U32_e64_]]
158    ; CHECK: [[COPY11:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY10]]
159    ; CHECK: S_SETPC_B64_return [[COPY11]], implicit $vgpr0
160    %4:sreg_64 = COPY $sgpr30_sgpr31
161    %3:vgpr_32 = COPY $vgpr3
162    %2:vgpr_32 = COPY $vgpr2
163    %1:vgpr_32 = COPY $vgpr1
164    %0:vgpr_32 = COPY $vgpr0
165    %17:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
166    %18:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
167    %9:vreg_64 = COPY %18
168    %8:vreg_128 = GLOBAL_LOAD_DWORDX4 %9, 16, 0, implicit $exec :: (load (s128) from %ir.p1, align 4, !alias.scope !5, !noalias !8, addrspace 1)
169    %10:vreg_64 = COPY %18
170    GLOBAL_STORE_DWORDX4 %10, killed %8, 0, 0, implicit $exec :: (store (s128) into %ir.p0, align 4, !alias.scope !10, !noalias !11, addrspace 1)
171    %12:vreg_64 = COPY %17
172    %11:vreg_64 = GLOBAL_LOAD_DWORDX2 killed %12, 0, 0, implicit $exec :: (load (s64) from %ir.1, align 4, !alias.scope !3, !noalias !0, addrspace 1)
173    %13:vgpr_32 = COPY %11.sub0
174    %14:vgpr_32 = COPY %11.sub1
175    %15:vgpr_32 = V_ADD_U32_e64 killed %13, killed %14, 0, implicit $exec
176    %5:ccr_sgpr_64 = COPY %4
177    $vgpr0 = COPY %15
178    %16:ccr_sgpr_64 = COPY %5
179    S_SETPC_B64_return %16, implicit $vgpr0
180
181...
182