1; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
2
3define i64 @lshr40_and255(i64 %a) {
4; CHECK-LABEL: lshr40_and255:
5; CHECK:       # %bb.0:
6; CHECK-NEXT:    bstrpick.d $a0, $a0, 47, 40
7; CHECK-NEXT:    jirl $zero, $ra, 0
8  %shr = lshr i64 %a, 40
9  %and = and i64 %shr, 255
10  ret i64 %and
11}
12
13define i64 @ashr50_and511(i64 %a) {
14; CHECK-LABEL: ashr50_and511:
15; CHECK:       # %bb.0:
16; CHECK-NEXT:    bstrpick.d $a0, $a0, 58, 50
17; CHECK-NEXT:    jirl $zero, $ra, 0
18  %shr = ashr i64 %a, 50
19  %and = and i64 %shr, 511
20  ret i64 %and
21}
22
23define i64 @zext_i32_to_i64(i32 %a) {
24; CHECK-LABEL: zext_i32_to_i64:
25; CHECK:       # %bb.0:
26; CHECK-NEXT:    bstrpick.d $a0, $a0, 31, 0
27; CHECK-NEXT:    jirl $zero, $ra, 0
28  %res = zext i32 %a to i64
29  ret i64 %res
30}
31
32define i64 @and8191(i64 %a) {
33; CHECK-LABEL: and8191:
34; CHECK:       # %bb.0:
35; CHECK-NEXT:    bstrpick.d $a0, $a0, 12, 0
36; CHECK-NEXT:    jirl $zero, $ra, 0
37  %and = and i64 %a, 8191
38  ret i64 %and
39}
40
41;; Check that andi but not bstrpick.d is generated.
42define i64 @and4095(i64 %a) {
43; CHECK-LABEL: and4095:
44; CHECK:       # %bb.0:
45; CHECK-NEXT:    andi $a0, $a0, 4095
46; CHECK-NEXT:    jirl $zero, $ra, 0
47  %and = and i64 %a, 4095
48  ret i64 %and
49}
50
51;; (srl (and a, 0xff0), 4) => (BSTRPICK a, 11, 4)
52define i64 @and0xff0_lshr4(i64 %a) {
53; CHECK-LABEL: and0xff0_lshr4:
54; CHECK:       # %bb.0:
55; CHECK-NEXT:    bstrpick.d $a0, $a0, 11, 4
56; CHECK-NEXT:    jirl $zero, $ra, 0
57  %and = and i64 %a, 4080
58  %shr = lshr i64 %and, 4
59  ret i64 %shr
60}
61
62;; (sra (and a, 0xff0), 5) can also be combined to (BSTRPICK a, 11, 5).
63;; This is because (sra (and a, 0xff0)) would be combined to (srl (and a, 0xff0), 5)
64;; firstly by DAGCombiner::SimplifyDemandedBits.
65define i64 @and4080_ashr5(i64 %a) {
66; CHECK-LABEL: and4080_ashr5:
67; CHECK:       # %bb.0:
68; CHECK-NEXT:    bstrpick.d $a0, $a0, 11, 5
69; CHECK-NEXT:    jirl $zero, $ra, 0
70  %and = and i64 %a, 4080
71  %shr = ashr i64 %and, 5
72  ret i64 %shr
73}
74
75;; Negative test: the second operand of AND is not a shifted mask
76define i64 @and0xf30_lshr4(i64 %a) {
77; CHECK-LABEL: and0xf30_lshr4:
78; CHECK:       # %bb.0:
79; CHECK-NEXT:    andi $a0, $a0, 3888
80; CHECK-NEXT:    srli.d $a0, $a0, 4
81; CHECK-NEXT:    jirl $zero, $ra, 0
82  %and = and i64 %a, 3888
83  %shr = lshr i64 %and, 4
84  ret i64 %shr
85}
86
87;; Negative test: Shamt < MaskIdx
88define i64 @and0xff0_lshr3(i64 %a) {
89; CHECK-LABEL: and0xff0_lshr3:
90; CHECK:       # %bb.0:
91; CHECK-NEXT:    andi $a0, $a0, 4080
92; CHECK-NEXT:    srli.d $a0, $a0, 3
93; CHECK-NEXT:    jirl $zero, $ra, 0
94  %and = and i64 %a, 4080
95  %shr = lshr i64 %and, 3
96  ret i64 %shr
97}
98