1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=hexagon < %s | FileCheck %s
3
4; Function Attrs: nounwind
5define <32 x i32> @f0(i8* %a0, i32 %a1) #0 {
6; CHECK-LABEL: f0:
7; CHECK:       // %bb.0: // %b0
8; CHECK-NEXT:    {
9; CHECK-NEXT:     r0 = add(r1,r0)
10; CHECK-NEXT:    }
11; CHECK-NEXT:    {
12; CHECK-NEXT:     r7 = #8
13; CHECK-NEXT:    }
14; CHECK-NEXT:    {
15; CHECK-NEXT:     r4 = ##.LCPI0_0
16; CHECK-NEXT:    }
17; CHECK-NEXT:    {
18; CHECK-NEXT:     r2 = #-1
19; CHECK-NEXT:    }
20; CHECK-NEXT:    {
21; CHECK-NEXT:     v0 = vmem(r0+#1)
22; CHECK-NEXT:    }
23; CHECK-NEXT:    {
24; CHECK-NEXT:     v1 = vmem(r0+#2)
25; CHECK-NEXT:    }
26; CHECK-NEXT:    {
27; CHECK-NEXT:     r0 = add(r0,#128)
28; CHECK-NEXT:    }
29; CHECK-NEXT:    {
30; CHECK-NEXT:     v1 = valign(v1,v0,r7)
31; CHECK-NEXT:    }
32; CHECK-NEXT:    {
33; CHECK-NEXT:     v2 = vmem(r4+#0)
34; CHECK-NEXT:    }
35; CHECK-NEXT:    {
36; CHECK-NEXT:     q0 = vand(v2,r2)
37; CHECK-NEXT:    }
38; CHECK-NEXT:    {
39; CHECK-NEXT:     v0.w = vadd(v0.w,v1.w)
40; CHECK-NEXT:    }
41; CHECK-NEXT:    {
42; CHECK-NEXT:     if (q0) vmem(r0+#0) = v0
43; CHECK-NEXT:    }
44; CHECK-NEXT:    {
45; CHECK-NEXT:     jumpr r31
46; CHECK-NEXT:    }
47b0:
48  %v0 = add i32 %a1, 128
49  %v1 = getelementptr i8, i8* %a0, i32 %v0
50  %v2 = bitcast i8* %v1 to <32 x i32>*
51  %v3 = tail call <32 x i32> @llvm.masked.load.v32i32.p0v32i32(<32 x i32>* %v2, i32 128, <32 x i1> <i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <32 x i32> undef)
52  %v4 = add i32 %a1, 136
53  %v5 = getelementptr i8, i8* %a0, i32 %v4
54  %v6 = bitcast i8* %v5 to <32 x i32>*
55  %v7 = tail call <32 x i32> @llvm.masked.load.v32i32.p0v32i32(<32 x i32>* %v6, i32 8, <32 x i1> <i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <32 x i32> undef)
56  %v8 = add <32 x i32> %v3, %v7
57  tail call void @llvm.masked.store.v32i32.p0v32i32(<32 x i32> %v8, <32 x i32>* %v2, i32 128, <32 x i1> <i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>)
58  ret <32 x i32> %v8
59}
60
61; Function Attrs: argmemonly nounwind readonly willreturn
62declare <32 x i32> @llvm.masked.load.v32i32.p0v32i32(<32 x i32>*, i32 immarg, <32 x i1>, <32 x i32>) #1
63
64; Function Attrs: argmemonly nounwind willreturn
65declare void @llvm.masked.store.v32i32.p0v32i32(<32 x i32>, <32 x i32>*, i32 immarg, <32 x i1>) #2
66
67attributes #0 = { nounwind "target-cpu"="hexagonv66" "target-features"="+hvx,+hvx-length128b,-packets" }
68attributes #1 = { argmemonly nounwind readonly willreturn }
69attributes #2 = { argmemonly nounwind willreturn }
70