1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+2e3 | FileCheck %s 3 4define i32 @selectRR_eq_i32(i32 %x, i32 %y, i32 %n, i32 %m) { 5; CHECK-LABEL: selectRR_eq_i32: 6; CHECK: # %bb.0: # %entry 7; CHECK-NEXT: cmpne16 a1, a0 8; CHECK-NEXT: movf32 a2, a3 9; CHECK-NEXT: mov16 a0, a2 10; CHECK-NEXT: rts16 11entry: 12 %icmp = icmp eq i32 %y, %x 13 %ret = select i1 %icmp, i32 %m, i32 %n 14 ret i32 %ret 15} 16 17define i32 @selectRI_eq_i32(i32 %x, i32 %n, i32 %m) { 18; CHECK-LABEL: selectRI_eq_i32: 19; CHECK: # %bb.0: # %entry 20; CHECK-NEXT: cmpnei16 a0, 10 21; CHECK-NEXT: movf32 a1, a2 22; CHECK-NEXT: mov16 a0, a1 23; CHECK-NEXT: rts16 24entry: 25 %icmp = icmp eq i32 %x, 10 26 %ret = select i1 %icmp, i32 %m, i32 %n 27 ret i32 %ret 28} 29 30define i32 @selectRX_eq_i32(i32 %x, i32 %n, i32 %m) { 31; CHECK-LABEL: selectRX_eq_i32: 32; CHECK: # %bb.0: # %entry 33; CHECK-NEXT: movih32 a3, 729 34; CHECK-NEXT: ori32 a3, a3, 2033 35; CHECK-NEXT: cmpne16 a0, a3 36; CHECK-NEXT: movf32 a1, a2 37; CHECK-NEXT: mov16 a0, a1 38; CHECK-NEXT: rts16 39entry: 40 %icmp = icmp eq i32 %x, 47777777 41 %ret = select i1 %icmp, i32 %m, i32 %n 42 ret i32 %ret 43} 44 45define i32 @selectC_eq_i32(i1 %c, i32 %n, i32 %m) { 46; CHECK-LABEL: selectC_eq_i32: 47; CHECK: # %bb.0: # %entry 48; CHECK-NEXT: btsti32 a0, 0 49; CHECK-NEXT: movt32 a1, a2 50; CHECK-NEXT: mov16 a0, a1 51; CHECK-NEXT: rts16 52entry: 53 %ret = select i1 %c, i32 %m, i32 %n 54 ret i32 %ret 55} 56 57define i64 @selectRR_eq_i64(i64 %x, i64 %y, i64 %n, i64 %m) { 58; CHECK-LABEL: selectRR_eq_i64: 59; CHECK: # %bb.0: # %entry 60; CHECK-NEXT: xor16 a1, a3 61; CHECK-NEXT: xor16 a0, a2 62; CHECK-NEXT: or16 a0, a1 63; CHECK-NEXT: cmpnei16 a0, 0 64; CHECK-NEXT: movi16 a0, 0 65; CHECK-NEXT: addu16 a0, sp 66; CHECK-NEXT: mov16 a1, a0 67; CHECK-NEXT: addi16 a0, sp, 8 68; CHECK-NEXT: movf32 a1, a0 69; CHECK-NEXT: ld16.w a0, (a1, 0) 70; CHECK-NEXT: ld16.w a1, (a1, 4) 71; CHECK-NEXT: rts16 72entry: 73 %icmp = icmp eq i64 %y, %x 74 %ret = select i1 %icmp, i64 %m, i64 %n 75 ret i64 %ret 76} 77 78define i64 @selectRI_eq_i64(i64 %x, i64 %n, i64 %m) { 79; CHECK-LABEL: selectRI_eq_i64: 80; CHECK: # %bb.0: # %entry 81; CHECK-NEXT: ld32.w t0, (sp, 4) 82; CHECK-NEXT: ld32.w t1, (sp, 0) 83; CHECK-NEXT: xori32 a0, a0, 10 84; CHECK-NEXT: or16 a0, a1 85; CHECK-NEXT: cmpnei16 a0, 0 86; CHECK-NEXT: movf32 a2, t1 87; CHECK-NEXT: movf32 a3, t0 88; CHECK-NEXT: mov16 a0, a2 89; CHECK-NEXT: mov16 a1, a3 90; CHECK-NEXT: rts16 91entry: 92 %icmp = icmp eq i64 %x, 10 93 %ret = select i1 %icmp, i64 %m, i64 %n 94 ret i64 %ret 95} 96 97define i64 @selectRX_eq_i64(i64 %x, i64 %n, i64 %m) { 98; CHECK-LABEL: selectRX_eq_i64: 99; CHECK: # %bb.0: # %entry 100; CHECK-NEXT: subi16 sp, sp, 4 101; CHECK-NEXT: .cfi_def_cfa_offset 4 102; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill 103; CHECK-NEXT: .cfi_offset l0, -4 104; CHECK-NEXT: .cfi_def_cfa_offset 4 105; CHECK-NEXT: ld32.w t0, (sp, 8) 106; CHECK-NEXT: ld32.w t1, (sp, 4) 107; CHECK-NEXT: movih32 l0, 729 108; CHECK-NEXT: ori32 l0, l0, 2033 109; CHECK-NEXT: xor16 a0, l0 110; CHECK-NEXT: or16 a0, a1 111; CHECK-NEXT: cmpnei16 a0, 0 112; CHECK-NEXT: movf32 a2, t1 113; CHECK-NEXT: movf32 a3, t0 114; CHECK-NEXT: mov16 a0, a2 115; CHECK-NEXT: mov16 a1, a3 116; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload 117; CHECK-NEXT: addi16 sp, sp, 4 118; CHECK-NEXT: rts16 119entry: 120 %icmp = icmp eq i64 %x, 47777777 121 %ret = select i1 %icmp, i64 %m, i64 %n 122 ret i64 %ret 123} 124 125define i64 @selectC_eq_i64(i1 %c, i64 %n, i64 %m) { 126; CHECK-LABEL: selectC_eq_i64: 127; CHECK: # %bb.0: # %entry 128; CHECK-NEXT: ld32.w t0, (sp, 0) 129; CHECK-NEXT: btsti32 a0, 0 130; CHECK-NEXT: movt32 a1, a3 131; CHECK-NEXT: movt32 a2, t0 132; CHECK-NEXT: mov16 a0, a1 133; CHECK-NEXT: mov16 a1, a2 134; CHECK-NEXT: rts16 135entry: 136 %ret = select i1 %c, i64 %m, i64 %n 137 ret i64 %ret 138} 139 140 141define i16 @selectRR_eq_i16(i16 %x, i16 %y, i16 %n, i16 %m) { 142; CHECK-LABEL: selectRR_eq_i16: 143; CHECK: # %bb.0: # %entry 144; CHECK-NEXT: zexth16 a0, a0 145; CHECK-NEXT: zexth16 a1, a1 146; CHECK-NEXT: cmpne16 a1, a0 147; CHECK-NEXT: movf32 a2, a3 148; CHECK-NEXT: mov16 a0, a2 149; CHECK-NEXT: rts16 150entry: 151 %icmp = icmp eq i16 %y, %x 152 %ret = select i1 %icmp, i16 %m, i16 %n 153 ret i16 %ret 154} 155 156define i16 @selectRI_eq_i16(i16 %x, i16 %n, i16 %m) { 157; CHECK-LABEL: selectRI_eq_i16: 158; CHECK: # %bb.0: # %entry 159; CHECK-NEXT: zexth16 a0, a0 160; CHECK-NEXT: cmpnei16 a0, 10 161; CHECK-NEXT: movf32 a1, a2 162; CHECK-NEXT: mov16 a0, a1 163; CHECK-NEXT: rts16 164entry: 165 %icmp = icmp eq i16 %x, 10 166 %ret = select i1 %icmp, i16 %m, i16 %n 167 ret i16 %ret 168} 169 170define i16 @selectRX_eq_i16(i16 %x, i16 %n, i16 %m) { 171; CHECK-LABEL: selectRX_eq_i16: 172; CHECK: # %bb.0: # %entry 173; CHECK-NEXT: zexth16 a0, a0 174; CHECK-NEXT: cmpnei32 a0, 2033 175; CHECK-NEXT: movf32 a1, a2 176; CHECK-NEXT: mov16 a0, a1 177; CHECK-NEXT: rts16 178entry: 179 %icmp = icmp eq i16 %x, 47777777 180 %ret = select i1 %icmp, i16 %m, i16 %n 181 ret i16 %ret 182} 183 184define i16 @selectC_eq_i16(i1 %c, i16 %n, i16 %m) { 185; CHECK-LABEL: selectC_eq_i16: 186; CHECK: # %bb.0: # %entry 187; CHECK-NEXT: btsti32 a0, 0 188; CHECK-NEXT: movt32 a1, a2 189; CHECK-NEXT: mov16 a0, a1 190; CHECK-NEXT: rts16 191entry: 192 %ret = select i1 %c, i16 %m, i16 %n 193 ret i16 %ret 194} 195 196 197define i8 @selectRR_eq_i8(i8 %x, i8 %y, i8 %n, i8 %m) { 198; CHECK-LABEL: selectRR_eq_i8: 199; CHECK: # %bb.0: # %entry 200; CHECK-NEXT: zextb16 a0, a0 201; CHECK-NEXT: zextb16 a1, a1 202; CHECK-NEXT: cmpne16 a1, a0 203; CHECK-NEXT: movf32 a2, a3 204; CHECK-NEXT: mov16 a0, a2 205; CHECK-NEXT: rts16 206entry: 207 %icmp = icmp eq i8 %y, %x 208 %ret = select i1 %icmp, i8 %m, i8 %n 209 ret i8 %ret 210} 211 212define i8 @selectRI_eq_i8(i8 %x, i8 %n, i8 %m) { 213; CHECK-LABEL: selectRI_eq_i8: 214; CHECK: # %bb.0: # %entry 215; CHECK-NEXT: zextb16 a0, a0 216; CHECK-NEXT: cmpnei16 a0, 10 217; CHECK-NEXT: movf32 a1, a2 218; CHECK-NEXT: mov16 a0, a1 219; CHECK-NEXT: rts16 220entry: 221 %icmp = icmp eq i8 %x, 10 222 %ret = select i1 %icmp, i8 %m, i8 %n 223 ret i8 %ret 224} 225 226define i8 @selectRX_eq_i8(i8 %x, i8 %n, i8 %m) { 227; CHECK-LABEL: selectRX_eq_i8: 228; CHECK: # %bb.0: # %entry 229; CHECK-NEXT: zextb16 a0, a0 230; CHECK-NEXT: cmpnei32 a0, 241 231; CHECK-NEXT: movf32 a1, a2 232; CHECK-NEXT: mov16 a0, a1 233; CHECK-NEXT: rts16 234entry: 235 %icmp = icmp eq i8 %x, 47777777 236 %ret = select i1 %icmp, i8 %m, i8 %n 237 ret i8 %ret 238} 239 240define i8 @selectC_eq_i8(i1 %c, i8 %n, i8 %m) { 241; CHECK-LABEL: selectC_eq_i8: 242; CHECK: # %bb.0: # %entry 243; CHECK-NEXT: btsti32 a0, 0 244; CHECK-NEXT: movt32 a1, a2 245; CHECK-NEXT: mov16 a0, a1 246; CHECK-NEXT: rts16 247entry: 248 %ret = select i1 %c, i8 %m, i8 %n 249 ret i8 %ret 250} 251 252 253define i1 @selectRR_eq_i1(i1 %x, i1 %y, i1 %n, i1 %m) { 254; CHECK-LABEL: selectRR_eq_i1: 255; CHECK: # %bb.0: # %entry 256; CHECK-NEXT: xor16 a0, a1 257; CHECK-NEXT: btsti32 a0, 0 258; CHECK-NEXT: movt32 a3, a2 259; CHECK-NEXT: mov16 a0, a3 260; CHECK-NEXT: rts16 261entry: 262 %icmp = icmp eq i1 %y, %x 263 %ret = select i1 %icmp, i1 %m, i1 %n 264 ret i1 %ret 265} 266 267define i1 @selectRI_eq_i1(i1 %x, i1 %n, i1 %m) { 268; CHECK-LABEL: selectRI_eq_i1: 269; CHECK: # %bb.0: # %entry 270; CHECK-NEXT: btsti32 a0, 0 271; CHECK-NEXT: movt32 a2, a1 272; CHECK-NEXT: mov16 a0, a2 273; CHECK-NEXT: rts16 274entry: 275 %icmp = icmp eq i1 %x, 10 276 %ret = select i1 %icmp, i1 %m, i1 %n 277 ret i1 %ret 278} 279 280define i1 @selectRX_eq_i1(i1 %x, i1 %n, i1 %m) { 281; CHECK-LABEL: selectRX_eq_i1: 282; CHECK: # %bb.0: # %entry 283; CHECK-NEXT: btsti32 a0, 0 284; CHECK-NEXT: movt32 a1, a2 285; CHECK-NEXT: mov16 a0, a1 286; CHECK-NEXT: rts16 287entry: 288 %icmp = icmp eq i1 %x, 47777777 289 %ret = select i1 %icmp, i1 %m, i1 %n 290 ret i1 %ret 291} 292 293define i1 @selectC_eq_i1(i1 %c, i1 %n, i1 %m) { 294; CHECK-LABEL: selectC_eq_i1: 295; CHECK: # %bb.0: # %entry 296; CHECK-NEXT: btsti32 a0, 0 297; CHECK-NEXT: movt32 a1, a2 298; CHECK-NEXT: mov16 a0, a1 299; CHECK-NEXT: rts16 300entry: 301 %ret = select i1 %c, i1 %m, i1 %n 302 ret i1 %ret 303} 304 305 306define i32 @selectRR_ne_i32(i32 %x, i32 %y, i32 %n, i32 %m) { 307; CHECK-LABEL: selectRR_ne_i32: 308; CHECK: # %bb.0: # %entry 309; CHECK-NEXT: cmpne16 a1, a0 310; CHECK-NEXT: movt32 a2, a3 311; CHECK-NEXT: mov16 a0, a2 312; CHECK-NEXT: rts16 313entry: 314 %icmp = icmp ne i32 %y, %x 315 %ret = select i1 %icmp, i32 %m, i32 %n 316 ret i32 %ret 317} 318 319define i32 @selectRI_ne_i32(i32 %x, i32 %n, i32 %m) { 320; CHECK-LABEL: selectRI_ne_i32: 321; CHECK: # %bb.0: # %entry 322; CHECK-NEXT: cmpnei16 a0, 10 323; CHECK-NEXT: movt32 a1, a2 324; CHECK-NEXT: mov16 a0, a1 325; CHECK-NEXT: rts16 326entry: 327 %icmp = icmp ne i32 %x, 10 328 %ret = select i1 %icmp, i32 %m, i32 %n 329 ret i32 %ret 330} 331 332define i32 @selectRX_ne_i32(i32 %x, i32 %n, i32 %m) { 333; CHECK-LABEL: selectRX_ne_i32: 334; CHECK: # %bb.0: # %entry 335; CHECK-NEXT: movih32 a3, 729 336; CHECK-NEXT: ori32 a3, a3, 2033 337; CHECK-NEXT: cmpne16 a0, a3 338; CHECK-NEXT: movt32 a1, a2 339; CHECK-NEXT: mov16 a0, a1 340; CHECK-NEXT: rts16 341entry: 342 %icmp = icmp ne i32 %x, 47777777 343 %ret = select i1 %icmp, i32 %m, i32 %n 344 ret i32 %ret 345} 346 347define i32 @selectC_ne_i32(i1 %c, i32 %n, i32 %m) { 348; CHECK-LABEL: selectC_ne_i32: 349; CHECK: # %bb.0: # %entry 350; CHECK-NEXT: btsti32 a0, 0 351; CHECK-NEXT: movt32 a1, a2 352; CHECK-NEXT: mov16 a0, a1 353; CHECK-NEXT: rts16 354entry: 355 %ret = select i1 %c, i32 %m, i32 %n 356 ret i32 %ret 357} 358 359define i64 @selectRR_ne_i64(i64 %x, i64 %y, i64 %n, i64 %m) { 360; CHECK-LABEL: selectRR_ne_i64: 361; CHECK: # %bb.0: # %entry 362; CHECK-NEXT: xor16 a1, a3 363; CHECK-NEXT: xor16 a0, a2 364; CHECK-NEXT: or16 a0, a1 365; CHECK-NEXT: cmpnei16 a0, 0 366; CHECK-NEXT: movi16 a0, 0 367; CHECK-NEXT: addu16 a0, sp 368; CHECK-NEXT: mov16 a1, a0 369; CHECK-NEXT: addi16 a0, sp, 8 370; CHECK-NEXT: movt32 a1, a0 371; CHECK-NEXT: ld16.w a0, (a1, 0) 372; CHECK-NEXT: ld16.w a1, (a1, 4) 373; CHECK-NEXT: rts16 374entry: 375 %icmp = icmp ne i64 %y, %x 376 %ret = select i1 %icmp, i64 %m, i64 %n 377 ret i64 %ret 378} 379 380define i64 @selectRI_ne_i64(i64 %x, i64 %n, i64 %m) { 381; CHECK-LABEL: selectRI_ne_i64: 382; CHECK: # %bb.0: # %entry 383; CHECK-NEXT: ld32.w t0, (sp, 4) 384; CHECK-NEXT: ld32.w t1, (sp, 0) 385; CHECK-NEXT: xori32 a0, a0, 10 386; CHECK-NEXT: or16 a0, a1 387; CHECK-NEXT: cmpnei16 a0, 0 388; CHECK-NEXT: movt32 a2, t1 389; CHECK-NEXT: movt32 a3, t0 390; CHECK-NEXT: mov16 a0, a2 391; CHECK-NEXT: mov16 a1, a3 392; CHECK-NEXT: rts16 393entry: 394 %icmp = icmp ne i64 %x, 10 395 %ret = select i1 %icmp, i64 %m, i64 %n 396 ret i64 %ret 397} 398 399define i64 @selectRX_ne_i64(i64 %x, i64 %n, i64 %m) { 400; CHECK-LABEL: selectRX_ne_i64: 401; CHECK: # %bb.0: # %entry 402; CHECK-NEXT: subi16 sp, sp, 4 403; CHECK-NEXT: .cfi_def_cfa_offset 4 404; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill 405; CHECK-NEXT: .cfi_offset l0, -4 406; CHECK-NEXT: .cfi_def_cfa_offset 4 407; CHECK-NEXT: ld32.w t0, (sp, 8) 408; CHECK-NEXT: ld32.w t1, (sp, 4) 409; CHECK-NEXT: movih32 l0, 729 410; CHECK-NEXT: ori32 l0, l0, 2033 411; CHECK-NEXT: xor16 a0, l0 412; CHECK-NEXT: or16 a0, a1 413; CHECK-NEXT: cmpnei16 a0, 0 414; CHECK-NEXT: movt32 a2, t1 415; CHECK-NEXT: movt32 a3, t0 416; CHECK-NEXT: mov16 a0, a2 417; CHECK-NEXT: mov16 a1, a3 418; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload 419; CHECK-NEXT: addi16 sp, sp, 4 420; CHECK-NEXT: rts16 421entry: 422 %icmp = icmp ne i64 %x, 47777777 423 %ret = select i1 %icmp, i64 %m, i64 %n 424 ret i64 %ret 425} 426 427define i64 @selectC_ne_i64(i1 %c, i64 %n, i64 %m) { 428; CHECK-LABEL: selectC_ne_i64: 429; CHECK: # %bb.0: # %entry 430; CHECK-NEXT: ld32.w t0, (sp, 0) 431; CHECK-NEXT: btsti32 a0, 0 432; CHECK-NEXT: movt32 a1, a3 433; CHECK-NEXT: movt32 a2, t0 434; CHECK-NEXT: mov16 a0, a1 435; CHECK-NEXT: mov16 a1, a2 436; CHECK-NEXT: rts16 437entry: 438 %ret = select i1 %c, i64 %m, i64 %n 439 ret i64 %ret 440} 441 442 443define i16 @selectRR_ne_i16(i16 %x, i16 %y, i16 %n, i16 %m) { 444; CHECK-LABEL: selectRR_ne_i16: 445; CHECK: # %bb.0: # %entry 446; CHECK-NEXT: zexth16 a0, a0 447; CHECK-NEXT: zexth16 a1, a1 448; CHECK-NEXT: cmpne16 a1, a0 449; CHECK-NEXT: movt32 a2, a3 450; CHECK-NEXT: mov16 a0, a2 451; CHECK-NEXT: rts16 452entry: 453 %icmp = icmp ne i16 %y, %x 454 %ret = select i1 %icmp, i16 %m, i16 %n 455 ret i16 %ret 456} 457 458define i16 @selectRI_ne_i16(i16 %x, i16 %n, i16 %m) { 459; CHECK-LABEL: selectRI_ne_i16: 460; CHECK: # %bb.0: # %entry 461; CHECK-NEXT: zexth16 a0, a0 462; CHECK-NEXT: cmpnei16 a0, 10 463; CHECK-NEXT: movt32 a1, a2 464; CHECK-NEXT: mov16 a0, a1 465; CHECK-NEXT: rts16 466entry: 467 %icmp = icmp ne i16 %x, 10 468 %ret = select i1 %icmp, i16 %m, i16 %n 469 ret i16 %ret 470} 471 472define i16 @selectRX_ne_i16(i16 %x, i16 %n, i16 %m) { 473; CHECK-LABEL: selectRX_ne_i16: 474; CHECK: # %bb.0: # %entry 475; CHECK-NEXT: zexth16 a0, a0 476; CHECK-NEXT: cmpnei32 a0, 2033 477; CHECK-NEXT: movt32 a1, a2 478; CHECK-NEXT: mov16 a0, a1 479; CHECK-NEXT: rts16 480entry: 481 %icmp = icmp ne i16 %x, 47777777 482 %ret = select i1 %icmp, i16 %m, i16 %n 483 ret i16 %ret 484} 485 486define i16 @selectC_ne_i16(i1 %c, i16 %n, i16 %m) { 487; CHECK-LABEL: selectC_ne_i16: 488; CHECK: # %bb.0: # %entry 489; CHECK-NEXT: btsti32 a0, 0 490; CHECK-NEXT: movt32 a1, a2 491; CHECK-NEXT: mov16 a0, a1 492; CHECK-NEXT: rts16 493entry: 494 %ret = select i1 %c, i16 %m, i16 %n 495 ret i16 %ret 496} 497 498 499define i8 @selectRR_ne_i8(i8 %x, i8 %y, i8 %n, i8 %m) { 500; CHECK-LABEL: selectRR_ne_i8: 501; CHECK: # %bb.0: # %entry 502; CHECK-NEXT: zextb16 a0, a0 503; CHECK-NEXT: zextb16 a1, a1 504; CHECK-NEXT: cmpne16 a1, a0 505; CHECK-NEXT: movt32 a2, a3 506; CHECK-NEXT: mov16 a0, a2 507; CHECK-NEXT: rts16 508entry: 509 %icmp = icmp ne i8 %y, %x 510 %ret = select i1 %icmp, i8 %m, i8 %n 511 ret i8 %ret 512} 513 514define i8 @selectRI_ne_i8(i8 %x, i8 %n, i8 %m) { 515; CHECK-LABEL: selectRI_ne_i8: 516; CHECK: # %bb.0: # %entry 517; CHECK-NEXT: zextb16 a0, a0 518; CHECK-NEXT: cmpnei16 a0, 10 519; CHECK-NEXT: movt32 a1, a2 520; CHECK-NEXT: mov16 a0, a1 521; CHECK-NEXT: rts16 522entry: 523 %icmp = icmp ne i8 %x, 10 524 %ret = select i1 %icmp, i8 %m, i8 %n 525 ret i8 %ret 526} 527 528define i8 @selectRX_ne_i8(i8 %x, i8 %n, i8 %m) { 529; CHECK-LABEL: selectRX_ne_i8: 530; CHECK: # %bb.0: # %entry 531; CHECK-NEXT: zextb16 a0, a0 532; CHECK-NEXT: cmpnei32 a0, 241 533; CHECK-NEXT: movt32 a1, a2 534; CHECK-NEXT: mov16 a0, a1 535; CHECK-NEXT: rts16 536entry: 537 %icmp = icmp ne i8 %x, 47777777 538 %ret = select i1 %icmp, i8 %m, i8 %n 539 ret i8 %ret 540} 541 542define i8 @selectC_ne_i8(i1 %c, i8 %n, i8 %m) { 543; CHECK-LABEL: selectC_ne_i8: 544; CHECK: # %bb.0: # %entry 545; CHECK-NEXT: btsti32 a0, 0 546; CHECK-NEXT: movt32 a1, a2 547; CHECK-NEXT: mov16 a0, a1 548; CHECK-NEXT: rts16 549entry: 550 %ret = select i1 %c, i8 %m, i8 %n 551 ret i8 %ret 552} 553 554 555define i1 @selectRR_ne_i1(i1 %x, i1 %y, i1 %n, i1 %m) { 556; CHECK-LABEL: selectRR_ne_i1: 557; CHECK: # %bb.0: # %entry 558; CHECK-NEXT: xor16 a0, a1 559; CHECK-NEXT: btsti32 a0, 0 560; CHECK-NEXT: movt32 a2, a3 561; CHECK-NEXT: mov16 a0, a2 562; CHECK-NEXT: rts16 563entry: 564 %icmp = icmp ne i1 %y, %x 565 %ret = select i1 %icmp, i1 %m, i1 %n 566 ret i1 %ret 567} 568 569define i1 @selectRI_ne_i1(i1 %x, i1 %n, i1 %m) { 570; CHECK-LABEL: selectRI_ne_i1: 571; CHECK: # %bb.0: # %entry 572; CHECK-NEXT: btsti32 a0, 0 573; CHECK-NEXT: movt32 a1, a2 574; CHECK-NEXT: mov16 a0, a1 575; CHECK-NEXT: rts16 576entry: 577 %icmp = icmp ne i1 %x, 10 578 %ret = select i1 %icmp, i1 %m, i1 %n 579 ret i1 %ret 580} 581 582define i1 @selectRX_ne_i1(i1 %x, i1 %n, i1 %m) { 583; CHECK-LABEL: selectRX_ne_i1: 584; CHECK: # %bb.0: # %entry 585; CHECK-NEXT: btsti32 a0, 0 586; CHECK-NEXT: movt32 a2, a1 587; CHECK-NEXT: mov16 a0, a2 588; CHECK-NEXT: rts16 589entry: 590 %icmp = icmp ne i1 %x, 47777777 591 %ret = select i1 %icmp, i1 %m, i1 %n 592 ret i1 %ret 593} 594 595define i1 @selectC_ne_i1(i1 %c, i1 %n, i1 %m) { 596; CHECK-LABEL: selectC_ne_i1: 597; CHECK: # %bb.0: # %entry 598; CHECK-NEXT: btsti32 a0, 0 599; CHECK-NEXT: movt32 a1, a2 600; CHECK-NEXT: mov16 a0, a1 601; CHECK-NEXT: rts16 602entry: 603 %ret = select i1 %c, i1 %m, i1 %n 604 ret i1 %ret 605} 606 607 608define i32 @selectRR_ugt_i32(i32 %x, i32 %y, i32 %n, i32 %m) { 609; CHECK-LABEL: selectRR_ugt_i32: 610; CHECK: # %bb.0: # %entry 611; CHECK-NEXT: cmphs16 a0, a1 612; CHECK-NEXT: movf32 a2, a3 613; CHECK-NEXT: mov16 a0, a2 614; CHECK-NEXT: rts16 615entry: 616 %icmp = icmp ugt i32 %y, %x 617 %ret = select i1 %icmp, i32 %m, i32 %n 618 ret i32 %ret 619} 620 621define i32 @selectRI_ugt_i32(i32 %x, i32 %n, i32 %m) { 622; CHECK-LABEL: selectRI_ugt_i32: 623; CHECK: # %bb.0: # %entry 624; CHECK-NEXT: movi16 a3, 10 625; CHECK-NEXT: cmphs16 a3, a0 626; CHECK-NEXT: movf32 a1, a2 627; CHECK-NEXT: mov16 a0, a1 628; CHECK-NEXT: rts16 629entry: 630 %icmp = icmp ugt i32 %x, 10 631 %ret = select i1 %icmp, i32 %m, i32 %n 632 ret i32 %ret 633} 634 635define i32 @selectRX_ugt_i32(i32 %x, i32 %n, i32 %m) { 636; CHECK-LABEL: selectRX_ugt_i32: 637; CHECK: # %bb.0: # %entry 638; CHECK-NEXT: movih32 a3, 729 639; CHECK-NEXT: ori32 a3, a3, 2033 640; CHECK-NEXT: cmphs16 a3, a0 641; CHECK-NEXT: movf32 a1, a2 642; CHECK-NEXT: mov16 a0, a1 643; CHECK-NEXT: rts16 644entry: 645 %icmp = icmp ugt i32 %x, 47777777 646 %ret = select i1 %icmp, i32 %m, i32 %n 647 ret i32 %ret 648} 649 650define i32 @selectC_ugt_i32(i1 %c, i32 %n, i32 %m) { 651; CHECK-LABEL: selectC_ugt_i32: 652; CHECK: # %bb.0: # %entry 653; CHECK-NEXT: btsti32 a0, 0 654; CHECK-NEXT: movt32 a1, a2 655; CHECK-NEXT: mov16 a0, a1 656; CHECK-NEXT: rts16 657entry: 658 %ret = select i1 %c, i32 %m, i32 %n 659 ret i32 %ret 660} 661 662define i64 @selectRR_ugt_i64(i64 %x, i64 %y, i64 %n, i64 %m) { 663; CHECK-LABEL: selectRR_ugt_i64: 664; CHECK: # %bb.0: # %entry 665; CHECK-NEXT: .cfi_def_cfa_offset 0 666; CHECK-NEXT: subi16 sp, sp, 8 667; CHECK-NEXT: .cfi_def_cfa_offset 8 668; CHECK-NEXT: cmpne16 a3, a1 669; CHECK-NEXT: mvc32 t0 670; CHECK-NEXT: st32.w t0, (sp, 4) 671; CHECK-NEXT: cmphs16 a1, a3 672; CHECK-NEXT: mvcv16 a1 673; CHECK-NEXT: cmphs16 a0, a2 674; CHECK-NEXT: mvcv16 a0 675; CHECK-NEXT: ld16.w a2, (sp, 4) 676; CHECK-NEXT: btsti32 a2, 0 677; CHECK-NEXT: movf32 a1, a0 678; CHECK-NEXT: addi16 a2, sp, 8 679; CHECK-NEXT: addi16 a0, sp, 16 680; CHECK-NEXT: btsti32 a1, 0 681; CHECK-NEXT: movt32 a2, a0 682; CHECK-NEXT: ld16.w a0, (a2, 0) 683; CHECK-NEXT: ld16.w a1, (a2, 4) 684; CHECK-NEXT: addi16 sp, sp, 8 685; CHECK-NEXT: rts16 686entry: 687 %icmp = icmp ugt i64 %y, %x 688 %ret = select i1 %icmp, i64 %m, i64 %n 689 ret i64 %ret 690} 691 692define i64 @selectRI_ugt_i64(i64 %x, i64 %n, i64 %m) { 693; CHECK-LABEL: selectRI_ugt_i64: 694; CHECK: # %bb.0: # %entry 695; CHECK-NEXT: subi16 sp, sp, 4 696; CHECK-NEXT: .cfi_def_cfa_offset 4 697; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill 698; CHECK-NEXT: .cfi_offset l0, -4 699; CHECK-NEXT: .cfi_def_cfa_offset 4 700; CHECK-NEXT: ld32.w t0, (sp, 8) 701; CHECK-NEXT: ld32.w t1, (sp, 4) 702; CHECK-NEXT: movi16 l0, 10 703; CHECK-NEXT: cmphs16 l0, a0 704; CHECK-NEXT: mvcv16 a0 705; CHECK-NEXT: cmpnei16 a1, 0 706; CHECK-NEXT: mvc32 a1 707; CHECK-NEXT: movf32 a1, a0 708; CHECK-NEXT: btsti32 a1, 0 709; CHECK-NEXT: movt32 a2, t1 710; CHECK-NEXT: movt32 a3, t0 711; CHECK-NEXT: mov16 a0, a2 712; CHECK-NEXT: mov16 a1, a3 713; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload 714; CHECK-NEXT: addi16 sp, sp, 4 715; CHECK-NEXT: rts16 716entry: 717 %icmp = icmp ugt i64 %x, 10 718 %ret = select i1 %icmp, i64 %m, i64 %n 719 ret i64 %ret 720} 721 722define i64 @selectRX_ugt_i64(i64 %x, i64 %n, i64 %m) { 723; CHECK-LABEL: selectRX_ugt_i64: 724; CHECK: # %bb.0: # %entry 725; CHECK-NEXT: subi16 sp, sp, 4 726; CHECK-NEXT: .cfi_def_cfa_offset 4 727; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill 728; CHECK-NEXT: .cfi_offset l0, -4 729; CHECK-NEXT: .cfi_def_cfa_offset 4 730; CHECK-NEXT: ld32.w t0, (sp, 8) 731; CHECK-NEXT: ld32.w t1, (sp, 4) 732; CHECK-NEXT: movih32 l0, 729 733; CHECK-NEXT: ori32 l0, l0, 2033 734; CHECK-NEXT: cmphs16 l0, a0 735; CHECK-NEXT: mvcv16 a0 736; CHECK-NEXT: cmpnei16 a1, 0 737; CHECK-NEXT: mvc32 a1 738; CHECK-NEXT: movf32 a1, a0 739; CHECK-NEXT: btsti32 a1, 0 740; CHECK-NEXT: movt32 a2, t1 741; CHECK-NEXT: movt32 a3, t0 742; CHECK-NEXT: mov16 a0, a2 743; CHECK-NEXT: mov16 a1, a3 744; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload 745; CHECK-NEXT: addi16 sp, sp, 4 746; CHECK-NEXT: rts16 747entry: 748 %icmp = icmp ugt i64 %x, 47777777 749 %ret = select i1 %icmp, i64 %m, i64 %n 750 ret i64 %ret 751} 752 753define i64 @selectC_ugt_i64(i1 %c, i64 %n, i64 %m) { 754; CHECK-LABEL: selectC_ugt_i64: 755; CHECK: # %bb.0: # %entry 756; CHECK-NEXT: ld32.w t0, (sp, 0) 757; CHECK-NEXT: btsti32 a0, 0 758; CHECK-NEXT: movt32 a1, a3 759; CHECK-NEXT: movt32 a2, t0 760; CHECK-NEXT: mov16 a0, a1 761; CHECK-NEXT: mov16 a1, a2 762; CHECK-NEXT: rts16 763entry: 764 %ret = select i1 %c, i64 %m, i64 %n 765 ret i64 %ret 766} 767 768 769define i16 @selectRR_ugt_i16(i16 %x, i16 %y, i16 %n, i16 %m) { 770; CHECK-LABEL: selectRR_ugt_i16: 771; CHECK: # %bb.0: # %entry 772; CHECK-NEXT: zexth16 a1, a1 773; CHECK-NEXT: zexth16 a0, a0 774; CHECK-NEXT: cmphs16 a0, a1 775; CHECK-NEXT: movf32 a2, a3 776; CHECK-NEXT: mov16 a0, a2 777; CHECK-NEXT: rts16 778entry: 779 %icmp = icmp ugt i16 %y, %x 780 %ret = select i1 %icmp, i16 %m, i16 %n 781 ret i16 %ret 782} 783 784define i16 @selectRI_ugt_i16(i16 %x, i16 %n, i16 %m) { 785; CHECK-LABEL: selectRI_ugt_i16: 786; CHECK: # %bb.0: # %entry 787; CHECK-NEXT: zexth16 a0, a0 788; CHECK-NEXT: movi16 a3, 10 789; CHECK-NEXT: cmphs16 a3, a0 790; CHECK-NEXT: movf32 a1, a2 791; CHECK-NEXT: mov16 a0, a1 792; CHECK-NEXT: rts16 793entry: 794 %icmp = icmp ugt i16 %x, 10 795 %ret = select i1 %icmp, i16 %m, i16 %n 796 ret i16 %ret 797} 798 799define i16 @selectRX_ugt_i16(i16 %x, i16 %n, i16 %m) { 800; CHECK-LABEL: selectRX_ugt_i16: 801; CHECK: # %bb.0: # %entry 802; CHECK-NEXT: zexth16 a0, a0 803; CHECK-NEXT: movi32 a3, 2033 804; CHECK-NEXT: cmphs16 a3, a0 805; CHECK-NEXT: movf32 a1, a2 806; CHECK-NEXT: mov16 a0, a1 807; CHECK-NEXT: rts16 808entry: 809 %icmp = icmp ugt i16 %x, 47777777 810 %ret = select i1 %icmp, i16 %m, i16 %n 811 ret i16 %ret 812} 813 814define i16 @selectC_ugt_i16(i1 %c, i16 %n, i16 %m) { 815; CHECK-LABEL: selectC_ugt_i16: 816; CHECK: # %bb.0: # %entry 817; CHECK-NEXT: btsti32 a0, 0 818; CHECK-NEXT: movt32 a1, a2 819; CHECK-NEXT: mov16 a0, a1 820; CHECK-NEXT: rts16 821entry: 822 %ret = select i1 %c, i16 %m, i16 %n 823 ret i16 %ret 824} 825 826 827define i8 @selectRR_ugt_i8(i8 %x, i8 %y, i8 %n, i8 %m) { 828; CHECK-LABEL: selectRR_ugt_i8: 829; CHECK: # %bb.0: # %entry 830; CHECK-NEXT: zextb16 a1, a1 831; CHECK-NEXT: zextb16 a0, a0 832; CHECK-NEXT: cmphs16 a0, a1 833; CHECK-NEXT: movf32 a2, a3 834; CHECK-NEXT: mov16 a0, a2 835; CHECK-NEXT: rts16 836entry: 837 %icmp = icmp ugt i8 %y, %x 838 %ret = select i1 %icmp, i8 %m, i8 %n 839 ret i8 %ret 840} 841 842define i8 @selectRI_ugt_i8(i8 %x, i8 %n, i8 %m) { 843; CHECK-LABEL: selectRI_ugt_i8: 844; CHECK: # %bb.0: # %entry 845; CHECK-NEXT: zextb16 a0, a0 846; CHECK-NEXT: movi16 a3, 10 847; CHECK-NEXT: cmphs16 a3, a0 848; CHECK-NEXT: movf32 a1, a2 849; CHECK-NEXT: mov16 a0, a1 850; CHECK-NEXT: rts16 851entry: 852 %icmp = icmp ugt i8 %x, 10 853 %ret = select i1 %icmp, i8 %m, i8 %n 854 ret i8 %ret 855} 856 857define i8 @selectRX_ugt_i8(i8 %x, i8 %n, i8 %m) { 858; CHECK-LABEL: selectRX_ugt_i8: 859; CHECK: # %bb.0: # %entry 860; CHECK-NEXT: zextb16 a0, a0 861; CHECK-NEXT: movi16 a3, 241 862; CHECK-NEXT: cmphs16 a3, a0 863; CHECK-NEXT: movf32 a1, a2 864; CHECK-NEXT: mov16 a0, a1 865; CHECK-NEXT: rts16 866entry: 867 %icmp = icmp ugt i8 %x, 47777777 868 %ret = select i1 %icmp, i8 %m, i8 %n 869 ret i8 %ret 870} 871 872define i8 @selectC_ugt_i8(i1 %c, i8 %n, i8 %m) { 873; CHECK-LABEL: selectC_ugt_i8: 874; CHECK: # %bb.0: # %entry 875; CHECK-NEXT: btsti32 a0, 0 876; CHECK-NEXT: movt32 a1, a2 877; CHECK-NEXT: mov16 a0, a1 878; CHECK-NEXT: rts16 879entry: 880 %ret = select i1 %c, i8 %m, i8 %n 881 ret i8 %ret 882} 883 884 885define i1 @selectRR_ugt_i1(i1 %x, i1 %y, i1 %n, i1 %m) { 886; CHECK-LABEL: selectRR_ugt_i1: 887; CHECK: # %bb.0: # %entry 888; CHECK-NEXT: btsti32 a0, 0 889; CHECK-NEXT: movt32 a3, a2 890; CHECK-NEXT: btsti32 a1, 0 891; CHECK-NEXT: movt32 a2, a3 892; CHECK-NEXT: mov16 a0, a2 893; CHECK-NEXT: rts16 894entry: 895 %icmp = icmp ugt i1 %y, %x 896 %ret = select i1 %icmp, i1 %m, i1 %n 897 ret i1 %ret 898} 899 900define i1 @selectRI_ugt_i1(i1 %x, i1 %n, i1 %m) { 901; CHECK-LABEL: selectRI_ugt_i1: 902; CHECK: # %bb.0: # %entry 903; CHECK-NEXT: btsti32 a0, 0 904; CHECK-NEXT: movt32 a1, a2 905; CHECK-NEXT: mov16 a0, a1 906; CHECK-NEXT: rts16 907entry: 908 %icmp = icmp ugt i1 %x, 10 909 %ret = select i1 %icmp, i1 %m, i1 %n 910 ret i1 %ret 911} 912 913define i1 @selectRX_ugt_i1(i1 %x, i1 %n, i1 %m) { 914; CHECK-LABEL: selectRX_ugt_i1: 915; CHECK: # %bb.0: # %entry 916; CHECK-NEXT: mov16 a0, a1 917; CHECK-NEXT: rts16 918entry: 919 %icmp = icmp ugt i1 %x, 47777777 920 %ret = select i1 %icmp, i1 %m, i1 %n 921 ret i1 %ret 922} 923 924define i1 @selectC_ugt_i1(i1 %c, i1 %n, i1 %m) { 925; CHECK-LABEL: selectC_ugt_i1: 926; CHECK: # %bb.0: # %entry 927; CHECK-NEXT: btsti32 a0, 0 928; CHECK-NEXT: movt32 a1, a2 929; CHECK-NEXT: mov16 a0, a1 930; CHECK-NEXT: rts16 931entry: 932 %ret = select i1 %c, i1 %m, i1 %n 933 ret i1 %ret 934} 935 936 937define i32 @selectRR_uge_i32(i32 %x, i32 %y, i32 %n, i32 %m) { 938; CHECK-LABEL: selectRR_uge_i32: 939; CHECK: # %bb.0: # %entry 940; CHECK-NEXT: cmphs16 a1, a0 941; CHECK-NEXT: movt32 a2, a3 942; CHECK-NEXT: mov16 a0, a2 943; CHECK-NEXT: rts16 944entry: 945 %icmp = icmp uge i32 %y, %x 946 %ret = select i1 %icmp, i32 %m, i32 %n 947 ret i32 %ret 948} 949 950define i32 @selectRI_uge_i32(i32 %x, i32 %n, i32 %m) { 951; CHECK-LABEL: selectRI_uge_i32: 952; CHECK: # %bb.0: # %entry 953; CHECK-NEXT: movi16 a3, 9 954; CHECK-NEXT: cmphs16 a3, a0 955; CHECK-NEXT: movf32 a1, a2 956; CHECK-NEXT: mov16 a0, a1 957; CHECK-NEXT: rts16 958entry: 959 %icmp = icmp uge i32 %x, 10 960 %ret = select i1 %icmp, i32 %m, i32 %n 961 ret i32 %ret 962} 963 964define i32 @selectRX_uge_i32(i32 %x, i32 %n, i32 %m) { 965; CHECK-LABEL: selectRX_uge_i32: 966; CHECK: # %bb.0: # %entry 967; CHECK-NEXT: movih32 a3, 729 968; CHECK-NEXT: ori32 a3, a3, 2032 969; CHECK-NEXT: cmphs16 a3, a0 970; CHECK-NEXT: movf32 a1, a2 971; CHECK-NEXT: mov16 a0, a1 972; CHECK-NEXT: rts16 973entry: 974 %icmp = icmp uge i32 %x, 47777777 975 %ret = select i1 %icmp, i32 %m, i32 %n 976 ret i32 %ret 977} 978 979define i32 @selectC_uge_i32(i1 %c, i32 %n, i32 %m) { 980; CHECK-LABEL: selectC_uge_i32: 981; CHECK: # %bb.0: # %entry 982; CHECK-NEXT: btsti32 a0, 0 983; CHECK-NEXT: movt32 a1, a2 984; CHECK-NEXT: mov16 a0, a1 985; CHECK-NEXT: rts16 986entry: 987 %ret = select i1 %c, i32 %m, i32 %n 988 ret i32 %ret 989} 990 991define i64 @selectRR_uge_i64(i64 %x, i64 %y, i64 %n, i64 %m) { 992; CHECK-LABEL: selectRR_uge_i64: 993; CHECK: # %bb.0: # %entry 994; CHECK-NEXT: .cfi_def_cfa_offset 0 995; CHECK-NEXT: subi16 sp, sp, 16 996; CHECK-NEXT: .cfi_def_cfa_offset 16 997; CHECK-NEXT: cmphs16 a3, a1 998; CHECK-NEXT: mvc32 t0 999; CHECK-NEXT: st32.w t0, (sp, 12) 1000; CHECK-NEXT: cmphs16 a2, a0 1001; CHECK-NEXT: mvc32 a0 1002; CHECK-NEXT: st16.w a0, (sp, 4) 1003; CHECK-NEXT: cmpne16 a3, a1 1004; CHECK-NEXT: mvc32 a0 1005; CHECK-NEXT: st16.w a0, (sp, 8) 1006; CHECK-NEXT: ld16.w a0, (sp, 4) 1007; CHECK-NEXT: btsti32 a0, 0 1008; CHECK-NEXT: mvc32 a0 1009; CHECK-NEXT: ld16.w a1, (sp, 12) 1010; CHECK-NEXT: btsti32 a1, 0 1011; CHECK-NEXT: mvc32 a1 1012; CHECK-NEXT: ld16.w a2, (sp, 8) 1013; CHECK-NEXT: btsti32 a2, 0 1014; CHECK-NEXT: movf32 a1, a0 1015; CHECK-NEXT: addi16 a2, sp, 16 1016; CHECK-NEXT: addi16 a0, sp, 24 1017; CHECK-NEXT: btsti32 a1, 0 1018; CHECK-NEXT: movt32 a2, a0 1019; CHECK-NEXT: ld16.w a0, (a2, 0) 1020; CHECK-NEXT: ld16.w a1, (a2, 4) 1021; CHECK-NEXT: addi16 sp, sp, 16 1022; CHECK-NEXT: rts16 1023entry: 1024 %icmp = icmp uge i64 %y, %x 1025 %ret = select i1 %icmp, i64 %m, i64 %n 1026 ret i64 %ret 1027} 1028 1029define i64 @selectRI_uge_i64(i64 %x, i64 %n, i64 %m) { 1030; CHECK-LABEL: selectRI_uge_i64: 1031; CHECK: # %bb.0: # %entry 1032; CHECK-NEXT: subi16 sp, sp, 4 1033; CHECK-NEXT: .cfi_def_cfa_offset 4 1034; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill 1035; CHECK-NEXT: .cfi_offset l0, -4 1036; CHECK-NEXT: .cfi_def_cfa_offset 4 1037; CHECK-NEXT: ld32.w t0, (sp, 8) 1038; CHECK-NEXT: ld32.w t1, (sp, 4) 1039; CHECK-NEXT: movi16 l0, 9 1040; CHECK-NEXT: cmphs16 l0, a0 1041; CHECK-NEXT: mvcv16 a0 1042; CHECK-NEXT: cmpnei16 a1, 0 1043; CHECK-NEXT: mvc32 a1 1044; CHECK-NEXT: movf32 a1, a0 1045; CHECK-NEXT: btsti32 a1, 0 1046; CHECK-NEXT: movt32 a2, t1 1047; CHECK-NEXT: movt32 a3, t0 1048; CHECK-NEXT: mov16 a0, a2 1049; CHECK-NEXT: mov16 a1, a3 1050; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload 1051; CHECK-NEXT: addi16 sp, sp, 4 1052; CHECK-NEXT: rts16 1053entry: 1054 %icmp = icmp uge i64 %x, 10 1055 %ret = select i1 %icmp, i64 %m, i64 %n 1056 ret i64 %ret 1057} 1058 1059define i64 @selectRX_uge_i64(i64 %x, i64 %n, i64 %m) { 1060; CHECK-LABEL: selectRX_uge_i64: 1061; CHECK: # %bb.0: # %entry 1062; CHECK-NEXT: subi16 sp, sp, 4 1063; CHECK-NEXT: .cfi_def_cfa_offset 4 1064; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill 1065; CHECK-NEXT: .cfi_offset l0, -4 1066; CHECK-NEXT: .cfi_def_cfa_offset 4 1067; CHECK-NEXT: ld32.w t0, (sp, 8) 1068; CHECK-NEXT: ld32.w t1, (sp, 4) 1069; CHECK-NEXT: movih32 l0, 729 1070; CHECK-NEXT: ori32 l0, l0, 2032 1071; CHECK-NEXT: cmphs16 l0, a0 1072; CHECK-NEXT: mvcv16 a0 1073; CHECK-NEXT: cmpnei16 a1, 0 1074; CHECK-NEXT: mvc32 a1 1075; CHECK-NEXT: movf32 a1, a0 1076; CHECK-NEXT: btsti32 a1, 0 1077; CHECK-NEXT: movt32 a2, t1 1078; CHECK-NEXT: movt32 a3, t0 1079; CHECK-NEXT: mov16 a0, a2 1080; CHECK-NEXT: mov16 a1, a3 1081; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload 1082; CHECK-NEXT: addi16 sp, sp, 4 1083; CHECK-NEXT: rts16 1084entry: 1085 %icmp = icmp uge i64 %x, 47777777 1086 %ret = select i1 %icmp, i64 %m, i64 %n 1087 ret i64 %ret 1088} 1089 1090define i64 @selectC_uge_i64(i1 %c, i64 %n, i64 %m) { 1091; CHECK-LABEL: selectC_uge_i64: 1092; CHECK: # %bb.0: # %entry 1093; CHECK-NEXT: ld32.w t0, (sp, 0) 1094; CHECK-NEXT: btsti32 a0, 0 1095; CHECK-NEXT: movt32 a1, a3 1096; CHECK-NEXT: movt32 a2, t0 1097; CHECK-NEXT: mov16 a0, a1 1098; CHECK-NEXT: mov16 a1, a2 1099; CHECK-NEXT: rts16 1100entry: 1101 %ret = select i1 %c, i64 %m, i64 %n 1102 ret i64 %ret 1103} 1104 1105 1106define i16 @selectRR_uge_i16(i16 %x, i16 %y, i16 %n, i16 %m) { 1107; CHECK-LABEL: selectRR_uge_i16: 1108; CHECK: # %bb.0: # %entry 1109; CHECK-NEXT: zexth16 a0, a0 1110; CHECK-NEXT: zexth16 a1, a1 1111; CHECK-NEXT: cmphs16 a1, a0 1112; CHECK-NEXT: movt32 a2, a3 1113; CHECK-NEXT: mov16 a0, a2 1114; CHECK-NEXT: rts16 1115entry: 1116 %icmp = icmp uge i16 %y, %x 1117 %ret = select i1 %icmp, i16 %m, i16 %n 1118 ret i16 %ret 1119} 1120 1121define i16 @selectRI_uge_i16(i16 %x, i16 %n, i16 %m) { 1122; CHECK-LABEL: selectRI_uge_i16: 1123; CHECK: # %bb.0: # %entry 1124; CHECK-NEXT: zexth16 a0, a0 1125; CHECK-NEXT: movi16 a3, 9 1126; CHECK-NEXT: cmphs16 a3, a0 1127; CHECK-NEXT: movf32 a1, a2 1128; CHECK-NEXT: mov16 a0, a1 1129; CHECK-NEXT: rts16 1130entry: 1131 %icmp = icmp uge i16 %x, 10 1132 %ret = select i1 %icmp, i16 %m, i16 %n 1133 ret i16 %ret 1134} 1135 1136define i16 @selectRX_uge_i16(i16 %x, i16 %n, i16 %m) { 1137; CHECK-LABEL: selectRX_uge_i16: 1138; CHECK: # %bb.0: # %entry 1139; CHECK-NEXT: zexth16 a0, a0 1140; CHECK-NEXT: movi32 a3, 2032 1141; CHECK-NEXT: cmphs16 a3, a0 1142; CHECK-NEXT: movf32 a1, a2 1143; CHECK-NEXT: mov16 a0, a1 1144; CHECK-NEXT: rts16 1145entry: 1146 %icmp = icmp uge i16 %x, 47777777 1147 %ret = select i1 %icmp, i16 %m, i16 %n 1148 ret i16 %ret 1149} 1150 1151define i16 @selectC_uge_i16(i1 %c, i16 %n, i16 %m) { 1152; CHECK-LABEL: selectC_uge_i16: 1153; CHECK: # %bb.0: # %entry 1154; CHECK-NEXT: btsti32 a0, 0 1155; CHECK-NEXT: movt32 a1, a2 1156; CHECK-NEXT: mov16 a0, a1 1157; CHECK-NEXT: rts16 1158entry: 1159 %ret = select i1 %c, i16 %m, i16 %n 1160 ret i16 %ret 1161} 1162 1163 1164define i8 @selectRR_uge_i8(i8 %x, i8 %y, i8 %n, i8 %m) { 1165; CHECK-LABEL: selectRR_uge_i8: 1166; CHECK: # %bb.0: # %entry 1167; CHECK-NEXT: zextb16 a0, a0 1168; CHECK-NEXT: zextb16 a1, a1 1169; CHECK-NEXT: cmphs16 a1, a0 1170; CHECK-NEXT: movt32 a2, a3 1171; CHECK-NEXT: mov16 a0, a2 1172; CHECK-NEXT: rts16 1173entry: 1174 %icmp = icmp uge i8 %y, %x 1175 %ret = select i1 %icmp, i8 %m, i8 %n 1176 ret i8 %ret 1177} 1178 1179define i8 @selectRI_uge_i8(i8 %x, i8 %n, i8 %m) { 1180; CHECK-LABEL: selectRI_uge_i8: 1181; CHECK: # %bb.0: # %entry 1182; CHECK-NEXT: zextb16 a0, a0 1183; CHECK-NEXT: movi16 a3, 9 1184; CHECK-NEXT: cmphs16 a3, a0 1185; CHECK-NEXT: movf32 a1, a2 1186; CHECK-NEXT: mov16 a0, a1 1187; CHECK-NEXT: rts16 1188entry: 1189 %icmp = icmp uge i8 %x, 10 1190 %ret = select i1 %icmp, i8 %m, i8 %n 1191 ret i8 %ret 1192} 1193 1194define i8 @selectRX_uge_i8(i8 %x, i8 %n, i8 %m) { 1195; CHECK-LABEL: selectRX_uge_i8: 1196; CHECK: # %bb.0: # %entry 1197; CHECK-NEXT: zextb16 a0, a0 1198; CHECK-NEXT: movi16 a3, 240 1199; CHECK-NEXT: cmphs16 a3, a0 1200; CHECK-NEXT: movf32 a1, a2 1201; CHECK-NEXT: mov16 a0, a1 1202; CHECK-NEXT: rts16 1203entry: 1204 %icmp = icmp uge i8 %x, 47777777 1205 %ret = select i1 %icmp, i8 %m, i8 %n 1206 ret i8 %ret 1207} 1208 1209define i8 @selectC_uge_i8(i1 %c, i8 %n, i8 %m) { 1210; CHECK-LABEL: selectC_uge_i8: 1211; CHECK: # %bb.0: # %entry 1212; CHECK-NEXT: btsti32 a0, 0 1213; CHECK-NEXT: movt32 a1, a2 1214; CHECK-NEXT: mov16 a0, a1 1215; CHECK-NEXT: rts16 1216entry: 1217 %ret = select i1 %c, i8 %m, i8 %n 1218 ret i8 %ret 1219} 1220 1221 1222define i1 @selectRR_uge_i1(i1 %x, i1 %y, i1 %n, i1 %m) { 1223; CHECK-LABEL: selectRR_uge_i1: 1224; CHECK: # %bb.0: # %entry 1225; CHECK-NEXT: btsti32 a0, 0 1226; CHECK-NEXT: mov16 a0, a3 1227; CHECK-NEXT: movt32 a0, a2 1228; CHECK-NEXT: btsti32 a1, 0 1229; CHECK-NEXT: movt32 a0, a3 1230; CHECK-NEXT: rts16 1231entry: 1232 %icmp = icmp uge i1 %y, %x 1233 %ret = select i1 %icmp, i1 %m, i1 %n 1234 ret i1 %ret 1235} 1236 1237define i1 @selectRI_uge_i1(i1 %x, i1 %n, i1 %m) { 1238; CHECK-LABEL: selectRI_uge_i1: 1239; CHECK: # %bb.0: # %entry 1240; CHECK-NEXT: mov16 a0, a2 1241; CHECK-NEXT: rts16 1242entry: 1243 %icmp = icmp uge i1 %x, 10 1244 %ret = select i1 %icmp, i1 %m, i1 %n 1245 ret i1 %ret 1246} 1247 1248define i1 @selectRX_uge_i1(i1 %x, i1 %n, i1 %m) { 1249; CHECK-LABEL: selectRX_uge_i1: 1250; CHECK: # %bb.0: # %entry 1251; CHECK-NEXT: btsti32 a0, 0 1252; CHECK-NEXT: movt32 a1, a2 1253; CHECK-NEXT: mov16 a0, a1 1254; CHECK-NEXT: rts16 1255entry: 1256 %icmp = icmp uge i1 %x, 47777777 1257 %ret = select i1 %icmp, i1 %m, i1 %n 1258 ret i1 %ret 1259} 1260 1261define i1 @selectC_uge_i1(i1 %c, i1 %n, i1 %m) { 1262; CHECK-LABEL: selectC_uge_i1: 1263; CHECK: # %bb.0: # %entry 1264; CHECK-NEXT: btsti32 a0, 0 1265; CHECK-NEXT: movt32 a1, a2 1266; CHECK-NEXT: mov16 a0, a1 1267; CHECK-NEXT: rts16 1268entry: 1269 %ret = select i1 %c, i1 %m, i1 %n 1270 ret i1 %ret 1271} 1272 1273 1274define i32 @selectRR_ult_i32(i32 %x, i32 %y, i32 %n, i32 %m) { 1275; CHECK-LABEL: selectRR_ult_i32: 1276; CHECK: # %bb.0: # %entry 1277; CHECK-NEXT: cmphs16 a1, a0 1278; CHECK-NEXT: movf32 a2, a3 1279; CHECK-NEXT: mov16 a0, a2 1280; CHECK-NEXT: rts16 1281entry: 1282 %icmp = icmp ult i32 %y, %x 1283 %ret = select i1 %icmp, i32 %m, i32 %n 1284 ret i32 %ret 1285} 1286 1287define i32 @selectRI_ult_i32(i32 %x, i32 %n, i32 %m) { 1288; CHECK-LABEL: selectRI_ult_i32: 1289; CHECK: # %bb.0: # %entry 1290; CHECK-NEXT: cmphsi16 a0, 10 1291; CHECK-NEXT: movf32 a1, a2 1292; CHECK-NEXT: mov16 a0, a1 1293; CHECK-NEXT: rts16 1294entry: 1295 %icmp = icmp ult i32 %x, 10 1296 %ret = select i1 %icmp, i32 %m, i32 %n 1297 ret i32 %ret 1298} 1299 1300define i32 @selectRX_ult_i32(i32 %x, i32 %n, i32 %m) { 1301; CHECK-LABEL: selectRX_ult_i32: 1302; CHECK: # %bb.0: # %entry 1303; CHECK-NEXT: movih32 a3, 729 1304; CHECK-NEXT: ori32 a3, a3, 2033 1305; CHECK-NEXT: cmphs16 a0, a3 1306; CHECK-NEXT: movf32 a1, a2 1307; CHECK-NEXT: mov16 a0, a1 1308; CHECK-NEXT: rts16 1309entry: 1310 %icmp = icmp ult i32 %x, 47777777 1311 %ret = select i1 %icmp, i32 %m, i32 %n 1312 ret i32 %ret 1313} 1314 1315define i32 @selectC_ult_i32(i1 %c, i32 %n, i32 %m) { 1316; CHECK-LABEL: selectC_ult_i32: 1317; CHECK: # %bb.0: # %entry 1318; CHECK-NEXT: btsti32 a0, 0 1319; CHECK-NEXT: movt32 a1, a2 1320; CHECK-NEXT: mov16 a0, a1 1321; CHECK-NEXT: rts16 1322entry: 1323 %ret = select i1 %c, i32 %m, i32 %n 1324 ret i32 %ret 1325} 1326 1327define i64 @selectRR_ult_i64(i64 %x, i64 %y, i64 %n, i64 %m) { 1328; CHECK-LABEL: selectRR_ult_i64: 1329; CHECK: # %bb.0: # %entry 1330; CHECK-NEXT: .cfi_def_cfa_offset 0 1331; CHECK-NEXT: subi16 sp, sp, 8 1332; CHECK-NEXT: .cfi_def_cfa_offset 8 1333; CHECK-NEXT: cmpne16 a3, a1 1334; CHECK-NEXT: mvc32 t0 1335; CHECK-NEXT: st32.w t0, (sp, 4) 1336; CHECK-NEXT: cmphs16 a3, a1 1337; CHECK-NEXT: mvcv16 a1 1338; CHECK-NEXT: cmphs16 a2, a0 1339; CHECK-NEXT: mvcv16 a0 1340; CHECK-NEXT: ld16.w a2, (sp, 4) 1341; CHECK-NEXT: btsti32 a2, 0 1342; CHECK-NEXT: movf32 a1, a0 1343; CHECK-NEXT: addi16 a2, sp, 8 1344; CHECK-NEXT: addi16 a0, sp, 16 1345; CHECK-NEXT: btsti32 a1, 0 1346; CHECK-NEXT: movt32 a2, a0 1347; CHECK-NEXT: ld16.w a0, (a2, 0) 1348; CHECK-NEXT: ld16.w a1, (a2, 4) 1349; CHECK-NEXT: addi16 sp, sp, 8 1350; CHECK-NEXT: rts16 1351entry: 1352 %icmp = icmp ult i64 %y, %x 1353 %ret = select i1 %icmp, i64 %m, i64 %n 1354 ret i64 %ret 1355} 1356 1357define i64 @selectRI_ult_i64(i64 %x, i64 %n, i64 %m) { 1358; CHECK-LABEL: selectRI_ult_i64: 1359; CHECK: # %bb.0: # %entry 1360; CHECK-NEXT: .cfi_def_cfa_offset 0 1361; CHECK-NEXT: subi16 sp, sp, 8 1362; CHECK-NEXT: .cfi_def_cfa_offset 8 1363; CHECK-NEXT: ld32.w t0, (sp, 12) 1364; CHECK-NEXT: ld32.w t1, (sp, 8) 1365; CHECK-NEXT: cmpnei16 a1, 0 1366; CHECK-NEXT: st16.w a2, (sp, 0) 1367; CHECK-NEXT: mvc32 a1 1368; CHECK-NEXT: st16.w a1, (sp, 4) 1369; CHECK-NEXT: cmphsi16 a0, 10 1370; CHECK-NEXT: mvcv16 a0 1371; CHECK-NEXT: movi16 a1, 0 1372; CHECK-NEXT: ld16.w a2, (sp, 4) 1373; CHECK-NEXT: btsti32 a2, 0 1374; CHECK-NEXT: ld16.w a2, (sp, 0) 1375; CHECK-NEXT: movf32 a1, a0 1376; CHECK-NEXT: btsti32 a1, 0 1377; CHECK-NEXT: movt32 a2, t1 1378; CHECK-NEXT: movt32 a3, t0 1379; CHECK-NEXT: mov16 a0, a2 1380; CHECK-NEXT: mov16 a1, a3 1381; CHECK-NEXT: addi16 sp, sp, 8 1382; CHECK-NEXT: rts16 1383entry: 1384 %icmp = icmp ult i64 %x, 10 1385 %ret = select i1 %icmp, i64 %m, i64 %n 1386 ret i64 %ret 1387} 1388 1389define i64 @selectRX_ult_i64(i64 %x, i64 %n, i64 %m) { 1390; CHECK-LABEL: selectRX_ult_i64: 1391; CHECK: # %bb.0: # %entry 1392; CHECK-NEXT: subi16 sp, sp, 4 1393; CHECK-NEXT: .cfi_def_cfa_offset 4 1394; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill 1395; CHECK-NEXT: .cfi_offset l0, -4 1396; CHECK-NEXT: .cfi_def_cfa_offset 4 1397; CHECK-NEXT: ld32.w t0, (sp, 8) 1398; CHECK-NEXT: ld32.w t1, (sp, 4) 1399; CHECK-NEXT: movih32 l0, 729 1400; CHECK-NEXT: ori32 l0, l0, 2033 1401; CHECK-NEXT: cmphs16 a0, l0 1402; CHECK-NEXT: mvcv16 a0 1403; CHECK-NEXT: cmpnei16 a1, 0 1404; CHECK-NEXT: movi16 a1, 0 1405; CHECK-NEXT: movf32 a1, a0 1406; CHECK-NEXT: btsti32 a1, 0 1407; CHECK-NEXT: movt32 a2, t1 1408; CHECK-NEXT: movt32 a3, t0 1409; CHECK-NEXT: mov16 a0, a2 1410; CHECK-NEXT: mov16 a1, a3 1411; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload 1412; CHECK-NEXT: addi16 sp, sp, 4 1413; CHECK-NEXT: rts16 1414entry: 1415 %icmp = icmp ult i64 %x, 47777777 1416 %ret = select i1 %icmp, i64 %m, i64 %n 1417 ret i64 %ret 1418} 1419 1420define i64 @selectC_ult_i64(i1 %c, i64 %n, i64 %m) { 1421; CHECK-LABEL: selectC_ult_i64: 1422; CHECK: # %bb.0: # %entry 1423; CHECK-NEXT: ld32.w t0, (sp, 0) 1424; CHECK-NEXT: btsti32 a0, 0 1425; CHECK-NEXT: movt32 a1, a3 1426; CHECK-NEXT: movt32 a2, t0 1427; CHECK-NEXT: mov16 a0, a1 1428; CHECK-NEXT: mov16 a1, a2 1429; CHECK-NEXT: rts16 1430entry: 1431 %ret = select i1 %c, i64 %m, i64 %n 1432 ret i64 %ret 1433} 1434 1435 1436define i16 @selectRR_ult_i16(i16 %x, i16 %y, i16 %n, i16 %m) { 1437; CHECK-LABEL: selectRR_ult_i16: 1438; CHECK: # %bb.0: # %entry 1439; CHECK-NEXT: zexth16 a0, a0 1440; CHECK-NEXT: zexth16 a1, a1 1441; CHECK-NEXT: cmphs16 a1, a0 1442; CHECK-NEXT: movf32 a2, a3 1443; CHECK-NEXT: mov16 a0, a2 1444; CHECK-NEXT: rts16 1445entry: 1446 %icmp = icmp ult i16 %y, %x 1447 %ret = select i1 %icmp, i16 %m, i16 %n 1448 ret i16 %ret 1449} 1450 1451define i16 @selectRI_ult_i16(i16 %x, i16 %n, i16 %m) { 1452; CHECK-LABEL: selectRI_ult_i16: 1453; CHECK: # %bb.0: # %entry 1454; CHECK-NEXT: zexth16 a0, a0 1455; CHECK-NEXT: cmphsi16 a0, 10 1456; CHECK-NEXT: movf32 a1, a2 1457; CHECK-NEXT: mov16 a0, a1 1458; CHECK-NEXT: rts16 1459entry: 1460 %icmp = icmp ult i16 %x, 10 1461 %ret = select i1 %icmp, i16 %m, i16 %n 1462 ret i16 %ret 1463} 1464 1465define i16 @selectRX_ult_i16(i16 %x, i16 %n, i16 %m) { 1466; CHECK-LABEL: selectRX_ult_i16: 1467; CHECK: # %bb.0: # %entry 1468; CHECK-NEXT: zexth16 a0, a0 1469; CHECK-NEXT: cmphsi32 a0, 2033 1470; CHECK-NEXT: movf32 a1, a2 1471; CHECK-NEXT: mov16 a0, a1 1472; CHECK-NEXT: rts16 1473entry: 1474 %icmp = icmp ult i16 %x, 47777777 1475 %ret = select i1 %icmp, i16 %m, i16 %n 1476 ret i16 %ret 1477} 1478 1479define i16 @selectC_ult_i16(i1 %c, i16 %n, i16 %m) { 1480; CHECK-LABEL: selectC_ult_i16: 1481; CHECK: # %bb.0: # %entry 1482; CHECK-NEXT: btsti32 a0, 0 1483; CHECK-NEXT: movt32 a1, a2 1484; CHECK-NEXT: mov16 a0, a1 1485; CHECK-NEXT: rts16 1486entry: 1487 %ret = select i1 %c, i16 %m, i16 %n 1488 ret i16 %ret 1489} 1490 1491 1492define i8 @selectRR_ult_i8(i8 %x, i8 %y, i8 %n, i8 %m) { 1493; CHECK-LABEL: selectRR_ult_i8: 1494; CHECK: # %bb.0: # %entry 1495; CHECK-NEXT: zextb16 a0, a0 1496; CHECK-NEXT: zextb16 a1, a1 1497; CHECK-NEXT: cmphs16 a1, a0 1498; CHECK-NEXT: movf32 a2, a3 1499; CHECK-NEXT: mov16 a0, a2 1500; CHECK-NEXT: rts16 1501entry: 1502 %icmp = icmp ult i8 %y, %x 1503 %ret = select i1 %icmp, i8 %m, i8 %n 1504 ret i8 %ret 1505} 1506 1507define i8 @selectRI_ult_i8(i8 %x, i8 %n, i8 %m) { 1508; CHECK-LABEL: selectRI_ult_i8: 1509; CHECK: # %bb.0: # %entry 1510; CHECK-NEXT: zextb16 a0, a0 1511; CHECK-NEXT: cmphsi16 a0, 10 1512; CHECK-NEXT: movf32 a1, a2 1513; CHECK-NEXT: mov16 a0, a1 1514; CHECK-NEXT: rts16 1515entry: 1516 %icmp = icmp ult i8 %x, 10 1517 %ret = select i1 %icmp, i8 %m, i8 %n 1518 ret i8 %ret 1519} 1520 1521define i8 @selectRX_ult_i8(i8 %x, i8 %n, i8 %m) { 1522; CHECK-LABEL: selectRX_ult_i8: 1523; CHECK: # %bb.0: # %entry 1524; CHECK-NEXT: zextb16 a0, a0 1525; CHECK-NEXT: cmphsi32 a0, 241 1526; CHECK-NEXT: movf32 a1, a2 1527; CHECK-NEXT: mov16 a0, a1 1528; CHECK-NEXT: rts16 1529entry: 1530 %icmp = icmp ult i8 %x, 47777777 1531 %ret = select i1 %icmp, i8 %m, i8 %n 1532 ret i8 %ret 1533} 1534 1535define i8 @selectC_ult_i8(i1 %c, i8 %n, i8 %m) { 1536; CHECK-LABEL: selectC_ult_i8: 1537; CHECK: # %bb.0: # %entry 1538; CHECK-NEXT: btsti32 a0, 0 1539; CHECK-NEXT: movt32 a1, a2 1540; CHECK-NEXT: mov16 a0, a1 1541; CHECK-NEXT: rts16 1542entry: 1543 %ret = select i1 %c, i8 %m, i8 %n 1544 ret i8 %ret 1545} 1546 1547 1548define i1 @selectRR_ult_i1(i1 %x, i1 %y, i1 %n, i1 %m) { 1549; CHECK-LABEL: selectRR_ult_i1: 1550; CHECK: # %bb.0: # %entry 1551; CHECK-NEXT: btsti32 a1, 0 1552; CHECK-NEXT: movt32 a3, a2 1553; CHECK-NEXT: btsti32 a0, 0 1554; CHECK-NEXT: movt32 a2, a3 1555; CHECK-NEXT: mov16 a0, a2 1556; CHECK-NEXT: rts16 1557entry: 1558 %icmp = icmp ult i1 %y, %x 1559 %ret = select i1 %icmp, i1 %m, i1 %n 1560 ret i1 %ret 1561} 1562 1563define i1 @selectRI_ult_i1(i1 %x, i1 %n, i1 %m) { 1564; CHECK-LABEL: selectRI_ult_i1: 1565; CHECK: # %bb.0: # %entry 1566; CHECK-NEXT: mov16 a0, a1 1567; CHECK-NEXT: rts16 1568entry: 1569 %icmp = icmp ult i1 %x, 10 1570 %ret = select i1 %icmp, i1 %m, i1 %n 1571 ret i1 %ret 1572} 1573 1574define i1 @selectRX_ult_i1(i1 %x, i1 %n, i1 %m) { 1575; CHECK-LABEL: selectRX_ult_i1: 1576; CHECK: # %bb.0: # %entry 1577; CHECK-NEXT: btsti32 a0, 0 1578; CHECK-NEXT: movt32 a2, a1 1579; CHECK-NEXT: mov16 a0, a2 1580; CHECK-NEXT: rts16 1581entry: 1582 %icmp = icmp ult i1 %x, 47777777 1583 %ret = select i1 %icmp, i1 %m, i1 %n 1584 ret i1 %ret 1585} 1586 1587define i1 @selectC_ult_i1(i1 %c, i1 %n, i1 %m) { 1588; CHECK-LABEL: selectC_ult_i1: 1589; CHECK: # %bb.0: # %entry 1590; CHECK-NEXT: btsti32 a0, 0 1591; CHECK-NEXT: movt32 a1, a2 1592; CHECK-NEXT: mov16 a0, a1 1593; CHECK-NEXT: rts16 1594entry: 1595 %ret = select i1 %c, i1 %m, i1 %n 1596 ret i1 %ret 1597} 1598 1599define i32 @selectRR_ule_i32(i32 %x, i32 %y, i32 %n, i32 %m) { 1600; CHECK-LABEL: selectRR_ule_i32: 1601; CHECK: # %bb.0: # %entry 1602; CHECK-NEXT: cmphs16 a0, a1 1603; CHECK-NEXT: movt32 a2, a3 1604; CHECK-NEXT: mov16 a0, a2 1605; CHECK-NEXT: rts16 1606entry: 1607 %icmp = icmp ule i32 %y, %x 1608 %ret = select i1 %icmp, i32 %m, i32 %n 1609 ret i32 %ret 1610} 1611 1612define i32 @selectRI_ule_i32(i32 %x, i32 %n, i32 %m) { 1613; CHECK-LABEL: selectRI_ule_i32: 1614; CHECK: # %bb.0: # %entry 1615; CHECK-NEXT: cmphsi16 a0, 11 1616; CHECK-NEXT: movf32 a1, a2 1617; CHECK-NEXT: mov16 a0, a1 1618; CHECK-NEXT: rts16 1619entry: 1620 %icmp = icmp ule i32 %x, 10 1621 %ret = select i1 %icmp, i32 %m, i32 %n 1622 ret i32 %ret 1623} 1624 1625define i32 @selectRX_ule_i32(i32 %x, i32 %n, i32 %m) { 1626; CHECK-LABEL: selectRX_ule_i32: 1627; CHECK: # %bb.0: # %entry 1628; CHECK-NEXT: movih32 a3, 729 1629; CHECK-NEXT: ori32 a3, a3, 2034 1630; CHECK-NEXT: cmphs16 a0, a3 1631; CHECK-NEXT: movf32 a1, a2 1632; CHECK-NEXT: mov16 a0, a1 1633; CHECK-NEXT: rts16 1634entry: 1635 %icmp = icmp ule i32 %x, 47777777 1636 %ret = select i1 %icmp, i32 %m, i32 %n 1637 ret i32 %ret 1638} 1639 1640define i32 @selectC_ule_i32(i1 %c, i32 %n, i32 %m) { 1641; CHECK-LABEL: selectC_ule_i32: 1642; CHECK: # %bb.0: # %entry 1643; CHECK-NEXT: btsti32 a0, 0 1644; CHECK-NEXT: movt32 a1, a2 1645; CHECK-NEXT: mov16 a0, a1 1646; CHECK-NEXT: rts16 1647entry: 1648 %ret = select i1 %c, i32 %m, i32 %n 1649 ret i32 %ret 1650} 1651 1652define i64 @selectRR_ule_i64(i64 %x, i64 %y, i64 %n, i64 %m) { 1653; CHECK-LABEL: selectRR_ule_i64: 1654; CHECK: # %bb.0: # %entry 1655; CHECK-NEXT: .cfi_def_cfa_offset 0 1656; CHECK-NEXT: subi16 sp, sp, 16 1657; CHECK-NEXT: .cfi_def_cfa_offset 16 1658; CHECK-NEXT: cmphs16 a1, a3 1659; CHECK-NEXT: mvc32 t0 1660; CHECK-NEXT: st32.w t0, (sp, 12) 1661; CHECK-NEXT: cmphs16 a0, a2 1662; CHECK-NEXT: mvc32 a0 1663; CHECK-NEXT: st16.w a0, (sp, 4) 1664; CHECK-NEXT: cmpne16 a3, a1 1665; CHECK-NEXT: mvc32 a0 1666; CHECK-NEXT: st16.w a0, (sp, 8) 1667; CHECK-NEXT: ld16.w a0, (sp, 4) 1668; CHECK-NEXT: btsti32 a0, 0 1669; CHECK-NEXT: mvc32 a0 1670; CHECK-NEXT: ld16.w a1, (sp, 12) 1671; CHECK-NEXT: btsti32 a1, 0 1672; CHECK-NEXT: mvc32 a1 1673; CHECK-NEXT: ld16.w a2, (sp, 8) 1674; CHECK-NEXT: btsti32 a2, 0 1675; CHECK-NEXT: movf32 a1, a0 1676; CHECK-NEXT: addi16 a2, sp, 16 1677; CHECK-NEXT: addi16 a0, sp, 24 1678; CHECK-NEXT: btsti32 a1, 0 1679; CHECK-NEXT: movt32 a2, a0 1680; CHECK-NEXT: ld16.w a0, (a2, 0) 1681; CHECK-NEXT: ld16.w a1, (a2, 4) 1682; CHECK-NEXT: addi16 sp, sp, 16 1683; CHECK-NEXT: rts16 1684entry: 1685 %icmp = icmp ule i64 %y, %x 1686 %ret = select i1 %icmp, i64 %m, i64 %n 1687 ret i64 %ret 1688} 1689 1690define i64 @selectRI_ule_i64(i64 %x, i64 %n, i64 %m) { 1691; CHECK-LABEL: selectRI_ule_i64: 1692; CHECK: # %bb.0: # %entry 1693; CHECK-NEXT: .cfi_def_cfa_offset 0 1694; CHECK-NEXT: subi16 sp, sp, 8 1695; CHECK-NEXT: .cfi_def_cfa_offset 8 1696; CHECK-NEXT: ld32.w t0, (sp, 12) 1697; CHECK-NEXT: ld32.w t1, (sp, 8) 1698; CHECK-NEXT: cmpnei16 a1, 0 1699; CHECK-NEXT: st16.w a2, (sp, 0) 1700; CHECK-NEXT: mvc32 a1 1701; CHECK-NEXT: st16.w a1, (sp, 4) 1702; CHECK-NEXT: cmphsi16 a0, 11 1703; CHECK-NEXT: mvcv16 a0 1704; CHECK-NEXT: movi16 a1, 0 1705; CHECK-NEXT: ld16.w a2, (sp, 4) 1706; CHECK-NEXT: btsti32 a2, 0 1707; CHECK-NEXT: ld16.w a2, (sp, 0) 1708; CHECK-NEXT: movf32 a1, a0 1709; CHECK-NEXT: btsti32 a1, 0 1710; CHECK-NEXT: movt32 a2, t1 1711; CHECK-NEXT: movt32 a3, t0 1712; CHECK-NEXT: mov16 a0, a2 1713; CHECK-NEXT: mov16 a1, a3 1714; CHECK-NEXT: addi16 sp, sp, 8 1715; CHECK-NEXT: rts16 1716entry: 1717 %icmp = icmp ule i64 %x, 10 1718 %ret = select i1 %icmp, i64 %m, i64 %n 1719 ret i64 %ret 1720} 1721 1722define i64 @selectRX_ule_i64(i64 %x, i64 %n, i64 %m) { 1723; CHECK-LABEL: selectRX_ule_i64: 1724; CHECK: # %bb.0: # %entry 1725; CHECK-NEXT: subi16 sp, sp, 4 1726; CHECK-NEXT: .cfi_def_cfa_offset 4 1727; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill 1728; CHECK-NEXT: .cfi_offset l0, -4 1729; CHECK-NEXT: .cfi_def_cfa_offset 4 1730; CHECK-NEXT: ld32.w t0, (sp, 8) 1731; CHECK-NEXT: ld32.w t1, (sp, 4) 1732; CHECK-NEXT: movih32 l0, 729 1733; CHECK-NEXT: ori32 l0, l0, 2034 1734; CHECK-NEXT: cmphs16 a0, l0 1735; CHECK-NEXT: mvcv16 a0 1736; CHECK-NEXT: cmpnei16 a1, 0 1737; CHECK-NEXT: movi16 a1, 0 1738; CHECK-NEXT: movf32 a1, a0 1739; CHECK-NEXT: btsti32 a1, 0 1740; CHECK-NEXT: movt32 a2, t1 1741; CHECK-NEXT: movt32 a3, t0 1742; CHECK-NEXT: mov16 a0, a2 1743; CHECK-NEXT: mov16 a1, a3 1744; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload 1745; CHECK-NEXT: addi16 sp, sp, 4 1746; CHECK-NEXT: rts16 1747entry: 1748 %icmp = icmp ule i64 %x, 47777777 1749 %ret = select i1 %icmp, i64 %m, i64 %n 1750 ret i64 %ret 1751} 1752 1753define i64 @selectC_ule_i64(i1 %c, i64 %n, i64 %m) { 1754; CHECK-LABEL: selectC_ule_i64: 1755; CHECK: # %bb.0: # %entry 1756; CHECK-NEXT: ld32.w t0, (sp, 0) 1757; CHECK-NEXT: btsti32 a0, 0 1758; CHECK-NEXT: movt32 a1, a3 1759; CHECK-NEXT: movt32 a2, t0 1760; CHECK-NEXT: mov16 a0, a1 1761; CHECK-NEXT: mov16 a1, a2 1762; CHECK-NEXT: rts16 1763entry: 1764 %ret = select i1 %c, i64 %m, i64 %n 1765 ret i64 %ret 1766} 1767 1768 1769define i16 @selectRR_ule_i16(i16 %x, i16 %y, i16 %n, i16 %m) { 1770; CHECK-LABEL: selectRR_ule_i16: 1771; CHECK: # %bb.0: # %entry 1772; CHECK-NEXT: zexth16 a1, a1 1773; CHECK-NEXT: zexth16 a0, a0 1774; CHECK-NEXT: cmphs16 a0, a1 1775; CHECK-NEXT: movt32 a2, a3 1776; CHECK-NEXT: mov16 a0, a2 1777; CHECK-NEXT: rts16 1778entry: 1779 %icmp = icmp ule i16 %y, %x 1780 %ret = select i1 %icmp, i16 %m, i16 %n 1781 ret i16 %ret 1782} 1783 1784define i16 @selectRI_ule_i16(i16 %x, i16 %n, i16 %m) { 1785; CHECK-LABEL: selectRI_ule_i16: 1786; CHECK: # %bb.0: # %entry 1787; CHECK-NEXT: zexth16 a0, a0 1788; CHECK-NEXT: cmphsi16 a0, 11 1789; CHECK-NEXT: movf32 a1, a2 1790; CHECK-NEXT: mov16 a0, a1 1791; CHECK-NEXT: rts16 1792entry: 1793 %icmp = icmp ule i16 %x, 10 1794 %ret = select i1 %icmp, i16 %m, i16 %n 1795 ret i16 %ret 1796} 1797 1798define i16 @selectRX_ule_i16(i16 %x, i16 %n, i16 %m) { 1799; CHECK-LABEL: selectRX_ule_i16: 1800; CHECK: # %bb.0: # %entry 1801; CHECK-NEXT: zexth16 a0, a0 1802; CHECK-NEXT: cmphsi32 a0, 2034 1803; CHECK-NEXT: movf32 a1, a2 1804; CHECK-NEXT: mov16 a0, a1 1805; CHECK-NEXT: rts16 1806entry: 1807 %icmp = icmp ule i16 %x, 47777777 1808 %ret = select i1 %icmp, i16 %m, i16 %n 1809 ret i16 %ret 1810} 1811 1812define i16 @selectC_ule_i16(i1 %c, i16 %n, i16 %m) { 1813; CHECK-LABEL: selectC_ule_i16: 1814; CHECK: # %bb.0: # %entry 1815; CHECK-NEXT: btsti32 a0, 0 1816; CHECK-NEXT: movt32 a1, a2 1817; CHECK-NEXT: mov16 a0, a1 1818; CHECK-NEXT: rts16 1819entry: 1820 %ret = select i1 %c, i16 %m, i16 %n 1821 ret i16 %ret 1822} 1823 1824 1825define i8 @selectRR_ule_i8(i8 %x, i8 %y, i8 %n, i8 %m) { 1826; CHECK-LABEL: selectRR_ule_i8: 1827; CHECK: # %bb.0: # %entry 1828; CHECK-NEXT: zextb16 a1, a1 1829; CHECK-NEXT: zextb16 a0, a0 1830; CHECK-NEXT: cmphs16 a0, a1 1831; CHECK-NEXT: movt32 a2, a3 1832; CHECK-NEXT: mov16 a0, a2 1833; CHECK-NEXT: rts16 1834entry: 1835 %icmp = icmp ule i8 %y, %x 1836 %ret = select i1 %icmp, i8 %m, i8 %n 1837 ret i8 %ret 1838} 1839 1840define i8 @selectRI_ule_i8(i8 %x, i8 %n, i8 %m) { 1841; CHECK-LABEL: selectRI_ule_i8: 1842; CHECK: # %bb.0: # %entry 1843; CHECK-NEXT: zextb16 a0, a0 1844; CHECK-NEXT: cmphsi16 a0, 11 1845; CHECK-NEXT: movf32 a1, a2 1846; CHECK-NEXT: mov16 a0, a1 1847; CHECK-NEXT: rts16 1848entry: 1849 %icmp = icmp ule i8 %x, 10 1850 %ret = select i1 %icmp, i8 %m, i8 %n 1851 ret i8 %ret 1852} 1853 1854define i8 @selectRX_ule_i8(i8 %x, i8 %n, i8 %m) { 1855; CHECK-LABEL: selectRX_ule_i8: 1856; CHECK: # %bb.0: # %entry 1857; CHECK-NEXT: zextb16 a0, a0 1858; CHECK-NEXT: cmphsi32 a0, 242 1859; CHECK-NEXT: movf32 a1, a2 1860; CHECK-NEXT: mov16 a0, a1 1861; CHECK-NEXT: rts16 1862entry: 1863 %icmp = icmp ule i8 %x, 47777777 1864 %ret = select i1 %icmp, i8 %m, i8 %n 1865 ret i8 %ret 1866} 1867 1868define i8 @selectC_ule_i8(i1 %c, i8 %n, i8 %m) { 1869; CHECK-LABEL: selectC_ule_i8: 1870; CHECK: # %bb.0: # %entry 1871; CHECK-NEXT: btsti32 a0, 0 1872; CHECK-NEXT: movt32 a1, a2 1873; CHECK-NEXT: mov16 a0, a1 1874; CHECK-NEXT: rts16 1875entry: 1876 %ret = select i1 %c, i8 %m, i8 %n 1877 ret i8 %ret 1878} 1879 1880 1881define i1 @selectRR_ule_i1(i1 %x, i1 %y, i1 %n, i1 %m) { 1882; CHECK-LABEL: selectRR_ule_i1: 1883; CHECK: # %bb.0: # %entry 1884; CHECK-NEXT: btsti32 a1, 0 1885; CHECK-NEXT: mov16 a1, a3 1886; CHECK-NEXT: movt32 a1, a2 1887; CHECK-NEXT: btsti32 a0, 0 1888; CHECK-NEXT: movt32 a1, a3 1889; CHECK-NEXT: mov16 a0, a1 1890; CHECK-NEXT: rts16 1891entry: 1892 %icmp = icmp ule i1 %y, %x 1893 %ret = select i1 %icmp, i1 %m, i1 %n 1894 ret i1 %ret 1895} 1896 1897define i1 @selectRI_ule_i1(i1 %x, i1 %n, i1 %m) { 1898; CHECK-LABEL: selectRI_ule_i1: 1899; CHECK: # %bb.0: # %entry 1900; CHECK-NEXT: btsti32 a0, 0 1901; CHECK-NEXT: movt32 a2, a1 1902; CHECK-NEXT: mov16 a0, a2 1903; CHECK-NEXT: rts16 1904entry: 1905 %icmp = icmp ule i1 %x, 10 1906 %ret = select i1 %icmp, i1 %m, i1 %n 1907 ret i1 %ret 1908} 1909 1910define i1 @selectRX_ule_i1(i1 %x, i1 %n, i1 %m) { 1911; CHECK-LABEL: selectRX_ule_i1: 1912; CHECK: # %bb.0: # %entry 1913; CHECK-NEXT: mov16 a0, a2 1914; CHECK-NEXT: rts16 1915entry: 1916 %icmp = icmp ule i1 %x, 47777777 1917 %ret = select i1 %icmp, i1 %m, i1 %n 1918 ret i1 %ret 1919} 1920 1921define i1 @selectC_ule_i1(i1 %c, i1 %n, i1 %m) { 1922; CHECK-LABEL: selectC_ule_i1: 1923; CHECK: # %bb.0: # %entry 1924; CHECK-NEXT: btsti32 a0, 0 1925; CHECK-NEXT: movt32 a1, a2 1926; CHECK-NEXT: mov16 a0, a1 1927; CHECK-NEXT: rts16 1928entry: 1929 %ret = select i1 %c, i1 %m, i1 %n 1930 ret i1 %ret 1931} 1932 1933 1934define i32 @selectRR_sgt_i32(i32 %x, i32 %y, i32 %n, i32 %m) { 1935; CHECK-LABEL: selectRR_sgt_i32: 1936; CHECK: # %bb.0: # %entry 1937; CHECK-NEXT: cmplt16 a0, a1 1938; CHECK-NEXT: movt32 a2, a3 1939; CHECK-NEXT: mov16 a0, a2 1940; CHECK-NEXT: rts16 1941entry: 1942 %icmp = icmp sgt i32 %y, %x 1943 %ret = select i1 %icmp, i32 %m, i32 %n 1944 ret i32 %ret 1945} 1946 1947define i32 @selectRI_sgt_i32(i32 %x, i32 %n, i32 %m) { 1948; CHECK-LABEL: selectRI_sgt_i32: 1949; CHECK: # %bb.0: # %entry 1950; CHECK-NEXT: movi16 a3, 10 1951; CHECK-NEXT: cmplt16 a3, a0 1952; CHECK-NEXT: movt32 a1, a2 1953; CHECK-NEXT: mov16 a0, a1 1954; CHECK-NEXT: rts16 1955entry: 1956 %icmp = icmp sgt i32 %x, 10 1957 %ret = select i1 %icmp, i32 %m, i32 %n 1958 ret i32 %ret 1959} 1960 1961define i32 @selectRX_sgt_i32(i32 %x, i32 %n, i32 %m) { 1962; CHECK-LABEL: selectRX_sgt_i32: 1963; CHECK: # %bb.0: # %entry 1964; CHECK-NEXT: movih32 a3, 729 1965; CHECK-NEXT: ori32 a3, a3, 2033 1966; CHECK-NEXT: cmplt16 a3, a0 1967; CHECK-NEXT: movt32 a1, a2 1968; CHECK-NEXT: mov16 a0, a1 1969; CHECK-NEXT: rts16 1970entry: 1971 %icmp = icmp sgt i32 %x, 47777777 1972 %ret = select i1 %icmp, i32 %m, i32 %n 1973 ret i32 %ret 1974} 1975 1976define i32 @selectC_sgt_i32(i1 %c, i32 %n, i32 %m) { 1977; CHECK-LABEL: selectC_sgt_i32: 1978; CHECK: # %bb.0: # %entry 1979; CHECK-NEXT: btsti32 a0, 0 1980; CHECK-NEXT: movt32 a1, a2 1981; CHECK-NEXT: mov16 a0, a1 1982; CHECK-NEXT: rts16 1983entry: 1984 %ret = select i1 %c, i32 %m, i32 %n 1985 ret i32 %ret 1986} 1987 1988define i64 @selectRR_sgt_i64(i64 %x, i64 %y, i64 %n, i64 %m) { 1989; CHECK-LABEL: selectRR_sgt_i64: 1990; CHECK: # %bb.0: # %entry 1991; CHECK-NEXT: .cfi_def_cfa_offset 0 1992; CHECK-NEXT: subi16 sp, sp, 12 1993; CHECK-NEXT: .cfi_def_cfa_offset 12 1994; CHECK-NEXT: cmplt16 a1, a3 1995; CHECK-NEXT: mvc32 t0 1996; CHECK-NEXT: st32.w t0, (sp, 4) 1997; CHECK-NEXT: cmpne16 a3, a1 1998; CHECK-NEXT: mvc32 a1 1999; CHECK-NEXT: st16.w a1, (sp, 8) 2000; CHECK-NEXT: cmphs16 a0, a2 2001; CHECK-NEXT: mvcv16 a0 2002; CHECK-NEXT: ld16.w a1, (sp, 4) 2003; CHECK-NEXT: btsti32 a1, 0 2004; CHECK-NEXT: mvc32 a1 2005; CHECK-NEXT: ld16.w a2, (sp, 8) 2006; CHECK-NEXT: btsti32 a2, 0 2007; CHECK-NEXT: movf32 a1, a0 2008; CHECK-NEXT: addi16 a2, sp, 12 2009; CHECK-NEXT: addi16 a0, sp, 20 2010; CHECK-NEXT: btsti32 a1, 0 2011; CHECK-NEXT: movt32 a2, a0 2012; CHECK-NEXT: ld16.w a0, (a2, 0) 2013; CHECK-NEXT: ld16.w a1, (a2, 4) 2014; CHECK-NEXT: addi16 sp, sp, 12 2015; CHECK-NEXT: rts16 2016entry: 2017 %icmp = icmp sgt i64 %y, %x 2018 %ret = select i1 %icmp, i64 %m, i64 %n 2019 ret i64 %ret 2020} 2021 2022define i64 @selectRI_sgt_i64(i64 %x, i64 %n, i64 %m) { 2023; CHECK-LABEL: selectRI_sgt_i64: 2024; CHECK: # %bb.0: # %entry 2025; CHECK-NEXT: subi16 sp, sp, 4 2026; CHECK-NEXT: .cfi_def_cfa_offset 4 2027; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill 2028; CHECK-NEXT: .cfi_offset l0, -4 2029; CHECK-NEXT: subi16 sp, sp, 12 2030; CHECK-NEXT: .cfi_def_cfa_offset 16 2031; CHECK-NEXT: ld32.w t0, (sp, 20) 2032; CHECK-NEXT: ld32.w t1, (sp, 16) 2033; CHECK-NEXT: movi16 l0, 0 2034; CHECK-NEXT: cmplt16 l0, a1 2035; CHECK-NEXT: mvc32 l0 2036; CHECK-NEXT: st16.w l0, (sp, 8) 2037; CHECK-NEXT: movi16 l0, 10 2038; CHECK-NEXT: cmphs16 l0, a0 2039; CHECK-NEXT: mvcv16 a0 2040; CHECK-NEXT: cmpnei16 a1, 0 2041; CHECK-NEXT: mvc32 a1 2042; CHECK-NEXT: st16.w a1, (sp, 4) 2043; CHECK-NEXT: ld16.w a1, (sp, 8) 2044; CHECK-NEXT: btsti32 a1, 0 2045; CHECK-NEXT: mvc32 a1 2046; CHECK-NEXT: ld16.w l0, (sp, 4) 2047; CHECK-NEXT: btsti32 l0, 0 2048; CHECK-NEXT: movf32 a1, a0 2049; CHECK-NEXT: btsti32 a1, 0 2050; CHECK-NEXT: movt32 a2, t1 2051; CHECK-NEXT: movt32 a3, t0 2052; CHECK-NEXT: mov16 a0, a2 2053; CHECK-NEXT: mov16 a1, a3 2054; CHECK-NEXT: addi16 sp, sp, 12 2055; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload 2056; CHECK-NEXT: addi16 sp, sp, 4 2057; CHECK-NEXT: rts16 2058entry: 2059 %icmp = icmp sgt i64 %x, 10 2060 %ret = select i1 %icmp, i64 %m, i64 %n 2061 ret i64 %ret 2062} 2063 2064define i64 @selectRX_sgt_i64(i64 %x, i64 %n, i64 %m) { 2065; CHECK-LABEL: selectRX_sgt_i64: 2066; CHECK: # %bb.0: # %entry 2067; CHECK-NEXT: subi16 sp, sp, 4 2068; CHECK-NEXT: .cfi_def_cfa_offset 4 2069; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill 2070; CHECK-NEXT: .cfi_offset l0, -4 2071; CHECK-NEXT: subi16 sp, sp, 12 2072; CHECK-NEXT: .cfi_def_cfa_offset 16 2073; CHECK-NEXT: ld32.w t0, (sp, 20) 2074; CHECK-NEXT: ld32.w t1, (sp, 16) 2075; CHECK-NEXT: movi16 l0, 0 2076; CHECK-NEXT: cmplt16 l0, a1 2077; CHECK-NEXT: mvc32 l0 2078; CHECK-NEXT: st16.w l0, (sp, 8) 2079; CHECK-NEXT: movih32 l0, 729 2080; CHECK-NEXT: ori32 l0, l0, 2033 2081; CHECK-NEXT: cmphs16 l0, a0 2082; CHECK-NEXT: mvcv16 a0 2083; CHECK-NEXT: cmpnei16 a1, 0 2084; CHECK-NEXT: mvc32 a1 2085; CHECK-NEXT: st16.w a1, (sp, 4) 2086; CHECK-NEXT: ld16.w a1, (sp, 8) 2087; CHECK-NEXT: btsti32 a1, 0 2088; CHECK-NEXT: mvc32 a1 2089; CHECK-NEXT: ld16.w l0, (sp, 4) 2090; CHECK-NEXT: btsti32 l0, 0 2091; CHECK-NEXT: movf32 a1, a0 2092; CHECK-NEXT: btsti32 a1, 0 2093; CHECK-NEXT: movt32 a2, t1 2094; CHECK-NEXT: movt32 a3, t0 2095; CHECK-NEXT: mov16 a0, a2 2096; CHECK-NEXT: mov16 a1, a3 2097; CHECK-NEXT: addi16 sp, sp, 12 2098; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload 2099; CHECK-NEXT: addi16 sp, sp, 4 2100; CHECK-NEXT: rts16 2101entry: 2102 %icmp = icmp sgt i64 %x, 47777777 2103 %ret = select i1 %icmp, i64 %m, i64 %n 2104 ret i64 %ret 2105} 2106 2107define i64 @selectC_sgt_i64(i1 %c, i64 %n, i64 %m) { 2108; CHECK-LABEL: selectC_sgt_i64: 2109; CHECK: # %bb.0: # %entry 2110; CHECK-NEXT: ld32.w t0, (sp, 0) 2111; CHECK-NEXT: btsti32 a0, 0 2112; CHECK-NEXT: movt32 a1, a3 2113; CHECK-NEXT: movt32 a2, t0 2114; CHECK-NEXT: mov16 a0, a1 2115; CHECK-NEXT: mov16 a1, a2 2116; CHECK-NEXT: rts16 2117entry: 2118 %ret = select i1 %c, i64 %m, i64 %n 2119 ret i64 %ret 2120} 2121 2122 2123define i16 @selectRR_sgt_i16(i16 %x, i16 %y, i16 %n, i16 %m) { 2124; CHECK-LABEL: selectRR_sgt_i16: 2125; CHECK: # %bb.0: # %entry 2126; CHECK-NEXT: sexth16 a1, a1 2127; CHECK-NEXT: sexth16 a0, a0 2128; CHECK-NEXT: cmplt16 a0, a1 2129; CHECK-NEXT: movt32 a2, a3 2130; CHECK-NEXT: mov16 a0, a2 2131; CHECK-NEXT: rts16 2132entry: 2133 %icmp = icmp sgt i16 %y, %x 2134 %ret = select i1 %icmp, i16 %m, i16 %n 2135 ret i16 %ret 2136} 2137 2138define i16 @selectRI_sgt_i16(i16 %x, i16 %n, i16 %m) { 2139; CHECK-LABEL: selectRI_sgt_i16: 2140; CHECK: # %bb.0: # %entry 2141; CHECK-NEXT: sexth16 a0, a0 2142; CHECK-NEXT: movi16 a3, 10 2143; CHECK-NEXT: cmplt16 a3, a0 2144; CHECK-NEXT: movt32 a1, a2 2145; CHECK-NEXT: mov16 a0, a1 2146; CHECK-NEXT: rts16 2147entry: 2148 %icmp = icmp sgt i16 %x, 10 2149 %ret = select i1 %icmp, i16 %m, i16 %n 2150 ret i16 %ret 2151} 2152 2153define i16 @selectRX_sgt_i16(i16 %x, i16 %n, i16 %m) { 2154; CHECK-LABEL: selectRX_sgt_i16: 2155; CHECK: # %bb.0: # %entry 2156; CHECK-NEXT: sexth16 a0, a0 2157; CHECK-NEXT: movi32 a3, 2033 2158; CHECK-NEXT: cmplt16 a3, a0 2159; CHECK-NEXT: movt32 a1, a2 2160; CHECK-NEXT: mov16 a0, a1 2161; CHECK-NEXT: rts16 2162entry: 2163 %icmp = icmp sgt i16 %x, 47777777 2164 %ret = select i1 %icmp, i16 %m, i16 %n 2165 ret i16 %ret 2166} 2167 2168define i16 @selectC_sgt_i16(i1 %c, i16 %n, i16 %m) { 2169; CHECK-LABEL: selectC_sgt_i16: 2170; CHECK: # %bb.0: # %entry 2171; CHECK-NEXT: btsti32 a0, 0 2172; CHECK-NEXT: movt32 a1, a2 2173; CHECK-NEXT: mov16 a0, a1 2174; CHECK-NEXT: rts16 2175entry: 2176 %ret = select i1 %c, i16 %m, i16 %n 2177 ret i16 %ret 2178} 2179 2180 2181define i8 @selectRR_sgt_i8(i8 %x, i8 %y, i8 %n, i8 %m) { 2182; CHECK-LABEL: selectRR_sgt_i8: 2183; CHECK: # %bb.0: # %entry 2184; CHECK-NEXT: sextb16 a1, a1 2185; CHECK-NEXT: sextb16 a0, a0 2186; CHECK-NEXT: cmplt16 a0, a1 2187; CHECK-NEXT: movt32 a2, a3 2188; CHECK-NEXT: mov16 a0, a2 2189; CHECK-NEXT: rts16 2190entry: 2191 %icmp = icmp sgt i8 %y, %x 2192 %ret = select i1 %icmp, i8 %m, i8 %n 2193 ret i8 %ret 2194} 2195 2196define i8 @selectRI_sgt_i8(i8 %x, i8 %n, i8 %m) { 2197; CHECK-LABEL: selectRI_sgt_i8: 2198; CHECK: # %bb.0: # %entry 2199; CHECK-NEXT: sextb16 a0, a0 2200; CHECK-NEXT: movi16 a3, 10 2201; CHECK-NEXT: cmplt16 a3, a0 2202; CHECK-NEXT: movt32 a1, a2 2203; CHECK-NEXT: mov16 a0, a1 2204; CHECK-NEXT: rts16 2205entry: 2206 %icmp = icmp sgt i8 %x, 10 2207 %ret = select i1 %icmp, i8 %m, i8 %n 2208 ret i8 %ret 2209} 2210 2211define i8 @selectRX_sgt_i8(i8 %x, i8 %n, i8 %m) { 2212; CHECK-LABEL: selectRX_sgt_i8: 2213; CHECK: # %bb.0: # %entry 2214; CHECK-NEXT: sextb16 a0, a0 2215; CHECK-NEXT: movih32 a3, 65535 2216; CHECK-NEXT: ori32 a3, a3, 65521 2217; CHECK-NEXT: cmplt16 a3, a0 2218; CHECK-NEXT: movt32 a1, a2 2219; CHECK-NEXT: mov16 a0, a1 2220; CHECK-NEXT: rts16 2221entry: 2222 %icmp = icmp sgt i8 %x, 47777777 2223 %ret = select i1 %icmp, i8 %m, i8 %n 2224 ret i8 %ret 2225} 2226 2227define i8 @selectC_sgt_i8(i1 %c, i8 %n, i8 %m) { 2228; CHECK-LABEL: selectC_sgt_i8: 2229; CHECK: # %bb.0: # %entry 2230; CHECK-NEXT: btsti32 a0, 0 2231; CHECK-NEXT: movt32 a1, a2 2232; CHECK-NEXT: mov16 a0, a1 2233; CHECK-NEXT: rts16 2234entry: 2235 %ret = select i1 %c, i8 %m, i8 %n 2236 ret i8 %ret 2237} 2238 2239 2240define i1 @selectRR_sgt_i1(i1 %x, i1 %y, i1 %n, i1 %m) { 2241; CHECK-LABEL: selectRR_sgt_i1: 2242; CHECK: # %bb.0: # %entry 2243; CHECK-NEXT: btsti32 a1, 0 2244; CHECK-NEXT: movt32 a3, a2 2245; CHECK-NEXT: btsti32 a0, 0 2246; CHECK-NEXT: movt32 a2, a3 2247; CHECK-NEXT: mov16 a0, a2 2248; CHECK-NEXT: rts16 2249entry: 2250 %icmp = icmp sgt i1 %y, %x 2251 %ret = select i1 %icmp, i1 %m, i1 %n 2252 ret i1 %ret 2253} 2254 2255define i1 @selectRI_sgt_i1(i1 %x, i1 %n, i1 %m) { 2256; CHECK-LABEL: selectRI_sgt_i1: 2257; CHECK: # %bb.0: # %entry 2258; CHECK-NEXT: mov16 a0, a1 2259; CHECK-NEXT: rts16 2260entry: 2261 %icmp = icmp sgt i1 %x, 10 2262 %ret = select i1 %icmp, i1 %m, i1 %n 2263 ret i1 %ret 2264} 2265 2266define i1 @selectRX_sgt_i1(i1 %x, i1 %n, i1 %m) { 2267; CHECK-LABEL: selectRX_sgt_i1: 2268; CHECK: # %bb.0: # %entry 2269; CHECK-NEXT: btsti32 a0, 0 2270; CHECK-NEXT: movt32 a2, a1 2271; CHECK-NEXT: mov16 a0, a2 2272; CHECK-NEXT: rts16 2273entry: 2274 %icmp = icmp sgt i1 %x, 47777777 2275 %ret = select i1 %icmp, i1 %m, i1 %n 2276 ret i1 %ret 2277} 2278 2279define i1 @selectC_sgt_i1(i1 %c, i1 %n, i1 %m) { 2280; CHECK-LABEL: selectC_sgt_i1: 2281; CHECK: # %bb.0: # %entry 2282; CHECK-NEXT: btsti32 a0, 0 2283; CHECK-NEXT: movt32 a1, a2 2284; CHECK-NEXT: mov16 a0, a1 2285; CHECK-NEXT: rts16 2286entry: 2287 %ret = select i1 %c, i1 %m, i1 %n 2288 ret i1 %ret 2289} 2290 2291 2292define i32 @selectRR_sge_i32(i32 %x, i32 %y, i32 %n, i32 %m) { 2293; CHECK-LABEL: selectRR_sge_i32: 2294; CHECK: # %bb.0: # %entry 2295; CHECK-NEXT: cmplt16 a1, a0 2296; CHECK-NEXT: movf32 a2, a3 2297; CHECK-NEXT: mov16 a0, a2 2298; CHECK-NEXT: rts16 2299entry: 2300 %icmp = icmp sge i32 %y, %x 2301 %ret = select i1 %icmp, i32 %m, i32 %n 2302 ret i32 %ret 2303} 2304 2305define i32 @selectRI_sge_i32(i32 %x, i32 %n, i32 %m) { 2306; CHECK-LABEL: selectRI_sge_i32: 2307; CHECK: # %bb.0: # %entry 2308; CHECK-NEXT: movi16 a3, 9 2309; CHECK-NEXT: cmplt16 a3, a0 2310; CHECK-NEXT: movt32 a1, a2 2311; CHECK-NEXT: mov16 a0, a1 2312; CHECK-NEXT: rts16 2313entry: 2314 %icmp = icmp sge i32 %x, 10 2315 %ret = select i1 %icmp, i32 %m, i32 %n 2316 ret i32 %ret 2317} 2318 2319define i32 @selectRX_sge_i32(i32 %x, i32 %n, i32 %m) { 2320; CHECK-LABEL: selectRX_sge_i32: 2321; CHECK: # %bb.0: # %entry 2322; CHECK-NEXT: movih32 a3, 729 2323; CHECK-NEXT: ori32 a3, a3, 2032 2324; CHECK-NEXT: cmplt16 a3, a0 2325; CHECK-NEXT: movt32 a1, a2 2326; CHECK-NEXT: mov16 a0, a1 2327; CHECK-NEXT: rts16 2328entry: 2329 %icmp = icmp sge i32 %x, 47777777 2330 %ret = select i1 %icmp, i32 %m, i32 %n 2331 ret i32 %ret 2332} 2333 2334define i32 @selectC_sge_i32(i1 %c, i32 %n, i32 %m) { 2335; CHECK-LABEL: selectC_sge_i32: 2336; CHECK: # %bb.0: # %entry 2337; CHECK-NEXT: btsti32 a0, 0 2338; CHECK-NEXT: movt32 a1, a2 2339; CHECK-NEXT: mov16 a0, a1 2340; CHECK-NEXT: rts16 2341entry: 2342 %ret = select i1 %c, i32 %m, i32 %n 2343 ret i32 %ret 2344} 2345 2346define i64 @selectRR_sge_i64(i64 %x, i64 %y, i64 %n, i64 %m) { 2347; CHECK-LABEL: selectRR_sge_i64: 2348; CHECK: # %bb.0: # %entry 2349; CHECK-NEXT: .cfi_def_cfa_offset 0 2350; CHECK-NEXT: subi16 sp, sp, 12 2351; CHECK-NEXT: .cfi_def_cfa_offset 12 2352; CHECK-NEXT: cmphs16 a2, a0 2353; CHECK-NEXT: mvc32 a0 2354; CHECK-NEXT: st16.w a0, (sp, 4) 2355; CHECK-NEXT: cmpne16 a3, a1 2356; CHECK-NEXT: mvc32 a0 2357; CHECK-NEXT: st16.w a0, (sp, 8) 2358; CHECK-NEXT: cmplt16 a3, a1 2359; CHECK-NEXT: mvcv16 a0 2360; CHECK-NEXT: ld16.w a1, (sp, 4) 2361; CHECK-NEXT: btsti32 a1, 0 2362; CHECK-NEXT: mvc32 a1 2363; CHECK-NEXT: ld16.w a2, (sp, 8) 2364; CHECK-NEXT: btsti32 a2, 0 2365; CHECK-NEXT: movf32 a0, a1 2366; CHECK-NEXT: addi16 a1, sp, 12 2367; CHECK-NEXT: addi16 a2, sp, 20 2368; CHECK-NEXT: btsti32 a0, 0 2369; CHECK-NEXT: movt32 a1, a2 2370; CHECK-NEXT: ld16.w a0, (a1, 0) 2371; CHECK-NEXT: ld16.w a1, (a1, 4) 2372; CHECK-NEXT: addi16 sp, sp, 12 2373; CHECK-NEXT: rts16 2374entry: 2375 %icmp = icmp sge i64 %y, %x 2376 %ret = select i1 %icmp, i64 %m, i64 %n 2377 ret i64 %ret 2378} 2379 2380define i64 @selectRI_sge_i64(i64 %x, i64 %n, i64 %m) { 2381; CHECK-LABEL: selectRI_sge_i64: 2382; CHECK: # %bb.0: # %entry 2383; CHECK-NEXT: subi16 sp, sp, 4 2384; CHECK-NEXT: .cfi_def_cfa_offset 4 2385; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill 2386; CHECK-NEXT: .cfi_offset l0, -4 2387; CHECK-NEXT: subi16 sp, sp, 12 2388; CHECK-NEXT: .cfi_def_cfa_offset 16 2389; CHECK-NEXT: ld32.w t0, (sp, 20) 2390; CHECK-NEXT: ld32.w t1, (sp, 16) 2391; CHECK-NEXT: movi16 l0, 0 2392; CHECK-NEXT: cmplt16 l0, a1 2393; CHECK-NEXT: mvc32 l0 2394; CHECK-NEXT: st16.w l0, (sp, 8) 2395; CHECK-NEXT: movi16 l0, 9 2396; CHECK-NEXT: cmphs16 l0, a0 2397; CHECK-NEXT: mvcv16 a0 2398; CHECK-NEXT: cmpnei16 a1, 0 2399; CHECK-NEXT: mvc32 a1 2400; CHECK-NEXT: st16.w a1, (sp, 4) 2401; CHECK-NEXT: ld16.w a1, (sp, 8) 2402; CHECK-NEXT: btsti32 a1, 0 2403; CHECK-NEXT: mvc32 a1 2404; CHECK-NEXT: ld16.w l0, (sp, 4) 2405; CHECK-NEXT: btsti32 l0, 0 2406; CHECK-NEXT: movf32 a1, a0 2407; CHECK-NEXT: btsti32 a1, 0 2408; CHECK-NEXT: movt32 a2, t1 2409; CHECK-NEXT: movt32 a3, t0 2410; CHECK-NEXT: mov16 a0, a2 2411; CHECK-NEXT: mov16 a1, a3 2412; CHECK-NEXT: addi16 sp, sp, 12 2413; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload 2414; CHECK-NEXT: addi16 sp, sp, 4 2415; CHECK-NEXT: rts16 2416entry: 2417 %icmp = icmp sge i64 %x, 10 2418 %ret = select i1 %icmp, i64 %m, i64 %n 2419 ret i64 %ret 2420} 2421 2422define i64 @selectRX_sge_i64(i64 %x, i64 %n, i64 %m) { 2423; CHECK-LABEL: selectRX_sge_i64: 2424; CHECK: # %bb.0: # %entry 2425; CHECK-NEXT: subi16 sp, sp, 4 2426; CHECK-NEXT: .cfi_def_cfa_offset 4 2427; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill 2428; CHECK-NEXT: .cfi_offset l0, -4 2429; CHECK-NEXT: subi16 sp, sp, 12 2430; CHECK-NEXT: .cfi_def_cfa_offset 16 2431; CHECK-NEXT: ld32.w t0, (sp, 20) 2432; CHECK-NEXT: ld32.w t1, (sp, 16) 2433; CHECK-NEXT: movi16 l0, 0 2434; CHECK-NEXT: cmplt16 l0, a1 2435; CHECK-NEXT: mvc32 l0 2436; CHECK-NEXT: st16.w l0, (sp, 8) 2437; CHECK-NEXT: movih32 l0, 729 2438; CHECK-NEXT: ori32 l0, l0, 2032 2439; CHECK-NEXT: cmphs16 l0, a0 2440; CHECK-NEXT: mvcv16 a0 2441; CHECK-NEXT: cmpnei16 a1, 0 2442; CHECK-NEXT: mvc32 a1 2443; CHECK-NEXT: st16.w a1, (sp, 4) 2444; CHECK-NEXT: ld16.w a1, (sp, 8) 2445; CHECK-NEXT: btsti32 a1, 0 2446; CHECK-NEXT: mvc32 a1 2447; CHECK-NEXT: ld16.w l0, (sp, 4) 2448; CHECK-NEXT: btsti32 l0, 0 2449; CHECK-NEXT: movf32 a1, a0 2450; CHECK-NEXT: btsti32 a1, 0 2451; CHECK-NEXT: movt32 a2, t1 2452; CHECK-NEXT: movt32 a3, t0 2453; CHECK-NEXT: mov16 a0, a2 2454; CHECK-NEXT: mov16 a1, a3 2455; CHECK-NEXT: addi16 sp, sp, 12 2456; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload 2457; CHECK-NEXT: addi16 sp, sp, 4 2458; CHECK-NEXT: rts16 2459entry: 2460 %icmp = icmp sge i64 %x, 47777777 2461 %ret = select i1 %icmp, i64 %m, i64 %n 2462 ret i64 %ret 2463} 2464 2465define i64 @selectC_sge_i64(i1 %c, i64 %n, i64 %m) { 2466; CHECK-LABEL: selectC_sge_i64: 2467; CHECK: # %bb.0: # %entry 2468; CHECK-NEXT: ld32.w t0, (sp, 0) 2469; CHECK-NEXT: btsti32 a0, 0 2470; CHECK-NEXT: movt32 a1, a3 2471; CHECK-NEXT: movt32 a2, t0 2472; CHECK-NEXT: mov16 a0, a1 2473; CHECK-NEXT: mov16 a1, a2 2474; CHECK-NEXT: rts16 2475entry: 2476 %ret = select i1 %c, i64 %m, i64 %n 2477 ret i64 %ret 2478} 2479 2480 2481define i16 @selectRR_sge_i16(i16 %x, i16 %y, i16 %n, i16 %m) { 2482; CHECK-LABEL: selectRR_sge_i16: 2483; CHECK: # %bb.0: # %entry 2484; CHECK-NEXT: sexth16 a0, a0 2485; CHECK-NEXT: sexth16 a1, a1 2486; CHECK-NEXT: cmplt16 a1, a0 2487; CHECK-NEXT: movf32 a2, a3 2488; CHECK-NEXT: mov16 a0, a2 2489; CHECK-NEXT: rts16 2490entry: 2491 %icmp = icmp sge i16 %y, %x 2492 %ret = select i1 %icmp, i16 %m, i16 %n 2493 ret i16 %ret 2494} 2495 2496define i16 @selectRI_sge_i16(i16 %x, i16 %n, i16 %m) { 2497; CHECK-LABEL: selectRI_sge_i16: 2498; CHECK: # %bb.0: # %entry 2499; CHECK-NEXT: sexth16 a0, a0 2500; CHECK-NEXT: movi16 a3, 9 2501; CHECK-NEXT: cmplt16 a3, a0 2502; CHECK-NEXT: movt32 a1, a2 2503; CHECK-NEXT: mov16 a0, a1 2504; CHECK-NEXT: rts16 2505entry: 2506 %icmp = icmp sge i16 %x, 10 2507 %ret = select i1 %icmp, i16 %m, i16 %n 2508 ret i16 %ret 2509} 2510 2511define i16 @selectRX_sge_i16(i16 %x, i16 %n, i16 %m) { 2512; CHECK-LABEL: selectRX_sge_i16: 2513; CHECK: # %bb.0: # %entry 2514; CHECK-NEXT: sexth16 a0, a0 2515; CHECK-NEXT: movi32 a3, 2032 2516; CHECK-NEXT: cmplt16 a3, a0 2517; CHECK-NEXT: movt32 a1, a2 2518; CHECK-NEXT: mov16 a0, a1 2519; CHECK-NEXT: rts16 2520entry: 2521 %icmp = icmp sge i16 %x, 47777777 2522 %ret = select i1 %icmp, i16 %m, i16 %n 2523 ret i16 %ret 2524} 2525 2526define i16 @selectC_sge_i16(i1 %c, i16 %n, i16 %m) { 2527; CHECK-LABEL: selectC_sge_i16: 2528; CHECK: # %bb.0: # %entry 2529; CHECK-NEXT: btsti32 a0, 0 2530; CHECK-NEXT: movt32 a1, a2 2531; CHECK-NEXT: mov16 a0, a1 2532; CHECK-NEXT: rts16 2533entry: 2534 %ret = select i1 %c, i16 %m, i16 %n 2535 ret i16 %ret 2536} 2537 2538 2539define i8 @selectRR_sge_i8(i8 %x, i8 %y, i8 %n, i8 %m) { 2540; CHECK-LABEL: selectRR_sge_i8: 2541; CHECK: # %bb.0: # %entry 2542; CHECK-NEXT: sextb16 a0, a0 2543; CHECK-NEXT: sextb16 a1, a1 2544; CHECK-NEXT: cmplt16 a1, a0 2545; CHECK-NEXT: movf32 a2, a3 2546; CHECK-NEXT: mov16 a0, a2 2547; CHECK-NEXT: rts16 2548entry: 2549 %icmp = icmp sge i8 %y, %x 2550 %ret = select i1 %icmp, i8 %m, i8 %n 2551 ret i8 %ret 2552} 2553 2554define i8 @selectRI_sge_i8(i8 %x, i8 %n, i8 %m) { 2555; CHECK-LABEL: selectRI_sge_i8: 2556; CHECK: # %bb.0: # %entry 2557; CHECK-NEXT: sextb16 a0, a0 2558; CHECK-NEXT: movi16 a3, 9 2559; CHECK-NEXT: cmplt16 a3, a0 2560; CHECK-NEXT: movt32 a1, a2 2561; CHECK-NEXT: mov16 a0, a1 2562; CHECK-NEXT: rts16 2563entry: 2564 %icmp = icmp sge i8 %x, 10 2565 %ret = select i1 %icmp, i8 %m, i8 %n 2566 ret i8 %ret 2567} 2568 2569define i8 @selectRX_sge_i8(i8 %x, i8 %n, i8 %m) { 2570; CHECK-LABEL: selectRX_sge_i8: 2571; CHECK: # %bb.0: # %entry 2572; CHECK-NEXT: sextb16 a0, a0 2573; CHECK-NEXT: movih32 a3, 65535 2574; CHECK-NEXT: ori32 a3, a3, 65520 2575; CHECK-NEXT: cmplt16 a3, a0 2576; CHECK-NEXT: movt32 a1, a2 2577; CHECK-NEXT: mov16 a0, a1 2578; CHECK-NEXT: rts16 2579entry: 2580 %icmp = icmp sge i8 %x, 47777777 2581 %ret = select i1 %icmp, i8 %m, i8 %n 2582 ret i8 %ret 2583} 2584 2585define i8 @selectC_sge_i8(i1 %c, i8 %n, i8 %m) { 2586; CHECK-LABEL: selectC_sge_i8: 2587; CHECK: # %bb.0: # %entry 2588; CHECK-NEXT: btsti32 a0, 0 2589; CHECK-NEXT: movt32 a1, a2 2590; CHECK-NEXT: mov16 a0, a1 2591; CHECK-NEXT: rts16 2592entry: 2593 %ret = select i1 %c, i8 %m, i8 %n 2594 ret i8 %ret 2595} 2596 2597 2598define i1 @selectRR_sge_i1(i1 %x, i1 %y, i1 %n, i1 %m) { 2599; CHECK-LABEL: selectRR_sge_i1: 2600; CHECK: # %bb.0: # %entry 2601; CHECK-NEXT: btsti32 a1, 0 2602; CHECK-NEXT: mov16 a1, a3 2603; CHECK-NEXT: movt32 a1, a2 2604; CHECK-NEXT: btsti32 a0, 0 2605; CHECK-NEXT: movt32 a1, a3 2606; CHECK-NEXT: mov16 a0, a1 2607; CHECK-NEXT: rts16 2608entry: 2609 %icmp = icmp sge i1 %y, %x 2610 %ret = select i1 %icmp, i1 %m, i1 %n 2611 ret i1 %ret 2612} 2613 2614define i1 @selectRI_sge_i1(i1 %x, i1 %n, i1 %m) { 2615; CHECK-LABEL: selectRI_sge_i1: 2616; CHECK: # %bb.0: # %entry 2617; CHECK-NEXT: btsti32 a0, 0 2618; CHECK-NEXT: movt32 a2, a1 2619; CHECK-NEXT: mov16 a0, a2 2620; CHECK-NEXT: rts16 2621entry: 2622 %icmp = icmp sge i1 %x, 10 2623 %ret = select i1 %icmp, i1 %m, i1 %n 2624 ret i1 %ret 2625} 2626 2627define i1 @selectRX_sge_i1(i1 %x, i1 %n, i1 %m) { 2628; CHECK-LABEL: selectRX_sge_i1: 2629; CHECK: # %bb.0: # %entry 2630; CHECK-NEXT: mov16 a0, a2 2631; CHECK-NEXT: rts16 2632entry: 2633 %icmp = icmp sge i1 %x, 47777777 2634 %ret = select i1 %icmp, i1 %m, i1 %n 2635 ret i1 %ret 2636} 2637 2638define i1 @selectC_sge_i1(i1 %c, i1 %n, i1 %m) { 2639; CHECK-LABEL: selectC_sge_i1: 2640; CHECK: # %bb.0: # %entry 2641; CHECK-NEXT: btsti32 a0, 0 2642; CHECK-NEXT: movt32 a1, a2 2643; CHECK-NEXT: mov16 a0, a1 2644; CHECK-NEXT: rts16 2645entry: 2646 %ret = select i1 %c, i1 %m, i1 %n 2647 ret i1 %ret 2648} 2649 2650 2651define i32 @selectRR_slt_i32(i32 %x, i32 %y, i32 %n, i32 %m) { 2652; CHECK-LABEL: selectRR_slt_i32: 2653; CHECK: # %bb.0: # %entry 2654; CHECK-NEXT: cmplt16 a1, a0 2655; CHECK-NEXT: movt32 a2, a3 2656; CHECK-NEXT: mov16 a0, a2 2657; CHECK-NEXT: rts16 2658entry: 2659 %icmp = icmp slt i32 %y, %x 2660 %ret = select i1 %icmp, i32 %m, i32 %n 2661 ret i32 %ret 2662} 2663 2664define i32 @selectRI_slt_i32(i32 %x, i32 %n, i32 %m) { 2665; CHECK-LABEL: selectRI_slt_i32: 2666; CHECK: # %bb.0: # %entry 2667; CHECK-NEXT: cmplti16 a0, 10 2668; CHECK-NEXT: movt32 a1, a2 2669; CHECK-NEXT: mov16 a0, a1 2670; CHECK-NEXT: rts16 2671entry: 2672 %icmp = icmp slt i32 %x, 10 2673 %ret = select i1 %icmp, i32 %m, i32 %n 2674 ret i32 %ret 2675} 2676 2677define i32 @selectRX_slt_i32(i32 %x, i32 %n, i32 %m) { 2678; CHECK-LABEL: selectRX_slt_i32: 2679; CHECK: # %bb.0: # %entry 2680; CHECK-NEXT: movih32 a3, 729 2681; CHECK-NEXT: ori32 a3, a3, 2033 2682; CHECK-NEXT: cmplt16 a0, a3 2683; CHECK-NEXT: movt32 a1, a2 2684; CHECK-NEXT: mov16 a0, a1 2685; CHECK-NEXT: rts16 2686entry: 2687 %icmp = icmp slt i32 %x, 47777777 2688 %ret = select i1 %icmp, i32 %m, i32 %n 2689 ret i32 %ret 2690} 2691 2692define i32 @selectC_slt_i32(i1 %c, i32 %n, i32 %m) { 2693; CHECK-LABEL: selectC_slt_i32: 2694; CHECK: # %bb.0: # %entry 2695; CHECK-NEXT: btsti32 a0, 0 2696; CHECK-NEXT: movt32 a1, a2 2697; CHECK-NEXT: mov16 a0, a1 2698; CHECK-NEXT: rts16 2699entry: 2700 %ret = select i1 %c, i32 %m, i32 %n 2701 ret i32 %ret 2702} 2703 2704define i64 @selectRR_slt_i64(i64 %x, i64 %y, i64 %n, i64 %m) { 2705; CHECK-LABEL: selectRR_slt_i64: 2706; CHECK: # %bb.0: # %entry 2707; CHECK-NEXT: .cfi_def_cfa_offset 0 2708; CHECK-NEXT: subi16 sp, sp, 12 2709; CHECK-NEXT: .cfi_def_cfa_offset 12 2710; CHECK-NEXT: cmplt16 a3, a1 2711; CHECK-NEXT: mvc32 t0 2712; CHECK-NEXT: st32.w t0, (sp, 4) 2713; CHECK-NEXT: cmpne16 a3, a1 2714; CHECK-NEXT: mvc32 a1 2715; CHECK-NEXT: st16.w a1, (sp, 8) 2716; CHECK-NEXT: cmphs16 a2, a0 2717; CHECK-NEXT: mvcv16 a0 2718; CHECK-NEXT: ld16.w a1, (sp, 4) 2719; CHECK-NEXT: btsti32 a1, 0 2720; CHECK-NEXT: mvc32 a1 2721; CHECK-NEXT: ld16.w a2, (sp, 8) 2722; CHECK-NEXT: btsti32 a2, 0 2723; CHECK-NEXT: movf32 a1, a0 2724; CHECK-NEXT: addi16 a2, sp, 12 2725; CHECK-NEXT: addi16 a0, sp, 20 2726; CHECK-NEXT: btsti32 a1, 0 2727; CHECK-NEXT: movt32 a2, a0 2728; CHECK-NEXT: ld16.w a0, (a2, 0) 2729; CHECK-NEXT: ld16.w a1, (a2, 4) 2730; CHECK-NEXT: addi16 sp, sp, 12 2731; CHECK-NEXT: rts16 2732entry: 2733 %icmp = icmp slt i64 %y, %x 2734 %ret = select i1 %icmp, i64 %m, i64 %n 2735 ret i64 %ret 2736} 2737 2738define i64 @selectRI_slt_i64(i64 %x, i64 %n, i64 %m) { 2739; CHECK-LABEL: selectRI_slt_i64: 2740; CHECK: # %bb.0: # %entry 2741; CHECK-NEXT: subi16 sp, sp, 4 2742; CHECK-NEXT: .cfi_def_cfa_offset 4 2743; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill 2744; CHECK-NEXT: .cfi_offset l0, -4 2745; CHECK-NEXT: subi16 sp, sp, 12 2746; CHECK-NEXT: .cfi_def_cfa_offset 16 2747; CHECK-NEXT: ld32.w t0, (sp, 20) 2748; CHECK-NEXT: ld32.w t1, (sp, 16) 2749; CHECK-NEXT: movi16 l0, 0 2750; CHECK-NEXT: cmplt16 a1, l0 2751; CHECK-NEXT: mvc32 l0 2752; CHECK-NEXT: st16.w l0, (sp, 4) 2753; CHECK-NEXT: cmpnei16 a1, 0 2754; CHECK-NEXT: mvc32 a1 2755; CHECK-NEXT: st16.w a1, (sp, 8) 2756; CHECK-NEXT: cmphsi16 a0, 10 2757; CHECK-NEXT: mvcv16 a0 2758; CHECK-NEXT: ld16.w a1, (sp, 4) 2759; CHECK-NEXT: btsti32 a1, 0 2760; CHECK-NEXT: mvc32 a1 2761; CHECK-NEXT: ld16.w l0, (sp, 8) 2762; CHECK-NEXT: btsti32 l0, 0 2763; CHECK-NEXT: movf32 a1, a0 2764; CHECK-NEXT: btsti32 a1, 0 2765; CHECK-NEXT: movt32 a2, t1 2766; CHECK-NEXT: movt32 a3, t0 2767; CHECK-NEXT: mov16 a0, a2 2768; CHECK-NEXT: mov16 a1, a3 2769; CHECK-NEXT: addi16 sp, sp, 12 2770; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload 2771; CHECK-NEXT: addi16 sp, sp, 4 2772; CHECK-NEXT: rts16 2773entry: 2774 %icmp = icmp slt i64 %x, 10 2775 %ret = select i1 %icmp, i64 %m, i64 %n 2776 ret i64 %ret 2777} 2778 2779define i64 @selectRX_slt_i64(i64 %x, i64 %n, i64 %m) { 2780; CHECK-LABEL: selectRX_slt_i64: 2781; CHECK: # %bb.0: # %entry 2782; CHECK-NEXT: subi16 sp, sp, 4 2783; CHECK-NEXT: .cfi_def_cfa_offset 4 2784; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill 2785; CHECK-NEXT: .cfi_offset l0, -4 2786; CHECK-NEXT: subi16 sp, sp, 12 2787; CHECK-NEXT: .cfi_def_cfa_offset 16 2788; CHECK-NEXT: ld32.w t0, (sp, 20) 2789; CHECK-NEXT: ld32.w t1, (sp, 16) 2790; CHECK-NEXT: movi16 l0, 0 2791; CHECK-NEXT: cmplt16 a1, l0 2792; CHECK-NEXT: mvc32 l0 2793; CHECK-NEXT: st16.w l0, (sp, 8) 2794; CHECK-NEXT: movih32 l0, 729 2795; CHECK-NEXT: ori32 l0, l0, 2033 2796; CHECK-NEXT: cmphs16 a0, l0 2797; CHECK-NEXT: mvcv16 a0 2798; CHECK-NEXT: cmpnei16 a1, 0 2799; CHECK-NEXT: mvc32 a1 2800; CHECK-NEXT: st16.w a1, (sp, 4) 2801; CHECK-NEXT: ld16.w a1, (sp, 8) 2802; CHECK-NEXT: btsti32 a1, 0 2803; CHECK-NEXT: mvc32 a1 2804; CHECK-NEXT: ld16.w l0, (sp, 4) 2805; CHECK-NEXT: btsti32 l0, 0 2806; CHECK-NEXT: movf32 a1, a0 2807; CHECK-NEXT: btsti32 a1, 0 2808; CHECK-NEXT: movt32 a2, t1 2809; CHECK-NEXT: movt32 a3, t0 2810; CHECK-NEXT: mov16 a0, a2 2811; CHECK-NEXT: mov16 a1, a3 2812; CHECK-NEXT: addi16 sp, sp, 12 2813; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload 2814; CHECK-NEXT: addi16 sp, sp, 4 2815; CHECK-NEXT: rts16 2816entry: 2817 %icmp = icmp slt i64 %x, 47777777 2818 %ret = select i1 %icmp, i64 %m, i64 %n 2819 ret i64 %ret 2820} 2821 2822define i64 @selectC_slt_i64(i1 %c, i64 %n, i64 %m) { 2823; CHECK-LABEL: selectC_slt_i64: 2824; CHECK: # %bb.0: # %entry 2825; CHECK-NEXT: ld32.w t0, (sp, 0) 2826; CHECK-NEXT: btsti32 a0, 0 2827; CHECK-NEXT: movt32 a1, a3 2828; CHECK-NEXT: movt32 a2, t0 2829; CHECK-NEXT: mov16 a0, a1 2830; CHECK-NEXT: mov16 a1, a2 2831; CHECK-NEXT: rts16 2832entry: 2833 %ret = select i1 %c, i64 %m, i64 %n 2834 ret i64 %ret 2835} 2836 2837 2838define i16 @selectRR_slt_i16(i16 %x, i16 %y, i16 %n, i16 %m) { 2839; CHECK-LABEL: selectRR_slt_i16: 2840; CHECK: # %bb.0: # %entry 2841; CHECK-NEXT: sexth16 a0, a0 2842; CHECK-NEXT: sexth16 a1, a1 2843; CHECK-NEXT: cmplt16 a1, a0 2844; CHECK-NEXT: movt32 a2, a3 2845; CHECK-NEXT: mov16 a0, a2 2846; CHECK-NEXT: rts16 2847entry: 2848 %icmp = icmp slt i16 %y, %x 2849 %ret = select i1 %icmp, i16 %m, i16 %n 2850 ret i16 %ret 2851} 2852 2853define i16 @selectRI_slt_i16(i16 %x, i16 %n, i16 %m) { 2854; CHECK-LABEL: selectRI_slt_i16: 2855; CHECK: # %bb.0: # %entry 2856; CHECK-NEXT: sexth16 a0, a0 2857; CHECK-NEXT: cmplti16 a0, 10 2858; CHECK-NEXT: movt32 a1, a2 2859; CHECK-NEXT: mov16 a0, a1 2860; CHECK-NEXT: rts16 2861entry: 2862 %icmp = icmp slt i16 %x, 10 2863 %ret = select i1 %icmp, i16 %m, i16 %n 2864 ret i16 %ret 2865} 2866 2867define i16 @selectRX_slt_i16(i16 %x, i16 %n, i16 %m) { 2868; CHECK-LABEL: selectRX_slt_i16: 2869; CHECK: # %bb.0: # %entry 2870; CHECK-NEXT: sexth16 a0, a0 2871; CHECK-NEXT: cmplti32 a0, 2033 2872; CHECK-NEXT: movt32 a1, a2 2873; CHECK-NEXT: mov16 a0, a1 2874; CHECK-NEXT: rts16 2875entry: 2876 %icmp = icmp slt i16 %x, 47777777 2877 %ret = select i1 %icmp, i16 %m, i16 %n 2878 ret i16 %ret 2879} 2880 2881define i16 @selectC_slt_i16(i1 %c, i16 %n, i16 %m) { 2882; CHECK-LABEL: selectC_slt_i16: 2883; CHECK: # %bb.0: # %entry 2884; CHECK-NEXT: btsti32 a0, 0 2885; CHECK-NEXT: movt32 a1, a2 2886; CHECK-NEXT: mov16 a0, a1 2887; CHECK-NEXT: rts16 2888entry: 2889 %ret = select i1 %c, i16 %m, i16 %n 2890 ret i16 %ret 2891} 2892 2893 2894define i8 @selectRR_slt_i8(i8 %x, i8 %y, i8 %n, i8 %m) { 2895; CHECK-LABEL: selectRR_slt_i8: 2896; CHECK: # %bb.0: # %entry 2897; CHECK-NEXT: sextb16 a0, a0 2898; CHECK-NEXT: sextb16 a1, a1 2899; CHECK-NEXT: cmplt16 a1, a0 2900; CHECK-NEXT: movt32 a2, a3 2901; CHECK-NEXT: mov16 a0, a2 2902; CHECK-NEXT: rts16 2903entry: 2904 %icmp = icmp slt i8 %y, %x 2905 %ret = select i1 %icmp, i8 %m, i8 %n 2906 ret i8 %ret 2907} 2908 2909define i8 @selectRI_slt_i8(i8 %x, i8 %n, i8 %m) { 2910; CHECK-LABEL: selectRI_slt_i8: 2911; CHECK: # %bb.0: # %entry 2912; CHECK-NEXT: sextb16 a0, a0 2913; CHECK-NEXT: cmplti16 a0, 10 2914; CHECK-NEXT: movt32 a1, a2 2915; CHECK-NEXT: mov16 a0, a1 2916; CHECK-NEXT: rts16 2917entry: 2918 %icmp = icmp slt i8 %x, 10 2919 %ret = select i1 %icmp, i8 %m, i8 %n 2920 ret i8 %ret 2921} 2922 2923define i8 @selectRX_slt_i8(i8 %x, i8 %n, i8 %m) { 2924; CHECK-LABEL: selectRX_slt_i8: 2925; CHECK: # %bb.0: # %entry 2926; CHECK-NEXT: sextb16 a0, a0 2927; CHECK-NEXT: movih32 a3, 65535 2928; CHECK-NEXT: ori32 a3, a3, 65521 2929; CHECK-NEXT: cmplt16 a0, a3 2930; CHECK-NEXT: movt32 a1, a2 2931; CHECK-NEXT: mov16 a0, a1 2932; CHECK-NEXT: rts16 2933entry: 2934 %icmp = icmp slt i8 %x, 47777777 2935 %ret = select i1 %icmp, i8 %m, i8 %n 2936 ret i8 %ret 2937} 2938 2939define i8 @selectC_slt_i8(i1 %c, i8 %n, i8 %m) { 2940; CHECK-LABEL: selectC_slt_i8: 2941; CHECK: # %bb.0: # %entry 2942; CHECK-NEXT: btsti32 a0, 0 2943; CHECK-NEXT: movt32 a1, a2 2944; CHECK-NEXT: mov16 a0, a1 2945; CHECK-NEXT: rts16 2946entry: 2947 %ret = select i1 %c, i8 %m, i8 %n 2948 ret i8 %ret 2949} 2950 2951 2952define i1 @selectRR_slt_i1(i1 %x, i1 %y, i1 %n, i1 %m) { 2953; CHECK-LABEL: selectRR_slt_i1: 2954; CHECK: # %bb.0: # %entry 2955; CHECK-NEXT: btsti32 a0, 0 2956; CHECK-NEXT: movt32 a3, a2 2957; CHECK-NEXT: btsti32 a1, 0 2958; CHECK-NEXT: movt32 a2, a3 2959; CHECK-NEXT: mov16 a0, a2 2960; CHECK-NEXT: rts16 2961entry: 2962 %icmp = icmp slt i1 %y, %x 2963 %ret = select i1 %icmp, i1 %m, i1 %n 2964 ret i1 %ret 2965} 2966 2967define i1 @selectRI_slt_i1(i1 %x, i1 %n, i1 %m) { 2968; CHECK-LABEL: selectRI_slt_i1: 2969; CHECK: # %bb.0: # %entry 2970; CHECK-NEXT: btsti32 a0, 0 2971; CHECK-NEXT: movt32 a1, a2 2972; CHECK-NEXT: mov16 a0, a1 2973; CHECK-NEXT: rts16 2974entry: 2975 %icmp = icmp slt i1 %x, 10 2976 %ret = select i1 %icmp, i1 %m, i1 %n 2977 ret i1 %ret 2978} 2979 2980define i1 @selectRX_slt_i1(i1 %x, i1 %n, i1 %m) { 2981; CHECK-LABEL: selectRX_slt_i1: 2982; CHECK: # %bb.0: # %entry 2983; CHECK-NEXT: mov16 a0, a1 2984; CHECK-NEXT: rts16 2985entry: 2986 %icmp = icmp slt i1 %x, 47777777 2987 %ret = select i1 %icmp, i1 %m, i1 %n 2988 ret i1 %ret 2989} 2990 2991define i1 @selectC_slt_i1(i1 %c, i1 %n, i1 %m) { 2992; CHECK-LABEL: selectC_slt_i1: 2993; CHECK: # %bb.0: # %entry 2994; CHECK-NEXT: btsti32 a0, 0 2995; CHECK-NEXT: movt32 a1, a2 2996; CHECK-NEXT: mov16 a0, a1 2997; CHECK-NEXT: rts16 2998entry: 2999 %ret = select i1 %c, i1 %m, i1 %n 3000 ret i1 %ret 3001} 3002 3003define i32 @selectRR_sle_i32(i32 %x, i32 %y, i32 %n, i32 %m) { 3004; CHECK-LABEL: selectRR_sle_i32: 3005; CHECK: # %bb.0: # %entry 3006; CHECK-NEXT: cmplt16 a0, a1 3007; CHECK-NEXT: movf32 a2, a3 3008; CHECK-NEXT: mov16 a0, a2 3009; CHECK-NEXT: rts16 3010entry: 3011 %icmp = icmp sle i32 %y, %x 3012 %ret = select i1 %icmp, i32 %m, i32 %n 3013 ret i32 %ret 3014} 3015 3016define i32 @selectRI_sle_i32(i32 %x, i32 %n, i32 %m) { 3017; CHECK-LABEL: selectRI_sle_i32: 3018; CHECK: # %bb.0: # %entry 3019; CHECK-NEXT: cmplti16 a0, 11 3020; CHECK-NEXT: movt32 a1, a2 3021; CHECK-NEXT: mov16 a0, a1 3022; CHECK-NEXT: rts16 3023entry: 3024 %icmp = icmp sle i32 %x, 10 3025 %ret = select i1 %icmp, i32 %m, i32 %n 3026 ret i32 %ret 3027} 3028 3029define i32 @selectRX_sle_i32(i32 %x, i32 %n, i32 %m) { 3030; CHECK-LABEL: selectRX_sle_i32: 3031; CHECK: # %bb.0: # %entry 3032; CHECK-NEXT: movih32 a3, 729 3033; CHECK-NEXT: ori32 a3, a3, 2034 3034; CHECK-NEXT: cmplt16 a0, a3 3035; CHECK-NEXT: movt32 a1, a2 3036; CHECK-NEXT: mov16 a0, a1 3037; CHECK-NEXT: rts16 3038entry: 3039 %icmp = icmp sle i32 %x, 47777777 3040 %ret = select i1 %icmp, i32 %m, i32 %n 3041 ret i32 %ret 3042} 3043 3044define i32 @selectC_sle_i32(i1 %c, i32 %n, i32 %m) { 3045; CHECK-LABEL: selectC_sle_i32: 3046; CHECK: # %bb.0: # %entry 3047; CHECK-NEXT: btsti32 a0, 0 3048; CHECK-NEXT: movt32 a1, a2 3049; CHECK-NEXT: mov16 a0, a1 3050; CHECK-NEXT: rts16 3051entry: 3052 %ret = select i1 %c, i32 %m, i32 %n 3053 ret i32 %ret 3054} 3055 3056define i64 @selectRR_sle_i64(i64 %x, i64 %y, i64 %n, i64 %m) { 3057; CHECK-LABEL: selectRR_sle_i64: 3058; CHECK: # %bb.0: # %entry 3059; CHECK-NEXT: .cfi_def_cfa_offset 0 3060; CHECK-NEXT: subi16 sp, sp, 12 3061; CHECK-NEXT: .cfi_def_cfa_offset 12 3062; CHECK-NEXT: cmphs16 a0, a2 3063; CHECK-NEXT: mvc32 a0 3064; CHECK-NEXT: st16.w a0, (sp, 4) 3065; CHECK-NEXT: cmpne16 a3, a1 3066; CHECK-NEXT: mvc32 a0 3067; CHECK-NEXT: st16.w a0, (sp, 8) 3068; CHECK-NEXT: cmplt16 a1, a3 3069; CHECK-NEXT: mvcv16 a0 3070; CHECK-NEXT: ld16.w a1, (sp, 4) 3071; CHECK-NEXT: btsti32 a1, 0 3072; CHECK-NEXT: mvc32 a1 3073; CHECK-NEXT: ld16.w a2, (sp, 8) 3074; CHECK-NEXT: btsti32 a2, 0 3075; CHECK-NEXT: movf32 a0, a1 3076; CHECK-NEXT: addi16 a1, sp, 12 3077; CHECK-NEXT: addi16 a2, sp, 20 3078; CHECK-NEXT: btsti32 a0, 0 3079; CHECK-NEXT: movt32 a1, a2 3080; CHECK-NEXT: ld16.w a0, (a1, 0) 3081; CHECK-NEXT: ld16.w a1, (a1, 4) 3082; CHECK-NEXT: addi16 sp, sp, 12 3083; CHECK-NEXT: rts16 3084entry: 3085 %icmp = icmp sle i64 %y, %x 3086 %ret = select i1 %icmp, i64 %m, i64 %n 3087 ret i64 %ret 3088} 3089 3090define i64 @selectRI_sle_i64(i64 %x, i64 %n, i64 %m) { 3091; CHECK-LABEL: selectRI_sle_i64: 3092; CHECK: # %bb.0: # %entry 3093; CHECK-NEXT: subi16 sp, sp, 4 3094; CHECK-NEXT: .cfi_def_cfa_offset 4 3095; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill 3096; CHECK-NEXT: .cfi_offset l0, -4 3097; CHECK-NEXT: subi16 sp, sp, 12 3098; CHECK-NEXT: .cfi_def_cfa_offset 16 3099; CHECK-NEXT: ld32.w t0, (sp, 20) 3100; CHECK-NEXT: ld32.w t1, (sp, 16) 3101; CHECK-NEXT: movi16 l0, 0 3102; CHECK-NEXT: cmplt16 a1, l0 3103; CHECK-NEXT: mvc32 l0 3104; CHECK-NEXT: st16.w l0, (sp, 4) 3105; CHECK-NEXT: cmpnei16 a1, 0 3106; CHECK-NEXT: mvc32 a1 3107; CHECK-NEXT: st16.w a1, (sp, 8) 3108; CHECK-NEXT: cmphsi16 a0, 11 3109; CHECK-NEXT: mvcv16 a0 3110; CHECK-NEXT: ld16.w a1, (sp, 4) 3111; CHECK-NEXT: btsti32 a1, 0 3112; CHECK-NEXT: mvc32 a1 3113; CHECK-NEXT: ld16.w l0, (sp, 8) 3114; CHECK-NEXT: btsti32 l0, 0 3115; CHECK-NEXT: movf32 a1, a0 3116; CHECK-NEXT: btsti32 a1, 0 3117; CHECK-NEXT: movt32 a2, t1 3118; CHECK-NEXT: movt32 a3, t0 3119; CHECK-NEXT: mov16 a0, a2 3120; CHECK-NEXT: mov16 a1, a3 3121; CHECK-NEXT: addi16 sp, sp, 12 3122; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload 3123; CHECK-NEXT: addi16 sp, sp, 4 3124; CHECK-NEXT: rts16 3125entry: 3126 %icmp = icmp sle i64 %x, 10 3127 %ret = select i1 %icmp, i64 %m, i64 %n 3128 ret i64 %ret 3129} 3130 3131define i64 @selectRX_sle_i64(i64 %x, i64 %n, i64 %m) { 3132; CHECK-LABEL: selectRX_sle_i64: 3133; CHECK: # %bb.0: # %entry 3134; CHECK-NEXT: subi16 sp, sp, 4 3135; CHECK-NEXT: .cfi_def_cfa_offset 4 3136; CHECK-NEXT: st16.w l0, (sp, 0) # 4-byte Folded Spill 3137; CHECK-NEXT: .cfi_offset l0, -4 3138; CHECK-NEXT: subi16 sp, sp, 12 3139; CHECK-NEXT: .cfi_def_cfa_offset 16 3140; CHECK-NEXT: ld32.w t0, (sp, 20) 3141; CHECK-NEXT: ld32.w t1, (sp, 16) 3142; CHECK-NEXT: movi16 l0, 0 3143; CHECK-NEXT: cmplt16 a1, l0 3144; CHECK-NEXT: mvc32 l0 3145; CHECK-NEXT: st16.w l0, (sp, 8) 3146; CHECK-NEXT: movih32 l0, 729 3147; CHECK-NEXT: ori32 l0, l0, 2034 3148; CHECK-NEXT: cmphs16 a0, l0 3149; CHECK-NEXT: mvcv16 a0 3150; CHECK-NEXT: cmpnei16 a1, 0 3151; CHECK-NEXT: mvc32 a1 3152; CHECK-NEXT: st16.w a1, (sp, 4) 3153; CHECK-NEXT: ld16.w a1, (sp, 8) 3154; CHECK-NEXT: btsti32 a1, 0 3155; CHECK-NEXT: mvc32 a1 3156; CHECK-NEXT: ld16.w l0, (sp, 4) 3157; CHECK-NEXT: btsti32 l0, 0 3158; CHECK-NEXT: movf32 a1, a0 3159; CHECK-NEXT: btsti32 a1, 0 3160; CHECK-NEXT: movt32 a2, t1 3161; CHECK-NEXT: movt32 a3, t0 3162; CHECK-NEXT: mov16 a0, a2 3163; CHECK-NEXT: mov16 a1, a3 3164; CHECK-NEXT: addi16 sp, sp, 12 3165; CHECK-NEXT: ld16.w l0, (sp, 0) # 4-byte Folded Reload 3166; CHECK-NEXT: addi16 sp, sp, 4 3167; CHECK-NEXT: rts16 3168entry: 3169 %icmp = icmp sle i64 %x, 47777777 3170 %ret = select i1 %icmp, i64 %m, i64 %n 3171 ret i64 %ret 3172} 3173 3174define i64 @selectC_sle_i64(i1 %c, i64 %n, i64 %m) { 3175; CHECK-LABEL: selectC_sle_i64: 3176; CHECK: # %bb.0: # %entry 3177; CHECK-NEXT: ld32.w t0, (sp, 0) 3178; CHECK-NEXT: btsti32 a0, 0 3179; CHECK-NEXT: movt32 a1, a3 3180; CHECK-NEXT: movt32 a2, t0 3181; CHECK-NEXT: mov16 a0, a1 3182; CHECK-NEXT: mov16 a1, a2 3183; CHECK-NEXT: rts16 3184entry: 3185 %ret = select i1 %c, i64 %m, i64 %n 3186 ret i64 %ret 3187} 3188 3189 3190define i16 @selectRR_sle_i16(i16 %x, i16 %y, i16 %n, i16 %m) { 3191; CHECK-LABEL: selectRR_sle_i16: 3192; CHECK: # %bb.0: # %entry 3193; CHECK-NEXT: sexth16 a1, a1 3194; CHECK-NEXT: sexth16 a0, a0 3195; CHECK-NEXT: cmplt16 a0, a1 3196; CHECK-NEXT: movf32 a2, a3 3197; CHECK-NEXT: mov16 a0, a2 3198; CHECK-NEXT: rts16 3199entry: 3200 %icmp = icmp sle i16 %y, %x 3201 %ret = select i1 %icmp, i16 %m, i16 %n 3202 ret i16 %ret 3203} 3204 3205define i16 @selectRI_sle_i16(i16 %x, i16 %n, i16 %m) { 3206; CHECK-LABEL: selectRI_sle_i16: 3207; CHECK: # %bb.0: # %entry 3208; CHECK-NEXT: sexth16 a0, a0 3209; CHECK-NEXT: cmplti16 a0, 11 3210; CHECK-NEXT: movt32 a1, a2 3211; CHECK-NEXT: mov16 a0, a1 3212; CHECK-NEXT: rts16 3213entry: 3214 %icmp = icmp sle i16 %x, 10 3215 %ret = select i1 %icmp, i16 %m, i16 %n 3216 ret i16 %ret 3217} 3218 3219define i16 @selectRX_sle_i16(i16 %x, i16 %n, i16 %m) { 3220; CHECK-LABEL: selectRX_sle_i16: 3221; CHECK: # %bb.0: # %entry 3222; CHECK-NEXT: sexth16 a0, a0 3223; CHECK-NEXT: cmplti32 a0, 2034 3224; CHECK-NEXT: movt32 a1, a2 3225; CHECK-NEXT: mov16 a0, a1 3226; CHECK-NEXT: rts16 3227entry: 3228 %icmp = icmp sle i16 %x, 47777777 3229 %ret = select i1 %icmp, i16 %m, i16 %n 3230 ret i16 %ret 3231} 3232 3233define i16 @selectC_sle_i16(i1 %c, i16 %n, i16 %m) { 3234; CHECK-LABEL: selectC_sle_i16: 3235; CHECK: # %bb.0: # %entry 3236; CHECK-NEXT: btsti32 a0, 0 3237; CHECK-NEXT: movt32 a1, a2 3238; CHECK-NEXT: mov16 a0, a1 3239; CHECK-NEXT: rts16 3240entry: 3241 %ret = select i1 %c, i16 %m, i16 %n 3242 ret i16 %ret 3243} 3244 3245 3246define i8 @selectRR_sle_i8(i8 %x, i8 %y, i8 %n, i8 %m) { 3247; CHECK-LABEL: selectRR_sle_i8: 3248; CHECK: # %bb.0: # %entry 3249; CHECK-NEXT: sextb16 a1, a1 3250; CHECK-NEXT: sextb16 a0, a0 3251; CHECK-NEXT: cmplt16 a0, a1 3252; CHECK-NEXT: movf32 a2, a3 3253; CHECK-NEXT: mov16 a0, a2 3254; CHECK-NEXT: rts16 3255entry: 3256 %icmp = icmp sle i8 %y, %x 3257 %ret = select i1 %icmp, i8 %m, i8 %n 3258 ret i8 %ret 3259} 3260 3261define i8 @selectRI_sle_i8(i8 %x, i8 %n, i8 %m) { 3262; CHECK-LABEL: selectRI_sle_i8: 3263; CHECK: # %bb.0: # %entry 3264; CHECK-NEXT: sextb16 a0, a0 3265; CHECK-NEXT: cmplti16 a0, 11 3266; CHECK-NEXT: movt32 a1, a2 3267; CHECK-NEXT: mov16 a0, a1 3268; CHECK-NEXT: rts16 3269entry: 3270 %icmp = icmp sle i8 %x, 10 3271 %ret = select i1 %icmp, i8 %m, i8 %n 3272 ret i8 %ret 3273} 3274 3275define i8 @selectRX_sle_i8(i8 %x, i8 %n, i8 %m) { 3276; CHECK-LABEL: selectRX_sle_i8: 3277; CHECK: # %bb.0: # %entry 3278; CHECK-NEXT: sextb16 a0, a0 3279; CHECK-NEXT: movih32 a3, 65535 3280; CHECK-NEXT: ori32 a3, a3, 65522 3281; CHECK-NEXT: cmplt16 a0, a3 3282; CHECK-NEXT: movt32 a1, a2 3283; CHECK-NEXT: mov16 a0, a1 3284; CHECK-NEXT: rts16 3285entry: 3286 %icmp = icmp sle i8 %x, 47777777 3287 %ret = select i1 %icmp, i8 %m, i8 %n 3288 ret i8 %ret 3289} 3290 3291define i8 @selectC_sle_i8(i1 %c, i8 %n, i8 %m) { 3292; CHECK-LABEL: selectC_sle_i8: 3293; CHECK: # %bb.0: # %entry 3294; CHECK-NEXT: btsti32 a0, 0 3295; CHECK-NEXT: movt32 a1, a2 3296; CHECK-NEXT: mov16 a0, a1 3297; CHECK-NEXT: rts16 3298entry: 3299 %ret = select i1 %c, i8 %m, i8 %n 3300 ret i8 %ret 3301} 3302 3303 3304define i1 @selectRR_sle_i1(i1 %x, i1 %y, i1 %n, i1 %m) { 3305; CHECK-LABEL: selectRR_sle_i1: 3306; CHECK: # %bb.0: # %entry 3307; CHECK-NEXT: btsti32 a0, 0 3308; CHECK-NEXT: mov16 a0, a3 3309; CHECK-NEXT: movt32 a0, a2 3310; CHECK-NEXT: btsti32 a1, 0 3311; CHECK-NEXT: movt32 a0, a3 3312; CHECK-NEXT: rts16 3313entry: 3314 %icmp = icmp sle i1 %y, %x 3315 %ret = select i1 %icmp, i1 %m, i1 %n 3316 ret i1 %ret 3317} 3318 3319define i1 @selectRI_sle_i1(i1 %x, i1 %n, i1 %m) { 3320; CHECK-LABEL: selectRI_sle_i1: 3321; CHECK: # %bb.0: # %entry 3322; CHECK-NEXT: mov16 a0, a2 3323; CHECK-NEXT: rts16 3324entry: 3325 %icmp = icmp sle i1 %x, 10 3326 %ret = select i1 %icmp, i1 %m, i1 %n 3327 ret i1 %ret 3328} 3329 3330define i1 @selectRX_sle_i1(i1 %x, i1 %n, i1 %m) { 3331; CHECK-LABEL: selectRX_sle_i1: 3332; CHECK: # %bb.0: # %entry 3333; CHECK-NEXT: btsti32 a0, 0 3334; CHECK-NEXT: movt32 a1, a2 3335; CHECK-NEXT: mov16 a0, a1 3336; CHECK-NEXT: rts16 3337entry: 3338 %icmp = icmp sle i1 %x, 47777777 3339 %ret = select i1 %icmp, i1 %m, i1 %n 3340 ret i1 %ret 3341} 3342 3343define i1 @selectC_sle_i1(i1 %c, i1 %n, i1 %m) { 3344; CHECK-LABEL: selectC_sle_i1: 3345; CHECK: # %bb.0: # %entry 3346; CHECK-NEXT: btsti32 a0, 0 3347; CHECK-NEXT: movt32 a1, a2 3348; CHECK-NEXT: mov16 a0, a1 3349; CHECK-NEXT: rts16 3350entry: 3351 %ret = select i1 %c, i1 %m, i1 %n 3352 ret i1 %ret 3353} 3354