1; RUN: opt < %s  -cost-model -analyze -mtriple=arm-apple-ios6.0.0 -mcpu=cortex-a8 | FileCheck %s --check-prefix=COST
2; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
3; Make sure that ARM backend with NEON handles vselect.
4
5define void @vmax_v4i32(<4 x i32>* %m, <4 x i32> %a, <4 x i32> %b) {
6; CHECK: vmax.s32 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
7    %cmpres = icmp sgt <4 x i32> %a, %b
8    %maxres = select <4 x i1> %cmpres, <4 x i32> %a,  <4 x i32> %b
9    store <4 x i32> %maxres, <4 x i32>* %m
10    ret void
11}
12
13%T0_10 = type <16 x i16>
14%T1_10 = type <16 x i1>
15; CHECK-LABEL: func_blend10:
16define void @func_blend10(%T0_10* %loadaddr, %T0_10* %loadaddr2,
17                           %T1_10* %blend, %T0_10* %storeaddr) {
18  %v0 = load %T0_10, %T0_10* %loadaddr
19  %v1 = load %T0_10, %T0_10* %loadaddr2
20  %c = icmp slt %T0_10 %v0, %v1
21; CHECK: vmin.s16
22; CHECK: vmin.s16
23; COST: func_blend10
24; COST: cost of 2 {{.*}} select
25  %r = select %T1_10 %c, %T0_10 %v0, %T0_10 %v1
26  store %T0_10 %r, %T0_10* %storeaddr
27  ret void
28}
29%T0_14 = type <8 x i32>
30%T1_14 = type <8 x i1>
31; CHECK-LABEL: func_blend14:
32define void @func_blend14(%T0_14* %loadaddr, %T0_14* %loadaddr2,
33                           %T1_14* %blend, %T0_14* %storeaddr) {
34  %v0 = load %T0_14, %T0_14* %loadaddr
35  %v1 = load %T0_14, %T0_14* %loadaddr2
36  %c = icmp slt %T0_14 %v0, %v1
37; CHECK: vmin.s32
38; CHECK: vmin.s32
39; COST: func_blend14
40; COST: cost of 2 {{.*}} select
41  %r = select %T1_14 %c, %T0_14 %v0, %T0_14 %v1
42  store %T0_14 %r, %T0_14* %storeaddr
43  ret void
44}
45%T0_15 = type <16 x i32>
46%T1_15 = type <16 x i1>
47; CHECK-LABEL: func_blend15:
48define void @func_blend15(%T0_15* %loadaddr, %T0_15* %loadaddr2,
49                           %T1_15* %blend, %T0_15* %storeaddr) {
50; CHECK: vmin.s32
51; CHECK: vmin.s32
52  %v0 = load %T0_15, %T0_15* %loadaddr
53  %v1 = load %T0_15, %T0_15* %loadaddr2
54  %c = icmp slt %T0_15 %v0, %v1
55; COST: func_blend15
56; COST: cost of 4 {{.*}} select
57  %r = select %T1_15 %c, %T0_15 %v0, %T0_15 %v1
58  store %T0_15 %r, %T0_15* %storeaddr
59  ret void
60}
61
62; We adjusted the cost model of the following selects. When we improve code
63; lowering we also need to adjust the cost.
64%T0_18 = type <4 x i64>
65%T1_18 = type <4 x i1>
66define void @func_blend18(%T0_18* %loadaddr, %T0_18* %loadaddr2,
67                           %T1_18* %blend, %T0_18* %storeaddr) {
68; CHECK-LABEL: func_blend18:
69; CHECK:       @ %bb.0:
70; CHECK-NEXT:    .save {r4, r5, r6, r7, r11, lr}
71; CHECK-NEXT:    push {r4, r5, r6, r7, r11, lr}
72; CHECK-NEXT:    vld1.64 {d22, d23}, [r0:128]!
73; CHECK-NEXT:    vld1.64 {d18, d19}, [r1:128]!
74; CHECK-NEXT:    vld1.64 {d16, d17}, [r1:128]
75; CHECK-NEXT:    mov r1, #0
76; CHECK-NEXT:    vld1.64 {d20, d21}, [r0:128]
77; CHECK-NEXT:    vmov.32 r12, d16[0]
78; CHECK-NEXT:    vmov.32 r2, d20[0]
79; CHECK-NEXT:    vmov.32 lr, d16[1]
80; CHECK-NEXT:    vmov.32 r0, d20[1]
81; CHECK-NEXT:    vmov.32 r7, d18[0]
82; CHECK-NEXT:    vmov.32 r5, d22[0]
83; CHECK-NEXT:    vmov.32 r4, d22[1]
84; CHECK-NEXT:    vmov.32 r6, d17[0]
85; CHECK-NEXT:    subs r2, r2, r12
86; CHECK-NEXT:    vmov.32 r2, d18[1]
87; CHECK-NEXT:    sbcs r0, r0, lr
88; CHECK-NEXT:    mov r0, #0
89; CHECK-NEXT:    movlt r0, #1
90; CHECK-NEXT:    cmp r0, #0
91; CHECK-NEXT:    mvnne r0, #0
92; CHECK-NEXT:    subs r7, r5, r7
93; CHECK-NEXT:    vmov.32 r7, d21[0]
94; CHECK-NEXT:    vmov.32 r5, d17[1]
95; CHECK-NEXT:    sbcs r2, r4, r2
96; CHECK-NEXT:    vmov.32 r4, d21[1]
97; CHECK-NEXT:    mov r2, #0
98; CHECK-NEXT:    movlt r2, #1
99; CHECK-NEXT:    cmp r2, #0
100; CHECK-NEXT:    mvnne r2, #0
101; CHECK-NEXT:    subs r7, r7, r6
102; CHECK-NEXT:    vmov.32 r6, d23[0]
103; CHECK-NEXT:    vmov.32 r7, d19[0]
104; CHECK-NEXT:    sbcs r5, r4, r5
105; CHECK-NEXT:    mov r4, #0
106; CHECK-NEXT:    movlt r4, #1
107; CHECK-NEXT:    vmov.32 r5, d19[1]
108; CHECK-NEXT:    subs r7, r6, r7
109; CHECK-NEXT:    vmov.32 r7, d23[1]
110; CHECK-NEXT:    sbcs r7, r7, r5
111; CHECK-NEXT:    movlt r1, #1
112; CHECK-NEXT:    cmp r1, #0
113; CHECK-NEXT:    mvnne r1, #0
114; CHECK-NEXT:    cmp r4, #0
115; CHECK-NEXT:    vdup.32 d25, r1
116; CHECK-NEXT:    mvnne r4, #0
117; CHECK-NEXT:    vdup.32 d24, r2
118; CHECK-NEXT:    vdup.32 d27, r4
119; CHECK-NEXT:    vbsl q12, q11, q9
120; CHECK-NEXT:    vdup.32 d26, r0
121; CHECK-NEXT:    vbsl q13, q10, q8
122; CHECK-NEXT:    vst1.64 {d24, d25}, [r3:128]!
123; CHECK-NEXT:    vst1.64 {d26, d27}, [r3:128]
124; CHECK-NEXT:    pop {r4, r5, r6, r7, r11, lr}
125; CHECK-NEXT:    mov pc, lr
126  %v0 = load %T0_18, %T0_18* %loadaddr
127  %v1 = load %T0_18, %T0_18* %loadaddr2
128  %c = icmp slt %T0_18 %v0, %v1
129; COST: func_blend18
130; COST: cost of 19 {{.*}} select
131  %r = select %T1_18 %c, %T0_18 %v0, %T0_18 %v1
132  store %T0_18 %r, %T0_18* %storeaddr
133  ret void
134}
135%T0_19 = type <8 x i64>
136%T1_19 = type <8 x i1>
137define void @func_blend19(%T0_19* %loadaddr, %T0_19* %loadaddr2,
138                           %T1_19* %blend, %T0_19* %storeaddr) {
139; CHECK-LABEL: func_blend19:
140; CHECK:       @ %bb.0:
141; CHECK-NEXT:    .save {r4, r5, r6, lr}
142; CHECK-NEXT:    push {r4, r5, r6, lr}
143; CHECK-NEXT:    mov r12, r1
144; CHECK-NEXT:    mov r2, r0
145; CHECK-NEXT:    vld1.64 {d24, d25}, [r12:128]!
146; CHECK-NEXT:    mov r6, #0
147; CHECK-NEXT:    mov lr, #0
148; CHECK-NEXT:    vld1.64 {d28, d29}, [r2:128]!
149; CHECK-NEXT:    vld1.64 {d16, d17}, [r12:128]
150; CHECK-NEXT:    vld1.64 {d18, d19}, [r2:128]
151; CHECK-NEXT:    add r2, r1, #32
152; CHECK-NEXT:    add r1, r1, #48
153; CHECK-NEXT:    vld1.64 {d20, d21}, [r2:128]
154; CHECK-NEXT:    add r2, r0, #32
155; CHECK-NEXT:    add r0, r0, #48
156; CHECK-NEXT:    vld1.64 {d30, d31}, [r2:128]
157; CHECK-NEXT:    vmov.32 r4, d16[0]
158; CHECK-NEXT:    vmov.32 r2, d18[0]
159; CHECK-NEXT:    vmov.32 r12, d16[1]
160; CHECK-NEXT:    vmov.32 r5, d18[1]
161; CHECK-NEXT:    vld1.64 {d22, d23}, [r1:128]
162; CHECK-NEXT:    vmov.32 r1, d21[0]
163; CHECK-NEXT:    vld1.64 {d26, d27}, [r0:128]
164; CHECK-NEXT:    vmov.32 r0, d21[1]
165; CHECK-NEXT:    subs r2, r2, r4
166; CHECK-NEXT:    vmov.32 r4, d31[1]
167; CHECK-NEXT:    vmov.32 r2, d31[0]
168; CHECK-NEXT:    sbcs r5, r5, r12
169; CHECK-NEXT:    mov r12, #0
170; CHECK-NEXT:    movlt r12, #1
171; CHECK-NEXT:    cmp r12, #0
172; CHECK-NEXT:    mvnne r12, #0
173; CHECK-NEXT:    vmov.32 r5, d25[0]
174; CHECK-NEXT:    subs r1, r2, r1
175; CHECK-NEXT:    mov r2, #0
176; CHECK-NEXT:    sbcs r0, r4, r0
177; CHECK-NEXT:    vmov.32 r1, d29[0]
178; CHECK-NEXT:    vmov.32 r0, d25[1]
179; CHECK-NEXT:    movlt r2, #1
180; CHECK-NEXT:    vmov.32 r4, d29[1]
181; CHECK-NEXT:    cmp r2, #0
182; CHECK-NEXT:    mvnne r2, #0
183; CHECK-NEXT:    vdup.32 d5, r2
184; CHECK-NEXT:    subs r1, r1, r5
185; CHECK-NEXT:    vmov.32 r5, d24[1]
186; CHECK-NEXT:    vmov.32 r1, d24[0]
187; CHECK-NEXT:    sbcs r0, r4, r0
188; CHECK-NEXT:    vmov.32 r4, d28[0]
189; CHECK-NEXT:    mov r0, #0
190; CHECK-NEXT:    movlt r0, #1
191; CHECK-NEXT:    cmp r0, #0
192; CHECK-NEXT:    mvnne r0, #0
193; CHECK-NEXT:    vdup.32 d1, r0
194; CHECK-NEXT:    vmov.32 r0, d19[0]
195; CHECK-NEXT:    subs r1, r4, r1
196; CHECK-NEXT:    vmov.32 r4, d17[0]
197; CHECK-NEXT:    vmov.32 r1, d28[1]
198; CHECK-NEXT:    sbcs r1, r1, r5
199; CHECK-NEXT:    vmov.32 r5, d17[1]
200; CHECK-NEXT:    mov r1, #0
201; CHECK-NEXT:    movlt r1, #1
202; CHECK-NEXT:    cmp r1, #0
203; CHECK-NEXT:    mvnne r1, #0
204; CHECK-NEXT:    subs r0, r0, r4
205; CHECK-NEXT:    vmov.32 r0, d19[1]
206; CHECK-NEXT:    vmov.32 r4, d22[0]
207; CHECK-NEXT:    vdup.32 d0, r1
208; CHECK-NEXT:    vmov.32 r1, d22[1]
209; CHECK-NEXT:    vbsl q0, q14, q12
210; CHECK-NEXT:    sbcs r0, r0, r5
211; CHECK-NEXT:    vmov.32 r5, d26[0]
212; CHECK-NEXT:    mov r0, #0
213; CHECK-NEXT:    movlt r0, #1
214; CHECK-NEXT:    subs r4, r5, r4
215; CHECK-NEXT:    vmov.32 r5, d20[0]
216; CHECK-NEXT:    vmov.32 r4, d26[1]
217; CHECK-NEXT:    sbcs r1, r4, r1
218; CHECK-NEXT:    vmov.32 r4, d30[0]
219; CHECK-NEXT:    mov r1, #0
220; CHECK-NEXT:    movlt r1, #1
221; CHECK-NEXT:    subs r4, r4, r5
222; CHECK-NEXT:    vmov.32 r5, d30[1]
223; CHECK-NEXT:    vmov.32 r4, d20[1]
224; CHECK-NEXT:    sbcs r4, r5, r4
225; CHECK-NEXT:    vmov.32 r5, d27[0]
226; CHECK-NEXT:    vmov.32 r4, d23[0]
227; CHECK-NEXT:    movlt r6, #1
228; CHECK-NEXT:    subs r4, r5, r4
229; CHECK-NEXT:    vmov.32 r5, d27[1]
230; CHECK-NEXT:    vmov.32 r4, d23[1]
231; CHECK-NEXT:    sbcs r4, r5, r4
232; CHECK-NEXT:    movlt lr, #1
233; CHECK-NEXT:    cmp lr, #0
234; CHECK-NEXT:    mvnne lr, #0
235; CHECK-NEXT:    cmp r6, #0
236; CHECK-NEXT:    mvnne r6, #0
237; CHECK-NEXT:    cmp r1, #0
238; CHECK-NEXT:    mvnne r1, #0
239; CHECK-NEXT:    cmp r0, #0
240; CHECK-NEXT:    vdup.32 d4, r6
241; CHECK-NEXT:    mvnne r0, #0
242; CHECK-NEXT:    vdup.32 d3, lr
243; CHECK-NEXT:    vbsl q2, q15, q10
244; CHECK-NEXT:    vdup.32 d21, r0
245; CHECK-NEXT:    add r0, r3, #32
246; CHECK-NEXT:    vdup.32 d2, r1
247; CHECK-NEXT:    vdup.32 d20, r12
248; CHECK-NEXT:    vbsl q1, q13, q11
249; CHECK-NEXT:    vst1.64 {d4, d5}, [r0:128]
250; CHECK-NEXT:    add r0, r3, #48
251; CHECK-NEXT:    vbsl q10, q9, q8
252; CHECK-NEXT:    vst1.64 {d0, d1}, [r3:128]!
253; CHECK-NEXT:    vst1.64 {d2, d3}, [r0:128]
254; CHECK-NEXT:    vst1.64 {d20, d21}, [r3:128]
255; CHECK-NEXT:    pop {r4, r5, r6, lr}
256; CHECK-NEXT:    mov pc, lr
257  %v0 = load %T0_19, %T0_19* %loadaddr
258  %v1 = load %T0_19, %T0_19* %loadaddr2
259  %c = icmp slt %T0_19 %v0, %v1
260; COST: func_blend19
261; COST: cost of 50 {{.*}} select
262  %r = select %T1_19 %c, %T0_19 %v0, %T0_19 %v1
263  store %T0_19 %r, %T0_19* %storeaddr
264  ret void
265}
266%T0_20 = type <16 x i64>
267%T1_20 = type <16 x i1>
268define void @func_blend20(%T0_20* %loadaddr, %T0_20* %loadaddr2,
269                           %T1_20* %blend, %T0_20* %storeaddr) {
270; CHECK-LABEL: func_blend20:
271; CHECK:       @ %bb.0:
272; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
273; CHECK-NEXT:    push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
274; CHECK-NEXT:    .pad #4
275; CHECK-NEXT:    sub sp, sp, #4
276; CHECK-NEXT:    .vsave {d8, d9, d10, d11}
277; CHECK-NEXT:    vpush {d8, d9, d10, d11}
278; CHECK-NEXT:    .pad #8
279; CHECK-NEXT:    sub sp, sp, #8
280; CHECK-NEXT:    add r9, r1, #64
281; CHECK-NEXT:    mov r2, #32
282; CHECK-NEXT:    add r8, r0, #64
283; CHECK-NEXT:    vld1.64 {d18, d19}, [r9:128], r2
284; CHECK-NEXT:    mov r10, #0
285; CHECK-NEXT:    vld1.64 {d22, d23}, [r8:128], r2
286; CHECK-NEXT:    vmov.32 r2, d19[0]
287; CHECK-NEXT:    str r3, [sp, #4] @ 4-byte Spill
288; CHECK-NEXT:    vmov.32 r7, d23[0]
289; CHECK-NEXT:    mov r3, #0
290; CHECK-NEXT:    vmov.32 r5, d19[1]
291; CHECK-NEXT:    vmov.32 r6, d23[1]
292; CHECK-NEXT:    vld1.64 {d2, d3}, [r9:128]!
293; CHECK-NEXT:    vmov.32 r12, d2[0]
294; CHECK-NEXT:    subs r2, r7, r2
295; CHECK-NEXT:    mov r7, r1
296; CHECK-NEXT:    vld1.64 {d20, d21}, [r7:128]!
297; CHECK-NEXT:    sbcs r2, r6, r5
298; CHECK-NEXT:    vmov.32 r5, d18[0]
299; CHECK-NEXT:    mov r2, #0
300; CHECK-NEXT:    vmov.32 r6, d22[0]
301; CHECK-NEXT:    movlt r2, #1
302; CHECK-NEXT:    cmp r2, #0
303; CHECK-NEXT:    vld1.64 {d0, d1}, [r7:128]
304; CHECK-NEXT:    mvnne r2, #0
305; CHECK-NEXT:    vdup.32 d17, r2
306; CHECK-NEXT:    mov r2, r0
307; CHECK-NEXT:    subs r5, r6, r5
308; CHECK-NEXT:    vmov.32 r6, d22[1]
309; CHECK-NEXT:    vmov.32 r5, d18[1]
310; CHECK-NEXT:    sbcs r5, r6, r5
311; CHECK-NEXT:    mov r5, #0
312; CHECK-NEXT:    movlt r5, #1
313; CHECK-NEXT:    cmp r5, #0
314; CHECK-NEXT:    mvnne r5, #0
315; CHECK-NEXT:    vdup.32 d16, r5
316; CHECK-NEXT:    vbsl q8, q11, q9
317; CHECK-NEXT:    vld1.64 {d22, d23}, [r2:128]!
318; CHECK-NEXT:    vmov.32 r5, d21[0]
319; CHECK-NEXT:    vmov.32 r6, d23[0]
320; CHECK-NEXT:    vld1.64 {d30, d31}, [r2:128]
321; CHECK-NEXT:    vmov.32 r2, d1[0]
322; CHECK-NEXT:    vmov.32 r7, d30[0]
323; CHECK-NEXT:    subs r5, r6, r5
324; CHECK-NEXT:    vmov.32 r6, d23[1]
325; CHECK-NEXT:    vmov.32 r5, d21[1]
326; CHECK-NEXT:    sbcs r5, r6, r5
327; CHECK-NEXT:    vmov.32 r6, d22[0]
328; CHECK-NEXT:    mov r5, #0
329; CHECK-NEXT:    movlt r5, #1
330; CHECK-NEXT:    cmp r5, #0
331; CHECK-NEXT:    mvnne r5, #0
332; CHECK-NEXT:    vdup.32 d19, r5
333; CHECK-NEXT:    vmov.32 r5, d20[0]
334; CHECK-NEXT:    subs r5, r6, r5
335; CHECK-NEXT:    vmov.32 r6, d22[1]
336; CHECK-NEXT:    vmov.32 r5, d20[1]
337; CHECK-NEXT:    sbcs r5, r6, r5
338; CHECK-NEXT:    mov r5, #0
339; CHECK-NEXT:    movlt r5, #1
340; CHECK-NEXT:    cmp r5, #0
341; CHECK-NEXT:    mvnne r5, #0
342; CHECK-NEXT:    vdup.32 d18, r5
343; CHECK-NEXT:    add r5, r0, #32
344; CHECK-NEXT:    vbsl q9, q11, q10
345; CHECK-NEXT:    vld1.64 {d22, d23}, [r5:128]
346; CHECK-NEXT:    add r5, r1, #32
347; CHECK-NEXT:    vld1.64 {d24, d25}, [r5:128]
348; CHECK-NEXT:    vmov.32 r5, d24[0]
349; CHECK-NEXT:    vmov.32 r6, d22[0]
350; CHECK-NEXT:    vmov.32 r4, d23[0]
351; CHECK-NEXT:    vld1.64 {d20, d21}, [r8:128]!
352; CHECK-NEXT:    vmov.32 r11, d21[0]
353; CHECK-NEXT:    subs r5, r6, r5
354; CHECK-NEXT:    vmov.32 r6, d22[1]
355; CHECK-NEXT:    vmov.32 r5, d24[1]
356; CHECK-NEXT:    sbcs r5, r6, r5
357; CHECK-NEXT:    vmov.32 r6, d25[0]
358; CHECK-NEXT:    movlt r10, #1
359; CHECK-NEXT:    cmp r10, #0
360; CHECK-NEXT:    mvnne r10, #0
361; CHECK-NEXT:    subs r4, r4, r6
362; CHECK-NEXT:    vmov.32 r6, d23[1]
363; CHECK-NEXT:    vmov.32 r4, d25[1]
364; CHECK-NEXT:    sbcs r4, r6, r4
365; CHECK-NEXT:    mov r6, #0
366; CHECK-NEXT:    vmov.32 r4, d31[0]
367; CHECK-NEXT:    movlt r6, #1
368; CHECK-NEXT:    cmp r6, #0
369; CHECK-NEXT:    mvnne r6, #0
370; CHECK-NEXT:    subs r2, r4, r2
371; CHECK-NEXT:    vmov.32 r4, d31[1]
372; CHECK-NEXT:    vmov.32 r2, d1[1]
373; CHECK-NEXT:    sbcs r2, r4, r2
374; CHECK-NEXT:    mov r2, #0
375; CHECK-NEXT:    movlt r2, #1
376; CHECK-NEXT:    cmp r2, #0
377; CHECK-NEXT:    mvnne r2, #0
378; CHECK-NEXT:    vdup.32 d27, r2
379; CHECK-NEXT:    add r2, r0, #48
380; CHECK-NEXT:    vld1.64 {d4, d5}, [r2:128]
381; CHECK-NEXT:    add r2, r1, #48
382; CHECK-NEXT:    add r0, r0, #80
383; CHECK-NEXT:    add r1, r1, #80
384; CHECK-NEXT:    vld1.64 {d6, d7}, [r2:128]
385; CHECK-NEXT:    vmov.32 r2, d7[0]
386; CHECK-NEXT:    vmov.32 r4, d5[0]
387; CHECK-NEXT:    vmov.32 r5, d4[0]
388; CHECK-NEXT:    vld1.64 {d8, d9}, [r0:128]
389; CHECK-NEXT:    subs r2, r4, r2
390; CHECK-NEXT:    vmov.32 r4, d5[1]
391; CHECK-NEXT:    vmov.32 r2, d7[1]
392; CHECK-NEXT:    sbcs r2, r4, r2
393; CHECK-NEXT:    vmov.32 r4, d0[0]
394; CHECK-NEXT:    mov r2, #0
395; CHECK-NEXT:    movlt r2, #1
396; CHECK-NEXT:    cmp r2, #0
397; CHECK-NEXT:    mvnne r2, #0
398; CHECK-NEXT:    vdup.32 d29, r2
399; CHECK-NEXT:    vmov.32 r2, d6[1]
400; CHECK-NEXT:    subs r4, r7, r4
401; CHECK-NEXT:    vmov.32 r7, d30[1]
402; CHECK-NEXT:    vmov.32 r4, d0[1]
403; CHECK-NEXT:    sbcs r4, r7, r4
404; CHECK-NEXT:    vmov.32 r7, d4[1]
405; CHECK-NEXT:    mov r4, #0
406; CHECK-NEXT:    movlt r4, #1
407; CHECK-NEXT:    cmp r4, #0
408; CHECK-NEXT:    mvnne r4, #0
409; CHECK-NEXT:    vdup.32 d26, r4
410; CHECK-NEXT:    vmov.32 r4, d6[0]
411; CHECK-NEXT:    vbsl q13, q15, q0
412; CHECK-NEXT:    vld1.64 {d0, d1}, [r9:128]
413; CHECK-NEXT:    vdup.32 d31, r6
414; CHECK-NEXT:    vmov.32 r9, d3[0]
415; CHECK-NEXT:    vdup.32 d30, r10
416; CHECK-NEXT:    vmov.32 r10, d21[1]
417; CHECK-NEXT:    vbsl q15, q11, q12
418; CHECK-NEXT:    subs r4, r5, r4
419; CHECK-NEXT:    sbcs r2, r7, r2
420; CHECK-NEXT:    vmov.32 r4, d0[1]
421; CHECK-NEXT:    mov r2, #0
422; CHECK-NEXT:    movlt r2, #1
423; CHECK-NEXT:    cmp r2, #0
424; CHECK-NEXT:    mvnne r2, #0
425; CHECK-NEXT:    vdup.32 d28, r2
426; CHECK-NEXT:    vbsl q14, q2, q3
427; CHECK-NEXT:    vld1.64 {d4, d5}, [r8:128]
428; CHECK-NEXT:    vmov.32 r2, d0[0]
429; CHECK-NEXT:    vmov.32 r6, d4[0]
430; CHECK-NEXT:    vmov.32 r5, d4[1]
431; CHECK-NEXT:    vld1.64 {d6, d7}, [r1:128]
432; CHECK-NEXT:    vmov.32 r7, d7[0]
433; CHECK-NEXT:    vmov.32 r1, d7[1]
434; CHECK-NEXT:    vmov.32 lr, d5[0]
435; CHECK-NEXT:    vmov.32 r8, d3[1]
436; CHECK-NEXT:    subs r0, r6, r2
437; CHECK-NEXT:    vmov.32 r2, d9[1]
438; CHECK-NEXT:    sbcs r0, r5, r4
439; CHECK-NEXT:    vmov.32 r4, d9[0]
440; CHECK-NEXT:    movlt r3, #1
441; CHECK-NEXT:    cmp r3, #0
442; CHECK-NEXT:    mvnne r3, #0
443; CHECK-NEXT:    vmov.32 r6, d8[1]
444; CHECK-NEXT:    mov r5, #0
445; CHECK-NEXT:    vmov.32 r0, d5[1]
446; CHECK-NEXT:    subs r4, r4, r7
447; CHECK-NEXT:    vmov.32 r7, d2[1]
448; CHECK-NEXT:    sbcs r1, r2, r1
449; CHECK-NEXT:    vmov.32 r2, d8[0]
450; CHECK-NEXT:    vmov.32 r1, d6[0]
451; CHECK-NEXT:    movlt r5, #1
452; CHECK-NEXT:    vmov.32 r4, d6[1]
453; CHECK-NEXT:    cmp r5, #0
454; CHECK-NEXT:    mvnne r5, #0
455; CHECK-NEXT:    vdup.32 d11, r5
456; CHECK-NEXT:    vmov.32 r5, d20[0]
457; CHECK-NEXT:    subs r1, r2, r1
458; CHECK-NEXT:    vmov.32 r2, d1[0]
459; CHECK-NEXT:    sbcs r1, r6, r4
460; CHECK-NEXT:    vmov.32 r6, d1[1]
461; CHECK-NEXT:    vmov.32 r4, d20[1]
462; CHECK-NEXT:    mov r1, #0
463; CHECK-NEXT:    movlt r1, #1
464; CHECK-NEXT:    cmp r1, #0
465; CHECK-NEXT:    mvnne r1, #0
466; CHECK-NEXT:    vdup.32 d10, r1
467; CHECK-NEXT:    mov r1, #0
468; CHECK-NEXT:    vbsl q5, q4, q3
469; CHECK-NEXT:    subs r2, lr, r2
470; CHECK-NEXT:    sbcs r0, r0, r6
471; CHECK-NEXT:    mov r0, #0
472; CHECK-NEXT:    movlt r0, #1
473; CHECK-NEXT:    subs r2, r5, r12
474; CHECK-NEXT:    sbcs r2, r4, r7
475; CHECK-NEXT:    mov r2, #0
476; CHECK-NEXT:    movlt r2, #1
477; CHECK-NEXT:    subs r7, r11, r9
478; CHECK-NEXT:    sbcs r7, r10, r8
479; CHECK-NEXT:    movlt r1, #1
480; CHECK-NEXT:    cmp r1, #0
481; CHECK-NEXT:    mvnne r1, #0
482; CHECK-NEXT:    cmp r2, #0
483; CHECK-NEXT:    vdup.32 d23, r1
484; CHECK-NEXT:    mvnne r2, #0
485; CHECK-NEXT:    cmp r0, #0
486; CHECK-NEXT:    ldr r1, [sp, #4] @ 4-byte Reload
487; CHECK-NEXT:    mvnne r0, #0
488; CHECK-NEXT:    vdup.32 d22, r2
489; CHECK-NEXT:    vdup.32 d25, r0
490; CHECK-NEXT:    add r0, r1, #80
491; CHECK-NEXT:    vbsl q11, q10, q1
492; CHECK-NEXT:    vdup.32 d24, r3
493; CHECK-NEXT:    vst1.64 {d10, d11}, [r0:128]
494; CHECK-NEXT:    add r0, r1, #32
495; CHECK-NEXT:    vbsl q12, q2, q0
496; CHECK-NEXT:    vst1.64 {d30, d31}, [r0:128]
497; CHECK-NEXT:    add r0, r1, #48
498; CHECK-NEXT:    vst1.64 {d28, d29}, [r0:128]
499; CHECK-NEXT:    add r0, r1, #64
500; CHECK-NEXT:    vst1.64 {d18, d19}, [r1:128]!
501; CHECK-NEXT:    vst1.64 {d26, d27}, [r1:128]
502; CHECK-NEXT:    mov r1, #32
503; CHECK-NEXT:    vst1.64 {d16, d17}, [r0:128], r1
504; CHECK-NEXT:    vst1.64 {d22, d23}, [r0:128]!
505; CHECK-NEXT:    vst1.64 {d24, d25}, [r0:128]
506; CHECK-NEXT:    add sp, sp, #8
507; CHECK-NEXT:    vpop {d8, d9, d10, d11}
508; CHECK-NEXT:    add sp, sp, #4
509; CHECK-NEXT:    pop {r4, r5, r6, r7, r8, r9, r10, r11, lr}
510; CHECK-NEXT:    mov pc, lr
511  %v0 = load %T0_20, %T0_20* %loadaddr
512  %v1 = load %T0_20, %T0_20* %loadaddr2
513  %c = icmp slt %T0_20 %v0, %v1
514; COST: func_blend20
515; COST: cost of 100 {{.*}} select
516  %r = select %T1_20 %c, %T0_20 %v0, %T0_20 %v1
517  store %T0_20 %r, %T0_20* %storeaddr
518  ret void
519}
520