1; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
2
3define arm_apcscc <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
4;CHECK: test_vrev64D8:
5;CHECK: vrev64.8
6	%tmp1 = load <8 x i8>* %A
7	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
8	ret <8 x i8> %tmp2
9}
10
11define arm_apcscc <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
12;CHECK: test_vrev64D16:
13;CHECK: vrev64.16
14	%tmp1 = load <4 x i16>* %A
15	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
16	ret <4 x i16> %tmp2
17}
18
19define arm_apcscc <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
20;CHECK: test_vrev64D32:
21;CHECK: vrev64.32
22	%tmp1 = load <2 x i32>* %A
23	%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
24	ret <2 x i32> %tmp2
25}
26
27define arm_apcscc <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
28;CHECK: test_vrev64Df:
29;CHECK: vrev64.32
30	%tmp1 = load <2 x float>* %A
31	%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
32	ret <2 x float> %tmp2
33}
34
35define arm_apcscc <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
36;CHECK: test_vrev64Q8:
37;CHECK: vrev64.8
38	%tmp1 = load <16 x i8>* %A
39	%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
40	ret <16 x i8> %tmp2
41}
42
43define arm_apcscc <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
44;CHECK: test_vrev64Q16:
45;CHECK: vrev64.16
46	%tmp1 = load <8 x i16>* %A
47	%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
48	ret <8 x i16> %tmp2
49}
50
51define arm_apcscc <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
52;CHECK: test_vrev64Q32:
53;CHECK: vrev64.32
54	%tmp1 = load <4 x i32>* %A
55	%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
56	ret <4 x i32> %tmp2
57}
58
59define arm_apcscc <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
60;CHECK: test_vrev64Qf:
61;CHECK: vrev64.32
62	%tmp1 = load <4 x float>* %A
63	%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
64	ret <4 x float> %tmp2
65}
66
67define arm_apcscc <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
68;CHECK: test_vrev32D8:
69;CHECK: vrev32.8
70	%tmp1 = load <8 x i8>* %A
71	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
72	ret <8 x i8> %tmp2
73}
74
75define arm_apcscc <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
76;CHECK: test_vrev32D16:
77;CHECK: vrev32.16
78	%tmp1 = load <4 x i16>* %A
79	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
80	ret <4 x i16> %tmp2
81}
82
83define arm_apcscc <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
84;CHECK: test_vrev32Q8:
85;CHECK: vrev32.8
86	%tmp1 = load <16 x i8>* %A
87	%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
88	ret <16 x i8> %tmp2
89}
90
91define arm_apcscc <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
92;CHECK: test_vrev32Q16:
93;CHECK: vrev32.16
94	%tmp1 = load <8 x i16>* %A
95	%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
96	ret <8 x i16> %tmp2
97}
98
99define arm_apcscc <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
100;CHECK: test_vrev16D8:
101;CHECK: vrev16.8
102	%tmp1 = load <8 x i8>* %A
103	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
104	ret <8 x i8> %tmp2
105}
106
107define arm_apcscc <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
108;CHECK: test_vrev16Q8:
109;CHECK: vrev16.8
110	%tmp1 = load <16 x i8>* %A
111	%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
112	ret <16 x i8> %tmp2
113}
114