1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=arm-eabi -mattr=+neon,+fullfp16 %s -o - | FileCheck --check-prefixes=CHECK,CHECK-LE %s 3; RUN: llc -mtriple=armeb-eabi -mattr=+neon,+fullfp16 %s -o - | FileCheck --check-prefixes=CHECK,CHECK-BE %s 4 5define arm_aapcs_vfpcc <8 x i8> @v_movi8() nounwind { 6; CHECK-LABEL: v_movi8: 7; CHECK: @ %bb.0: 8; CHECK-NEXT: vmov.i8 d0, #0x8 9; CHECK-NEXT: mov pc, lr 10 ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > 11} 12 13define arm_aapcs_vfpcc <4 x i16> @v_movi16a() nounwind { 14; CHECK-LABEL: v_movi16a: 15; CHECK: @ %bb.0: 16; CHECK-NEXT: vmov.i16 d0, #0x10 17; CHECK-NEXT: mov pc, lr 18 ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 > 19} 20 21define arm_aapcs_vfpcc <4 x i16> @v_movi16b() nounwind { 22; CHECK-LABEL: v_movi16b: 23; CHECK: @ %bb.0: 24; CHECK-NEXT: vmov.i16 d0, #0x1000 25; CHECK-NEXT: mov pc, lr 26 ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 > 27} 28 29define arm_aapcs_vfpcc <4 x i16> @v_mvni16a() nounwind { 30; CHECK-LABEL: v_mvni16a: 31; CHECK: @ %bb.0: 32; CHECK-NEXT: vmvn.i16 d0, #0x10 33; CHECK-NEXT: mov pc, lr 34 ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 > 35} 36 37define arm_aapcs_vfpcc <4 x i16> @v_mvni16b() nounwind { 38; CHECK-LABEL: v_mvni16b: 39; CHECK: @ %bb.0: 40; CHECK-NEXT: vmvn.i16 d0, #0x1000 41; CHECK-NEXT: mov pc, lr 42 ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 > 43} 44 45define arm_aapcs_vfpcc <2 x i32> @v_movi32a() nounwind { 46; CHECK-LABEL: v_movi32a: 47; CHECK: @ %bb.0: 48; CHECK-NEXT: vmov.i32 d0, #0x20 49; CHECK-NEXT: mov pc, lr 50 ret <2 x i32> < i32 32, i32 32 > 51} 52 53define arm_aapcs_vfpcc <2 x i32> @v_movi32b() nounwind { 54; CHECK-LABEL: v_movi32b: 55; CHECK: @ %bb.0: 56; CHECK-NEXT: vmov.i32 d0, #0x2000 57; CHECK-NEXT: mov pc, lr 58 ret <2 x i32> < i32 8192, i32 8192 > 59} 60 61define arm_aapcs_vfpcc <2 x i32> @v_movi32c() nounwind { 62; CHECK-LABEL: v_movi32c: 63; CHECK: @ %bb.0: 64; CHECK-NEXT: vmov.i32 d0, #0x200000 65; CHECK-NEXT: mov pc, lr 66 ret <2 x i32> < i32 2097152, i32 2097152 > 67} 68 69define arm_aapcs_vfpcc <2 x i32> @v_movi32d() nounwind { 70; CHECK-LABEL: v_movi32d: 71; CHECK: @ %bb.0: 72; CHECK-NEXT: vmov.i32 d0, #0x20000000 73; CHECK-NEXT: mov pc, lr 74 ret <2 x i32> < i32 536870912, i32 536870912 > 75} 76 77define arm_aapcs_vfpcc <2 x i32> @v_movi32e() nounwind { 78; CHECK-LABEL: v_movi32e: 79; CHECK: @ %bb.0: 80; CHECK-NEXT: vmov.i32 d0, #0x20ff 81; CHECK-NEXT: mov pc, lr 82 ret <2 x i32> < i32 8447, i32 8447 > 83} 84 85define arm_aapcs_vfpcc <2 x i32> @v_movi32f() nounwind { 86; CHECK-LABEL: v_movi32f: 87; CHECK: @ %bb.0: 88; CHECK-NEXT: vmov.i32 d0, #0x20ffff 89; CHECK-NEXT: mov pc, lr 90 ret <2 x i32> < i32 2162687, i32 2162687 > 91} 92 93define arm_aapcs_vfpcc <2 x i32> @v_mvni32a() nounwind { 94; CHECK-LABEL: v_mvni32a: 95; CHECK: @ %bb.0: 96; CHECK-NEXT: vmvn.i32 d0, #0x20 97; CHECK-NEXT: mov pc, lr 98 ret <2 x i32> < i32 4294967263, i32 4294967263 > 99} 100 101define arm_aapcs_vfpcc <2 x i32> @v_mvni32b() nounwind { 102; CHECK-LABEL: v_mvni32b: 103; CHECK: @ %bb.0: 104; CHECK-NEXT: vmvn.i32 d0, #0x2000 105; CHECK-NEXT: mov pc, lr 106 ret <2 x i32> < i32 4294959103, i32 4294959103 > 107} 108 109define arm_aapcs_vfpcc <2 x i32> @v_mvni32c() nounwind { 110; CHECK-LABEL: v_mvni32c: 111; CHECK: @ %bb.0: 112; CHECK-NEXT: vmvn.i32 d0, #0x200000 113; CHECK-NEXT: mov pc, lr 114 ret <2 x i32> < i32 4292870143, i32 4292870143 > 115} 116 117define arm_aapcs_vfpcc <2 x i32> @v_mvni32d() nounwind { 118; CHECK-LABEL: v_mvni32d: 119; CHECK: @ %bb.0: 120; CHECK-NEXT: vmvn.i32 d0, #0x20000000 121; CHECK-NEXT: mov pc, lr 122 ret <2 x i32> < i32 3758096383, i32 3758096383 > 123} 124 125define arm_aapcs_vfpcc <2 x i32> @v_mvni32e() nounwind { 126; CHECK-LABEL: v_mvni32e: 127; CHECK: @ %bb.0: 128; CHECK-NEXT: vmvn.i32 d0, #0x20ff 129; CHECK-NEXT: mov pc, lr 130 ret <2 x i32> < i32 4294958848, i32 4294958848 > 131} 132 133define arm_aapcs_vfpcc <2 x i32> @v_mvni32f() nounwind { 134; CHECK-LABEL: v_mvni32f: 135; CHECK: @ %bb.0: 136; CHECK-NEXT: vmvn.i32 d0, #0x20ffff 137; CHECK-NEXT: mov pc, lr 138 ret <2 x i32> < i32 4292804608, i32 4292804608 > 139} 140 141define arm_aapcs_vfpcc <1 x i64> @v_movi64() nounwind { 142; CHECK-LABEL: v_movi64: 143; CHECK: @ %bb.0: 144; CHECK-NEXT: vmov.i64 d0, #0xff0000ff0000ffff 145; CHECK-NEXT: mov pc, lr 146 ret <1 x i64> < i64 18374687574888349695 > 147} 148 149define arm_aapcs_vfpcc <16 x i8> @v_movQi8() nounwind { 150; CHECK-LABEL: v_movQi8: 151; CHECK: @ %bb.0: 152; CHECK-NEXT: vmov.i8 q0, #0x8 153; CHECK-NEXT: mov pc, lr 154 ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > 155} 156 157define arm_aapcs_vfpcc <8 x i16> @v_movQi16a() nounwind { 158; CHECK-LABEL: v_movQi16a: 159; CHECK: @ %bb.0: 160; CHECK-NEXT: vmov.i16 q0, #0x10 161; CHECK-NEXT: mov pc, lr 162 ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 > 163} 164 165define arm_aapcs_vfpcc <8 x i16> @v_movQi16b() nounwind { 166; CHECK-LABEL: v_movQi16b: 167; CHECK: @ %bb.0: 168; CHECK-NEXT: vmov.i16 q0, #0x1000 169; CHECK-NEXT: mov pc, lr 170 ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 > 171} 172 173define arm_aapcs_vfpcc <4 x i32> @v_movQi32a() nounwind { 174; CHECK-LABEL: v_movQi32a: 175; CHECK: @ %bb.0: 176; CHECK-NEXT: vmov.i32 q0, #0x20 177; CHECK-NEXT: mov pc, lr 178 ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 > 179} 180 181define arm_aapcs_vfpcc <4 x i32> @v_movQi32b() nounwind { 182; CHECK-LABEL: v_movQi32b: 183; CHECK: @ %bb.0: 184; CHECK-NEXT: vmov.i32 q0, #0x2000 185; CHECK-NEXT: mov pc, lr 186 ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 > 187} 188 189define arm_aapcs_vfpcc <4 x i32> @v_movQi32c() nounwind { 190; CHECK-LABEL: v_movQi32c: 191; CHECK: @ %bb.0: 192; CHECK-NEXT: vmov.i32 q0, #0x200000 193; CHECK-NEXT: mov pc, lr 194 ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 > 195} 196 197define arm_aapcs_vfpcc <4 x i32> @v_movQi32d() nounwind { 198; CHECK-LABEL: v_movQi32d: 199; CHECK: @ %bb.0: 200; CHECK-NEXT: vmov.i32 q0, #0x20000000 201; CHECK-NEXT: mov pc, lr 202 ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 > 203} 204 205define arm_aapcs_vfpcc <4 x i32> @v_movQi32e() nounwind { 206; CHECK-LABEL: v_movQi32e: 207; CHECK: @ %bb.0: 208; CHECK-NEXT: vmov.i32 q0, #0x20ff 209; CHECK-NEXT: mov pc, lr 210 ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 > 211} 212 213define arm_aapcs_vfpcc <4 x i32> @v_movQi32f() nounwind { 214; CHECK-LABEL: v_movQi32f: 215; CHECK: @ %bb.0: 216; CHECK-NEXT: vmov.i32 q0, #0x20ffff 217; CHECK-NEXT: mov pc, lr 218 ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 > 219} 220 221define arm_aapcs_vfpcc <2 x i64> @v_movQi64() nounwind { 222; CHECK-LABEL: v_movQi64: 223; CHECK: @ %bb.0: 224; CHECK-NEXT: vmov.i64 q0, #0xff0000ff0000ffff 225; CHECK-NEXT: mov pc, lr 226 ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 > 227} 228 229; Check for correct assembler printing for immediate values. 230%struct.int8x8_t = type { <8 x i8> } 231define arm_aapcs_vfpcc void @vdupn128(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind { 232; CHECK-LABEL: vdupn128: 233; CHECK: @ %bb.0: @ %entry 234; CHECK-NEXT: vmov.i8 d16, #0x80 235; CHECK-NEXT: vstr d16, [r0] 236; CHECK-NEXT: mov pc, lr 237entry: 238 %0 = getelementptr inbounds %struct.int8x8_t, %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1] 239 store <8 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>, <8 x i8>* %0, align 8 240 ret void 241} 242 243define arm_aapcs_vfpcc void @vdupnneg75(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind { 244; CHECK-LABEL: vdupnneg75: 245; CHECK: @ %bb.0: @ %entry 246; CHECK-NEXT: vmov.i8 d16, #0xb5 247; CHECK-NEXT: vstr d16, [r0] 248; CHECK-NEXT: mov pc, lr 249entry: 250 %0 = getelementptr inbounds %struct.int8x8_t, %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1] 251 store <8 x i8> <i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75>, <8 x i8>* %0, align 8 252 ret void 253} 254 255define arm_aapcs_vfpcc <8 x i16> @vmovls8(<8 x i8>* %A) nounwind { 256; CHECK-LE-LABEL: vmovls8: 257; CHECK-LE: @ %bb.0: 258; CHECK-LE-NEXT: vld1.8 {d16}, [r0:64] 259; CHECK-LE-NEXT: vmovl.s8 q0, d16 260; CHECK-LE-NEXT: mov pc, lr 261; 262; CHECK-BE-LABEL: vmovls8: 263; CHECK-BE: @ %bb.0: 264; CHECK-BE-NEXT: vld1.8 {d16}, [r0:64] 265; CHECK-BE-NEXT: vmovl.s8 q8, d16 266; CHECK-BE-NEXT: vrev64.16 q0, q8 267; CHECK-BE-NEXT: mov pc, lr 268 %tmp1 = load <8 x i8>, <8 x i8>* %A 269 %tmp2 = sext <8 x i8> %tmp1 to <8 x i16> 270 ret <8 x i16> %tmp2 271} 272 273define arm_aapcs_vfpcc <4 x i32> @vmovls16(<4 x i16>* %A) nounwind { 274; CHECK-LE-LABEL: vmovls16: 275; CHECK-LE: @ %bb.0: 276; CHECK-LE-NEXT: vld1.16 {d16}, [r0:64] 277; CHECK-LE-NEXT: vmovl.s16 q0, d16 278; CHECK-LE-NEXT: mov pc, lr 279; 280; CHECK-BE-LABEL: vmovls16: 281; CHECK-BE: @ %bb.0: 282; CHECK-BE-NEXT: vld1.16 {d16}, [r0:64] 283; CHECK-BE-NEXT: vmovl.s16 q8, d16 284; CHECK-BE-NEXT: vrev64.32 q0, q8 285; CHECK-BE-NEXT: mov pc, lr 286 %tmp1 = load <4 x i16>, <4 x i16>* %A 287 %tmp2 = sext <4 x i16> %tmp1 to <4 x i32> 288 ret <4 x i32> %tmp2 289} 290 291define arm_aapcs_vfpcc <2 x i64> @vmovls32(<2 x i32>* %A) nounwind { 292; CHECK-LABEL: vmovls32: 293; CHECK: @ %bb.0: 294; CHECK-NEXT: vld1.32 {d16}, [r0:64] 295; CHECK-NEXT: vmovl.s32 q0, d16 296; CHECK-NEXT: mov pc, lr 297 %tmp1 = load <2 x i32>, <2 x i32>* %A 298 %tmp2 = sext <2 x i32> %tmp1 to <2 x i64> 299 ret <2 x i64> %tmp2 300} 301 302define arm_aapcs_vfpcc <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind { 303; CHECK-LE-LABEL: vmovlu8: 304; CHECK-LE: @ %bb.0: 305; CHECK-LE-NEXT: vld1.8 {d16}, [r0:64] 306; CHECK-LE-NEXT: vmovl.u8 q0, d16 307; CHECK-LE-NEXT: mov pc, lr 308; 309; CHECK-BE-LABEL: vmovlu8: 310; CHECK-BE: @ %bb.0: 311; CHECK-BE-NEXT: vld1.8 {d16}, [r0:64] 312; CHECK-BE-NEXT: vmovl.u8 q8, d16 313; CHECK-BE-NEXT: vrev64.16 q0, q8 314; CHECK-BE-NEXT: mov pc, lr 315 %tmp1 = load <8 x i8>, <8 x i8>* %A 316 %tmp2 = zext <8 x i8> %tmp1 to <8 x i16> 317 ret <8 x i16> %tmp2 318} 319 320define arm_aapcs_vfpcc <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind { 321; CHECK-LE-LABEL: vmovlu16: 322; CHECK-LE: @ %bb.0: 323; CHECK-LE-NEXT: vld1.16 {d16}, [r0:64] 324; CHECK-LE-NEXT: vmovl.u16 q0, d16 325; CHECK-LE-NEXT: mov pc, lr 326; 327; CHECK-BE-LABEL: vmovlu16: 328; CHECK-BE: @ %bb.0: 329; CHECK-BE-NEXT: vld1.16 {d16}, [r0:64] 330; CHECK-BE-NEXT: vmovl.u16 q8, d16 331; CHECK-BE-NEXT: vrev64.32 q0, q8 332; CHECK-BE-NEXT: mov pc, lr 333 %tmp1 = load <4 x i16>, <4 x i16>* %A 334 %tmp2 = zext <4 x i16> %tmp1 to <4 x i32> 335 ret <4 x i32> %tmp2 336} 337 338define arm_aapcs_vfpcc <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind { 339; CHECK-LABEL: vmovlu32: 340; CHECK: @ %bb.0: 341; CHECK-NEXT: vld1.32 {d16}, [r0:64] 342; CHECK-NEXT: vmovl.u32 q0, d16 343; CHECK-NEXT: mov pc, lr 344 %tmp1 = load <2 x i32>, <2 x i32>* %A 345 %tmp2 = zext <2 x i32> %tmp1 to <2 x i64> 346 ret <2 x i64> %tmp2 347} 348 349define arm_aapcs_vfpcc <8 x i8> @vmovni16(<8 x i16>* %A) nounwind { 350; CHECK-LE-LABEL: vmovni16: 351; CHECK-LE: @ %bb.0: 352; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0] 353; CHECK-LE-NEXT: vmovn.i16 d0, q8 354; CHECK-LE-NEXT: mov pc, lr 355; 356; CHECK-BE-LABEL: vmovni16: 357; CHECK-BE: @ %bb.0: 358; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0] 359; CHECK-BE-NEXT: vrev64.16 q8, q8 360; CHECK-BE-NEXT: vmovn.i16 d16, q8 361; CHECK-BE-NEXT: vrev64.8 d0, d16 362; CHECK-BE-NEXT: mov pc, lr 363 %tmp1 = load <8 x i16>, <8 x i16>* %A 364 %tmp2 = trunc <8 x i16> %tmp1 to <8 x i8> 365 ret <8 x i8> %tmp2 366} 367 368define arm_aapcs_vfpcc <4 x i16> @vmovni32(<4 x i32>* %A) nounwind { 369; CHECK-LE-LABEL: vmovni32: 370; CHECK-LE: @ %bb.0: 371; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0] 372; CHECK-LE-NEXT: vmovn.i32 d0, q8 373; CHECK-LE-NEXT: mov pc, lr 374; 375; CHECK-BE-LABEL: vmovni32: 376; CHECK-BE: @ %bb.0: 377; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0] 378; CHECK-BE-NEXT: vrev64.32 q8, q8 379; CHECK-BE-NEXT: vmovn.i32 d16, q8 380; CHECK-BE-NEXT: vrev64.16 d0, d16 381; CHECK-BE-NEXT: mov pc, lr 382 %tmp1 = load <4 x i32>, <4 x i32>* %A 383 %tmp2 = trunc <4 x i32> %tmp1 to <4 x i16> 384 ret <4 x i16> %tmp2 385} 386 387define arm_aapcs_vfpcc <2 x i32> @vmovni64(<2 x i64>* %A) nounwind { 388; CHECK-LE-LABEL: vmovni64: 389; CHECK-LE: @ %bb.0: 390; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0] 391; CHECK-LE-NEXT: vmovn.i64 d0, q8 392; CHECK-LE-NEXT: mov pc, lr 393; 394; CHECK-BE-LABEL: vmovni64: 395; CHECK-BE: @ %bb.0: 396; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0] 397; CHECK-BE-NEXT: vmovn.i64 d16, q8 398; CHECK-BE-NEXT: vrev64.32 d0, d16 399; CHECK-BE-NEXT: mov pc, lr 400 %tmp1 = load <2 x i64>, <2 x i64>* %A 401 %tmp2 = trunc <2 x i64> %tmp1 to <2 x i32> 402 ret <2 x i32> %tmp2 403} 404 405define arm_aapcs_vfpcc <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind { 406; CHECK-LE-LABEL: vqmovns16: 407; CHECK-LE: @ %bb.0: 408; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0] 409; CHECK-LE-NEXT: vqmovn.s16 d0, q8 410; CHECK-LE-NEXT: mov pc, lr 411; 412; CHECK-BE-LABEL: vqmovns16: 413; CHECK-BE: @ %bb.0: 414; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0] 415; CHECK-BE-NEXT: vrev64.16 q8, q8 416; CHECK-BE-NEXT: vqmovn.s16 d16, q8 417; CHECK-BE-NEXT: vrev64.8 d0, d16 418; CHECK-BE-NEXT: mov pc, lr 419 %tmp1 = load <8 x i16>, <8 x i16>* %A 420 %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %tmp1) 421 ret <8 x i8> %tmp2 422} 423 424define arm_aapcs_vfpcc <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind { 425; CHECK-LE-LABEL: vqmovns32: 426; CHECK-LE: @ %bb.0: 427; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0] 428; CHECK-LE-NEXT: vqmovn.s32 d0, q8 429; CHECK-LE-NEXT: mov pc, lr 430; 431; CHECK-BE-LABEL: vqmovns32: 432; CHECK-BE: @ %bb.0: 433; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0] 434; CHECK-BE-NEXT: vrev64.32 q8, q8 435; CHECK-BE-NEXT: vqmovn.s32 d16, q8 436; CHECK-BE-NEXT: vrev64.16 d0, d16 437; CHECK-BE-NEXT: mov pc, lr 438 %tmp1 = load <4 x i32>, <4 x i32>* %A 439 %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %tmp1) 440 ret <4 x i16> %tmp2 441} 442 443define arm_aapcs_vfpcc <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind { 444; CHECK-LE-LABEL: vqmovns64: 445; CHECK-LE: @ %bb.0: 446; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0] 447; CHECK-LE-NEXT: vqmovn.s64 d0, q8 448; CHECK-LE-NEXT: mov pc, lr 449; 450; CHECK-BE-LABEL: vqmovns64: 451; CHECK-BE: @ %bb.0: 452; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0] 453; CHECK-BE-NEXT: vqmovn.s64 d16, q8 454; CHECK-BE-NEXT: vrev64.32 d0, d16 455; CHECK-BE-NEXT: mov pc, lr 456 %tmp1 = load <2 x i64>, <2 x i64>* %A 457 %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1) 458 ret <2 x i32> %tmp2 459} 460 461define arm_aapcs_vfpcc <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind { 462; CHECK-LE-LABEL: vqmovnu16: 463; CHECK-LE: @ %bb.0: 464; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0] 465; CHECK-LE-NEXT: vqmovn.u16 d0, q8 466; CHECK-LE-NEXT: mov pc, lr 467; 468; CHECK-BE-LABEL: vqmovnu16: 469; CHECK-BE: @ %bb.0: 470; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0] 471; CHECK-BE-NEXT: vrev64.16 q8, q8 472; CHECK-BE-NEXT: vqmovn.u16 d16, q8 473; CHECK-BE-NEXT: vrev64.8 d0, d16 474; CHECK-BE-NEXT: mov pc, lr 475 %tmp1 = load <8 x i16>, <8 x i16>* %A 476 %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %tmp1) 477 ret <8 x i8> %tmp2 478} 479 480define arm_aapcs_vfpcc <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind { 481; CHECK-LE-LABEL: vqmovnu32: 482; CHECK-LE: @ %bb.0: 483; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0] 484; CHECK-LE-NEXT: vqmovn.u32 d0, q8 485; CHECK-LE-NEXT: mov pc, lr 486; 487; CHECK-BE-LABEL: vqmovnu32: 488; CHECK-BE: @ %bb.0: 489; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0] 490; CHECK-BE-NEXT: vrev64.32 q8, q8 491; CHECK-BE-NEXT: vqmovn.u32 d16, q8 492; CHECK-BE-NEXT: vrev64.16 d0, d16 493; CHECK-BE-NEXT: mov pc, lr 494 %tmp1 = load <4 x i32>, <4 x i32>* %A 495 %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %tmp1) 496 ret <4 x i16> %tmp2 497} 498 499define arm_aapcs_vfpcc <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind { 500; CHECK-LE-LABEL: vqmovnu64: 501; CHECK-LE: @ %bb.0: 502; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0] 503; CHECK-LE-NEXT: vqmovn.u64 d0, q8 504; CHECK-LE-NEXT: mov pc, lr 505; 506; CHECK-BE-LABEL: vqmovnu64: 507; CHECK-BE: @ %bb.0: 508; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0] 509; CHECK-BE-NEXT: vqmovn.u64 d16, q8 510; CHECK-BE-NEXT: vrev64.32 d0, d16 511; CHECK-BE-NEXT: mov pc, lr 512 %tmp1 = load <2 x i64>, <2 x i64>* %A 513 %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1) 514 ret <2 x i32> %tmp2 515} 516 517define arm_aapcs_vfpcc <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind { 518; CHECK-LE-LABEL: vqmovuns16: 519; CHECK-LE: @ %bb.0: 520; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0] 521; CHECK-LE-NEXT: vqmovun.s16 d0, q8 522; CHECK-LE-NEXT: mov pc, lr 523; 524; CHECK-BE-LABEL: vqmovuns16: 525; CHECK-BE: @ %bb.0: 526; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0] 527; CHECK-BE-NEXT: vrev64.16 q8, q8 528; CHECK-BE-NEXT: vqmovun.s16 d16, q8 529; CHECK-BE-NEXT: vrev64.8 d0, d16 530; CHECK-BE-NEXT: mov pc, lr 531 %tmp1 = load <8 x i16>, <8 x i16>* %A 532 %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %tmp1) 533 ret <8 x i8> %tmp2 534} 535 536define arm_aapcs_vfpcc <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind { 537; CHECK-LE-LABEL: vqmovuns32: 538; CHECK-LE: @ %bb.0: 539; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0] 540; CHECK-LE-NEXT: vqmovun.s32 d0, q8 541; CHECK-LE-NEXT: mov pc, lr 542; 543; CHECK-BE-LABEL: vqmovuns32: 544; CHECK-BE: @ %bb.0: 545; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0] 546; CHECK-BE-NEXT: vrev64.32 q8, q8 547; CHECK-BE-NEXT: vqmovun.s32 d16, q8 548; CHECK-BE-NEXT: vrev64.16 d0, d16 549; CHECK-BE-NEXT: mov pc, lr 550 %tmp1 = load <4 x i32>, <4 x i32>* %A 551 %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %tmp1) 552 ret <4 x i16> %tmp2 553} 554 555define arm_aapcs_vfpcc <2 x i32> @vqmovuns64(<2 x i64>* %A) nounwind { 556; CHECK-LE-LABEL: vqmovuns64: 557; CHECK-LE: @ %bb.0: 558; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0] 559; CHECK-LE-NEXT: vqmovun.s64 d0, q8 560; CHECK-LE-NEXT: mov pc, lr 561; 562; CHECK-BE-LABEL: vqmovuns64: 563; CHECK-BE: @ %bb.0: 564; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0] 565; CHECK-BE-NEXT: vqmovun.s64 d16, q8 566; CHECK-BE-NEXT: vrev64.32 d0, d16 567; CHECK-BE-NEXT: mov pc, lr 568 %tmp1 = load <2 x i64>, <2 x i64>* %A 569 %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1) 570 ret <2 x i32> %tmp2 571} 572 573declare <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16>) nounwind readnone 574declare <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32>) nounwind readnone 575declare <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64>) nounwind readnone 576 577declare <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16>) nounwind readnone 578declare <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32>) nounwind readnone 579declare <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64>) nounwind readnone 580 581declare <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16>) nounwind readnone 582declare <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32>) nounwind readnone 583declare <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64>) nounwind readnone 584 585; Truncating vector stores are not supported. The following should not crash. 586; Radar 8598391. 587define arm_aapcs_vfpcc void @noTruncStore(<4 x i32>* %a, <4 x i16>* %b) nounwind { 588; CHECK-LE-LABEL: noTruncStore: 589; CHECK-LE: @ %bb.0: 590; CHECK-LE-NEXT: vld1.64 {d16, d17}, [r0:128] 591; CHECK-LE-NEXT: vmovn.i32 d16, q8 592; CHECK-LE-NEXT: vstr d16, [r1] 593; CHECK-LE-NEXT: mov pc, lr 594; 595; CHECK-BE-LABEL: noTruncStore: 596; CHECK-BE: @ %bb.0: 597; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0:128] 598; CHECK-BE-NEXT: vrev64.32 q8, q8 599; CHECK-BE-NEXT: vmovn.i32 d16, q8 600; CHECK-BE-NEXT: vrev64.16 d16, d16 601; CHECK-BE-NEXT: vstr d16, [r1] 602; CHECK-BE-NEXT: mov pc, lr 603 %tmp1 = load <4 x i32>, <4 x i32>* %a, align 16 604 %tmp2 = trunc <4 x i32> %tmp1 to <4 x i16> 605 store <4 x i16> %tmp2, <4 x i16>* %b, align 8 606 ret void 607} 608 609; Use vmov.f32 to materialize f32 immediate splats 610; rdar://10437054 611define arm_aapcs_vfpcc void @v_mov_v2f32(<2 x float>* nocapture %p) nounwind { 612; CHECK-LABEL: v_mov_v2f32: 613; CHECK: @ %bb.0: @ %entry 614; CHECK-NEXT: vmov.f32 d16, #-1.600000e+01 615; CHECK-NEXT: vstr d16, [r0] 616; CHECK-NEXT: mov pc, lr 617entry: 618 store <2 x float> <float -1.600000e+01, float -1.600000e+01>, <2 x float>* %p, align 4 619 ret void 620} 621 622define arm_aapcs_vfpcc void @v_mov_v4f32(<4 x float>* nocapture %p) nounwind { 623; CHECK-LE-LABEL: v_mov_v4f32: 624; CHECK-LE: @ %bb.0: @ %entry 625; CHECK-LE-NEXT: vmov.f32 q8, #3.100000e+01 626; CHECK-LE-NEXT: vst1.32 {d16, d17}, [r0] 627; CHECK-LE-NEXT: mov pc, lr 628; 629; CHECK-BE-LABEL: v_mov_v4f32: 630; CHECK-BE: @ %bb.0: @ %entry 631; CHECK-BE-NEXT: vmov.f32 q8, #3.100000e+01 632; CHECK-BE-NEXT: vstmia r0, {d16, d17} 633; CHECK-BE-NEXT: mov pc, lr 634entry: 635 store <4 x float> <float 3.100000e+01, float 3.100000e+01, float 3.100000e+01, float 3.100000e+01>, <4 x float>* %p, align 4 636 ret void 637} 638 639define arm_aapcs_vfpcc void @v_mov_v4f32_undef(<4 x float> * nocapture %p) nounwind { 640; CHECK-LE-LABEL: v_mov_v4f32_undef: 641; CHECK-LE: @ %bb.0: @ %entry 642; CHECK-LE-NEXT: vmov.f32 q8, #1.000000e+00 643; CHECK-LE-NEXT: vld1.64 {d18, d19}, [r0] 644; CHECK-LE-NEXT: vadd.f32 q8, q9, q8 645; CHECK-LE-NEXT: vst1.64 {d16, d17}, [r0] 646; CHECK-LE-NEXT: mov pc, lr 647; 648; CHECK-BE-LABEL: v_mov_v4f32_undef: 649; CHECK-BE: @ %bb.0: @ %entry 650; CHECK-BE-NEXT: vld1.64 {d16, d17}, [r0] 651; CHECK-BE-NEXT: vmov.f32 q9, #1.000000e+00 652; CHECK-BE-NEXT: vrev64.32 q8, q8 653; CHECK-BE-NEXT: vadd.f32 q8, q8, q9 654; CHECK-BE-NEXT: vrev64.32 q8, q8 655; CHECK-BE-NEXT: vst1.64 {d16, d17}, [r0] 656; CHECK-BE-NEXT: mov pc, lr 657entry: 658 %a = load <4 x float> , <4 x float> *%p 659 %b = fadd <4 x float> %a, <float undef, float 1.0, float 1.0, float 1.0> 660 store <4 x float> %b, <4 x float> *%p 661 ret void 662} 663 664; Vector any_extends must be selected as either vmovl.u or vmovl.s. 665; rdar://10723651 666define arm_aapcs_vfpcc void @any_extend(<4 x i1> %x, <4 x i32> %y) nounwind ssp { 667; CHECK-LE-LABEL: any_extend: 668; CHECK-LE: @ %bb.0: @ %entry 669; CHECK-LE-NEXT: vmov.i16 d16, #0x1 670; CHECK-LE-NEXT: vand d16, d0, d16 671; CHECK-LE-NEXT: vmovl.u16 q8, d16 672; CHECK-LE-NEXT: vsub.i32 q8, q8, q1 673; CHECK-LE-NEXT: vmovn.i32 d16, q8 674; CHECK-LE-NEXT: vst1.16 {d16}, [r0] 675; 676; CHECK-BE-LABEL: any_extend: 677; CHECK-BE: @ %bb.0: @ %entry 678; CHECK-BE-NEXT: vmov.i16 d16, #0x1 679; CHECK-BE-NEXT: vrev64.32 d17, d0 680; CHECK-BE-NEXT: vrev64.32 q9, q1 681; CHECK-BE-NEXT: vand d16, d17, d16 682; CHECK-BE-NEXT: vrev32.16 d16, d16 683; CHECK-BE-NEXT: vmovl.u16 q8, d16 684; CHECK-BE-NEXT: vsub.i32 q8, q8, q9 685; CHECK-BE-NEXT: vmovn.i32 d16, q8 686; CHECK-BE-NEXT: vst1.16 {d16}, [r0] 687entry: 688 %and.i186 = zext <4 x i1> %x to <4 x i32> 689 %add.i185 = sub <4 x i32> %and.i186, %y 690 %sub.i = sub <4 x i32> %add.i185, zeroinitializer 691 %add.i = add <4 x i32> %sub.i, zeroinitializer 692 %vmovn.i = trunc <4 x i32> %add.i to <4 x i16> 693 tail call void @llvm.arm.neon.vst1.p0i8.v4i16(i8* undef, <4 x i16> %vmovn.i, i32 2) 694 unreachable 695} 696 697define arm_aapcs_vfpcc void @v_movi8_sti8(i8* %p) { 698; CHECK-LABEL: v_movi8_sti8: 699; CHECK: @ %bb.0: 700; CHECK-NEXT: vmov.i8 d16, #0x1 701; CHECK-NEXT: vst1.8 {d16}, [r0] 702; CHECK-NEXT: mov pc, lr 703 call void @llvm.arm.neon.vst1.p0i8.v8i8(i8* %p, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, i32 1) 704 ret void 705} 706 707define arm_aapcs_vfpcc void @v_movi8_sti16(i8* %p) { 708; CHECK-LABEL: v_movi8_sti16: 709; CHECK: @ %bb.0: 710; CHECK-NEXT: vmov.i8 d16, #0x1 711; CHECK-NEXT: vst1.16 {d16}, [r0] 712; CHECK-NEXT: mov pc, lr 713 %val = bitcast <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <4 x i16> 714 call void @llvm.arm.neon.vst1.p0i8.v4i16(i8* %p, <4 x i16> %val, i32 2) 715 ret void 716} 717 718define arm_aapcs_vfpcc void @v_movi8_stf16(i8* %p) { 719; CHECK-LABEL: v_movi8_stf16: 720; CHECK: @ %bb.0: 721; CHECK-NEXT: vmov.i8 d16, #0x1 722; CHECK-NEXT: vst1.16 {d16}, [r0] 723; CHECK-NEXT: mov pc, lr 724 %val = bitcast <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <4 x half> 725 call void @llvm.arm.neon.vst1.p0i8.v4f16(i8* %p, <4 x half> %val, i32 2) 726 ret void 727} 728 729define arm_aapcs_vfpcc void @v_movi8_sti32(i8* %p) { 730; CHECK-LABEL: v_movi8_sti32: 731; CHECK: @ %bb.0: 732; CHECK-NEXT: vmov.i8 d16, #0x1 733; CHECK-NEXT: vst1.32 {d16}, [r0] 734; CHECK-NEXT: mov pc, lr 735 %val = bitcast <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <2 x i32> 736 call void @llvm.arm.neon.vst1.p0i8.v2i32(i8* %p, <2 x i32> %val, i32 4) 737 ret void 738} 739 740define arm_aapcs_vfpcc void @v_movi8_stf32(i8* %p) { 741; CHECK-LABEL: v_movi8_stf32: 742; CHECK: @ %bb.0: 743; CHECK-NEXT: vmov.i8 d16, #0x1 744; CHECK-NEXT: vst1.32 {d16}, [r0] 745; CHECK-NEXT: mov pc, lr 746 %val = bitcast <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <2 x float> 747 call void @llvm.arm.neon.vst1.p0i8.v2f32(i8* %p, <2 x float> %val, i32 4) 748 ret void 749} 750 751define arm_aapcs_vfpcc void @v_movi8_sti64(i8* %p) { 752; CHECK-LABEL: v_movi8_sti64: 753; CHECK: @ %bb.0: 754; CHECK-NEXT: vmov.i8 d16, #0x1 755; CHECK-NEXT: vst1.64 {d16}, [r0:64] 756; CHECK-NEXT: mov pc, lr 757 %val = bitcast <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <1 x i64> 758 call void @llvm.arm.neon.vst1.p0i8.v1i64(i8* %p, <1 x i64> %val, i32 8) 759 ret void 760} 761 762define arm_aapcs_vfpcc void @v_movi16_sti16(i8* %p) { 763; CHECK-LABEL: v_movi16_sti16: 764; CHECK: @ %bb.0: 765; CHECK-NEXT: vmov.i16 d16, #0x1 766; CHECK-NEXT: vst1.16 {d16}, [r0] 767; CHECK-NEXT: mov pc, lr 768 call void @llvm.arm.neon.vst1.p0i8.v4i16(i8* %p, <4 x i16> <i16 1, i16 1, i16 1, i16 1>, i32 2) 769 ret void 770} 771 772define arm_aapcs_vfpcc void @v_movi16_stf16(i8* %p) { 773; CHECK-LABEL: v_movi16_stf16: 774; CHECK: @ %bb.0: 775; CHECK-NEXT: vmov.i16 d16, #0x1 776; CHECK-NEXT: vst1.16 {d16}, [r0] 777; CHECK-NEXT: mov pc, lr 778 %val = bitcast <4 x i16> <i16 1, i16 1, i16 1, i16 1> to <4 x half> 779 call void @llvm.arm.neon.vst1.p0i8.v4f16(i8* %p, <4 x half> %val, i32 2) 780 ret void 781} 782 783define arm_aapcs_vfpcc void @v_movi16_sti32(i8* %p) { 784; CHECK-LABEL: v_movi16_sti32: 785; CHECK: @ %bb.0: 786; CHECK-NEXT: vmov.i16 d16, #0x1 787; CHECK-NEXT: vst1.32 {d16}, [r0] 788; CHECK-NEXT: mov pc, lr 789 %val = bitcast <4 x i16> <i16 1, i16 1, i16 1, i16 1> to <2 x i32> 790 call void @llvm.arm.neon.vst1.p0i8.v2i32(i8* %p, <2 x i32> %val, i32 4) 791 ret void 792} 793 794define arm_aapcs_vfpcc void @v_movi16_stf32(i8* %p) { 795; CHECK-LABEL: v_movi16_stf32: 796; CHECK: @ %bb.0: 797; CHECK-NEXT: vmov.i16 d16, #0x1 798; CHECK-NEXT: vst1.32 {d16}, [r0] 799; CHECK-NEXT: mov pc, lr 800 %val = bitcast <4 x i16> <i16 1, i16 1, i16 1, i16 1> to <2 x float> 801 call void @llvm.arm.neon.vst1.p0i8.v2f32(i8* %p, <2 x float> %val, i32 4) 802 ret void 803} 804 805define arm_aapcs_vfpcc void @v_movi16_sti64(i8* %p) { 806; CHECK-LABEL: v_movi16_sti64: 807; CHECK: @ %bb.0: 808; CHECK-NEXT: vmov.i16 d16, #0x1 809; CHECK-NEXT: vst1.64 {d16}, [r0:64] 810; CHECK-NEXT: mov pc, lr 811 %val = bitcast <4 x i16> <i16 1, i16 1, i16 1, i16 1> to <1 x i64> 812 call void @llvm.arm.neon.vst1.p0i8.v1i64(i8* %p, <1 x i64> %val, i32 8) 813 ret void 814} 815 816define arm_aapcs_vfpcc void @v_movi32_sti32(i8* %p) { 817; CHECK-LABEL: v_movi32_sti32: 818; CHECK: @ %bb.0: 819; CHECK-NEXT: vmov.i32 d16, #0x1 820; CHECK-NEXT: vst1.32 {d16}, [r0] 821; CHECK-NEXT: mov pc, lr 822 call void @llvm.arm.neon.vst1.p0i8.v2i32(i8* %p, <2 x i32> <i32 1, i32 1>, i32 4) 823 ret void 824} 825 826define arm_aapcs_vfpcc void @v_movi32_stf32(i8* %p) { 827; CHECK-LABEL: v_movi32_stf32: 828; CHECK: @ %bb.0: 829; CHECK-NEXT: vmov.i32 d16, #0x1 830; CHECK-NEXT: vst1.32 {d16}, [r0] 831; CHECK-NEXT: mov pc, lr 832 %val = bitcast <2 x i32> <i32 1, i32 1> to <2 x float> 833 call void @llvm.arm.neon.vst1.p0i8.v2f32(i8* %p, <2 x float> %val, i32 4) 834 ret void 835} 836 837define arm_aapcs_vfpcc void @v_movi32_sti64(i8* %p) { 838; CHECK-LABEL: v_movi32_sti64: 839; CHECK: @ %bb.0: 840; CHECK-NEXT: vmov.i32 d16, #0x1 841; CHECK-NEXT: vst1.64 {d16}, [r0:64] 842; CHECK-NEXT: mov pc, lr 843 %val = bitcast <2 x i32> <i32 1, i32 1> to <1 x i64> 844 call void @llvm.arm.neon.vst1.p0i8.v1i64(i8* %p, <1 x i64> %val, i32 8) 845 ret void 846} 847 848define arm_aapcs_vfpcc void @v_movf32_stf32(i8* %p) { 849; CHECK-LABEL: v_movf32_stf32: 850; CHECK: @ %bb.0: 851; CHECK-NEXT: vmov.f32 d16, #1.000000e+00 852; CHECK-NEXT: vst1.32 {d16}, [r0] 853; CHECK-NEXT: mov pc, lr 854 call void @llvm.arm.neon.vst1.p0i8.v2f32(i8* %p, <2 x float> <float 1.0, float 1.0>, i32 4) 855 ret void 856} 857 858define arm_aapcs_vfpcc void@v_movf32_sti32(i8* %p) { 859; FIXME: We should use vmov.f32 instead of mov then vdup 860; CHECK-LABEL: v_movf32_sti32: 861; CHECK: @ %bb.0: 862; CHECK-NEXT: mov r1, #1065353216 863; CHECK-NEXT: vdup.32 d16, r1 864; CHECK-NEXT: vst1.32 {d16}, [r0] 865; CHECK-NEXT: mov pc, lr 866 %val = bitcast <2 x float> <float 1.0, float 1.0> to <2 x i32> 867 call void @llvm.arm.neon.vst1.p0i8.v2i32(i8* %p, <2 x i32> %val, i32 4) 868 ret void 869} 870 871define arm_aapcs_vfpcc void @v_movf32_sti64(i8* %p) { 872; CHECK-LE-LABEL: v_movf32_sti64: 873; CHECK-LE: @ %bb.0: 874; CHECK-LE-NEXT: mov r1, #1065353216 875; CHECK-LE-NEXT: vdup.32 d16, r1 876; CHECK-LE-NEXT: vst1.64 {d16}, [r0:64] 877; CHECK-LE-NEXT: mov pc, lr 878; 879; FIXME: vrev is not needed here 880; CHECK-BE-LABEL: v_movf32_sti64: 881; CHECK-BE: @ %bb.0: 882; CHECK-BE-NEXT: mov r1, #1065353216 883; CHECK-BE-NEXT: vdup.32 d16, r1 884; CHECK-BE-NEXT: vrev64.32 d16, d16 885; CHECK-BE-NEXT: vst1.64 {d16}, [r0:64] 886; CHECK-BE-NEXT: mov pc, lr 887 %val = bitcast <2 x float> <float 1.0, float 1.0> to <1 x i64> 888 call void @llvm.arm.neon.vst1.p0i8.v1i64(i8* %p, <1 x i64> %val, i32 8) 889 ret void 890} 891 892define arm_aapcs_vfpcc void @v_movi64_sti64(i8* %p) { 893; CHECK-LABEL: v_movi64_sti64: 894; CHECK: @ %bb.0: 895; CHECK-NEXT: vmov.i64 d16, #0xff 896; CHECK-NEXT: vst1.64 {d16}, [r0:64] 897; CHECK-NEXT: mov pc, lr 898 call void @llvm.arm.neon.vst1.p0i8.v1i64(i8* %p, <1 x i64> <i64 255>, i32 8) 899 ret void 900} 901 902define arm_aapcs_vfpcc void @v_movQi8_sti8(i8* %p) { 903; CHECK-LABEL: v_movQi8_sti8: 904; CHECK: @ %bb.0: 905; CHECK-NEXT: vmov.i8 q8, #0x1 906; CHECK-NEXT: vst1.8 {d16, d17}, [r0] 907; CHECK-NEXT: mov pc, lr 908 call void @llvm.arm.neon.vst1.p0i8.v16i8(i8* %p, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, i32 1) 909 ret void 910} 911 912define arm_aapcs_vfpcc void @v_movQi8_sti16(i8* %p) { 913; CHECK-LABEL: v_movQi8_sti16: 914; CHECK: @ %bb.0: 915; CHECK-NEXT: vmov.i8 q8, #0x1 916; CHECK-NEXT: vst1.16 {d16, d17}, [r0] 917; CHECK-NEXT: mov pc, lr 918 %val = bitcast <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <8 x i16> 919 call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %p, <8 x i16> %val, i32 2) 920 ret void 921} 922 923define arm_aapcs_vfpcc void @v_movQi8_stf16(i8* %p) { 924; CHECK-LABEL: v_movQi8_stf16: 925; CHECK: @ %bb.0: 926; CHECK-NEXT: vmov.i8 q8, #0x1 927; CHECK-NEXT: vst1.16 {d16, d17}, [r0] 928; CHECK-NEXT: mov pc, lr 929 %val = bitcast <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <8 x half> 930 call void @llvm.arm.neon.vst1.p0i8.v8f16(i8* %p, <8 x half> %val, i32 2) 931 ret void 932} 933 934define arm_aapcs_vfpcc void @v_movQi8_sti32(i8* %p) { 935; CHECK-LABEL: v_movQi8_sti32: 936; CHECK: @ %bb.0: 937; CHECK-NEXT: vmov.i8 q8, #0x1 938; CHECK-NEXT: vst1.32 {d16, d17}, [r0] 939; CHECK-NEXT: mov pc, lr 940 %val = bitcast <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <4 x i32> 941 call void @llvm.arm.neon.vst1.p0i8.v4i32(i8* %p, <4 x i32> %val, i32 4) 942 ret void 943} 944 945define arm_aapcs_vfpcc void @v_movQi8_stf32(i8* %p) { 946; CHECK-LABEL: v_movQi8_stf32: 947; CHECK: @ %bb.0: 948; CHECK-NEXT: vmov.i8 q8, #0x1 949; CHECK-NEXT: vst1.32 {d16, d17}, [r0] 950; CHECK-NEXT: mov pc, lr 951 %val = bitcast <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <4 x float> 952 call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* %p, <4 x float> %val, i32 4) 953 ret void 954} 955 956define arm_aapcs_vfpcc void @v_movQi8_sti64(i8* %p) { 957; CHECK-LABEL: v_movQi8_sti64: 958; CHECK: @ %bb.0: 959; CHECK-NEXT: vmov.i8 q8, #0x1 960; CHECK-NEXT: vst1.64 {d16, d17}, [r0:64] 961; CHECK-NEXT: mov pc, lr 962 %val = bitcast <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> to <2 x i64> 963 call void @llvm.arm.neon.vst1.p0i8.v2i64(i8* %p, <2 x i64> %val, i32 8) 964 ret void 965} 966 967define arm_aapcs_vfpcc void @v_movQi16_sti16(i8* %p) { 968; CHECK-LABEL: v_movQi16_sti16: 969; CHECK: @ %bb.0: 970; CHECK-NEXT: vmov.i16 q8, #0x1 971; CHECK-NEXT: vst1.16 {d16, d17}, [r0] 972; CHECK-NEXT: mov pc, lr 973 call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %p, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, i32 2) 974 ret void 975} 976 977define arm_aapcs_vfpcc void @v_movQi16_stf16(i8* %p) { 978; CHECK-LABEL: v_movQi16_stf16: 979; CHECK: @ %bb.0: 980; CHECK-NEXT: vmov.i16 q8, #0x1 981; CHECK-NEXT: vst1.16 {d16, d17}, [r0] 982; CHECK-NEXT: mov pc, lr 983 %val = bitcast <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> to <8 x half> 984 call void @llvm.arm.neon.vst1.p0i8.v8f16(i8* %p, <8 x half> %val, i32 2) 985 ret void 986} 987 988define arm_aapcs_vfpcc void @v_movQi16_sti32(i8* %p) { 989; CHECK-LABEL: v_movQi16_sti32: 990; CHECK: @ %bb.0: 991; CHECK-NEXT: vmov.i16 q8, #0x1 992; CHECK-NEXT: vst1.32 {d16, d17}, [r0] 993; CHECK-NEXT: mov pc, lr 994 %val = bitcast <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> to <4 x i32> 995 call void @llvm.arm.neon.vst1.p0i8.v4i32(i8* %p, <4 x i32> %val, i32 4) 996 ret void 997} 998 999define arm_aapcs_vfpcc void @v_movQi16_stf32(i8* %p) { 1000; CHECK-LABEL: v_movQi16_stf32: 1001; CHECK: @ %bb.0: 1002; CHECK-NEXT: vmov.i16 q8, #0x1 1003; CHECK-NEXT: vst1.32 {d16, d17}, [r0] 1004; CHECK-NEXT: mov pc, lr 1005 %val = bitcast <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> to <4 x float> 1006 call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* %p, <4 x float> %val, i32 4) 1007 ret void 1008} 1009 1010define arm_aapcs_vfpcc void @v_movQi16_sti64(i8* %p) { 1011; CHECK-LABEL: v_movQi16_sti64: 1012; CHECK: @ %bb.0: 1013; CHECK-NEXT: vmov.i16 q8, #0x1 1014; CHECK-NEXT: vst1.64 {d16, d17}, [r0:64] 1015; CHECK-NEXT: mov pc, lr 1016 %val = bitcast <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> to <2 x i64> 1017 call void @llvm.arm.neon.vst1.p0i8.v2i64(i8* %p, <2 x i64> %val, i32 8) 1018 ret void 1019} 1020 1021define arm_aapcs_vfpcc void @v_movQi32_sti32(i8* %p) { 1022; CHECK-LABEL: v_movQi32_sti32: 1023; CHECK: @ %bb.0: 1024; CHECK-NEXT: vmov.i32 q8, #0x1 1025; CHECK-NEXT: vst1.32 {d16, d17}, [r0] 1026; CHECK-NEXT: mov pc, lr 1027 call void @llvm.arm.neon.vst1.p0i8.v4i32(i8* %p, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, i32 4) 1028 ret void 1029} 1030 1031define arm_aapcs_vfpcc void @v_movQi32_stf32(i8* %p) { 1032; CHECK-LABEL: v_movQi32_stf32: 1033; CHECK: @ %bb.0: 1034; CHECK-NEXT: vmov.i32 q8, #0x1 1035; CHECK-NEXT: vst1.32 {d16, d17}, [r0] 1036; CHECK-NEXT: mov pc, lr 1037 %val = bitcast <4 x i32> <i32 1, i32 1, i32 1, i32 1> to <4 x float> 1038 call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* %p, <4 x float> %val, i32 4) 1039 ret void 1040} 1041 1042define arm_aapcs_vfpcc void @v_movQi32_sti64(i8* %p) { 1043; CHECK-LABEL: v_movQi32_sti64: 1044; CHECK: @ %bb.0: 1045; CHECK-NEXT: vmov.i32 q8, #0x1 1046; CHECK-NEXT: vst1.64 {d16, d17}, [r0:64] 1047; CHECK-NEXT: mov pc, lr 1048 %val = bitcast <4 x i32> <i32 1, i32 1, i32 1, i32 1> to <2 x i64> 1049 call void @llvm.arm.neon.vst1.p0i8.v2i64(i8* %p, <2 x i64> %val, i32 8) 1050 ret void 1051} 1052 1053define arm_aapcs_vfpcc void @v_movQf32_stf32(i8* %p) { 1054; CHECK-LABEL: v_movQf32_stf32: 1055; CHECK: @ %bb.0: 1056; CHECK-NEXT: vmov.f32 q8, #1.000000e+00 1057; CHECK-NEXT: vst1.32 {d16, d17}, [r0] 1058; CHECK-NEXT: mov pc, lr 1059 call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* %p, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, i32 4) 1060 ret void 1061} 1062 1063define arm_aapcs_vfpcc void @v_movQf32_sti32(i8* %p) { 1064; FIXME: We should use vmov.f32 instead of mov then vdup 1065; CHECK-LABEL: v_movQf32_sti32: 1066; CHECK: @ %bb.0: 1067; CHECK-NEXT: mov r1, #1065353216 1068; CHECK-NEXT: vdup.32 q8, r1 1069; CHECK-NEXT: vst1.32 {d16, d17}, [r0] 1070; CHECK-NEXT: mov pc, lr 1071 %val = bitcast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0> to <4 x i32> 1072 call void @llvm.arm.neon.vst1.p0i8.v4i32(i8* %p, <4 x i32> %val, i32 4) 1073 ret void 1074} 1075 1076define arm_aapcs_vfpcc void @v_movQf32_sti64(i8* %p) { 1077; CHECK-LE-LABEL: v_movQf32_sti64: 1078; CHECK-LE: @ %bb.0: 1079; CHECK-LE-NEXT: mov r1, #1065353216 1080; CHECK-LE-NEXT: vdup.32 q8, r1 1081; CHECK-LE-NEXT: vst1.64 {d16, d17}, [r0:64] 1082; CHECK-LE-NEXT: mov pc, lr 1083; 1084; FIXME: vrev is not needed here 1085; CHECK-BE-LABEL: v_movQf32_sti64: 1086; CHECK-BE: @ %bb.0: 1087; CHECK-BE-NEXT: mov r1, #1065353216 1088; CHECK-BE-NEXT: vdup.32 q8, r1 1089; CHECK-BE-NEXT: vrev64.32 q8, q8 1090; CHECK-BE-NEXT: vst1.64 {d16, d17}, [r0:64] 1091; CHECK-BE-NEXT: mov pc, lr 1092 %val = bitcast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0> to <2 x i64> 1093 call void @llvm.arm.neon.vst1.p0i8.v2i64(i8* %p, <2 x i64> %val, i32 8) 1094 ret void 1095} 1096 1097define arm_aapcs_vfpcc void @v_movQi64_sti64(i8* %p) { 1098; CHECK-LABEL: v_movQi64_sti64: 1099; CHECK: @ %bb.0: 1100; CHECK-NEXT: vmov.i64 q8, #0xff 1101; CHECK-NEXT: vst1.64 {d16, d17}, [r0:64] 1102; CHECK-NEXT: mov pc, lr 1103 call void @llvm.arm.neon.vst1.p0i8.v2i64(i8* %p, <2 x i64> <i64 255, i64 255>, i32 8) 1104 ret void 1105} 1106 1107define arm_aapcs_vfpcc void @v_mvni16_sti16(i8* %p) { 1108; CHECK-LABEL: v_mvni16_sti16: 1109; CHECK: @ %bb.0: 1110; CHECK-NEXT: vmvn.i16 d16, #0xfe 1111; CHECK-NEXT: vst1.16 {d16}, [r0] 1112; CHECK-NEXT: mov pc, lr 1113 call void @llvm.arm.neon.vst1.p0i8.v4i16(i8* %p, <4 x i16> <i16 65281, i16 65281, i16 65281, i16 65281>, i32 2) 1114 ret void 1115} 1116 1117define arm_aapcs_vfpcc void @v_mvni16_stf16(i8* %p) { 1118; CHECK-LABEL: v_mvni16_stf16: 1119; CHECK: @ %bb.0: 1120; CHECK-NEXT: vmvn.i16 d16, #0xfe 1121; CHECK-NEXT: vst1.16 {d16}, [r0] 1122; CHECK-NEXT: mov pc, lr 1123 %val = bitcast <4 x i16> <i16 65281, i16 65281, i16 65281, i16 65281> to <4 x half> 1124 call void @llvm.arm.neon.vst1.p0i8.v4f16(i8* %p, <4 x half> %val, i32 2) 1125 ret void 1126} 1127 1128define arm_aapcs_vfpcc void @v_mvni16_sti32(i8* %p) { 1129; CHECK-LABEL: v_mvni16_sti32: 1130; CHECK: @ %bb.0: 1131; CHECK-NEXT: vmvn.i16 d16, #0xfe 1132; CHECK-NEXT: vst1.32 {d16}, [r0] 1133; CHECK-NEXT: mov pc, lr 1134 %val = bitcast <4 x i16> <i16 65281, i16 65281, i16 65281, i16 65281> to <2 x i32> 1135 call void @llvm.arm.neon.vst1.p0i8.v2i32(i8* %p, <2 x i32> %val, i32 4) 1136 ret void 1137} 1138 1139define arm_aapcs_vfpcc void @v_mvni16_stf32(i8* %p) { 1140; CHECK-LABEL: v_mvni16_stf32: 1141; CHECK: @ %bb.0: 1142; CHECK-NEXT: vmvn.i16 d16, #0xfe 1143; CHECK-NEXT: vst1.32 {d16}, [r0] 1144; CHECK-NEXT: mov pc, lr 1145 %val = bitcast <4 x i16> <i16 65281, i16 65281, i16 65281, i16 65281> to <2 x float> 1146 call void @llvm.arm.neon.vst1.p0i8.v2f32(i8* %p, <2 x float> %val, i32 4) 1147 ret void 1148} 1149 1150define arm_aapcs_vfpcc void @v_mvni16_sti64(i8* %p) { 1151; CHECK-LABEL: v_mvni16_sti64: 1152; CHECK: @ %bb.0: 1153; CHECK-NEXT: vmvn.i16 d16, #0xfe 1154; CHECK-NEXT: vst1.64 {d16}, [r0:64] 1155; CHECK-NEXT: mov pc, lr 1156 %val = bitcast <4 x i16> <i16 65281, i16 65281, i16 65281, i16 65281> to <1 x i64> 1157 call void @llvm.arm.neon.vst1.p0i8.v1i64(i8* %p, <1 x i64> %val, i32 8) 1158 ret void 1159} 1160 1161define arm_aapcs_vfpcc void @v_mvni32_sti32(i8* %p) { 1162; CHECK-LABEL: v_mvni32_sti32: 1163; CHECK: @ %bb.0: 1164; CHECK-NEXT: vmvn.i32 d16, #0xfe 1165; CHECK-NEXT: vst1.32 {d16}, [r0] 1166; CHECK-NEXT: mov pc, lr 1167 call void @llvm.arm.neon.vst1.p0i8.v2i32(i8* %p, <2 x i32> <i32 4294967041, i32 4294967041>, i32 4) 1168 ret void 1169} 1170 1171define arm_aapcs_vfpcc void @v_mvni32_stf32(i8* %p) { 1172; CHECK-LABEL: v_mvni32_stf32: 1173; CHECK: @ %bb.0: 1174; CHECK-NEXT: vmvn.i32 d16, #0xfe 1175; CHECK-NEXT: vst1.32 {d16}, [r0] 1176; CHECK-NEXT: mov pc, lr 1177 %val = bitcast <2 x i32> <i32 4294967041, i32 4294967041> to <2 x float> 1178 call void @llvm.arm.neon.vst1.p0i8.v2f32(i8* %p, <2 x float> %val, i32 4) 1179 ret void 1180} 1181 1182define arm_aapcs_vfpcc void @v_mvni32_sti64(i8* %p) { 1183; CHECK-LABEL: v_mvni32_sti64: 1184; CHECK: @ %bb.0: 1185; CHECK-NEXT: vmvn.i32 d16, #0xfe 1186; CHECK-NEXT: vst1.64 {d16}, [r0:64] 1187; CHECK-NEXT: mov pc, lr 1188 %val = bitcast <2 x i32> <i32 4294967041, i32 4294967041> to <1 x i64> 1189 call void @llvm.arm.neon.vst1.p0i8.v1i64(i8* %p, <1 x i64> %val, i32 8) 1190 ret void 1191} 1192 1193 1194define arm_aapcs_vfpcc void @v_mvnQi16_sti16(i8* %p) { 1195; CHECK-LABEL: v_mvnQi16_sti16: 1196; CHECK: @ %bb.0: 1197; CHECK-NEXT: vmvn.i16 q8, #0xfe 1198; CHECK-NEXT: vst1.16 {d16, d17}, [r0] 1199; CHECK-NEXT: mov pc, lr 1200 call void @llvm.arm.neon.vst1.p0i8.v8i16(i8* %p, <8 x i16> <i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281>, i32 2) 1201 ret void 1202} 1203 1204define arm_aapcs_vfpcc void @v_mvnQi16_stf16(i8* %p) { 1205; CHECK-LABEL: v_mvnQi16_stf16: 1206; CHECK: @ %bb.0: 1207; CHECK-NEXT: vmvn.i16 q8, #0xfe 1208; CHECK-NEXT: vst1.16 {d16, d17}, [r0] 1209; CHECK-NEXT: mov pc, lr 1210 %val = bitcast <8 x i16> <i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281> to <8 x half> 1211 call void @llvm.arm.neon.vst1.p0i8.v8f16(i8* %p, <8 x half> %val, i32 2) 1212 ret void 1213} 1214 1215define arm_aapcs_vfpcc void @v_mvnQi16_sti32(i8* %p) { 1216; CHECK-LABEL: v_mvnQi16_sti32: 1217; CHECK: @ %bb.0: 1218; CHECK-NEXT: vmvn.i16 q8, #0xfe 1219; CHECK-NEXT: vst1.32 {d16, d17}, [r0] 1220; CHECK-NEXT: mov pc, lr 1221 %val = bitcast <8 x i16> <i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281> to <4 x i32> 1222 call void @llvm.arm.neon.vst1.p0i8.v4i32(i8* %p, <4 x i32> %val, i32 4) 1223 ret void 1224} 1225 1226define arm_aapcs_vfpcc void @v_mvnQi16_stf32(i8* %p) { 1227; CHECK-LABEL: v_mvnQi16_stf32: 1228; CHECK: @ %bb.0: 1229; CHECK-NEXT: vmvn.i16 q8, #0xfe 1230; CHECK-NEXT: vst1.32 {d16, d17}, [r0] 1231; CHECK-NEXT: mov pc, lr 1232 %val = bitcast <8 x i16> <i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281> to <4 x float> 1233 call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* %p, <4 x float> %val, i32 4) 1234 ret void 1235} 1236 1237define arm_aapcs_vfpcc void @v_mvnQi16_sti64(i8* %p) { 1238; CHECK-LABEL: v_mvnQi16_sti64: 1239; CHECK: @ %bb.0: 1240; CHECK-NEXT: vmvn.i16 q8, #0xfe 1241; CHECK-NEXT: vst1.64 {d16, d17}, [r0:64] 1242; CHECK-NEXT: mov pc, lr 1243 %val = bitcast <8 x i16> <i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281, i16 65281> to <2 x i64> 1244 call void @llvm.arm.neon.vst1.p0i8.v2i64(i8* %p, <2 x i64> %val, i32 8) 1245 ret void 1246} 1247 1248define arm_aapcs_vfpcc void @v_mvnQi32_sti32(i8* %p) { 1249; CHECK-LABEL: v_mvnQi32_sti32: 1250; CHECK: @ %bb.0: 1251; CHECK-NEXT: vmvn.i32 q8, #0xfe 1252; CHECK-NEXT: vst1.32 {d16, d17}, [r0] 1253; CHECK-NEXT: mov pc, lr 1254 call void @llvm.arm.neon.vst1.p0i8.v4i32(i8* %p, <4 x i32> <i32 4294967041, i32 4294967041, i32 4294967041, i32 4294967041>, i32 4) 1255 ret void 1256} 1257 1258define arm_aapcs_vfpcc void @v_mvnQi32_stf32(i8* %p) { 1259; CHECK-LABEL: v_mvnQi32_stf32: 1260; CHECK: @ %bb.0: 1261; CHECK-NEXT: vmvn.i32 q8, #0xfe 1262; CHECK-NEXT: vst1.32 {d16, d17}, [r0] 1263; CHECK-NEXT: mov pc, lr 1264 %val = bitcast <4 x i32> <i32 4294967041, i32 4294967041, i32 4294967041, i32 4294967041> to <4 x float> 1265 call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* %p, <4 x float> %val, i32 4) 1266 ret void 1267} 1268 1269define arm_aapcs_vfpcc void @v_mvnQi32_sti64(i8* %p) { 1270; CHECK-LABEL: v_mvnQi32_sti64: 1271; CHECK: @ %bb.0: 1272; CHECK-NEXT: vmvn.i32 q8, #0xfe 1273; CHECK-NEXT: vst1.64 {d16, d17}, [r0:64] 1274; CHECK-NEXT: mov pc, lr 1275 %val = bitcast <4 x i32> <i32 4294967041, i32 4294967041, i32 4294967041, i32 4294967041> to <2 x i64> 1276 call void @llvm.arm.neon.vst1.p0i8.v2i64(i8* %p, <2 x i64> %val, i32 8) 1277 ret void 1278} 1279 1280declare void @llvm.arm.neon.vst1.p0i8.v8i8(i8*, <8 x i8>, i32) nounwind 1281declare void @llvm.arm.neon.vst1.p0i8.v4i16(i8*, <4 x i16>, i32) nounwind 1282declare void @llvm.arm.neon.vst1.p0i8.v4f16(i8*, <4 x half>, i32) nounwind 1283declare void @llvm.arm.neon.vst1.p0i8.v2i32(i8*, <2 x i32>, i32) nounwind 1284declare void @llvm.arm.neon.vst1.p0i8.v2f32(i8*, <2 x float>, i32) nounwind 1285declare void @llvm.arm.neon.vst1.p0i8.v1i64(i8*, <1 x i64>, i32) nounwind 1286 1287declare void @llvm.arm.neon.vst1.p0i8.v16i8(i8*, <16 x i8>, i32) nounwind 1288declare void @llvm.arm.neon.vst1.p0i8.v8i16(i8*, <8 x i16>, i32) nounwind 1289declare void @llvm.arm.neon.vst1.p0i8.v8f16(i8*, <8 x half>, i32) nounwind 1290declare void @llvm.arm.neon.vst1.p0i8.v4i32(i8*, <4 x i32>, i32) nounwind 1291declare void @llvm.arm.neon.vst1.p0i8.v4f32(i8*, <4 x float>, i32) nounwind 1292declare void @llvm.arm.neon.vst1.p0i8.v2i64(i8*, <2 x i64>, i32) nounwind 1293