1; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
2; RUN: grep {vld1\\.8} %t | count 2
3; RUN: grep {vld1\\.16} %t | count 2
4; RUN: grep {vld1\\.32} %t | count 4
5; RUN: grep {vld1\\.64} %t | count 2
6
7define <8 x i8> @vld1i8(i8* %A) nounwind {
8	%tmp1 = call <8 x i8> @llvm.arm.neon.vld1i.v8i8(i8* %A)
9	ret <8 x i8> %tmp1
10}
11
12define <4 x i16> @vld1i16(i16* %A) nounwind {
13	%tmp1 = call <4 x i16> @llvm.arm.neon.vld1i.v4i16(i16* %A)
14	ret <4 x i16> %tmp1
15}
16
17define <2 x i32> @vld1i32(i32* %A) nounwind {
18	%tmp1 = call <2 x i32> @llvm.arm.neon.vld1i.v2i32(i32* %A)
19	ret <2 x i32> %tmp1
20}
21
22define <2 x float> @vld1f(float* %A) nounwind {
23	%tmp1 = call <2 x float> @llvm.arm.neon.vld1f.v2f32(float* %A)
24	ret <2 x float> %tmp1
25}
26
27define <1 x i64> @vld1i64(i64* %A) nounwind {
28	%tmp1 = call <1 x i64> @llvm.arm.neon.vld1i.v1i64(i64* %A)
29	ret <1 x i64> %tmp1
30}
31
32define <16 x i8> @vld1Qi8(i8* %A) nounwind {
33	%tmp1 = call <16 x i8> @llvm.arm.neon.vld1i.v16i8(i8* %A)
34	ret <16 x i8> %tmp1
35}
36
37define <8 x i16> @vld1Qi16(i16* %A) nounwind {
38	%tmp1 = call <8 x i16> @llvm.arm.neon.vld1i.v8i16(i16* %A)
39	ret <8 x i16> %tmp1
40}
41
42define <4 x i32> @vld1Qi32(i32* %A) nounwind {
43	%tmp1 = call <4 x i32> @llvm.arm.neon.vld1i.v4i32(i32* %A)
44	ret <4 x i32> %tmp1
45}
46
47define <4 x float> @vld1Qf(float* %A) nounwind {
48	%tmp1 = call <4 x float> @llvm.arm.neon.vld1f.v4f32(float* %A)
49	ret <4 x float> %tmp1
50}
51
52define <2 x i64> @vld1Qi64(i64* %A) nounwind {
53	%tmp1 = call <2 x i64> @llvm.arm.neon.vld1i.v2i64(i64* %A)
54	ret <2 x i64> %tmp1
55}
56
57declare <8 x i8>  @llvm.arm.neon.vld1i.v8i8(i8*) nounwind readnone
58declare <4 x i16> @llvm.arm.neon.vld1i.v4i16(i16*) nounwind readnone
59declare <2 x i32> @llvm.arm.neon.vld1i.v2i32(i32*) nounwind readnone
60declare <2 x float> @llvm.arm.neon.vld1f.v2f32(float*) nounwind readnone
61declare <1 x i64> @llvm.arm.neon.vld1i.v1i64(i64*) nounwind readnone
62
63declare <16 x i8> @llvm.arm.neon.vld1i.v16i8(i8*) nounwind readnone
64declare <8 x i16> @llvm.arm.neon.vld1i.v8i16(i16*) nounwind readnone
65declare <4 x i32> @llvm.arm.neon.vld1i.v4i32(i32*) nounwind readnone
66declare <4 x float> @llvm.arm.neon.vld1f.v4f32(float*) nounwind readnone
67declare <2 x i64> @llvm.arm.neon.vld1i.v2i64(i64*) nounwind readnone
68