1; RUN: llc -mtriple armv6-apple-darwin -filetype asm -o - %s | FileCheck %s
2
3define i32 @test1(i32 %x) {
4; CHECK-LABEL: test1:
5; CHECK:       @ %bb.0:
6; CHECK-NEXT:    uxtb16 r0, r0
7; CHECK-NEXT:    bx lr
8  %tmp1 = and i32 %x, 16711935
9  ret i32 %tmp1
10}
11
12define i32 @test2(i32 %x) {
13; CHECK-LABEL: test2:
14; CHECK:       @ %bb.0:
15; CHECK-NEXT:    uxtb16 r0, r0, ror #8
16; CHECK-NEXT:    bx lr
17  %tmp1 = lshr i32 %x, 8
18  %tmp2 = and i32 %tmp1, 16711935
19  ret i32 %tmp2
20}
21
22define i32 @test3(i32 %x) {
23; CHECK-LABEL: test3:
24; CHECK:       @ %bb.0:
25; CHECK-NEXT:    uxtb16 r0, r0, ror #8
26; CHECK-NEXT:    bx lr
27  %tmp1 = lshr i32 %x, 8
28  %tmp2 = and i32 %tmp1, 16711935
29  ret i32 %tmp2
30}
31
32define i32 @test4(i32 %x) {
33; CHECK-LABEL: test4:
34; CHECK:       @ %bb.0:
35; CHECK-NEXT:    uxtb16 r0, r0, ror #8
36; CHECK-NEXT:    bx lr
37  %tmp1 = lshr i32 %x, 8
38  %tmp6 = and i32 %tmp1, 16711935
39  ret i32 %tmp6
40}
41
42define i32 @test5(i32 %x) {
43; CHECK-LABEL: test5:
44; CHECK:       @ %bb.0:
45; CHECK-NEXT:    uxtb16 r0, r0, ror #8
46; CHECK-NEXT:    bx lr
47  %tmp1 = lshr i32 %x, 8
48  %tmp2 = and i32 %tmp1, 16711935
49  ret i32 %tmp2
50}
51
52define i32 @test6(i32 %x) {
53; CHECK-LABEL: test6:
54; CHECK:       @ %bb.0:
55; CHECK-NEXT:    uxtb16 r0, r0, ror #16
56; CHECK-NEXT:    bx lr
57  %tmp1 = lshr i32 %x, 16
58  %tmp2 = and i32 %tmp1, 255
59  %tmp4 = shl i32 %x, 16
60  %tmp5 = and i32 %tmp4, 16711680
61  %tmp6 = or i32 %tmp2, %tmp5
62  ret i32 %tmp6
63}
64
65define i32 @test7(i32 %x) {
66; CHECK-LABEL: test7:
67; CHECK:       @ %bb.0:
68; CHECK-NEXT:    uxtb16 r0, r0, ror #16
69; CHECK-NEXT:    bx lr
70  %tmp1 = lshr i32 %x, 16
71  %tmp2 = and i32 %tmp1, 255
72  %tmp4 = shl i32 %x, 16
73  %tmp5 = and i32 %tmp4, 16711680
74  %tmp6 = or i32 %tmp2, %tmp5
75  ret i32 %tmp6
76}
77
78define i32 @test8(i32 %x) {
79; CHECK-LABEL: test8:
80; CHECK:       @ %bb.0:
81; CHECK-NEXT:    uxtb16 r0, r0, ror #24
82; CHECK-NEXT:    bx lr
83  %tmp1 = shl i32 %x, 8
84  %tmp2 = and i32 %tmp1, 16711680
85  %tmp5 = lshr i32 %x, 24
86  %tmp6 = or i32 %tmp2, %tmp5
87  ret i32 %tmp6
88}
89
90define i32 @test9(i32 %x) {
91; CHECK-LABEL: test9:
92; CHECK:       @ %bb.0:
93; CHECK-NEXT:    uxtb16 r0, r0, ror #24
94; CHECK-NEXT:    bx lr
95  %tmp1 = lshr i32 %x, 24
96  %tmp4 = shl i32 %x, 8
97  %tmp5 = and i32 %tmp4, 16711680
98  %tmp6 = or i32 %tmp5, %tmp1
99  ret i32 %tmp6
100}
101
102define i32 @test10(i32 %p0) {
103; CHECK-LABEL: test10:
104; CHECK:       @ %bb.0:
105; CHECK-NEXT:    mov r1, #248
106; CHECK-NEXT:    orr r1, r1, #16252928
107; CHECK-NEXT:    and r0, r1, r0, lsr #7
108; CHECK-NEXT:    lsr r1, r0, #5
109; CHECK-NEXT:    uxtb16 r1, r1
110; CHECK-NEXT:    orr r0, r1, r0
111; CHECK-NEXT:    bx lr
112  %tmp1 = lshr i32 %p0, 7
113  %tmp2 = and i32 %tmp1, 16253176
114  %tmp4 = lshr i32 %tmp2, 5
115  %tmp5 = and i32 %tmp4, 458759
116  %tmp7 = or i32 %tmp5, %tmp2
117  ret i32 %tmp7
118}
119
120