1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
3; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2
4; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2
5; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM
6
7declare i4 @llvm.usub.sat.i4(i4, i4)
8declare i8 @llvm.usub.sat.i8(i8, i8)
9declare i16 @llvm.usub.sat.i16(i16, i16)
10declare i32 @llvm.usub.sat.i32(i32, i32)
11declare i64 @llvm.usub.sat.i64(i64, i64)
12
13define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
14; CHECK-T1-LABEL: func32:
15; CHECK-T1:       @ %bb.0:
16; CHECK-T1-NEXT:    muls r1, r2, r1
17; CHECK-T1-NEXT:    subs r0, r0, r1
18; CHECK-T1-NEXT:    bhs .LBB0_2
19; CHECK-T1-NEXT:  @ %bb.1:
20; CHECK-T1-NEXT:    movs r0, #0
21; CHECK-T1-NEXT:  .LBB0_2:
22; CHECK-T1-NEXT:    bx lr
23;
24; CHECK-T2-LABEL: func32:
25; CHECK-T2:       @ %bb.0:
26; CHECK-T2-NEXT:    muls r1, r2, r1
27; CHECK-T2-NEXT:    subs r0, r0, r1
28; CHECK-T2-NEXT:    it lo
29; CHECK-T2-NEXT:    movlo r0, #0
30; CHECK-T2-NEXT:    bx lr
31;
32; CHECK-ARM-LABEL: func32:
33; CHECK-ARM:       @ %bb.0:
34; CHECK-ARM-NEXT:    mul r1, r1, r2
35; CHECK-ARM-NEXT:    subs r0, r0, r1
36; CHECK-ARM-NEXT:    movlo r0, #0
37; CHECK-ARM-NEXT:    bx lr
38  %a = mul i32 %y, %z
39  %tmp = call i32 @llvm.usub.sat.i32(i32 %x, i32 %a)
40  ret i32 %tmp
41}
42
43define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
44; CHECK-T1-LABEL: func64:
45; CHECK-T1:       @ %bb.0:
46; CHECK-T1-NEXT:    .save {r4, lr}
47; CHECK-T1-NEXT:    push {r4, lr}
48; CHECK-T1-NEXT:    mov r2, r1
49; CHECK-T1-NEXT:    movs r1, #0
50; CHECK-T1-NEXT:    ldr r4, [sp, #12]
51; CHECK-T1-NEXT:    ldr r3, [sp, #8]
52; CHECK-T1-NEXT:    subs r3, r0, r3
53; CHECK-T1-NEXT:    sbcs r2, r4
54; CHECK-T1-NEXT:    mov r0, r1
55; CHECK-T1-NEXT:    adcs r0, r1
56; CHECK-T1-NEXT:    movs r4, #1
57; CHECK-T1-NEXT:    subs r4, r4, r0
58; CHECK-T1-NEXT:    mov r0, r1
59; CHECK-T1-NEXT:    beq .LBB1_3
60; CHECK-T1-NEXT:  @ %bb.1:
61; CHECK-T1-NEXT:    cmp r4, #0
62; CHECK-T1-NEXT:    beq .LBB1_4
63; CHECK-T1-NEXT:  .LBB1_2:
64; CHECK-T1-NEXT:    pop {r4, pc}
65; CHECK-T1-NEXT:  .LBB1_3:
66; CHECK-T1-NEXT:    mov r0, r3
67; CHECK-T1-NEXT:    cmp r4, #0
68; CHECK-T1-NEXT:    bne .LBB1_2
69; CHECK-T1-NEXT:  .LBB1_4:
70; CHECK-T1-NEXT:    mov r1, r2
71; CHECK-T1-NEXT:    pop {r4, pc}
72;
73; CHECK-T2-LABEL: func64:
74; CHECK-T2:       @ %bb.0:
75; CHECK-T2-NEXT:    ldrd r2, r3, [sp]
76; CHECK-T2-NEXT:    mov.w r12, #0
77; CHECK-T2-NEXT:    subs r0, r0, r2
78; CHECK-T2-NEXT:    sbcs r1, r3
79; CHECK-T2-NEXT:    adc r2, r12, #0
80; CHECK-T2-NEXT:    rsbs.w r2, r2, #1
81; CHECK-T2-NEXT:    itt ne
82; CHECK-T2-NEXT:    movne r0, #0
83; CHECK-T2-NEXT:    movne r1, #0
84; CHECK-T2-NEXT:    bx lr
85;
86; CHECK-ARM-LABEL: func64:
87; CHECK-ARM:       @ %bb.0:
88; CHECK-ARM-NEXT:    ldr r2, [sp]
89; CHECK-ARM-NEXT:    mov r12, #0
90; CHECK-ARM-NEXT:    ldr r3, [sp, #4]
91; CHECK-ARM-NEXT:    subs r0, r0, r2
92; CHECK-ARM-NEXT:    sbcs r1, r1, r3
93; CHECK-ARM-NEXT:    adc r2, r12, #0
94; CHECK-ARM-NEXT:    rsbs r2, r2, #1
95; CHECK-ARM-NEXT:    movwne r0, #0
96; CHECK-ARM-NEXT:    movwne r1, #0
97; CHECK-ARM-NEXT:    bx lr
98  %a = mul i64 %y, %z
99  %tmp = call i64 @llvm.usub.sat.i64(i64 %x, i64 %z)
100  ret i64 %tmp
101}
102
103define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y, i16 zeroext %z) nounwind {
104; CHECK-T1-LABEL: func16:
105; CHECK-T1:       @ %bb.0:
106; CHECK-T1-NEXT:    muls r1, r2, r1
107; CHECK-T1-NEXT:    uxth r1, r1
108; CHECK-T1-NEXT:    subs r0, r0, r1
109; CHECK-T1-NEXT:    bhs .LBB2_2
110; CHECK-T1-NEXT:  @ %bb.1:
111; CHECK-T1-NEXT:    movs r0, #0
112; CHECK-T1-NEXT:  .LBB2_2:
113; CHECK-T1-NEXT:    uxth r0, r0
114; CHECK-T1-NEXT:    bx lr
115;
116; CHECK-T2-LABEL: func16:
117; CHECK-T2:       @ %bb.0:
118; CHECK-T2-NEXT:    muls r1, r2, r1
119; CHECK-T2-NEXT:    uxth r1, r1
120; CHECK-T2-NEXT:    subs r0, r0, r1
121; CHECK-T2-NEXT:    it lo
122; CHECK-T2-NEXT:    movlo r0, #0
123; CHECK-T2-NEXT:    uxth r0, r0
124; CHECK-T2-NEXT:    bx lr
125;
126; CHECK-ARM-LABEL: func16:
127; CHECK-ARM:       @ %bb.0:
128; CHECK-ARM-NEXT:    mul r1, r1, r2
129; CHECK-ARM-NEXT:    uxth r1, r1
130; CHECK-ARM-NEXT:    subs r0, r0, r1
131; CHECK-ARM-NEXT:    movlo r0, #0
132; CHECK-ARM-NEXT:    uxth r0, r0
133; CHECK-ARM-NEXT:    bx lr
134  %a = mul i16 %y, %z
135  %tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %a)
136  ret i16 %tmp
137}
138
139define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y, i8 zeroext %z) nounwind {
140; CHECK-T1-LABEL: func8:
141; CHECK-T1:       @ %bb.0:
142; CHECK-T1-NEXT:    muls r1, r2, r1
143; CHECK-T1-NEXT:    uxtb r1, r1
144; CHECK-T1-NEXT:    subs r0, r0, r1
145; CHECK-T1-NEXT:    bhs .LBB3_2
146; CHECK-T1-NEXT:  @ %bb.1:
147; CHECK-T1-NEXT:    movs r0, #0
148; CHECK-T1-NEXT:  .LBB3_2:
149; CHECK-T1-NEXT:    uxtb r0, r0
150; CHECK-T1-NEXT:    bx lr
151;
152; CHECK-T2-LABEL: func8:
153; CHECK-T2:       @ %bb.0:
154; CHECK-T2-NEXT:    muls r1, r2, r1
155; CHECK-T2-NEXT:    uxtb r1, r1
156; CHECK-T2-NEXT:    subs r0, r0, r1
157; CHECK-T2-NEXT:    it lo
158; CHECK-T2-NEXT:    movlo r0, #0
159; CHECK-T2-NEXT:    uxtb r0, r0
160; CHECK-T2-NEXT:    bx lr
161;
162; CHECK-ARM-LABEL: func8:
163; CHECK-ARM:       @ %bb.0:
164; CHECK-ARM-NEXT:    smulbb r1, r1, r2
165; CHECK-ARM-NEXT:    uxtb r1, r1
166; CHECK-ARM-NEXT:    subs r0, r0, r1
167; CHECK-ARM-NEXT:    movlo r0, #0
168; CHECK-ARM-NEXT:    uxtb r0, r0
169; CHECK-ARM-NEXT:    bx lr
170  %a = mul i8 %y, %z
171  %tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %a)
172  ret i8 %tmp
173}
174
175define zeroext i4 @func4(i4 zeroext %x, i4 zeroext %y, i4 zeroext %z) nounwind {
176; CHECK-T1-LABEL: func4:
177; CHECK-T1:       @ %bb.0:
178; CHECK-T1-NEXT:    muls r1, r2, r1
179; CHECK-T1-NEXT:    movs r2, #15
180; CHECK-T1-NEXT:    ands r1, r2
181; CHECK-T1-NEXT:    subs r0, r0, r1
182; CHECK-T1-NEXT:    bhs .LBB4_2
183; CHECK-T1-NEXT:  @ %bb.1:
184; CHECK-T1-NEXT:    movs r0, #0
185; CHECK-T1-NEXT:  .LBB4_2:
186; CHECK-T1-NEXT:    ands r0, r2
187; CHECK-T1-NEXT:    bx lr
188;
189; CHECK-T2-LABEL: func4:
190; CHECK-T2:       @ %bb.0:
191; CHECK-T2-NEXT:    muls r1, r2, r1
192; CHECK-T2-NEXT:    and r1, r1, #15
193; CHECK-T2-NEXT:    subs r0, r0, r1
194; CHECK-T2-NEXT:    it lo
195; CHECK-T2-NEXT:    movlo r0, #0
196; CHECK-T2-NEXT:    and r0, r0, #15
197; CHECK-T2-NEXT:    bx lr
198;
199; CHECK-ARM-LABEL: func4:
200; CHECK-ARM:       @ %bb.0:
201; CHECK-ARM-NEXT:    smulbb r1, r1, r2
202; CHECK-ARM-NEXT:    and r1, r1, #15
203; CHECK-ARM-NEXT:    subs r0, r0, r1
204; CHECK-ARM-NEXT:    movlo r0, #0
205; CHECK-ARM-NEXT:    and r0, r0, #15
206; CHECK-ARM-NEXT:    bx lr
207  %a = mul i4 %y, %z
208  %tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %a)
209  ret i4 %tmp
210}
211