1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
3; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2
4; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2
5; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM
6
7declare i4 @llvm.usub.sat.i4(i4, i4)
8declare i8 @llvm.usub.sat.i8(i8, i8)
9declare i16 @llvm.usub.sat.i16(i16, i16)
10declare i32 @llvm.usub.sat.i32(i32, i32)
11declare i64 @llvm.usub.sat.i64(i64, i64)
12
13define i32 @func(i32 %x, i32 %y) nounwind {
14; CHECK-T1-LABEL: func:
15; CHECK-T1:       @ %bb.0:
16; CHECK-T1-NEXT:    subs r0, r0, r1
17; CHECK-T1-NEXT:    bhs .LBB0_2
18; CHECK-T1-NEXT:  @ %bb.1:
19; CHECK-T1-NEXT:    movs r0, #0
20; CHECK-T1-NEXT:  .LBB0_2:
21; CHECK-T1-NEXT:    bx lr
22;
23; CHECK-T2-LABEL: func:
24; CHECK-T2:       @ %bb.0:
25; CHECK-T2-NEXT:    subs r0, r0, r1
26; CHECK-T2-NEXT:    it lo
27; CHECK-T2-NEXT:    movlo r0, #0
28; CHECK-T2-NEXT:    bx lr
29;
30; CHECK-ARM-LABEL: func:
31; CHECK-ARM:       @ %bb.0:
32; CHECK-ARM-NEXT:    subs r0, r0, r1
33; CHECK-ARM-NEXT:    movlo r0, #0
34; CHECK-ARM-NEXT:    bx lr
35  %tmp = call i32 @llvm.usub.sat.i32(i32 %x, i32 %y)
36  ret i32 %tmp
37}
38
39define i64 @func2(i64 %x, i64 %y) nounwind {
40; CHECK-T1-LABEL: func2:
41; CHECK-T1:       @ %bb.0:
42; CHECK-T1-NEXT:    .save {r4, lr}
43; CHECK-T1-NEXT:    push {r4, lr}
44; CHECK-T1-NEXT:    mov r4, r1
45; CHECK-T1-NEXT:    movs r1, #0
46; CHECK-T1-NEXT:    subs r2, r0, r2
47; CHECK-T1-NEXT:    sbcs r4, r3
48; CHECK-T1-NEXT:    mov r0, r1
49; CHECK-T1-NEXT:    adcs r0, r1
50; CHECK-T1-NEXT:    movs r3, #1
51; CHECK-T1-NEXT:    subs r3, r3, r0
52; CHECK-T1-NEXT:    mov r0, r1
53; CHECK-T1-NEXT:    beq .LBB1_3
54; CHECK-T1-NEXT:  @ %bb.1:
55; CHECK-T1-NEXT:    cmp r3, #0
56; CHECK-T1-NEXT:    beq .LBB1_4
57; CHECK-T1-NEXT:  .LBB1_2:
58; CHECK-T1-NEXT:    pop {r4, pc}
59; CHECK-T1-NEXT:  .LBB1_3:
60; CHECK-T1-NEXT:    mov r0, r2
61; CHECK-T1-NEXT:    cmp r3, #0
62; CHECK-T1-NEXT:    bne .LBB1_2
63; CHECK-T1-NEXT:  .LBB1_4:
64; CHECK-T1-NEXT:    mov r1, r4
65; CHECK-T1-NEXT:    pop {r4, pc}
66;
67; CHECK-T2-LABEL: func2:
68; CHECK-T2:       @ %bb.0:
69; CHECK-T2-NEXT:    subs r0, r0, r2
70; CHECK-T2-NEXT:    mov.w r12, #0
71; CHECK-T2-NEXT:    sbcs r1, r3
72; CHECK-T2-NEXT:    adc r2, r12, #0
73; CHECK-T2-NEXT:    rsbs.w r2, r2, #1
74; CHECK-T2-NEXT:    itt ne
75; CHECK-T2-NEXT:    movne r0, #0
76; CHECK-T2-NEXT:    movne r1, #0
77; CHECK-T2-NEXT:    bx lr
78;
79; CHECK-ARM-LABEL: func2:
80; CHECK-ARM:       @ %bb.0:
81; CHECK-ARM-NEXT:    subs r0, r0, r2
82; CHECK-ARM-NEXT:    mov r12, #0
83; CHECK-ARM-NEXT:    sbcs r1, r1, r3
84; CHECK-ARM-NEXT:    adc r2, r12, #0
85; CHECK-ARM-NEXT:    rsbs r2, r2, #1
86; CHECK-ARM-NEXT:    movwne r0, #0
87; CHECK-ARM-NEXT:    movwne r1, #0
88; CHECK-ARM-NEXT:    bx lr
89  %tmp = call i64 @llvm.usub.sat.i64(i64 %x, i64 %y)
90  ret i64 %tmp
91}
92
93define zeroext i16 @func16(i16 zeroext %x, i16 zeroext %y) nounwind {
94; CHECK-T1-LABEL: func16:
95; CHECK-T1:       @ %bb.0:
96; CHECK-T1-NEXT:    subs r0, r0, r1
97; CHECK-T1-NEXT:    bhs .LBB2_2
98; CHECK-T1-NEXT:  @ %bb.1:
99; CHECK-T1-NEXT:    movs r0, #0
100; CHECK-T1-NEXT:  .LBB2_2:
101; CHECK-T1-NEXT:    uxth r0, r0
102; CHECK-T1-NEXT:    bx lr
103;
104; CHECK-T2-LABEL: func16:
105; CHECK-T2:       @ %bb.0:
106; CHECK-T2-NEXT:    subs r0, r0, r1
107; CHECK-T2-NEXT:    it lo
108; CHECK-T2-NEXT:    movlo r0, #0
109; CHECK-T2-NEXT:    uxth r0, r0
110; CHECK-T2-NEXT:    bx lr
111;
112; CHECK-ARM-LABEL: func16:
113; CHECK-ARM:       @ %bb.0:
114; CHECK-ARM-NEXT:    subs r0, r0, r1
115; CHECK-ARM-NEXT:    movlo r0, #0
116; CHECK-ARM-NEXT:    uxth r0, r0
117; CHECK-ARM-NEXT:    bx lr
118  %tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %y)
119  ret i16 %tmp
120}
121
122define zeroext i8 @func8(i8 zeroext %x, i8 zeroext %y) nounwind {
123; CHECK-T1-LABEL: func8:
124; CHECK-T1:       @ %bb.0:
125; CHECK-T1-NEXT:    subs r0, r0, r1
126; CHECK-T1-NEXT:    bhs .LBB3_2
127; CHECK-T1-NEXT:  @ %bb.1:
128; CHECK-T1-NEXT:    movs r0, #0
129; CHECK-T1-NEXT:  .LBB3_2:
130; CHECK-T1-NEXT:    uxtb r0, r0
131; CHECK-T1-NEXT:    bx lr
132;
133; CHECK-T2-LABEL: func8:
134; CHECK-T2:       @ %bb.0:
135; CHECK-T2-NEXT:    subs r0, r0, r1
136; CHECK-T2-NEXT:    it lo
137; CHECK-T2-NEXT:    movlo r0, #0
138; CHECK-T2-NEXT:    uxtb r0, r0
139; CHECK-T2-NEXT:    bx lr
140;
141; CHECK-ARM-LABEL: func8:
142; CHECK-ARM:       @ %bb.0:
143; CHECK-ARM-NEXT:    subs r0, r0, r1
144; CHECK-ARM-NEXT:    movlo r0, #0
145; CHECK-ARM-NEXT:    uxtb r0, r0
146; CHECK-ARM-NEXT:    bx lr
147  %tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %y)
148  ret i8 %tmp
149}
150
151define zeroext i4 @func3(i4 zeroext %x, i4 zeroext %y) nounwind {
152; CHECK-T1-LABEL: func3:
153; CHECK-T1:       @ %bb.0:
154; CHECK-T1-NEXT:    subs r1, r0, r1
155; CHECK-T1-NEXT:    bhs .LBB4_2
156; CHECK-T1-NEXT:  @ %bb.1:
157; CHECK-T1-NEXT:    movs r1, #0
158; CHECK-T1-NEXT:  .LBB4_2:
159; CHECK-T1-NEXT:    movs r0, #15
160; CHECK-T1-NEXT:    ands r0, r1
161; CHECK-T1-NEXT:    bx lr
162;
163; CHECK-T2-LABEL: func3:
164; CHECK-T2:       @ %bb.0:
165; CHECK-T2-NEXT:    subs r0, r0, r1
166; CHECK-T2-NEXT:    it lo
167; CHECK-T2-NEXT:    movlo r0, #0
168; CHECK-T2-NEXT:    and r0, r0, #15
169; CHECK-T2-NEXT:    bx lr
170;
171; CHECK-ARM-LABEL: func3:
172; CHECK-ARM:       @ %bb.0:
173; CHECK-ARM-NEXT:    subs r0, r0, r1
174; CHECK-ARM-NEXT:    movlo r0, #0
175; CHECK-ARM-NEXT:    and r0, r0, #15
176; CHECK-ARM-NEXT:    bx lr
177  %tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %y)
178  ret i4 %tmp
179}
180