1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=arm-eabi -mcpu=krait | FileCheck %s 3 4define void @func1(i16* %a, i16* %b, i16* %c) { 5; CHECK-LABEL: func1: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: add r3, r1, #16 8; CHECK-NEXT: vldr d18, [r2, #16] 9; CHECK-NEXT: vld1.16 {d16}, [r3:64] 10; CHECK-NEXT: vmovl.u16 q8, d16 11; CHECK-NEXT: vaddw.s16 q10, q8, d18 12; CHECK-NEXT: vmovn.i32 d19, q10 13; CHECK-NEXT: vldr d20, [r0, #16] 14; CHECK-NEXT: vstr d19, [r0, #16] 15; CHECK-NEXT: vldr d19, [r2, #16] 16; CHECK-NEXT: vmull.s16 q11, d18, d19 17; CHECK-NEXT: vmovl.s16 q9, d19 18; CHECK-NEXT: vmla.i32 q11, q8, q9 19; CHECK-NEXT: vmovn.i32 d16, q11 20; CHECK-NEXT: vstr d16, [r1, #16] 21; CHECK-NEXT: vldr d16, [r2, #16] 22; CHECK-NEXT: vmlal.s16 q11, d16, d20 23; CHECK-NEXT: vmovn.i32 d16, q11 24; CHECK-NEXT: vstr d16, [r0, #16] 25; CHECK-NEXT: bx lr 26entry: 27; The test case trying to vectorize the pseudo code below. 28; a[i] = b[i] + c[i]; 29; b[i] = a[i] * c[i]; 30; a[i] = b[i] + a[i] * c[i]; 31; Checking that vector load a[i] for "a[i] = b[i] + a[i] * c[i]" is 32; scheduled before the first vector store to "a[i] = b[i] + c[i]". 33; Checking that there is no vector load a[i] scheduled between the vector 34; stores to a[i], otherwise the load of a[i] will be polluted by the first 35; vector store to a[i]. 36; This test case check that the chain information is updated during 37; lowerMUL for the new created Load SDNode. 38 39 40 %scevgep0 = getelementptr i16, i16* %a, i32 8 41 %vector_ptr0 = bitcast i16* %scevgep0 to <4 x i16>* 42 %vec0 = load <4 x i16>, <4 x i16>* %vector_ptr0, align 8 43 %scevgep1 = getelementptr i16, i16* %b, i32 8 44 %vector_ptr1 = bitcast i16* %scevgep1 to <4 x i16>* 45 %vec1 = load <4 x i16>, <4 x i16>* %vector_ptr1, align 8 46 %0 = zext <4 x i16> %vec1 to <4 x i32> 47 %scevgep2 = getelementptr i16, i16* %c, i32 8 48 %vector_ptr2 = bitcast i16* %scevgep2 to <4 x i16>* 49 %vec2 = load <4 x i16>, <4 x i16>* %vector_ptr2, align 8 50 %1 = sext <4 x i16> %vec2 to <4 x i32> 51 %vec3 = add <4 x i32> %1, %0 52 %2 = trunc <4 x i32> %vec3 to <4 x i16> 53 %scevgep3 = getelementptr i16, i16* %a, i32 8 54 %vector_ptr3 = bitcast i16* %scevgep3 to <4 x i16>* 55 store <4 x i16> %2, <4 x i16>* %vector_ptr3, align 8 56 %vector_ptr4 = bitcast i16* %scevgep2 to <4 x i16>* 57 %vec4 = load <4 x i16>, <4 x i16>* %vector_ptr4, align 8 58 %3 = sext <4 x i16> %vec4 to <4 x i32> 59 %vec5 = mul <4 x i32> %3, %vec3 60 %4 = trunc <4 x i32> %vec5 to <4 x i16> 61 %vector_ptr5 = bitcast i16* %scevgep1 to <4 x i16>* 62 store <4 x i16> %4, <4 x i16>* %vector_ptr5, align 8 63 %5 = sext <4 x i16> %vec0 to <4 x i32> 64 %vector_ptr6 = bitcast i16* %scevgep2 to <4 x i16>* 65 %vec6 = load <4 x i16>, <4 x i16>* %vector_ptr6, align 8 66 %6 = sext <4 x i16> %vec6 to <4 x i32> 67 %vec7 = mul <4 x i32> %6, %5 68 %vec8 = add <4 x i32> %vec7, %vec5 69 %7 = trunc <4 x i32> %vec8 to <4 x i16> 70 %vector_ptr7 = bitcast i16* %scevgep3 to <4 x i16>* 71 store <4 x i16> %7, <4 x i16>* %vector_ptr7, align 8 72 ret void 73} 74 75define void @func2(i16* %a, i16* %b, i16* %c) { 76; CHECK-LABEL: func2: 77; CHECK: @ %bb.0: @ %entry 78; CHECK-NEXT: add r3, r1, #16 79; CHECK-NEXT: vldr d18, [r2, #16] 80; CHECK-NEXT: vld1.16 {d16}, [r3:64] 81; CHECK-NEXT: vmovl.u16 q8, d16 82; CHECK-NEXT: vaddw.s16 q10, q8, d18 83; CHECK-NEXT: vmovn.i32 d19, q10 84; CHECK-NEXT: vldr d20, [r0, #16] 85; CHECK-NEXT: vstr d19, [r0, #16] 86; CHECK-NEXT: vldr d19, [r2, #16] 87; CHECK-NEXT: vmull.s16 q11, d18, d19 88; CHECK-NEXT: vmovl.s16 q9, d19 89; CHECK-NEXT: vmla.i32 q11, q8, q9 90; CHECK-NEXT: vmovn.i32 d16, q11 91; CHECK-NEXT: vstr d16, [r1, #16] 92; CHECK-NEXT: vldr d16, [r2, #16] 93; CHECK-NEXT: vmlal.s16 q11, d16, d20 94; CHECK-NEXT: vaddw.s16 q8, q11, d20 95; CHECK-NEXT: vmovn.i32 d16, q8 96; CHECK-NEXT: vstr d16, [r0, #16] 97; CHECK-NEXT: bx lr 98entry: 99; The test case trying to vectorize the pseudo code below. 100; a[i] = b[i] + c[i]; 101; b[i] = a[i] * c[i]; 102; a[i] = b[i] + a[i] * c[i] + a[i]; 103; Checking that vector load a[i] for "a[i] = b[i] + a[i] * c[i] + a[i]" 104; is scheduled before the first vector store to "a[i] = b[i] + c[i]". 105; Checking that there is no vector load a[i] scheduled between the first 106; vector store to a[i] and the vector add of a[i], otherwise the load of 107; a[i] will be polluted by the first vector store to a[i]. 108; This test case check that both the chain and value of the new created 109; Load SDNode are updated during lowerMUL. 110 111 112 %scevgep0 = getelementptr i16, i16* %a, i32 8 113 %vector_ptr0 = bitcast i16* %scevgep0 to <4 x i16>* 114 %vec0 = load <4 x i16>, <4 x i16>* %vector_ptr0, align 8 115 %scevgep1 = getelementptr i16, i16* %b, i32 8 116 %vector_ptr1 = bitcast i16* %scevgep1 to <4 x i16>* 117 %vec1 = load <4 x i16>, <4 x i16>* %vector_ptr1, align 8 118 %0 = zext <4 x i16> %vec1 to <4 x i32> 119 %scevgep2 = getelementptr i16, i16* %c, i32 8 120 %vector_ptr2 = bitcast i16* %scevgep2 to <4 x i16>* 121 %vec2 = load <4 x i16>, <4 x i16>* %vector_ptr2, align 8 122 %1 = sext <4 x i16> %vec2 to <4 x i32> 123 %vec3 = add <4 x i32> %1, %0 124 %2 = trunc <4 x i32> %vec3 to <4 x i16> 125 %scevgep3 = getelementptr i16, i16* %a, i32 8 126 %vector_ptr3 = bitcast i16* %scevgep3 to <4 x i16>* 127 store <4 x i16> %2, <4 x i16>* %vector_ptr3, align 8 128 %vector_ptr4 = bitcast i16* %scevgep2 to <4 x i16>* 129 %vec4 = load <4 x i16>, <4 x i16>* %vector_ptr4, align 8 130 %3 = sext <4 x i16> %vec4 to <4 x i32> 131 %vec5 = mul <4 x i32> %3, %vec3 132 %4 = trunc <4 x i32> %vec5 to <4 x i16> 133 %vector_ptr5 = bitcast i16* %scevgep1 to <4 x i16>* 134 store <4 x i16> %4, <4 x i16>* %vector_ptr5, align 8 135 %5 = sext <4 x i16> %vec0 to <4 x i32> 136 %vector_ptr6 = bitcast i16* %scevgep2 to <4 x i16>* 137 %vec6 = load <4 x i16>, <4 x i16>* %vector_ptr6, align 8 138 %6 = sext <4 x i16> %vec6 to <4 x i32> 139 %vec7 = mul <4 x i32> %6, %5 140 %vec8 = add <4 x i32> %vec7, %vec5 141 %vec9 = add <4 x i32> %vec8, %5 142 %7 = trunc <4 x i32> %vec9 to <4 x i16> 143 %vector_ptr7 = bitcast i16* %scevgep3 to <4 x i16>* 144 store <4 x i16> %7, <4 x i16>* %vector_ptr7, align 8 145 ret void 146} 147