1; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=v7
2; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv4t-apple-ios | FileCheck %s --check-prefix=prev6
3; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv5-apple-ios | FileCheck %s --check-prefix=prev6
4; RUN: llc < %s -O0 -fast-isel-abort -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=v7
5
6; Can't test pre-ARMv6 Thumb because ARM FastISel currently only supports
7; Thumb2. The ARMFastISel::ARMEmitIntExt code should work for Thumb by always
8; using two shifts.
9
10; Note that lsl, asr and lsr in Thumb are all encoded as 16-bit instructions
11; and therefore must set flags. {{s?}} below denotes this, instead of
12; duplicating tests.
13
14; zext
15
16define i8 @zext_1_8(i1 %a) nounwind ssp {
17; v7: zext_1_8:
18; v7: and r0, r0, #1
19; prev6: zext_1_8:
20; prev6: and r0, r0, #1
21  %r = zext i1 %a to i8
22  ret i8 %r
23}
24
25define i16 @zext_1_16(i1 %a) nounwind ssp {
26; v7: zext_1_16:
27; v7: and r0, r0, #1
28; prev6: zext_1_16:
29; prev6: and r0, r0, #1
30  %r = zext i1 %a to i16
31  ret i16 %r
32}
33
34define i32 @zext_1_32(i1 %a) nounwind ssp {
35; v7: zext_1_32:
36; v7: and r0, r0, #1
37; prev6: zext_1_32:
38; prev6: and r0, r0, #1
39  %r = zext i1 %a to i32
40  ret i32 %r
41}
42
43define i16 @zext_8_16(i8 %a) nounwind ssp {
44; v7: zext_8_16:
45; v7: and r0, r0, #255
46; prev6: zext_8_16:
47; prev6: and r0, r0, #255
48  %r = zext i8 %a to i16
49  ret i16 %r
50}
51
52define i32 @zext_8_32(i8 %a) nounwind ssp {
53; v7: zext_8_32:
54; v7: and r0, r0, #255
55; prev6: zext_8_32:
56; prev6: and r0, r0, #255
57  %r = zext i8 %a to i32
58  ret i32 %r
59}
60
61define i32 @zext_16_32(i16 %a) nounwind ssp {
62; v7: zext_16_32:
63; v7: uxth r0, r0
64; prev6: zext_16_32:
65; prev6: lsl{{s?}} r0, r0, #16
66; prev6: lsr{{s?}} r0, r0, #16
67  %r = zext i16 %a to i32
68  ret i32 %r
69}
70
71; sext
72
73define i8 @sext_1_8(i1 %a) nounwind ssp {
74; v7: sext_1_8:
75; v7: lsl{{s?}} r0, r0, #31
76; v7: asr{{s?}} r0, r0, #31
77; prev6: sext_1_8:
78; prev6: lsl{{s?}} r0, r0, #31
79; prev6: asr{{s?}} r0, r0, #31
80  %r = sext i1 %a to i8
81  ret i8 %r
82}
83
84define i16 @sext_1_16(i1 %a) nounwind ssp {
85; v7: sext_1_16:
86; v7: lsl{{s?}} r0, r0, #31
87; v7: asr{{s?}} r0, r0, #31
88; prev6: sext_1_16:
89; prev6: lsl{{s?}} r0, r0, #31
90; prev6: asr{{s?}} r0, r0, #31
91  %r = sext i1 %a to i16
92  ret i16 %r
93}
94
95define i32 @sext_1_32(i1 %a) nounwind ssp {
96; v7: sext_1_32:
97; v7: lsl{{s?}} r0, r0, #31
98; v7: asr{{s?}} r0, r0, #31
99; prev6: sext_1_32:
100; prev6: lsl{{s?}} r0, r0, #31
101; prev6: asr{{s?}} r0, r0, #31
102  %r = sext i1 %a to i32
103  ret i32 %r
104}
105
106define i16 @sext_8_16(i8 %a) nounwind ssp {
107; v7: sext_8_16:
108; v7: sxtb r0, r0
109; prev6: sext_8_16:
110; prev6: lsl{{s?}} r0, r0, #24
111; prev6: asr{{s?}} r0, r0, #24
112  %r = sext i8 %a to i16
113  ret i16 %r
114}
115
116define i32 @sext_8_32(i8 %a) nounwind ssp {
117; v7: sext_8_32:
118; v7: sxtb r0, r0
119; prev6: sext_8_32:
120; prev6: lsl{{s?}} r0, r0, #24
121; prev6: asr{{s?}} r0, r0, #24
122  %r = sext i8 %a to i32
123  ret i32 %r
124}
125
126define i32 @sext_16_32(i16 %a) nounwind ssp {
127; v7: sext_16_32:
128; v7: sxth r0, r0
129; prev6: sext_16_32:
130; prev6: lsl{{s?}} r0, r0, #16
131; prev6: asr{{s?}} r0, r0, #16
132  %r = sext i16 %a to i32
133  ret i32 %r
134}
135