1; RUN: llc -mtriple=armv7 -mattr=+neon -mcpu=swift %s -o - | FileCheck %s 2; RUN: llc -mtriple=armv7 -mattr=+neon -mcpu=cortex-a8 %s -o - | FileCheck --check-prefix=CHECK-NONEONFP %s 3; RUN: llc -mtriple=armv7 -mattr=-neon -mcpu=cortex-a8 %s -o - | FileCheck --check-prefix=CHECK-NONEON %s 4 5; RUN: llc -mtriple=thumbv7m -mcpu=cortex-m4 %s -o - \ 6; RUN: | FileCheck --check-prefix=CHECK-NO-XO %s 7 8; RUN: llc -mtriple=thumbv7m -arm-execute-only -mcpu=cortex-m4 %s -o - \ 9; RUN: | FileCheck --check-prefix=CHECK-XO-FLOAT --check-prefix=CHECK-XO-DOUBLE %s 10 11; RUN: llc -mtriple=thumbv7meb -arm-execute-only -mcpu=cortex-m4 %s -o - \ 12; RUN: | FileCheck --check-prefix=CHECK-XO-FLOAT --check-prefix=CHECK-XO-DOUBLE-BE %s 13 14; RUN: llc -mtriple=thumbv8m.main -mattr=fp-armv8 %s -o - \ 15; RUN: | FileCheck --check-prefix=CHECK-NO-XO %s 16 17; RUN: llc -mtriple=thumbv8m.main -arm-execute-only -mattr=fp-armv8 %s -o - \ 18; RUN: | FileCheck --check-prefix=CHECK-XO-FLOAT --check-prefix=CHECK-XO-DOUBLE %s 19 20; RUN: llc -mtriple=thumbv8m.maineb -arm-execute-only -mattr=fp-armv8 %s -o - \ 21; RUN: | FileCheck --check-prefix=CHECK-XO-FLOAT --check-prefix=CHECK-XO-DOUBLE-BE %s 22 23 24define arm_aapcs_vfpcc float @test_vmov_f32() { 25; CHECK-LABEL: test_vmov_f32: 26; CHECK: vmov.f32 d0, #1.0 27 28; CHECK-NONEONFP: vmov.f32 s0, #1.0 29 ret float 1.0 30} 31 32define arm_aapcs_vfpcc float @test_vmov_imm() { 33; CHECK-LABEL: test_vmov_imm: 34; CHECK: vmov.i32 d0, #0 35 36; CHECK-NONEON-LABEL: test_vmov_imm: 37; CHECK-NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}} 38 39; CHECK-NO-XO-LABEL: test_vmov_imm: 40; CHECK-NO-XO: vldr s0, {{.?LCPI[0-9]+_[0-9]+}} 41 42; CHECK-XO-FLOAT-LABEL: test_vmov_imm: 43; CHECK-XO-FLOAT: movs [[REG:r[0-9]+]], #0 44; CHECK-XO-FLOAT: vmov {{s[0-9]+}}, [[REG]] 45; CHECK-XO-FLOAT-NOT: vldr 46 ret float 0.0 47} 48 49define arm_aapcs_vfpcc float @test_vmvn_imm() { 50; CHECK-LABEL: test_vmvn_imm: 51; CHECK: vmvn.i32 d0, #0xb0000000 52 53; CHECK-NONEON-LABEL: test_vmvn_imm: 54; CHECK-NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}} 55 56; CHECK-NO-XO-LABEL: test_vmvn_imm: 57; CHECK-NO-XO: vldr s0, {{.?LCPI[0-9]+_[0-9]+}} 58 59; CHECK-XO-FLOAT-LABEL: test_vmvn_imm: 60; CHECK-XO-FLOAT: mvn [[REG:r[0-9]+]], #-1342177280 61; CHECK-XO-FLOAT: vmov {{s[0-9]+}}, [[REG]] 62; CHECK-XO-FLOAT-NOT: vldr 63 ret float 8589934080.0 64} 65 66define arm_aapcs_vfpcc double @test_vmov_f64() { 67; CHECK-LABEL: test_vmov_f64: 68; CHECK: vmov.f64 d0, #1.0 69 70; CHECK-NONEON-LABEL: test_vmov_f64: 71; CHECK-NONEON: vmov.f64 d0, #1.0 72 73 ret double 1.0 74} 75 76define arm_aapcs_vfpcc double @test_vmov_double_imm() { 77; CHECK-LABEL: test_vmov_double_imm: 78; CHECK: vmov.i32 d0, #0 79 80; CHECK-NONEON-LABEL: test_vmov_double_imm: 81; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} 82 83; CHECK-NO-XO-LABEL: test_vmov_double_imm: 84; CHECK-NO-XO: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} 85 86; CHECK-XO-DOUBLE-LABEL: test_vmov_double_imm: 87; CHECK-XO-DOUBLE: movs [[REG:r[0-9]+]], #0 88; CHECK-XO-DOUBLE: vmov {{d[0-9]+}}, [[REG]], [[REG]] 89; CHECK-XO-DOUBLE-NOT: vldr 90 91; CHECK-XO-DOUBLE-BE-LABEL: test_vmov_double_imm: 92; CHECK-XO-DOUBLE-BE: movs [[REG:r[0-9]+]], #0 93; CHECK-XO-DOUBLE-BE: vmov {{d[0-9]+}}, [[REG]], [[REG]] 94; CHECK-XO-DOUBLE-NOT: vldr 95 ret double 0.0 96} 97 98define arm_aapcs_vfpcc double @test_vmvn_double_imm() { 99; CHECK-LABEL: test_vmvn_double_imm: 100; CHECK: vmvn.i32 d0, #0xb0000000 101 102; CHECK-NONEON-LABEL: test_vmvn_double_imm: 103; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} 104 105; CHECK-NO-XO-LABEL: test_vmvn_double_imm: 106; CHECK-NO-XO: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} 107 108; CHECK-XO-DOUBLE-LABEL: test_vmvn_double_imm: 109; CHECK-XO-DOUBLE: mvn [[REG:r[0-9]+]], #-1342177280 110; CHECK-XO-DOUBLE: vmov {{d[0-9]+}}, [[REG]], [[REG]] 111; CHECK-XO-DOUBLE-NOT: vldr 112 113; CHECK-XO-DOUBLE-BE-LABEL: test_vmvn_double_imm: 114; CHECK-XO-DOUBLE-BE: mvn [[REG:r[0-9]+]], #-1342177280 115; CHECK-XO-DOUBLE-BE: vmov {{d[0-9]+}}, [[REG]], [[REG]] 116; CHECK-XO-DOUBLE-BE-NOT: vldr 117 ret double 0x4fffffff4fffffff 118} 119 120; Make sure we don't ignore the high half of 64-bit values when deciding whether 121; a vmov/vmvn is possible. 122define arm_aapcs_vfpcc double @test_notvmvn_double_imm() { 123; CHECK-LABEL: test_notvmvn_double_imm: 124; CHECK: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} 125 126; CHECK-NONEON-LABEL: test_notvmvn_double_imm: 127; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} 128 129; CHECK-NO-XO-LABEL: test_notvmvn_double_imm: 130; CHECK-NO-XO: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} 131 132; CHECK-XO-DOUBLE-LABEL: test_notvmvn_double_imm: 133; CHECK-XO-DOUBLE: mvn [[REG1:r[0-9]+]], #-1342177280 134; CHECK-XO-DOUBLE: mov.w [[REG2:r[0-9]+]], #-1 135; CHECK-XO-DOUBLE: vmov {{d[0-9]+}}, [[REG2]], [[REG1]] 136; CHECK-XO-DOUBLE-NOT: vldr 137 138; CHECK-XO-DOUBLE-BE-LABEL: test_notvmvn_double_imm: 139; CHECK-XO-DOUBLE-BE: mov.w [[REG1:r[0-9]+]], #-1 140; CHECK-XO-DOUBLE-BE: mvn [[REG2:r[0-9]+]], #-1342177280 141; CHECK-XO-DOUBLE-BE: vmov {{d[0-9]+}}, [[REG2]], [[REG1]] 142; CHECK-XO-DOUBLE-BE-NOT: vldr 143 ret double 0x4fffffffffffffff 144} 145 146define arm_aapcs_vfpcc float @lower_const_f32_xo() { 147; CHECK-NO-XO-LABEL: lower_const_f32_xo 148; CHECK-NO-XO: vldr {{s[0-9]+}}, {{.?LCPI[0-9]+_[0-9]+}} 149 150; CHECK-XO-FLOAT-LABEL: lower_const_f32_xo 151; CHECK-XO-FLOAT: movw [[REG:r[0-9]+]], #29884 152; CHECK-XO-FLOAT: movt [[REG]], #16083 153; CHECK-XO-FLOAT: vmov {{s[0-9]+}}, [[REG]] 154; CHECK-XO-FLOAT-NOT: vldr 155 ret float 0x3FDA6E9780000000 156} 157 158define arm_aapcs_vfpcc double @lower_const_f64_xo() { 159; CHECK-NO-XO-LABEL: lower_const_f64_xo 160; CHECK-NO-XO: vldr {{d[0-9]+}}, {{.?LCPI[0-9]+_[0-9]+}} 161 162; CHECK-XO-DOUBLE-LABEL: lower_const_f64_xo 163; CHECK-XO-DOUBLE: movw [[REG1:r[0-9]+]], #6291 164; CHECK-XO-DOUBLE: movw [[REG2:r[0-9]+]], #27263 165; CHECK-XO-DOUBLE: movt [[REG1]], #16340 166; CHECK-XO-DOUBLE: movt [[REG2]], #29884 167; CHECK-XO-DOUBLE: vmov {{d[0-9]+}}, [[REG2]], [[REG1]] 168; CHECK-XO-DOUBLE-NOT: vldr 169 170; CHECK-XO-DOUBLE-BE-LABEL: lower_const_f64_xo 171; CHECK-XO-DOUBLE-BE: movw [[REG1:r[0-9]+]], #27263 172; CHECK-XO-DOUBLE-BE: movw [[REG2:r[0-9]+]], #6291 173; CHECK-XO-DOUBLE-BE: movt [[REG1]], #29884 174; CHECK-XO-DOUBLE-BE: movt [[REG2]], #16340 175; CHECK-XO-DOUBLE-BE: vmov {{d[0-9]+}}, [[REG2]], [[REG1]] 176; CHECK-XO-DOUBLE-BE-NOT: vldr 177 ret double 3.140000e-01 178} 179