1; RUN: llc -mtriple=armv7 %s -o - | FileCheck %s
2; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s --check-prefix=CHECK-T2
3
4define i1 @f1(i32 %a, i32 %b) {
5; CHECK-LABEL: f1:
6; CHECK: mov r2, #0
7; CHECK: cmp r0, r1
8; CHECK: movwne r2, #1
9; CHECK: mov r0, r2
10; CHECK-T2: mov{{.*}} r2, #0
11; CHECK-T2: cmp r0, r1
12; CHECK-T2: movne r2, #1
13; CHECK-T2: mov r0, r2
14    %tmp = icmp ne i32 %a, %b
15    ret i1 %tmp
16}
17
18define i1 @f2(i32 %a, i32 %b) {
19; CHECK-LABEL: f2:
20; CHECK: mov r2, #0
21; CHECK: cmp r0, r1
22; CHECK: movweq r2, #1
23; CHECK: mov r0, r2
24; CHECK-T2: mov{{.*}} r2, #0
25; CHECK-T2: cmp r0, r1
26; CHECK-T2: moveq r2, #1
27; CHECK-T2: mov r0, r2
28    %tmp = icmp eq i32 %a, %b
29    ret i1 %tmp
30}
31
32define i1 @f6(i32 %a, i32 %b) {
33; CHECK-LABEL: f6:
34; CHECK: mov r2, #0
35; CHECK: cmp {{.*}}, r1, lsl #5
36; CHECK: movweq r2, #1
37; CHECK: mov r0, r2
38; CHECK-T2: mov{{.*}} r2, #0
39; CHECK-T2: cmp.w r0, r1, lsl #5
40; CHECK-T2: moveq r2, #1
41; CHECK-T2: mov r0, r2
42    %tmp = shl i32 %b, 5
43    %tmp1 = icmp eq i32 %a, %tmp
44    ret i1 %tmp1
45}
46
47define i1 @f7(i32 %a, i32 %b) {
48; CHECK-LABEL: f7:
49; CHECK: mov r2, #0
50; CHECK: cmp r0, r1, lsr #6
51; CHECK: movwne r2, #1
52; CHECK: mov r0, r2
53; CHECK-T2: mov{{.*}} r2, #0
54; CHECK-T2: cmp.w r0, r1, lsr #6
55; CHECK-T2: movne r2, #1
56; CHECK-T2: mov r0, r2
57    %tmp = lshr i32 %b, 6
58    %tmp1 = icmp ne i32 %a, %tmp
59    ret i1 %tmp1
60}
61
62define i1 @f8(i32 %a, i32 %b) {
63; CHECK-LABEL: f8:
64; CHECK: mov r2, #0
65; CHECK: cmp r0, r1, asr #7
66; CHECK: movweq r2, #1
67; CHECK: mov r0, r2
68; CHECK-T2: mov{{.*}} r2, #0
69; CHECK-T2: cmp.w r0, r1, asr #7
70; CHECK-T2: moveq r2, #1
71; CHECK-T2: mov r0, r2
72    %tmp = ashr i32 %b, 7
73    %tmp1 = icmp eq i32 %a, %tmp
74    ret i1 %tmp1
75}
76
77define i1 @f9(i32 %a) {
78; CHECK-LABEL: f9:
79; CHECK: mov r1, #0
80; CHECK: cmp r0, r0, ror #8
81; CHECK: movwne r1, #1
82; CHECK: mov r0, r1
83; CHECK-T2: mov{{.*}} r1, #0
84; CHECK-T2: cmp.w r0, r0, ror #8
85; CHECK-T2: movne r1, #1
86; CHECK-T2: mov r0, r1
87    %l8 = shl i32 %a, 24
88    %r8 = lshr i32 %a, 8
89    %tmp = or i32 %l8, %r8
90    %tmp1 = icmp ne i32 %a, %tmp
91    ret i1 %tmp1
92}
93
94; CHECK-LABEL: swap_cmp_shl
95; CHECK: mov r2, #0
96; CHECK: cmp r1, r0, lsl #11
97; CHECK: movwlt r2, #1
98; CHECK-T2: mov{{.*}} r2, #0
99; CHECK-T2: cmp.w r1, r0, lsl #11
100; CHECK-T2: movlt r2, #1
101define arm_aapcscc i32 @swap_cmp_shl(i32 %a, i32 %b) {
102entry:
103  %shift = shl i32 %a, 11
104  %cmp = icmp sgt i32 %shift, %b
105  %conv = zext i1 %cmp to i32
106  ret i32 %conv
107}
108
109; CHECK-LABEL: swap_cmp_lshr
110; CHECK: mov r2, #0
111; CHECK: cmp r1, r0, lsr #11
112; CHECK: movwhi r2, #1
113; CHECK-T2: mov{{.*}} r2, #0
114; CHECK-T2: cmp.w r1, r0, lsr #11
115; CHECK-T2: movhi r2, #1
116define arm_aapcscc i32 @swap_cmp_lshr(i32 %a, i32 %b) {
117entry:
118  %shift = lshr i32 %a, 11
119  %cmp = icmp ult i32 %shift, %b
120  %conv = zext i1 %cmp to i32
121  ret i32 %conv
122}
123
124; CHECK-LABEL: swap_cmp_ashr
125; CHECK: mov r2, #0
126; CHECK: cmp r1, r0, asr #11
127; CHECK: movwle r2, #1
128; CHECK-T2: mov{{.*}} r2, #0
129; CHECK-T2: cmp.w r1, r0, asr #11
130; CHECK-T2: movle r2, #1
131define arm_aapcscc i32 @swap_cmp_ashr(i32 %a, i32 %b) {
132entry:
133  %shift = ashr i32 %a, 11
134  %cmp = icmp sge i32 %shift, %b
135  %conv = zext i1 %cmp to i32
136  ret i32 %conv
137}
138
139; CHECK-LABEL: swap_cmp_rotr
140; CHECK: mov r2, #0
141; CHECK: cmp r1, r0, ror #11
142; CHECK: movwls r2, #1
143; CHECK-T2: mov{{.*}} r2, #0
144; CHECK-T2: cmp.w r1, r0, ror #11
145; CHECK-T2: movls r2, #1
146define arm_aapcscc i32 @swap_cmp_rotr(i32 %a, i32 %b) {
147entry:
148  %lsr = lshr i32 %a, 11
149  %lsl = shl i32 %a, 21
150  %ror = or i32 %lsr, %lsl
151  %cmp = icmp uge i32 %ror, %b
152  %conv = zext i1 %cmp to i32
153  ret i32 %conv
154}
155