1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=arm -mattr=+v6t2 | FileCheck %s 3 4%struct.F = type { [3 x i8], i8 } 5 6@X = common global %struct.F zeroinitializer, align 4 ; <%struct.F*> [#uses=1] 7 8define void @f1([1 x i32] %f.coerce0) nounwind { 9; CHECK-LABEL: f1: 10; CHECK: @ %bb.0: @ %entry 11; CHECK-NEXT: movw r0, :lower16:X 12; CHECK-NEXT: mov r2, #10 13; CHECK-NEXT: movt r0, :upper16:X 14; CHECK-NEXT: ldr r1, [r0] 15; CHECK-NEXT: bfi r1, r2, #22, #4 16; CHECK-NEXT: str r1, [r0] 17; CHECK-NEXT: bx lr 18entry: 19 %0 = load i32, i32* bitcast (%struct.F* @X to i32*), align 4 ; <i32> [#uses=1] 20 %1 = and i32 %0, -62914561 ; <i32> [#uses=1] 21 %2 = or i32 %1, 41943040 ; <i32> [#uses=1] 22 store i32 %2, i32* bitcast (%struct.F* @X to i32*), align 4 23 ret void 24} 25 26define i32 @f2(i32 %A, i32 %B) nounwind { 27; CHECK-LABEL: f2: 28; CHECK: @ %bb.0: @ %entry 29; CHECK-NEXT: lsr r1, r1, #7 30; CHECK-NEXT: bfi r0, r1, #7, #16 31; CHECK-NEXT: bx lr 32entry: 33 %and = and i32 %A, -8388481 ; <i32> [#uses=1] 34 %and2 = and i32 %B, 8388480 ; <i32> [#uses=1] 35 %or = or i32 %and2, %and ; <i32> [#uses=1] 36 ret i32 %or 37} 38 39define i32 @f3(i32 %A, i32 %B) nounwind { 40; CHECK-LABEL: f3: 41; CHECK: @ %bb.0: @ %entry 42; CHECK-NEXT: lsr r0, r0, #7 43; CHECK-NEXT: bfi r1, r0, #7, #16 44; CHECK-NEXT: mov r0, r1 45; CHECK-NEXT: bx lr 46entry: 47 %and = and i32 %A, 8388480 ; <i32> [#uses=1] 48 %and2 = and i32 %B, -8388481 ; <i32> [#uses=1] 49 %or = or i32 %and2, %and ; <i32> [#uses=1] 50 ret i32 %or 51} 52 53; rdar://8752056 54define i32 @f4(i32 %a) nounwind { 55; CHECK-LABEL: f4: 56; CHECK: @ %bb.0: 57; CHECK-NEXT: movw r1, #3137 58; CHECK-NEXT: bfi r1, r0, #15, #5 59; CHECK-NEXT: mov r0, r1 60; CHECK-NEXT: bx lr 61 %1 = shl i32 %a, 15 62 %ins7 = and i32 %1, 1015808 63 %ins12 = or i32 %ins7, 3137 64 ret i32 %ins12 65} 66 67; rdar://8458663 68define i32 @f5(i32 %a, i32 %b) nounwind { 69; CHECK-LABEL: f5: 70; CHECK: @ %bb.0: @ %entry 71; CHECK-NEXT: bfi r0, r1, #20, #4 72; CHECK-NEXT: bx lr 73entry: 74 %0 = and i32 %a, -15728641 75 %1 = shl i32 %b, 20 76 %2 = and i32 %1, 15728640 77 %3 = or i32 %2, %0 78 ret i32 %3 79} 80 81; rdar://9609030 82define i32 @f6(i32 %a, i32 %b) nounwind readnone { 83; CHECK-LABEL: f6: 84; CHECK: @ %bb.0: @ %entry 85; CHECK-NEXT: bfi r0, r1, #8, #9 86; CHECK-NEXT: bx lr 87entry: 88 %and = and i32 %a, -130817 89 %and2 = shl i32 %b, 8 90 %shl = and i32 %and2, 130816 91 %or = or i32 %shl, %and 92 ret i32 %or 93} 94 95define i32 @f7(i32 %x, i32 %y) { 96; CHECK-LABEL: f7: 97; CHECK: @ %bb.0: 98; CHECK-NEXT: lsr r2, r0, #2 99; CHECK-NEXT: bic r0, r1, #255 100; CHECK-NEXT: bfi r0, r2, #4, #1 101; CHECK-NEXT: bx lr 102 %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00 103 %and = and i32 %x, 4 104 %or = or i32 %y2, 16 105 %cmp = icmp ne i32 %and, 0 106 %sel = select i1 %cmp, i32 %or, i32 %y2 107 ret i32 %sel 108} 109 110define i32 @f8(i32 %x, i32 %y) { 111; CHECK-LABEL: f8: 112; CHECK: @ %bb.0: 113; CHECK-NEXT: lsr r2, r0, #2 114; CHECK-NEXT: bic r0, r1, #255 115; CHECK-NEXT: bfi r0, r2, #4, #1 116; CHECK-NEXT: bfi r0, r2, #5, #1 117; CHECK-NEXT: bx lr 118 %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00 119 %and = and i32 %x, 4 120 %or = or i32 %y2, 48 121 %cmp = icmp ne i32 %and, 0 122 %sel = select i1 %cmp, i32 %or, i32 %y2 123 ret i32 %sel 124} 125 126define i32 @f9(i32 %x, i32 %y) { 127; CHECK-LABEL: f9: 128; CHECK: @ %bb.0: 129; CHECK-NEXT: bic r1, r1, #255 130; CHECK-NEXT: tst r0, #4 131; CHECK-NEXT: orreq r1, r1, #48 132; CHECK-NEXT: mov r0, r1 133; CHECK-NEXT: bx lr 134 %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00 135 %and = and i32 %x, 4 136 %or = or i32 %y2, 48 137 %cmp = icmp ne i32 %and, 0 138 %sel = select i1 %cmp, i32 %y2, i32 %or 139 ret i32 %sel 140} 141 142define i32 @f10(i32 %x, i32 %y) { 143; CHECK-LABEL: f10: 144; CHECK: @ %bb.0: 145; CHECK-NEXT: lsr r2, r0, #1 146; CHECK-NEXT: bic r0, r1, #255 147; CHECK-NEXT: bfi r0, r2, #4, #2 148; CHECK-NEXT: bx lr 149 %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00 150 %and = and i32 %x, 4 151 %or = or i32 %y2, 32 152 %cmp = icmp ne i32 %and, 0 153 %sel = select i1 %cmp, i32 %or, i32 %y2 154 155 %aand = and i32 %x, 2 156 %aor = or i32 %sel, 16 157 %acmp = icmp ne i32 %aand, 0 158 %asel = select i1 %acmp, i32 %aor, i32 %sel 159 160 ret i32 %asel 161} 162 163define i32 @f11(i32 %x, i32 %y) { 164; CHECK-LABEL: f11: 165; CHECK: @ %bb.0: 166; CHECK-NEXT: lsr r2, r0, #1 167; CHECK-NEXT: bic r0, r1, #255 168; CHECK-NEXT: bfi r0, r2, #4, #3 169; CHECK-NEXT: bx lr 170 %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00 171 %and = and i32 %x, 4 172 %or = or i32 %y2, 32 173 %cmp = icmp ne i32 %and, 0 174 %sel = select i1 %cmp, i32 %or, i32 %y2 175 176 %aand = and i32 %x, 2 177 %aor = or i32 %sel, 16 178 %acmp = icmp ne i32 %aand, 0 179 %asel = select i1 %acmp, i32 %aor, i32 %sel 180 181 %band = and i32 %x, 8 182 %bor = or i32 %asel, 64 183 %bcmp = icmp ne i32 %band, 0 184 %bsel = select i1 %bcmp, i32 %bor, i32 %asel 185 186 ret i32 %bsel 187} 188 189define i32 @f12(i32 %x, i32 %y) { 190; CHECK-LABEL: f12: 191; CHECK: @ %bb.0: 192; CHECK-NEXT: lsr r2, r0, #2 193; CHECK-NEXT: bic r0, r1, #255 194; CHECK-NEXT: bfi r0, r2, #4, #1 195; CHECK-NEXT: bx lr 196 %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00 197 %and = and i32 %x, 4 198 %or = or i32 %y2, 16 199 %cmp = icmp eq i32 %and, 0 200 %sel = select i1 %cmp, i32 %y2, i32 %or 201 ret i32 %sel 202} 203 204define i32 @f13(i32 %x, i32 %y) { 205; CHECK-LABEL: f13: 206; CHECK: @ %bb.0: 207; CHECK-NEXT: and r2, r0, #4 208; CHECK-NEXT: bic r0, r1, #255 209; CHECK-NEXT: cmp r2, #42 210; CHECK-NEXT: orrne r0, r0, #16 211; CHECK-NEXT: bx lr 212 %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00 213 %and = and i32 %x, 4 214 %or = or i32 %y2, 16 215 %cmp = icmp eq i32 %and, 42 ; Not comparing against zero! 216 %sel = select i1 %cmp, i32 %y2, i32 %or 217 ret i32 %sel 218} 219