1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple armv8---eabi -mattr=+aes,+fix-cortex-a57-aes-1742098 -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=CHECK-FIX,CHECK-FIX-NOSCHED 3 4; These CPUs should have the fix enabled by default. They use different 5; FileCheck prefixes because some instructions are scheduled differently. 6; 7; RUN: llc -mtriple armv8---eabi -mcpu=cortex-a57 -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=CHECK-FIX,CHECK-CORTEX-FIX 8; RUN: llc -mtriple armv8---eabi -mcpu=cortex-a72 -verify-machineinstrs -o - %s | FileCheck %s --check-prefixes=CHECK-FIX,CHECK-CORTEX-FIX 9 10; This checks that adding `+fix-cortex-a57-aes-1742098` causes `vorr` to be 11; inserted wherever the compiler cannot prove that either input to the first aes 12; instruction in a fused aes pair was set by 64-bit Neon register writes or 13; 128-bit Neon register writes. All other register writes are unsafe, and 14; require a `vorr` to protect the AES input. 15 16declare <16 x i8> @llvm.arm.neon.aese(<16 x i8>, <16 x i8>) 17declare <16 x i8> @llvm.arm.neon.aesmc(<16 x i8>) 18declare <16 x i8> @llvm.arm.neon.aesd(<16 x i8>, <16 x i8>) 19declare <16 x i8> @llvm.arm.neon.aesimc(<16 x i8>) 20 21declare arm_aapcs_vfpcc <16 x i8> @get_input() local_unnamed_addr 22declare arm_aapcs_vfpcc <16 x i8> @get_inputf16(half) local_unnamed_addr 23declare arm_aapcs_vfpcc <16 x i8> @get_inputf32(float) local_unnamed_addr 24 25 26 27define arm_aapcs_vfpcc void @aese_zero(<16 x i8>* %0) nounwind { 28; CHECK-FIX-LABEL: aese_zero: 29; CHECK-FIX: @ %bb.0: 30; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r0] 31; CHECK-FIX-NEXT: vmov.i32 q9, #0x0 32; CHECK-FIX-NEXT: aese.8 q9, q8 33; CHECK-FIX-NEXT: aesmc.8 q8, q9 34; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r0] 35; CHECK-FIX-NEXT: bx lr 36 %2 = load <16 x i8>, <16 x i8>* %0, align 8 37 %3 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> zeroinitializer, <16 x i8> %2) 38 %4 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %3) 39 store <16 x i8> %4, <16 x i8>* %0, align 8 40 ret void 41} 42 43define arm_aapcs_vfpcc void @aese_via_call1(<16 x i8>* %0) nounwind { 44; CHECK-FIX-LABEL: aese_via_call1: 45; CHECK-FIX: @ %bb.0: 46; CHECK-FIX-NEXT: .save {r4, lr} 47; CHECK-FIX-NEXT: push {r4, lr} 48; CHECK-FIX-NEXT: mov r4, r0 49; CHECK-FIX-NEXT: bl get_input 50; CHECK-FIX-NEXT: vorr q0, q0, q0 51; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r4] 52; CHECK-FIX-NEXT: aese.8 q0, q8 53; CHECK-FIX-NEXT: aesmc.8 q8, q0 54; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r4] 55; CHECK-FIX-NEXT: pop {r4, pc} 56 %2 = call arm_aapcs_vfpcc <16 x i8> @get_input() 57 %3 = load <16 x i8>, <16 x i8>* %0, align 8 58 %4 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %2, <16 x i8> %3) 59 %5 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %4) 60 store <16 x i8> %5, <16 x i8>* %0, align 8 61 ret void 62} 63 64define arm_aapcs_vfpcc void @aese_via_call2(half %0, <16 x i8>* %1) nounwind { 65; CHECK-FIX-LABEL: aese_via_call2: 66; CHECK-FIX: @ %bb.0: 67; CHECK-FIX-NEXT: .save {r4, lr} 68; CHECK-FIX-NEXT: push {r4, lr} 69; CHECK-FIX-NEXT: mov r4, r0 70; CHECK-FIX-NEXT: bl get_inputf16 71; CHECK-FIX-NEXT: vorr q0, q0, q0 72; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r4] 73; CHECK-FIX-NEXT: aese.8 q0, q8 74; CHECK-FIX-NEXT: aesmc.8 q8, q0 75; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r4] 76; CHECK-FIX-NEXT: pop {r4, pc} 77 %3 = call arm_aapcs_vfpcc <16 x i8> @get_inputf16(half %0) 78 %4 = load <16 x i8>, <16 x i8>* %1, align 8 79 %5 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %3, <16 x i8> %4) 80 %6 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %5) 81 store <16 x i8> %6, <16 x i8>* %1, align 8 82 ret void 83} 84 85define arm_aapcs_vfpcc void @aese_via_call3(float %0, <16 x i8>* %1) nounwind { 86; CHECK-FIX-LABEL: aese_via_call3: 87; CHECK-FIX: @ %bb.0: 88; CHECK-FIX-NEXT: .save {r4, lr} 89; CHECK-FIX-NEXT: push {r4, lr} 90; CHECK-FIX-NEXT: mov r4, r0 91; CHECK-FIX-NEXT: bl get_inputf32 92; CHECK-FIX-NEXT: vorr q0, q0, q0 93; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r4] 94; CHECK-FIX-NEXT: aese.8 q0, q8 95; CHECK-FIX-NEXT: aesmc.8 q8, q0 96; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r4] 97; CHECK-FIX-NEXT: pop {r4, pc} 98 %3 = call arm_aapcs_vfpcc <16 x i8> @get_inputf32(float %0) 99 %4 = load <16 x i8>, <16 x i8>* %1, align 8 100 %5 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %3, <16 x i8> %4) 101 %6 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %5) 102 store <16 x i8> %6, <16 x i8>* %1, align 8 103 ret void 104} 105 106define arm_aapcs_vfpcc void @aese_once_via_ptr(<16 x i8>* %0, <16 x i8>* %1) nounwind { 107; CHECK-FIX-LABEL: aese_once_via_ptr: 108; CHECK-FIX: @ %bb.0: 109; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r0] 110; CHECK-FIX-NEXT: vld1.64 {d18, d19}, [r1] 111; CHECK-FIX-NEXT: aese.8 q9, q8 112; CHECK-FIX-NEXT: aesmc.8 q8, q9 113; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r1] 114; CHECK-FIX-NEXT: bx lr 115 %3 = load <16 x i8>, <16 x i8>* %1, align 8 116 %4 = load <16 x i8>, <16 x i8>* %0, align 8 117 %5 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %3, <16 x i8> %4) 118 %6 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %5) 119 store <16 x i8> %6, <16 x i8>* %1, align 8 120 ret void 121} 122 123define arm_aapcs_vfpcc <16 x i8> @aese_once_via_val(<16 x i8> %0, <16 x i8> %1) nounwind { 124; CHECK-FIX-LABEL: aese_once_via_val: 125; CHECK-FIX: @ %bb.0: 126; CHECK-FIX-NEXT: vorr q1, q1, q1 127; CHECK-FIX-NEXT: vorr q0, q0, q0 128; CHECK-FIX-NEXT: aese.8 q1, q0 129; CHECK-FIX-NEXT: aesmc.8 q0, q1 130; CHECK-FIX-NEXT: bx lr 131 %3 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %1, <16 x i8> %0) 132 %4 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %3) 133 ret <16 x i8> %4 134} 135 136define arm_aapcs_vfpcc void @aese_twice_via_ptr(<16 x i8>* %0, <16 x i8>* %1) nounwind { 137; CHECK-FIX-LABEL: aese_twice_via_ptr: 138; CHECK-FIX: @ %bb.0: 139; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r0] 140; CHECK-FIX-NEXT: vld1.64 {d18, d19}, [r1] 141; CHECK-FIX-NEXT: aese.8 q9, q8 142; CHECK-FIX-NEXT: aesmc.8 q8, q9 143; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r1] 144; CHECK-FIX-NEXT: vld1.64 {d18, d19}, [r0] 145; CHECK-FIX-NEXT: aese.8 q8, q9 146; CHECK-FIX-NEXT: aesmc.8 q8, q8 147; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r1] 148; CHECK-FIX-NEXT: bx lr 149 %3 = load <16 x i8>, <16 x i8>* %1, align 8 150 %4 = load <16 x i8>, <16 x i8>* %0, align 8 151 %5 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %3, <16 x i8> %4) 152 %6 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %5) 153 store <16 x i8> %6, <16 x i8>* %1, align 8 154 %7 = load <16 x i8>, <16 x i8>* %0, align 8 155 %8 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %6, <16 x i8> %7) 156 %9 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %8) 157 store <16 x i8> %9, <16 x i8>* %1, align 8 158 ret void 159} 160 161define arm_aapcs_vfpcc <16 x i8> @aese_twice_via_val(<16 x i8> %0, <16 x i8> %1) nounwind { 162; CHECK-FIX-LABEL: aese_twice_via_val: 163; CHECK-FIX: @ %bb.0: 164; CHECK-FIX-NEXT: vorr q1, q1, q1 165; CHECK-FIX-NEXT: vorr q0, q0, q0 166; CHECK-FIX-NEXT: vorr q0, q0, q0 167; CHECK-FIX-NEXT: aese.8 q1, q0 168; CHECK-FIX-NEXT: aesmc.8 q8, q1 169; CHECK-FIX-NEXT: aese.8 q8, q0 170; CHECK-FIX-NEXT: aesmc.8 q0, q8 171; CHECK-FIX-NEXT: bx lr 172 %3 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %1, <16 x i8> %0) 173 %4 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %3) 174 %5 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %4, <16 x i8> %0) 175 %6 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %5) 176 ret <16 x i8> %6 177} 178 179define arm_aapcs_vfpcc void @aese_loop_via_ptr(i32 %0, <16 x i8>* %1, <16 x i8>* %2) nounwind { 180; CHECK-FIX-NOSCHED-LABEL: aese_loop_via_ptr: 181; CHECK-FIX-NOSCHED: @ %bb.0: 182; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 183; CHECK-FIX-NOSCHED-NEXT: bxeq lr 184; CHECK-FIX-NOSCHED-NEXT: .LBB8_1: @ =>This Inner Loop Header: Depth=1 185; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r1] 186; CHECK-FIX-NOSCHED-NEXT: subs r0, r0, #1 187; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d18, d19}, [r2] 188; CHECK-FIX-NOSCHED-NEXT: aese.8 q9, q8 189; CHECK-FIX-NOSCHED-NEXT: aesmc.8 q8, q9 190; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r2] 191; CHECK-FIX-NOSCHED-NEXT: bne .LBB8_1 192; CHECK-FIX-NOSCHED-NEXT: @ %bb.2: 193; CHECK-FIX-NOSCHED-NEXT: bx lr 194; 195; CHECK-CORTEX-FIX-LABEL: aese_loop_via_ptr: 196; CHECK-CORTEX-FIX: @ %bb.0: 197; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 198; CHECK-CORTEX-FIX-NEXT: bxeq lr 199; CHECK-CORTEX-FIX-NEXT: .LBB8_1: @ =>This Inner Loop Header: Depth=1 200; CHECK-CORTEX-FIX-NEXT: vld1.64 {d16, d17}, [r1] 201; CHECK-CORTEX-FIX-NEXT: vld1.64 {d18, d19}, [r2] 202; CHECK-CORTEX-FIX-NEXT: subs r0, r0, #1 203; CHECK-CORTEX-FIX-NEXT: aese.8 q9, q8 204; CHECK-CORTEX-FIX-NEXT: aesmc.8 q8, q9 205; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r2] 206; CHECK-CORTEX-FIX-NEXT: bne .LBB8_1 207; CHECK-CORTEX-FIX-NEXT: @ %bb.2: 208; CHECK-CORTEX-FIX-NEXT: bx lr 209 %4 = icmp eq i32 %0, 0 210 br i1 %4, label %5, label %6 211 2125: 213 ret void 214 2156: 216 %7 = phi i32 [ %12, %6 ], [ 0, %3 ] 217 %8 = load <16 x i8>, <16 x i8>* %2, align 8 218 %9 = load <16 x i8>, <16 x i8>* %1, align 8 219 %10 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %8, <16 x i8> %9) 220 %11 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %10) 221 store <16 x i8> %11, <16 x i8>* %2, align 8 222 %12 = add nuw i32 %7, 1 223 %13 = icmp eq i32 %12, %0 224 br i1 %13, label %5, label %6 225} 226 227define arm_aapcs_vfpcc <16 x i8> @aese_loop_via_val(i32 %0, <16 x i8> %1, <16 x i8> %2) nounwind { 228; CHECK-FIX-LABEL: aese_loop_via_val: 229; CHECK-FIX: @ %bb.0: 230; CHECK-FIX-NEXT: vorr q1, q1, q1 231; CHECK-FIX-NEXT: vorr q0, q0, q0 232; CHECK-FIX-NEXT: cmp r0, #0 233; CHECK-FIX-NEXT: beq .LBB9_2 234; CHECK-FIX-NEXT: .LBB9_1: @ =>This Inner Loop Header: Depth=1 235; CHECK-FIX-NEXT: aese.8 q1, q0 236; CHECK-FIX-NEXT: subs r0, r0, #1 237; CHECK-FIX-NEXT: aesmc.8 q1, q1 238; CHECK-FIX-NEXT: bne .LBB9_1 239; CHECK-FIX-NEXT: .LBB9_2: 240; CHECK-FIX-NEXT: vorr q0, q1, q1 241; CHECK-FIX-NEXT: bx lr 242 %4 = icmp eq i32 %0, 0 243 br i1 %4, label %5, label %7 244 2455: 246 %6 = phi <16 x i8> [ %2, %3 ], [ %11, %7 ] 247 ret <16 x i8> %6 248 2497: 250 %8 = phi i32 [ %12, %7 ], [ 0, %3 ] 251 %9 = phi <16 x i8> [ %11, %7 ], [ %2, %3 ] 252 %10 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %9, <16 x i8> %1) 253 %11 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %10) 254 %12 = add nuw i32 %8, 1 255 %13 = icmp eq i32 %12, %0 256 br i1 %13, label %5, label %7 257} 258 259define arm_aapcs_vfpcc void @aese_set8_via_ptr(i8* %0, <16 x i8> %1, <16 x i8>* %2) nounwind { 260; CHECK-FIX-NOSCHED-LABEL: aese_set8_via_ptr: 261; CHECK-FIX-NOSCHED: @ %bb.0: 262; CHECK-FIX-NOSCHED-NEXT: vorr q0, q0, q0 263; CHECK-FIX-NOSCHED-NEXT: ldrb r0, [r0] 264; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r1] 265; CHECK-FIX-NOSCHED-NEXT: vmov.8 d0[0], r0 266; CHECK-FIX-NOSCHED-NEXT: vmov.8 d16[0], r0 267; CHECK-FIX-NOSCHED-NEXT: aese.8 q8, q0 268; CHECK-FIX-NOSCHED-NEXT: aesmc.8 q8, q8 269; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r1] 270; CHECK-FIX-NOSCHED-NEXT: bx lr 271; 272; CHECK-CORTEX-FIX-LABEL: aese_set8_via_ptr: 273; CHECK-CORTEX-FIX: @ %bb.0: 274; CHECK-CORTEX-FIX-NEXT: vorr q0, q0, q0 275; CHECK-CORTEX-FIX-NEXT: vld1.64 {d16, d17}, [r1] 276; CHECK-CORTEX-FIX-NEXT: ldrb r0, [r0] 277; CHECK-CORTEX-FIX-NEXT: vmov.8 d0[0], r0 278; CHECK-CORTEX-FIX-NEXT: vmov.8 d16[0], r0 279; CHECK-CORTEX-FIX-NEXT: aese.8 q8, q0 280; CHECK-CORTEX-FIX-NEXT: aesmc.8 q8, q8 281; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r1] 282; CHECK-CORTEX-FIX-NEXT: bx lr 283 %4 = load i8, i8* %0, align 1 284 %5 = load <16 x i8>, <16 x i8>* %2, align 8 285 %6 = insertelement <16 x i8> %5, i8 %4, i64 0 286 %7 = insertelement <16 x i8> %1, i8 %4, i64 0 287 %8 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %6, <16 x i8> %7) 288 %9 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %8) 289 store <16 x i8> %9, <16 x i8>* %2, align 8 290 ret void 291} 292 293define arm_aapcs_vfpcc void @aese_set8_via_val(i8 zeroext %0, <16 x i8> %1, <16 x i8>* %2) nounwind { 294; CHECK-FIX-LABEL: aese_set8_via_val: 295; CHECK-FIX: @ %bb.0: 296; CHECK-FIX-NEXT: vorr q0, q0, q0 297; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r1] 298; CHECK-FIX-NEXT: vmov.8 d0[0], r0 299; CHECK-FIX-NEXT: vmov.8 d16[0], r0 300; CHECK-FIX-NEXT: aese.8 q8, q0 301; CHECK-FIX-NEXT: aesmc.8 q8, q8 302; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r1] 303; CHECK-FIX-NEXT: bx lr 304 %4 = load <16 x i8>, <16 x i8>* %2, align 8 305 %5 = insertelement <16 x i8> %4, i8 %0, i64 0 306 %6 = insertelement <16 x i8> %1, i8 %0, i64 0 307 %7 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %5, <16 x i8> %6) 308 %8 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %7) 309 store <16 x i8> %8, <16 x i8>* %2, align 8 310 ret void 311} 312 313define arm_aapcs_vfpcc void @aese_set8_cond_via_ptr(i1 zeroext %0, i8* %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 314; CHECK-FIX-LABEL: aese_set8_cond_via_ptr: 315; CHECK-FIX: @ %bb.0: 316; CHECK-FIX-NEXT: vorr q0, q0, q0 317; CHECK-FIX-NEXT: cmp r0, #0 318; CHECK-FIX-NEXT: beq .LBB12_2 319; CHECK-FIX-NEXT: @ %bb.1: 320; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 321; CHECK-FIX-NEXT: vld1.8 {d16[0]}, [r1] 322; CHECK-FIX-NEXT: cmp r0, #0 323; CHECK-FIX-NEXT: bne .LBB12_3 324; CHECK-FIX-NEXT: b .LBB12_4 325; CHECK-FIX-NEXT: .LBB12_2: 326; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 327; CHECK-FIX-NEXT: cmp r0, #0 328; CHECK-FIX-NEXT: beq .LBB12_4 329; CHECK-FIX-NEXT: .LBB12_3: 330; CHECK-FIX-NEXT: vld1.8 {d0[0]}, [r1] 331; CHECK-FIX-NEXT: .LBB12_4: 332; CHECK-FIX-NEXT: aese.8 q8, q0 333; CHECK-FIX-NEXT: aesmc.8 q8, q8 334; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 335; CHECK-FIX-NEXT: bx lr 336 br i1 %0, label %5, label %9 337 3385: 339 %6 = load i8, i8* %1, align 1 340 %7 = load <16 x i8>, <16 x i8>* %3, align 8 341 %8 = insertelement <16 x i8> %7, i8 %6, i64 0 342 br label %11 343 3449: 345 %10 = load <16 x i8>, <16 x i8>* %3, align 8 346 br label %11 347 34811: 349 %12 = phi <16 x i8> [ %8, %5 ], [ %10, %9 ] 350 br i1 %0, label %13, label %16 351 35213: 353 %14 = load i8, i8* %1, align 1 354 %15 = insertelement <16 x i8> %2, i8 %14, i64 0 355 br label %16 356 35716: 358 %17 = phi <16 x i8> [ %15, %13 ], [ %2, %11 ] 359 %18 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %12, <16 x i8> %17) 360 %19 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %18) 361 store <16 x i8> %19, <16 x i8>* %3, align 8 362 ret void 363} 364 365define arm_aapcs_vfpcc void @aese_set8_cond_via_val(i1 zeroext %0, i8 zeroext %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 366; CHECK-FIX-LABEL: aese_set8_cond_via_val: 367; CHECK-FIX: @ %bb.0: 368; CHECK-FIX-NEXT: vorr q0, q0, q0 369; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 370; CHECK-FIX-NEXT: cmp r0, #0 371; CHECK-FIX-NEXT: beq .LBB13_2 372; CHECK-FIX-NEXT: @ %bb.1: 373; CHECK-FIX-NEXT: vmov.8 d16[0], r1 374; CHECK-FIX-NEXT: .LBB13_2: @ %select.end 375; CHECK-FIX-NEXT: cmp r0, #0 376; CHECK-FIX-NEXT: beq .LBB13_4 377; CHECK-FIX-NEXT: @ %bb.3: 378; CHECK-FIX-NEXT: vmov.8 d0[0], r1 379; CHECK-FIX-NEXT: .LBB13_4: @ %select.end1 380; CHECK-FIX-NEXT: aese.8 q8, q0 381; CHECK-FIX-NEXT: aesmc.8 q8, q8 382; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 383; CHECK-FIX-NEXT: bx lr 384 %5 = load <16 x i8>, <16 x i8>* %3, align 8 385 %6 = insertelement <16 x i8> %5, i8 %1, i64 0 386 %7 = select i1 %0, <16 x i8> %6, <16 x i8> %5 387 %8 = insertelement <16 x i8> %2, i8 %1, i64 0 388 %9 = select i1 %0, <16 x i8> %8, <16 x i8> %2 389 %10 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %7, <16 x i8> %9) 390 %11 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %10) 391 store <16 x i8> %11, <16 x i8>* %3, align 8 392 ret void 393} 394 395define arm_aapcs_vfpcc void @aese_set8_loop_via_ptr(i32 %0, i8* %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 396; CHECK-FIX-LABEL: aese_set8_loop_via_ptr: 397; CHECK-FIX: @ %bb.0: 398; CHECK-FIX-NEXT: vorr q0, q0, q0 399; CHECK-FIX-NEXT: ldrb r1, [r1] 400; CHECK-FIX-NEXT: cmp r0, #0 401; CHECK-FIX-NEXT: strb r1, [r2] 402; CHECK-FIX-NEXT: bxeq lr 403; CHECK-FIX-NEXT: .LBB14_1: 404; CHECK-FIX-NEXT: vmov.8 d0[0], r1 405; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 406; CHECK-FIX-NEXT: .LBB14_2: @ =>This Inner Loop Header: Depth=1 407; CHECK-FIX-NEXT: aese.8 q8, q0 408; CHECK-FIX-NEXT: subs r0, r0, #1 409; CHECK-FIX-NEXT: aesmc.8 q8, q8 410; CHECK-FIX-NEXT: bne .LBB14_2 411; CHECK-FIX-NEXT: @ %bb.3: 412; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 413; CHECK-FIX-NEXT: bx lr 414 %5 = load i8, i8* %1, align 1 415 %6 = insertelement <16 x i8> %2, i8 %5, i64 0 416 %7 = getelementptr inbounds <16 x i8>, <16 x i8>* %3, i32 0, i32 0 417 store i8 %5, i8* %7, align 8 418 %8 = icmp eq i32 %0, 0 419 br i1 %8, label %12, label %9 420 4219: 422 %10 = load <16 x i8>, <16 x i8>* %3, align 8 423 br label %13 424 42511: 426 store <16 x i8> %17, <16 x i8>* %3, align 8 427 br label %12 428 42912: 430 ret void 431 43213: 433 %14 = phi <16 x i8> [ %10, %9 ], [ %17, %13 ] 434 %15 = phi i32 [ 0, %9 ], [ %18, %13 ] 435 %16 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %14, <16 x i8> %6) 436 %17 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %16) 437 %18 = add nuw i32 %15, 1 438 %19 = icmp eq i32 %18, %0 439 br i1 %19, label %11, label %13 440} 441 442define arm_aapcs_vfpcc void @aese_set8_loop_via_val(i32 %0, i8 zeroext %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 443; CHECK-FIX-LABEL: aese_set8_loop_via_val: 444; CHECK-FIX: @ %bb.0: 445; CHECK-FIX-NEXT: vorr q0, q0, q0 446; CHECK-FIX-NEXT: cmp r0, #0 447; CHECK-FIX-NEXT: bxeq lr 448; CHECK-FIX-NEXT: .LBB15_1: 449; CHECK-FIX-NEXT: vmov.8 d0[0], r1 450; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 451; CHECK-FIX-NEXT: .LBB15_2: @ =>This Inner Loop Header: Depth=1 452; CHECK-FIX-NEXT: vmov.8 d16[0], r1 453; CHECK-FIX-NEXT: subs r0, r0, #1 454; CHECK-FIX-NEXT: aese.8 q8, q0 455; CHECK-FIX-NEXT: aesmc.8 q8, q8 456; CHECK-FIX-NEXT: bne .LBB15_2 457; CHECK-FIX-NEXT: @ %bb.3: 458; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 459; CHECK-FIX-NEXT: bx lr 460 %5 = icmp eq i32 %0, 0 461 br i1 %5, label %10, label %6 462 4636: 464 %7 = insertelement <16 x i8> %2, i8 %1, i64 0 465 %8 = load <16 x i8>, <16 x i8>* %3, align 8 466 br label %11 467 4689: 469 store <16 x i8> %16, <16 x i8>* %3, align 8 470 br label %10 471 47210: 473 ret void 474 47511: 476 %12 = phi <16 x i8> [ %8, %6 ], [ %16, %11 ] 477 %13 = phi i32 [ 0, %6 ], [ %17, %11 ] 478 %14 = insertelement <16 x i8> %12, i8 %1, i64 0 479 %15 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %14, <16 x i8> %7) 480 %16 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %15) 481 %17 = add nuw i32 %13, 1 482 %18 = icmp eq i32 %17, %0 483 br i1 %18, label %9, label %11 484} 485 486define arm_aapcs_vfpcc void @aese_set16_via_ptr(i16* %0, <16 x i8> %1, <16 x i8>* %2) nounwind { 487; CHECK-FIX-NOSCHED-LABEL: aese_set16_via_ptr: 488; CHECK-FIX-NOSCHED: @ %bb.0: 489; CHECK-FIX-NOSCHED-NEXT: vorr q0, q0, q0 490; CHECK-FIX-NOSCHED-NEXT: ldrh r0, [r0] 491; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r1] 492; CHECK-FIX-NOSCHED-NEXT: vmov.16 d0[0], r0 493; CHECK-FIX-NOSCHED-NEXT: vmov.16 d16[0], r0 494; CHECK-FIX-NOSCHED-NEXT: aese.8 q8, q0 495; CHECK-FIX-NOSCHED-NEXT: aesmc.8 q8, q8 496; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r1] 497; CHECK-FIX-NOSCHED-NEXT: bx lr 498; 499; CHECK-CORTEX-FIX-LABEL: aese_set16_via_ptr: 500; CHECK-CORTEX-FIX: @ %bb.0: 501; CHECK-CORTEX-FIX-NEXT: vorr q0, q0, q0 502; CHECK-CORTEX-FIX-NEXT: vld1.64 {d16, d17}, [r1] 503; CHECK-CORTEX-FIX-NEXT: ldrh r0, [r0] 504; CHECK-CORTEX-FIX-NEXT: vmov.16 d0[0], r0 505; CHECK-CORTEX-FIX-NEXT: vmov.16 d16[0], r0 506; CHECK-CORTEX-FIX-NEXT: aese.8 q8, q0 507; CHECK-CORTEX-FIX-NEXT: aesmc.8 q8, q8 508; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r1] 509; CHECK-CORTEX-FIX-NEXT: bx lr 510 %4 = load i16, i16* %0, align 2 511 %5 = bitcast <16 x i8>* %2 to <8 x i16>* 512 %6 = load <8 x i16>, <8 x i16>* %5, align 8 513 %7 = insertelement <8 x i16> %6, i16 %4, i64 0 514 %8 = bitcast <8 x i16> %7 to <16 x i8> 515 %9 = bitcast <16 x i8> %1 to <8 x i16> 516 %10 = insertelement <8 x i16> %9, i16 %4, i64 0 517 %11 = bitcast <8 x i16> %10 to <16 x i8> 518 %12 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %8, <16 x i8> %11) 519 %13 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %12) 520 store <16 x i8> %13, <16 x i8>* %2, align 8 521 ret void 522} 523 524define arm_aapcs_vfpcc void @aese_set16_via_val(i16 zeroext %0, <16 x i8> %1, <16 x i8>* %2) nounwind { 525; CHECK-FIX-LABEL: aese_set16_via_val: 526; CHECK-FIX: @ %bb.0: 527; CHECK-FIX-NEXT: vorr q0, q0, q0 528; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r1] 529; CHECK-FIX-NEXT: vmov.16 d0[0], r0 530; CHECK-FIX-NEXT: vmov.16 d16[0], r0 531; CHECK-FIX-NEXT: aese.8 q8, q0 532; CHECK-FIX-NEXT: aesmc.8 q8, q8 533; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r1] 534; CHECK-FIX-NEXT: bx lr 535 %4 = bitcast <16 x i8>* %2 to <8 x i16>* 536 %5 = load <8 x i16>, <8 x i16>* %4, align 8 537 %6 = insertelement <8 x i16> %5, i16 %0, i64 0 538 %7 = bitcast <8 x i16> %6 to <16 x i8> 539 %8 = bitcast <16 x i8> %1 to <8 x i16> 540 %9 = insertelement <8 x i16> %8, i16 %0, i64 0 541 %10 = bitcast <8 x i16> %9 to <16 x i8> 542 %11 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %7, <16 x i8> %10) 543 %12 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %11) 544 store <16 x i8> %12, <16 x i8>* %2, align 8 545 ret void 546} 547 548define arm_aapcs_vfpcc void @aese_set16_cond_via_ptr(i1 zeroext %0, i16* %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 549; CHECK-FIX-LABEL: aese_set16_cond_via_ptr: 550; CHECK-FIX: @ %bb.0: 551; CHECK-FIX-NEXT: vorr q0, q0, q0 552; CHECK-FIX-NEXT: cmp r0, #0 553; CHECK-FIX-NEXT: beq .LBB18_2 554; CHECK-FIX-NEXT: @ %bb.1: 555; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 556; CHECK-FIX-NEXT: vld1.16 {d16[0]}, [r1:16] 557; CHECK-FIX-NEXT: cmp r0, #0 558; CHECK-FIX-NEXT: bne .LBB18_3 559; CHECK-FIX-NEXT: b .LBB18_4 560; CHECK-FIX-NEXT: .LBB18_2: 561; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 562; CHECK-FIX-NEXT: cmp r0, #0 563; CHECK-FIX-NEXT: beq .LBB18_4 564; CHECK-FIX-NEXT: .LBB18_3: 565; CHECK-FIX-NEXT: vld1.16 {d0[0]}, [r1:16] 566; CHECK-FIX-NEXT: .LBB18_4: 567; CHECK-FIX-NEXT: aese.8 q8, q0 568; CHECK-FIX-NEXT: aesmc.8 q8, q8 569; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 570; CHECK-FIX-NEXT: bx lr 571 br i1 %0, label %5, label %10 572 5735: 574 %6 = load i16, i16* %1, align 2 575 %7 = bitcast <16 x i8>* %3 to <8 x i16>* 576 %8 = load <8 x i16>, <8 x i16>* %7, align 8 577 %9 = insertelement <8 x i16> %8, i16 %6, i64 0 578 br label %13 579 58010: 581 %11 = bitcast <16 x i8>* %3 to <8 x i16>* 582 %12 = load <8 x i16>, <8 x i16>* %11, align 8 583 br label %13 584 58513: 586 %14 = phi <8 x i16> [ %9, %5 ], [ %12, %10 ] 587 br i1 %0, label %15, label %19 588 58915: 590 %16 = load i16, i16* %1, align 2 591 %17 = bitcast <16 x i8> %2 to <8 x i16> 592 %18 = insertelement <8 x i16> %17, i16 %16, i64 0 593 br label %21 594 59519: 596 %20 = bitcast <16 x i8> %2 to <8 x i16> 597 br label %21 598 59921: 600 %22 = phi <8 x i16> [ %18, %15 ], [ %20, %19 ] 601 %23 = bitcast <8 x i16> %14 to <16 x i8> 602 %24 = bitcast <8 x i16> %22 to <16 x i8> 603 %25 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %23, <16 x i8> %24) 604 %26 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %25) 605 store <16 x i8> %26, <16 x i8>* %3, align 8 606 ret void 607} 608 609define arm_aapcs_vfpcc void @aese_set16_cond_via_val(i1 zeroext %0, i16 zeroext %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 610; CHECK-FIX-LABEL: aese_set16_cond_via_val: 611; CHECK-FIX: @ %bb.0: 612; CHECK-FIX-NEXT: vorr q0, q0, q0 613; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 614; CHECK-FIX-NEXT: cmp r0, #0 615; CHECK-FIX-NEXT: beq .LBB19_2 616; CHECK-FIX-NEXT: @ %bb.1: 617; CHECK-FIX-NEXT: vmov.16 d16[0], r1 618; CHECK-FIX-NEXT: .LBB19_2: @ %select.end 619; CHECK-FIX-NEXT: cmp r0, #0 620; CHECK-FIX-NEXT: beq .LBB19_4 621; CHECK-FIX-NEXT: @ %bb.3: 622; CHECK-FIX-NEXT: vmov.16 d0[0], r1 623; CHECK-FIX-NEXT: .LBB19_4: @ %select.end1 624; CHECK-FIX-NEXT: aese.8 q8, q0 625; CHECK-FIX-NEXT: aesmc.8 q8, q8 626; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 627; CHECK-FIX-NEXT: bx lr 628 %5 = bitcast <16 x i8>* %3 to <8 x i16>* 629 %6 = load <8 x i16>, <8 x i16>* %5, align 8 630 %7 = insertelement <8 x i16> %6, i16 %1, i64 0 631 %8 = select i1 %0, <8 x i16> %7, <8 x i16> %6 632 %9 = bitcast <16 x i8> %2 to <8 x i16> 633 %10 = insertelement <8 x i16> %9, i16 %1, i64 0 634 %11 = select i1 %0, <8 x i16> %10, <8 x i16> %9 635 %12 = bitcast <8 x i16> %8 to <16 x i8> 636 %13 = bitcast <8 x i16> %11 to <16 x i8> 637 %14 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %12, <16 x i8> %13) 638 %15 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %14) 639 store <16 x i8> %15, <16 x i8>* %3, align 8 640 ret void 641} 642 643define arm_aapcs_vfpcc void @aese_set16_loop_via_ptr(i32 %0, i16* %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 644; CHECK-FIX-LABEL: aese_set16_loop_via_ptr: 645; CHECK-FIX: @ %bb.0: 646; CHECK-FIX-NEXT: vorr q0, q0, q0 647; CHECK-FIX-NEXT: ldrh r1, [r1] 648; CHECK-FIX-NEXT: cmp r0, #0 649; CHECK-FIX-NEXT: strh r1, [r2] 650; CHECK-FIX-NEXT: bxeq lr 651; CHECK-FIX-NEXT: .LBB20_1: 652; CHECK-FIX-NEXT: vmov.16 d0[0], r1 653; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 654; CHECK-FIX-NEXT: .LBB20_2: @ =>This Inner Loop Header: Depth=1 655; CHECK-FIX-NEXT: aese.8 q8, q0 656; CHECK-FIX-NEXT: subs r0, r0, #1 657; CHECK-FIX-NEXT: aesmc.8 q8, q8 658; CHECK-FIX-NEXT: bne .LBB20_2 659; CHECK-FIX-NEXT: @ %bb.3: 660; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 661; CHECK-FIX-NEXT: bx lr 662 %5 = load i16, i16* %1, align 2 663 %6 = bitcast <16 x i8> %2 to <8 x i16> 664 %7 = insertelement <8 x i16> %6, i16 %5, i64 0 665 %8 = bitcast <8 x i16> %7 to <16 x i8> 666 %9 = bitcast <16 x i8>* %3 to i16* 667 store i16 %5, i16* %9, align 8 668 %10 = icmp eq i32 %0, 0 669 br i1 %10, label %14, label %11 670 67111: 672 %12 = load <16 x i8>, <16 x i8>* %3, align 8 673 br label %15 674 67513: 676 store <16 x i8> %19, <16 x i8>* %3, align 8 677 br label %14 678 67914: 680 ret void 681 68215: 683 %16 = phi <16 x i8> [ %12, %11 ], [ %19, %15 ] 684 %17 = phi i32 [ 0, %11 ], [ %20, %15 ] 685 %18 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %16, <16 x i8> %8) 686 %19 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %18) 687 %20 = add nuw i32 %17, 1 688 %21 = icmp eq i32 %20, %0 689 br i1 %21, label %13, label %15 690} 691 692define arm_aapcs_vfpcc void @aese_set16_loop_via_val(i32 %0, i16 zeroext %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 693; CHECK-FIX-LABEL: aese_set16_loop_via_val: 694; CHECK-FIX: @ %bb.0: 695; CHECK-FIX-NEXT: vorr q0, q0, q0 696; CHECK-FIX-NEXT: cmp r0, #0 697; CHECK-FIX-NEXT: bxeq lr 698; CHECK-FIX-NEXT: .LBB21_1: 699; CHECK-FIX-NEXT: vmov.16 d0[0], r1 700; CHECK-FIX-NEXT: .LBB21_2: @ =>This Inner Loop Header: Depth=1 701; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 702; CHECK-FIX-NEXT: subs r0, r0, #1 703; CHECK-FIX-NEXT: vmov.16 d16[0], r1 704; CHECK-FIX-NEXT: aese.8 q8, q0 705; CHECK-FIX-NEXT: aesmc.8 q8, q8 706; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 707; CHECK-FIX-NEXT: bne .LBB21_2 708; CHECK-FIX-NEXT: @ %bb.3: 709; CHECK-FIX-NEXT: bx lr 710 %5 = icmp eq i32 %0, 0 711 br i1 %5, label %12, label %6 712 7136: 714 %7 = bitcast <16 x i8> %2 to <8 x i16> 715 %8 = insertelement <8 x i16> %7, i16 %1, i64 0 716 %9 = bitcast <8 x i16> %8 to <16 x i8> 717 %10 = bitcast <16 x i8>* %3 to <8 x i16>* 718 %11 = bitcast <16 x i8>* %3 to i16* 719 br label %13 720 72112: 722 ret void 723 72413: 725 %14 = phi i32 [ 0, %6 ], [ %20, %13 ] 726 %15 = load <8 x i16>, <8 x i16>* %10, align 8 727 %16 = insertelement <8 x i16> %15, i16 %1, i64 0 728 %17 = bitcast <8 x i16> %16 to <16 x i8> 729 store i16 %1, i16* %11, align 8 730 %18 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %17, <16 x i8> %9) 731 %19 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %18) 732 store <16 x i8> %19, <16 x i8>* %3, align 8 733 %20 = add nuw i32 %14, 1 734 %21 = icmp eq i32 %20, %0 735 br i1 %21, label %12, label %13 736} 737 738define arm_aapcs_vfpcc void @aese_set32_via_ptr(i32* %0, <16 x i8> %1, <16 x i8>* %2) nounwind { 739; CHECK-FIX-NOSCHED-LABEL: aese_set32_via_ptr: 740; CHECK-FIX-NOSCHED: @ %bb.0: 741; CHECK-FIX-NOSCHED-NEXT: vorr q0, q0, q0 742; CHECK-FIX-NOSCHED-NEXT: ldr r0, [r0] 743; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r1] 744; CHECK-FIX-NOSCHED-NEXT: vmov.32 d0[0], r0 745; CHECK-FIX-NOSCHED-NEXT: vmov.32 d16[0], r0 746; CHECK-FIX-NOSCHED-NEXT: aese.8 q8, q0 747; CHECK-FIX-NOSCHED-NEXT: aesmc.8 q8, q8 748; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r1] 749; CHECK-FIX-NOSCHED-NEXT: bx lr 750; 751; CHECK-CORTEX-FIX-LABEL: aese_set32_via_ptr: 752; CHECK-CORTEX-FIX: @ %bb.0: 753; CHECK-CORTEX-FIX-NEXT: vorr q0, q0, q0 754; CHECK-CORTEX-FIX-NEXT: vld1.64 {d16, d17}, [r1] 755; CHECK-CORTEX-FIX-NEXT: ldr r0, [r0] 756; CHECK-CORTEX-FIX-NEXT: vmov.32 d0[0], r0 757; CHECK-CORTEX-FIX-NEXT: vmov.32 d16[0], r0 758; CHECK-CORTEX-FIX-NEXT: aese.8 q8, q0 759; CHECK-CORTEX-FIX-NEXT: aesmc.8 q8, q8 760; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r1] 761; CHECK-CORTEX-FIX-NEXT: bx lr 762 %4 = load i32, i32* %0, align 4 763 %5 = bitcast <16 x i8>* %2 to <4 x i32>* 764 %6 = load <4 x i32>, <4 x i32>* %5, align 8 765 %7 = insertelement <4 x i32> %6, i32 %4, i64 0 766 %8 = bitcast <4 x i32> %7 to <16 x i8> 767 %9 = bitcast <16 x i8> %1 to <4 x i32> 768 %10 = insertelement <4 x i32> %9, i32 %4, i64 0 769 %11 = bitcast <4 x i32> %10 to <16 x i8> 770 %12 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %8, <16 x i8> %11) 771 %13 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %12) 772 store <16 x i8> %13, <16 x i8>* %2, align 8 773 ret void 774} 775 776define arm_aapcs_vfpcc void @aese_set32_via_val(i32 %0, <16 x i8> %1, <16 x i8>* %2) nounwind { 777; CHECK-FIX-LABEL: aese_set32_via_val: 778; CHECK-FIX: @ %bb.0: 779; CHECK-FIX-NEXT: vorr q0, q0, q0 780; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r1] 781; CHECK-FIX-NEXT: vmov.32 d0[0], r0 782; CHECK-FIX-NEXT: vmov.32 d16[0], r0 783; CHECK-FIX-NEXT: aese.8 q8, q0 784; CHECK-FIX-NEXT: aesmc.8 q8, q8 785; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r1] 786; CHECK-FIX-NEXT: bx lr 787 %4 = bitcast <16 x i8>* %2 to <4 x i32>* 788 %5 = load <4 x i32>, <4 x i32>* %4, align 8 789 %6 = insertelement <4 x i32> %5, i32 %0, i64 0 790 %7 = bitcast <4 x i32> %6 to <16 x i8> 791 %8 = bitcast <16 x i8> %1 to <4 x i32> 792 %9 = insertelement <4 x i32> %8, i32 %0, i64 0 793 %10 = bitcast <4 x i32> %9 to <16 x i8> 794 %11 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %7, <16 x i8> %10) 795 %12 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %11) 796 store <16 x i8> %12, <16 x i8>* %2, align 8 797 ret void 798} 799 800define arm_aapcs_vfpcc void @aese_set32_cond_via_ptr(i1 zeroext %0, i32* %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 801; CHECK-FIX-LABEL: aese_set32_cond_via_ptr: 802; CHECK-FIX: @ %bb.0: 803; CHECK-FIX-NEXT: vorr q0, q0, q0 804; CHECK-FIX-NEXT: cmp r0, #0 805; CHECK-FIX-NEXT: beq .LBB24_2 806; CHECK-FIX-NEXT: @ %bb.1: 807; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 808; CHECK-FIX-NEXT: vld1.32 {d16[0]}, [r1:32] 809; CHECK-FIX-NEXT: cmp r0, #0 810; CHECK-FIX-NEXT: bne .LBB24_3 811; CHECK-FIX-NEXT: b .LBB24_4 812; CHECK-FIX-NEXT: .LBB24_2: 813; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 814; CHECK-FIX-NEXT: cmp r0, #0 815; CHECK-FIX-NEXT: beq .LBB24_4 816; CHECK-FIX-NEXT: .LBB24_3: 817; CHECK-FIX-NEXT: vld1.32 {d0[0]}, [r1:32] 818; CHECK-FIX-NEXT: .LBB24_4: 819; CHECK-FIX-NEXT: aese.8 q8, q0 820; CHECK-FIX-NEXT: aesmc.8 q8, q8 821; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 822; CHECK-FIX-NEXT: bx lr 823 br i1 %0, label %5, label %10 824 8255: 826 %6 = load i32, i32* %1, align 4 827 %7 = bitcast <16 x i8>* %3 to <4 x i32>* 828 %8 = load <4 x i32>, <4 x i32>* %7, align 8 829 %9 = insertelement <4 x i32> %8, i32 %6, i64 0 830 br label %13 831 83210: 833 %11 = bitcast <16 x i8>* %3 to <4 x i32>* 834 %12 = load <4 x i32>, <4 x i32>* %11, align 8 835 br label %13 836 83713: 838 %14 = phi <4 x i32> [ %9, %5 ], [ %12, %10 ] 839 br i1 %0, label %15, label %19 840 84115: 842 %16 = load i32, i32* %1, align 4 843 %17 = bitcast <16 x i8> %2 to <4 x i32> 844 %18 = insertelement <4 x i32> %17, i32 %16, i64 0 845 br label %21 846 84719: 848 %20 = bitcast <16 x i8> %2 to <4 x i32> 849 br label %21 850 85121: 852 %22 = phi <4 x i32> [ %18, %15 ], [ %20, %19 ] 853 %23 = bitcast <4 x i32> %14 to <16 x i8> 854 %24 = bitcast <4 x i32> %22 to <16 x i8> 855 %25 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %23, <16 x i8> %24) 856 %26 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %25) 857 store <16 x i8> %26, <16 x i8>* %3, align 8 858 ret void 859} 860 861define arm_aapcs_vfpcc void @aese_set32_cond_via_val(i1 zeroext %0, i32 %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 862; CHECK-FIX-LABEL: aese_set32_cond_via_val: 863; CHECK-FIX: @ %bb.0: 864; CHECK-FIX-NEXT: vorr q0, q0, q0 865; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 866; CHECK-FIX-NEXT: cmp r0, #0 867; CHECK-FIX-NEXT: beq .LBB25_2 868; CHECK-FIX-NEXT: @ %bb.1: 869; CHECK-FIX-NEXT: vmov.32 d16[0], r1 870; CHECK-FIX-NEXT: .LBB25_2: @ %select.end 871; CHECK-FIX-NEXT: cmp r0, #0 872; CHECK-FIX-NEXT: beq .LBB25_4 873; CHECK-FIX-NEXT: @ %bb.3: 874; CHECK-FIX-NEXT: vmov.32 d0[0], r1 875; CHECK-FIX-NEXT: .LBB25_4: @ %select.end1 876; CHECK-FIX-NEXT: aese.8 q8, q0 877; CHECK-FIX-NEXT: aesmc.8 q8, q8 878; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 879; CHECK-FIX-NEXT: bx lr 880 %5 = bitcast <16 x i8>* %3 to <4 x i32>* 881 %6 = load <4 x i32>, <4 x i32>* %5, align 8 882 %7 = insertelement <4 x i32> %6, i32 %1, i64 0 883 %8 = select i1 %0, <4 x i32> %7, <4 x i32> %6 884 %9 = bitcast <16 x i8> %2 to <4 x i32> 885 %10 = insertelement <4 x i32> %9, i32 %1, i64 0 886 %11 = select i1 %0, <4 x i32> %10, <4 x i32> %9 887 %12 = bitcast <4 x i32> %8 to <16 x i8> 888 %13 = bitcast <4 x i32> %11 to <16 x i8> 889 %14 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %12, <16 x i8> %13) 890 %15 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %14) 891 store <16 x i8> %15, <16 x i8>* %3, align 8 892 ret void 893} 894 895define arm_aapcs_vfpcc void @aese_set32_loop_via_ptr(i32 %0, i32* %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 896; CHECK-FIX-LABEL: aese_set32_loop_via_ptr: 897; CHECK-FIX: @ %bb.0: 898; CHECK-FIX-NEXT: vorr q0, q0, q0 899; CHECK-FIX-NEXT: ldr r1, [r1] 900; CHECK-FIX-NEXT: cmp r0, #0 901; CHECK-FIX-NEXT: str r1, [r2] 902; CHECK-FIX-NEXT: bxeq lr 903; CHECK-FIX-NEXT: .LBB26_1: 904; CHECK-FIX-NEXT: vmov.32 d0[0], r1 905; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 906; CHECK-FIX-NEXT: .LBB26_2: @ =>This Inner Loop Header: Depth=1 907; CHECK-FIX-NEXT: aese.8 q8, q0 908; CHECK-FIX-NEXT: subs r0, r0, #1 909; CHECK-FIX-NEXT: aesmc.8 q8, q8 910; CHECK-FIX-NEXT: bne .LBB26_2 911; CHECK-FIX-NEXT: @ %bb.3: 912; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 913; CHECK-FIX-NEXT: bx lr 914 %5 = load i32, i32* %1, align 4 915 %6 = bitcast <16 x i8> %2 to <4 x i32> 916 %7 = insertelement <4 x i32> %6, i32 %5, i64 0 917 %8 = bitcast <4 x i32> %7 to <16 x i8> 918 %9 = bitcast <16 x i8>* %3 to i32* 919 store i32 %5, i32* %9, align 8 920 %10 = icmp eq i32 %0, 0 921 br i1 %10, label %14, label %11 922 92311: 924 %12 = load <16 x i8>, <16 x i8>* %3, align 8 925 br label %15 926 92713: 928 store <16 x i8> %19, <16 x i8>* %3, align 8 929 br label %14 930 93114: 932 ret void 933 93415: 935 %16 = phi <16 x i8> [ %12, %11 ], [ %19, %15 ] 936 %17 = phi i32 [ 0, %11 ], [ %20, %15 ] 937 %18 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %16, <16 x i8> %8) 938 %19 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %18) 939 %20 = add nuw i32 %17, 1 940 %21 = icmp eq i32 %20, %0 941 br i1 %21, label %13, label %15 942} 943 944define arm_aapcs_vfpcc void @aese_set32_loop_via_val(i32 %0, i32 %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 945; CHECK-FIX-LABEL: aese_set32_loop_via_val: 946; CHECK-FIX: @ %bb.0: 947; CHECK-FIX-NEXT: vorr q0, q0, q0 948; CHECK-FIX-NEXT: cmp r0, #0 949; CHECK-FIX-NEXT: bxeq lr 950; CHECK-FIX-NEXT: .LBB27_1: 951; CHECK-FIX-NEXT: vmov.32 d0[0], r1 952; CHECK-FIX-NEXT: .LBB27_2: @ =>This Inner Loop Header: Depth=1 953; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 954; CHECK-FIX-NEXT: subs r0, r0, #1 955; CHECK-FIX-NEXT: vmov.32 d16[0], r1 956; CHECK-FIX-NEXT: aese.8 q8, q0 957; CHECK-FIX-NEXT: aesmc.8 q8, q8 958; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 959; CHECK-FIX-NEXT: bne .LBB27_2 960; CHECK-FIX-NEXT: @ %bb.3: 961; CHECK-FIX-NEXT: bx lr 962 %5 = icmp eq i32 %0, 0 963 br i1 %5, label %12, label %6 964 9656: 966 %7 = bitcast <16 x i8> %2 to <4 x i32> 967 %8 = insertelement <4 x i32> %7, i32 %1, i64 0 968 %9 = bitcast <4 x i32> %8 to <16 x i8> 969 %10 = bitcast <16 x i8>* %3 to <4 x i32>* 970 %11 = bitcast <16 x i8>* %3 to i32* 971 br label %13 972 97312: 974 ret void 975 97613: 977 %14 = phi i32 [ 0, %6 ], [ %20, %13 ] 978 %15 = load <4 x i32>, <4 x i32>* %10, align 8 979 %16 = insertelement <4 x i32> %15, i32 %1, i64 0 980 %17 = bitcast <4 x i32> %16 to <16 x i8> 981 store i32 %1, i32* %11, align 8 982 %18 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %17, <16 x i8> %9) 983 %19 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %18) 984 store <16 x i8> %19, <16 x i8>* %3, align 8 985 %20 = add nuw i32 %14, 1 986 %21 = icmp eq i32 %20, %0 987 br i1 %21, label %12, label %13 988} 989 990define arm_aapcs_vfpcc void @aese_set64_via_ptr(i64* %0, <16 x i8> %1, <16 x i8>* %2) nounwind { 991; CHECK-FIX-NOSCHED-LABEL: aese_set64_via_ptr: 992; CHECK-FIX-NOSCHED: @ %bb.0: 993; CHECK-FIX-NOSCHED-NEXT: vorr q0, q0, q0 994; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r1] 995; CHECK-FIX-NOSCHED-NEXT: vldr d0, [r0] 996; CHECK-FIX-NOSCHED-NEXT: vorr d16, d0, d0 997; CHECK-FIX-NOSCHED-NEXT: aese.8 q8, q0 998; CHECK-FIX-NOSCHED-NEXT: aesmc.8 q8, q8 999; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r1] 1000; CHECK-FIX-NOSCHED-NEXT: bx lr 1001; 1002; CHECK-CORTEX-FIX-LABEL: aese_set64_via_ptr: 1003; CHECK-CORTEX-FIX: @ %bb.0: 1004; CHECK-CORTEX-FIX-NEXT: vorr q0, q0, q0 1005; CHECK-CORTEX-FIX-NEXT: vldr d0, [r0] 1006; CHECK-CORTEX-FIX-NEXT: vld1.64 {d16, d17}, [r1] 1007; CHECK-CORTEX-FIX-NEXT: vorr d16, d0, d0 1008; CHECK-CORTEX-FIX-NEXT: aese.8 q8, q0 1009; CHECK-CORTEX-FIX-NEXT: aesmc.8 q8, q8 1010; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r1] 1011; CHECK-CORTEX-FIX-NEXT: bx lr 1012 %4 = load i64, i64* %0, align 8 1013 %5 = bitcast <16 x i8>* %2 to <2 x i64>* 1014 %6 = load <2 x i64>, <2 x i64>* %5, align 8 1015 %7 = insertelement <2 x i64> %6, i64 %4, i64 0 1016 %8 = bitcast <2 x i64> %7 to <16 x i8> 1017 %9 = bitcast <16 x i8> %1 to <2 x i64> 1018 %10 = insertelement <2 x i64> %9, i64 %4, i64 0 1019 %11 = bitcast <2 x i64> %10 to <16 x i8> 1020 %12 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %8, <16 x i8> %11) 1021 %13 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %12) 1022 store <16 x i8> %13, <16 x i8>* %2, align 8 1023 ret void 1024} 1025 1026define arm_aapcs_vfpcc void @aese_set64_via_val(i64 %0, <16 x i8> %1, <16 x i8>* %2) nounwind { 1027; CHECK-FIX-LABEL: aese_set64_via_val: 1028; CHECK-FIX: @ %bb.0: 1029; CHECK-FIX-NEXT: vorr q0, q0, q0 1030; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 1031; CHECK-FIX-NEXT: vmov.32 d0[0], r0 1032; CHECK-FIX-NEXT: vmov.32 d16[0], r0 1033; CHECK-FIX-NEXT: vmov.32 d0[1], r1 1034; CHECK-FIX-NEXT: vmov.32 d16[1], r1 1035; CHECK-FIX-NEXT: aese.8 q8, q0 1036; CHECK-FIX-NEXT: aesmc.8 q8, q8 1037; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 1038; CHECK-FIX-NEXT: bx lr 1039 %4 = bitcast <16 x i8>* %2 to <2 x i64>* 1040 %5 = load <2 x i64>, <2 x i64>* %4, align 8 1041 %6 = insertelement <2 x i64> %5, i64 %0, i64 0 1042 %7 = bitcast <2 x i64> %6 to <16 x i8> 1043 %8 = bitcast <16 x i8> %1 to <2 x i64> 1044 %9 = insertelement <2 x i64> %8, i64 %0, i64 0 1045 %10 = bitcast <2 x i64> %9 to <16 x i8> 1046 %11 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %7, <16 x i8> %10) 1047 %12 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %11) 1048 store <16 x i8> %12, <16 x i8>* %2, align 8 1049 ret void 1050} 1051 1052define arm_aapcs_vfpcc void @aese_set64_cond_via_ptr(i1 zeroext %0, i64* %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 1053; CHECK-FIX-NOSCHED-LABEL: aese_set64_cond_via_ptr: 1054; CHECK-FIX-NOSCHED: @ %bb.0: 1055; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 1056; CHECK-FIX-NOSCHED-NEXT: beq .LBB30_2 1057; CHECK-FIX-NOSCHED-NEXT: @ %bb.1: 1058; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r2] 1059; CHECK-FIX-NOSCHED-NEXT: vldr d16, [r1] 1060; CHECK-FIX-NOSCHED-NEXT: b .LBB30_3 1061; CHECK-FIX-NOSCHED-NEXT: .LBB30_2: 1062; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r2] 1063; CHECK-FIX-NOSCHED-NEXT: .LBB30_3: 1064; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 1065; CHECK-FIX-NOSCHED-NEXT: vldrne d0, [r1] 1066; CHECK-FIX-NOSCHED-NEXT: vorr q0, q0, q0 1067; CHECK-FIX-NOSCHED-NEXT: aese.8 q8, q0 1068; CHECK-FIX-NOSCHED-NEXT: aesmc.8 q8, q8 1069; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r2] 1070; CHECK-FIX-NOSCHED-NEXT: bx lr 1071; 1072; CHECK-CORTEX-FIX-LABEL: aese_set64_cond_via_ptr: 1073; CHECK-CORTEX-FIX: @ %bb.0: 1074; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 1075; CHECK-CORTEX-FIX-NEXT: beq .LBB30_2 1076; CHECK-CORTEX-FIX-NEXT: @ %bb.1: 1077; CHECK-CORTEX-FIX-NEXT: vldr d18, [r1] 1078; CHECK-CORTEX-FIX-NEXT: vld1.64 {d16, d17}, [r2] 1079; CHECK-CORTEX-FIX-NEXT: vorr d16, d18, d18 1080; CHECK-CORTEX-FIX-NEXT: b .LBB30_3 1081; CHECK-CORTEX-FIX-NEXT: .LBB30_2: 1082; CHECK-CORTEX-FIX-NEXT: vld1.64 {d16, d17}, [r2] 1083; CHECK-CORTEX-FIX-NEXT: .LBB30_3: 1084; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 1085; CHECK-CORTEX-FIX-NEXT: vldrne d0, [r1] 1086; CHECK-CORTEX-FIX-NEXT: vorr q0, q0, q0 1087; CHECK-CORTEX-FIX-NEXT: aese.8 q8, q0 1088; CHECK-CORTEX-FIX-NEXT: aesmc.8 q8, q8 1089; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r2] 1090; CHECK-CORTEX-FIX-NEXT: bx lr 1091 br i1 %0, label %5, label %10 1092 10935: 1094 %6 = load i64, i64* %1, align 8 1095 %7 = bitcast <16 x i8>* %3 to <2 x i64>* 1096 %8 = load <2 x i64>, <2 x i64>* %7, align 8 1097 %9 = insertelement <2 x i64> %8, i64 %6, i64 0 1098 br label %13 1099 110010: 1101 %11 = bitcast <16 x i8>* %3 to <2 x i64>* 1102 %12 = load <2 x i64>, <2 x i64>* %11, align 8 1103 br label %13 1104 110513: 1106 %14 = phi <2 x i64> [ %9, %5 ], [ %12, %10 ] 1107 br i1 %0, label %15, label %19 1108 110915: 1110 %16 = load i64, i64* %1, align 8 1111 %17 = bitcast <16 x i8> %2 to <2 x i64> 1112 %18 = insertelement <2 x i64> %17, i64 %16, i64 0 1113 br label %21 1114 111519: 1116 %20 = bitcast <16 x i8> %2 to <2 x i64> 1117 br label %21 1118 111921: 1120 %22 = phi <2 x i64> [ %18, %15 ], [ %20, %19 ] 1121 %23 = bitcast <2 x i64> %14 to <16 x i8> 1122 %24 = bitcast <2 x i64> %22 to <16 x i8> 1123 %25 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %23, <16 x i8> %24) 1124 %26 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %25) 1125 store <16 x i8> %26, <16 x i8>* %3, align 8 1126 ret void 1127} 1128 1129define arm_aapcs_vfpcc void @aese_set64_cond_via_val(i1 zeroext %0, i64 %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 1130; CHECK-FIX-LABEL: aese_set64_cond_via_val: 1131; CHECK-FIX: @ %bb.0: 1132; CHECK-FIX-NEXT: vorr q0, q0, q0 1133; CHECK-FIX-NEXT: ldr r1, [sp] 1134; CHECK-FIX-NEXT: cmp r0, #0 1135; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r1] 1136; CHECK-FIX-NEXT: beq .LBB31_2 1137; CHECK-FIX-NEXT: @ %bb.1: 1138; CHECK-FIX-NEXT: vmov.32 d16[0], r2 1139; CHECK-FIX-NEXT: vmov.32 d16[1], r3 1140; CHECK-FIX-NEXT: .LBB31_2: @ %select.end 1141; CHECK-FIX-NEXT: cmp r0, #0 1142; CHECK-FIX-NEXT: beq .LBB31_4 1143; CHECK-FIX-NEXT: @ %bb.3: 1144; CHECK-FIX-NEXT: vmov.32 d0[0], r2 1145; CHECK-FIX-NEXT: vmov.32 d0[1], r3 1146; CHECK-FIX-NEXT: .LBB31_4: @ %select.end1 1147; CHECK-FIX-NEXT: aese.8 q8, q0 1148; CHECK-FIX-NEXT: aesmc.8 q8, q8 1149; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r1] 1150; CHECK-FIX-NEXT: bx lr 1151 %5 = bitcast <16 x i8>* %3 to <2 x i64>* 1152 %6 = load <2 x i64>, <2 x i64>* %5, align 8 1153 %7 = insertelement <2 x i64> %6, i64 %1, i64 0 1154 %8 = select i1 %0, <2 x i64> %7, <2 x i64> %6 1155 %9 = bitcast <16 x i8> %2 to <2 x i64> 1156 %10 = insertelement <2 x i64> %9, i64 %1, i64 0 1157 %11 = select i1 %0, <2 x i64> %10, <2 x i64> %9 1158 %12 = bitcast <2 x i64> %8 to <16 x i8> 1159 %13 = bitcast <2 x i64> %11 to <16 x i8> 1160 %14 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %12, <16 x i8> %13) 1161 %15 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %14) 1162 store <16 x i8> %15, <16 x i8>* %3, align 8 1163 ret void 1164} 1165 1166define arm_aapcs_vfpcc void @aese_set64_loop_via_ptr(i32 %0, i64* %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 1167; CHECK-FIX-NOSCHED-LABEL: aese_set64_loop_via_ptr: 1168; CHECK-FIX-NOSCHED: @ %bb.0: 1169; CHECK-FIX-NOSCHED-NEXT: vorr q0, q0, q0 1170; CHECK-FIX-NOSCHED-NEXT: .save {r4, r5, r11, lr} 1171; CHECK-FIX-NOSCHED-NEXT: push {r4, r5, r11, lr} 1172; CHECK-FIX-NOSCHED-NEXT: ldrd r4, r5, [r1] 1173; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 1174; CHECK-FIX-NOSCHED-NEXT: strd r4, r5, [r2] 1175; CHECK-FIX-NOSCHED-NEXT: beq .LBB32_4 1176; CHECK-FIX-NOSCHED-NEXT: @ %bb.1: 1177; CHECK-FIX-NOSCHED-NEXT: vmov d0, r4, r5 1178; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r2] 1179; CHECK-FIX-NOSCHED-NEXT: .LBB32_2: @ =>This Inner Loop Header: Depth=1 1180; CHECK-FIX-NOSCHED-NEXT: aese.8 q8, q0 1181; CHECK-FIX-NOSCHED-NEXT: subs r0, r0, #1 1182; CHECK-FIX-NOSCHED-NEXT: aesmc.8 q8, q8 1183; CHECK-FIX-NOSCHED-NEXT: bne .LBB32_2 1184; CHECK-FIX-NOSCHED-NEXT: @ %bb.3: 1185; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r2] 1186; CHECK-FIX-NOSCHED-NEXT: .LBB32_4: 1187; CHECK-FIX-NOSCHED-NEXT: pop {r4, r5, r11, pc} 1188; 1189; CHECK-CORTEX-FIX-LABEL: aese_set64_loop_via_ptr: 1190; CHECK-CORTEX-FIX: @ %bb.0: 1191; CHECK-CORTEX-FIX-NEXT: vorr q0, q0, q0 1192; CHECK-CORTEX-FIX-NEXT: .save {r4, r5, r11, lr} 1193; CHECK-CORTEX-FIX-NEXT: push {r4, r5, r11, lr} 1194; CHECK-CORTEX-FIX-NEXT: ldrd r4, r5, [r1] 1195; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 1196; CHECK-CORTEX-FIX-NEXT: strd r4, r5, [r2] 1197; CHECK-CORTEX-FIX-NEXT: popeq {r4, r5, r11, pc} 1198; CHECK-CORTEX-FIX-NEXT: .LBB32_1: 1199; CHECK-CORTEX-FIX-NEXT: vmov d0, r4, r5 1200; CHECK-CORTEX-FIX-NEXT: vld1.64 {d16, d17}, [r2] 1201; CHECK-CORTEX-FIX-NEXT: .LBB32_2: @ =>This Inner Loop Header: Depth=1 1202; CHECK-CORTEX-FIX-NEXT: aese.8 q8, q0 1203; CHECK-CORTEX-FIX-NEXT: subs r0, r0, #1 1204; CHECK-CORTEX-FIX-NEXT: aesmc.8 q8, q8 1205; CHECK-CORTEX-FIX-NEXT: bne .LBB32_2 1206; CHECK-CORTEX-FIX-NEXT: @ %bb.3: 1207; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r2] 1208; CHECK-CORTEX-FIX-NEXT: pop {r4, r5, r11, pc} 1209 %5 = load i64, i64* %1, align 8 1210 %6 = bitcast <16 x i8> %2 to <2 x i64> 1211 %7 = insertelement <2 x i64> %6, i64 %5, i64 0 1212 %8 = bitcast <2 x i64> %7 to <16 x i8> 1213 %9 = bitcast <16 x i8>* %3 to i64* 1214 store i64 %5, i64* %9, align 8 1215 %10 = icmp eq i32 %0, 0 1216 br i1 %10, label %14, label %11 1217 121811: 1219 %12 = load <16 x i8>, <16 x i8>* %3, align 8 1220 br label %15 1221 122213: 1223 store <16 x i8> %19, <16 x i8>* %3, align 8 1224 br label %14 1225 122614: 1227 ret void 1228 122915: 1230 %16 = phi <16 x i8> [ %12, %11 ], [ %19, %15 ] 1231 %17 = phi i32 [ 0, %11 ], [ %20, %15 ] 1232 %18 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %16, <16 x i8> %8) 1233 %19 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %18) 1234 %20 = add nuw i32 %17, 1 1235 %21 = icmp eq i32 %20, %0 1236 br i1 %21, label %13, label %15 1237} 1238 1239define arm_aapcs_vfpcc void @aese_set64_loop_via_val(i32 %0, i64 %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 1240; CHECK-FIX-LABEL: aese_set64_loop_via_val: 1241; CHECK-FIX: @ %bb.0: 1242; CHECK-FIX-NEXT: vorr q0, q0, q0 1243; CHECK-FIX-NEXT: cmp r0, #0 1244; CHECK-FIX-NEXT: bxeq lr 1245; CHECK-FIX-NEXT: .LBB33_1: 1246; CHECK-FIX-NEXT: vmov.32 d0[0], r2 1247; CHECK-FIX-NEXT: ldr r1, [sp] 1248; CHECK-FIX-NEXT: vmov.32 d0[1], r3 1249; CHECK-FIX-NEXT: .LBB33_2: @ =>This Inner Loop Header: Depth=1 1250; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r1] 1251; CHECK-FIX-NEXT: subs r0, r0, #1 1252; CHECK-FIX-NEXT: vmov.32 d16[0], r2 1253; CHECK-FIX-NEXT: vmov.32 d16[1], r3 1254; CHECK-FIX-NEXT: aese.8 q8, q0 1255; CHECK-FIX-NEXT: aesmc.8 q8, q8 1256; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r1] 1257; CHECK-FIX-NEXT: bne .LBB33_2 1258; CHECK-FIX-NEXT: @ %bb.3: 1259; CHECK-FIX-NEXT: bx lr 1260 %5 = icmp eq i32 %0, 0 1261 br i1 %5, label %12, label %6 1262 12636: 1264 %7 = bitcast <16 x i8> %2 to <2 x i64> 1265 %8 = insertelement <2 x i64> %7, i64 %1, i64 0 1266 %9 = bitcast <2 x i64> %8 to <16 x i8> 1267 %10 = bitcast <16 x i8>* %3 to <2 x i64>* 1268 %11 = bitcast <16 x i8>* %3 to i64* 1269 br label %13 1270 127112: 1272 ret void 1273 127413: 1275 %14 = phi i32 [ 0, %6 ], [ %20, %13 ] 1276 %15 = load <2 x i64>, <2 x i64>* %10, align 8 1277 %16 = insertelement <2 x i64> %15, i64 %1, i64 0 1278 %17 = bitcast <2 x i64> %16 to <16 x i8> 1279 store i64 %1, i64* %11, align 8 1280 %18 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %17, <16 x i8> %9) 1281 %19 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %18) 1282 store <16 x i8> %19, <16 x i8>* %3, align 8 1283 %20 = add nuw i32 %14, 1 1284 %21 = icmp eq i32 %20, %0 1285 br i1 %21, label %12, label %13 1286} 1287 1288define arm_aapcs_vfpcc void @aese_setf16_via_ptr(half* %0, <16 x i8> %1, <16 x i8>* %2) nounwind { 1289; CHECK-FIX-NOSCHED-LABEL: aese_setf16_via_ptr: 1290; CHECK-FIX-NOSCHED: @ %bb.0: 1291; CHECK-FIX-NOSCHED-NEXT: vorr q0, q0, q0 1292; CHECK-FIX-NOSCHED-NEXT: ldrh r0, [r0] 1293; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r1] 1294; CHECK-FIX-NOSCHED-NEXT: vmov.16 d0[0], r0 1295; CHECK-FIX-NOSCHED-NEXT: vmov.16 d16[0], r0 1296; CHECK-FIX-NOSCHED-NEXT: aese.8 q8, q0 1297; CHECK-FIX-NOSCHED-NEXT: aesmc.8 q8, q8 1298; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r1] 1299; CHECK-FIX-NOSCHED-NEXT: bx lr 1300; 1301; CHECK-CORTEX-FIX-LABEL: aese_setf16_via_ptr: 1302; CHECK-CORTEX-FIX: @ %bb.0: 1303; CHECK-CORTEX-FIX-NEXT: vorr q0, q0, q0 1304; CHECK-CORTEX-FIX-NEXT: vld1.64 {d16, d17}, [r1] 1305; CHECK-CORTEX-FIX-NEXT: ldrh r0, [r0] 1306; CHECK-CORTEX-FIX-NEXT: vmov.16 d0[0], r0 1307; CHECK-CORTEX-FIX-NEXT: vmov.16 d16[0], r0 1308; CHECK-CORTEX-FIX-NEXT: aese.8 q8, q0 1309; CHECK-CORTEX-FIX-NEXT: aesmc.8 q8, q8 1310; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r1] 1311; CHECK-CORTEX-FIX-NEXT: bx lr 1312 %4 = bitcast half* %0 to i16* 1313 %5 = load i16, i16* %4, align 2 1314 %6 = bitcast <16 x i8>* %2 to <8 x i16>* 1315 %7 = load <8 x i16>, <8 x i16>* %6, align 8 1316 %8 = insertelement <8 x i16> %7, i16 %5, i64 0 1317 %9 = bitcast <8 x i16> %8 to <16 x i8> 1318 %10 = bitcast <16 x i8> %1 to <8 x i16> 1319 %11 = insertelement <8 x i16> %10, i16 %5, i64 0 1320 %12 = bitcast <8 x i16> %11 to <16 x i8> 1321 %13 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %9, <16 x i8> %12) 1322 %14 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %13) 1323 store <16 x i8> %14, <16 x i8>* %2, align 8 1324 ret void 1325} 1326 1327define arm_aapcs_vfpcc void @aese_setf16_via_val(half %0, <16 x i8> %1, <16 x i8>* %2) nounwind { 1328; CHECK-FIX-LABEL: aese_setf16_via_val: 1329; CHECK-FIX: @ %bb.0: 1330; CHECK-FIX-NEXT: vorr q1, q1, q1 1331; CHECK-FIX-NEXT: vmov r1, s0 1332; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r0] 1333; CHECK-FIX-NEXT: vmov.16 d2[0], r1 1334; CHECK-FIX-NEXT: vmov.16 d16[0], r1 1335; CHECK-FIX-NEXT: aese.8 q8, q1 1336; CHECK-FIX-NEXT: aesmc.8 q8, q8 1337; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r0] 1338; CHECK-FIX-NEXT: bx lr 1339 %4 = bitcast <16 x i8>* %2 to <8 x i16>* 1340 %5 = load <8 x i16>, <8 x i16>* %4, align 8 1341 %6 = bitcast half %0 to i16 1342 %7 = insertelement <8 x i16> %5, i16 %6, i64 0 1343 %8 = bitcast <8 x i16> %7 to <16 x i8> 1344 %9 = bitcast <16 x i8> %1 to <8 x i16> 1345 %10 = insertelement <8 x i16> %9, i16 %6, i64 0 1346 %11 = bitcast <8 x i16> %10 to <16 x i8> 1347 %12 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %8, <16 x i8> %11) 1348 %13 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %12) 1349 store <16 x i8> %13, <16 x i8>* %2, align 8 1350 ret void 1351} 1352 1353define arm_aapcs_vfpcc void @aese_setf16_cond_via_ptr(i1 zeroext %0, half* %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 1354; CHECK-FIX-NOSCHED-LABEL: aese_setf16_cond_via_ptr: 1355; CHECK-FIX-NOSCHED: @ %bb.0: 1356; CHECK-FIX-NOSCHED-NEXT: .save {r4, r5, r6, r7, r8, lr} 1357; CHECK-FIX-NOSCHED-NEXT: push {r4, r5, r6, r7, r8, lr} 1358; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 1359; CHECK-FIX-NOSCHED-NEXT: beq .LBB36_2 1360; CHECK-FIX-NOSCHED-NEXT: @ %bb.1: 1361; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r2] 1362; CHECK-FIX-NOSCHED-NEXT: vld1.16 {d16[0]}, [r1:16] 1363; CHECK-FIX-NOSCHED-NEXT: vmov r3, r4, d17 1364; CHECK-FIX-NOSCHED-NEXT: vmov lr, r12, d16 1365; CHECK-FIX-NOSCHED-NEXT: vmov s6, r3 1366; CHECK-FIX-NOSCHED-NEXT: lsr r3, r3, #16 1367; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s8, s6 1368; CHECK-FIX-NOSCHED-NEXT: vmov s4, r4 1369; CHECK-FIX-NOSCHED-NEXT: lsr r4, r4, #16 1370; CHECK-FIX-NOSCHED-NEXT: vmov s10, r3 1371; CHECK-FIX-NOSCHED-NEXT: vmov s6, r12 1372; CHECK-FIX-NOSCHED-NEXT: lsr r12, r12, #16 1373; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s12, s6 1374; CHECK-FIX-NOSCHED-NEXT: vmov s6, lr 1375; CHECK-FIX-NOSCHED-NEXT: lsr lr, lr, #16 1376; CHECK-FIX-NOSCHED-NEXT: vmov s14, r12 1377; CHECK-FIX-NOSCHED-NEXT: vmov s7, lr 1378; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s5, s6 1379; CHECK-FIX-NOSCHED-NEXT: vmov s6, r4 1380; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s4, s4 1381; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s6, s6 1382; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s10, s10 1383; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s14, s14 1384; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s7, s7 1385; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 1386; CHECK-FIX-NOSCHED-NEXT: bne .LBB36_3 1387; CHECK-FIX-NOSCHED-NEXT: b .LBB36_4 1388; CHECK-FIX-NOSCHED-NEXT: .LBB36_2: 1389; CHECK-FIX-NOSCHED-NEXT: ldrh r4, [r2, #10] 1390; CHECK-FIX-NOSCHED-NEXT: ldrh lr, [r2, #6] 1391; CHECK-FIX-NOSCHED-NEXT: ldrh r6, [r2, #2] 1392; CHECK-FIX-NOSCHED-NEXT: ldrh r7, [r2, #14] 1393; CHECK-FIX-NOSCHED-NEXT: vmov s8, r4 1394; CHECK-FIX-NOSCHED-NEXT: ldrh r3, [r2, #12] 1395; CHECK-FIX-NOSCHED-NEXT: vmov s12, lr 1396; CHECK-FIX-NOSCHED-NEXT: ldrh r12, [r2, #8] 1397; CHECK-FIX-NOSCHED-NEXT: vmov s5, r6 1398; CHECK-FIX-NOSCHED-NEXT: ldrh r5, [r2, #4] 1399; CHECK-FIX-NOSCHED-NEXT: vmov s4, r7 1400; CHECK-FIX-NOSCHED-NEXT: ldrh r8, [r2] 1401; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s6, s4 1402; CHECK-FIX-NOSCHED-NEXT: vmov s4, r3 1403; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s10, s8 1404; CHECK-FIX-NOSCHED-NEXT: vmov s8, r12 1405; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s14, s12 1406; CHECK-FIX-NOSCHED-NEXT: vmov s12, r5 1407; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s7, s5 1408; CHECK-FIX-NOSCHED-NEXT: vmov s5, r8 1409; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s4, s4 1410; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s8, s8 1411; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s12, s12 1412; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s5, s5 1413; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 1414; CHECK-FIX-NOSCHED-NEXT: beq .LBB36_4 1415; CHECK-FIX-NOSCHED-NEXT: .LBB36_3: 1416; CHECK-FIX-NOSCHED-NEXT: vld1.16 {d0[0]}, [r1:16] 1417; CHECK-FIX-NOSCHED-NEXT: .LBB36_4: 1418; CHECK-FIX-NOSCHED-NEXT: vmov r0, r1, d0 1419; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s5, s5 1420; CHECK-FIX-NOSCHED-NEXT: vmov r3, r7, d1 1421; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s12, s12 1422; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s8, s8 1423; CHECK-FIX-NOSCHED-NEXT: vmov s1, r1 1424; CHECK-FIX-NOSCHED-NEXT: lsr r1, r1, #16 1425; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s9, s1 1426; CHECK-FIX-NOSCHED-NEXT: vmov s1, r0 1427; CHECK-FIX-NOSCHED-NEXT: lsr r0, r0, #16 1428; CHECK-FIX-NOSCHED-NEXT: vmov s13, r1 1429; CHECK-FIX-NOSCHED-NEXT: vmov s15, r0 1430; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s11, s1 1431; CHECK-FIX-NOSCHED-NEXT: vmov r0, s5 1432; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s5, s7 1433; CHECK-FIX-NOSCHED-NEXT: vmov r1, s5 1434; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s15, s15 1435; CHECK-FIX-NOSCHED-NEXT: vmov s2, r3 1436; CHECK-FIX-NOSCHED-NEXT: lsr r3, r3, #16 1437; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s5, s15 1438; CHECK-FIX-NOSCHED-NEXT: vmov s3, r3 1439; CHECK-FIX-NOSCHED-NEXT: vmov r3, s5 1440; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s11, s11 1441; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s13, s13 1442; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s5, s9 1443; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s2, s2 1444; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s3, s3 1445; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s2, s2 1446; CHECK-FIX-NOSCHED-NEXT: vmov s0, r7 1447; CHECK-FIX-NOSCHED-NEXT: lsr r7, r7, #16 1448; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s0, s0 1449; CHECK-FIX-NOSCHED-NEXT: vmov s1, r7 1450; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s0, s0 1451; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s1, s1 1452; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r0, r1, lsl #16 1453; CHECK-FIX-NOSCHED-NEXT: vmov r1, s11 1454; CHECK-FIX-NOSCHED-NEXT: vmov.32 d16[0], r0 1455; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r1, r3, lsl #16 1456; CHECK-FIX-NOSCHED-NEXT: vmov r1, s12 1457; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s12, s14 1458; CHECK-FIX-NOSCHED-NEXT: vmov.32 d18[0], r0 1459; CHECK-FIX-NOSCHED-NEXT: vmov r0, s12 1460; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s12, s13 1461; CHECK-FIX-NOSCHED-NEXT: vmov r3, s12 1462; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r1, r0, lsl #16 1463; CHECK-FIX-NOSCHED-NEXT: vmov r1, s5 1464; CHECK-FIX-NOSCHED-NEXT: vmov.32 d16[1], r0 1465; CHECK-FIX-NOSCHED-NEXT: pkhbt r1, r1, r3, lsl #16 1466; CHECK-FIX-NOSCHED-NEXT: vmov.32 d18[1], r1 1467; CHECK-FIX-NOSCHED-NEXT: vmov r1, s8 1468; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s8, s10 1469; CHECK-FIX-NOSCHED-NEXT: vmov r3, s8 1470; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r1, r3, lsl #16 1471; CHECK-FIX-NOSCHED-NEXT: vmov r1, s2 1472; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s2, s3 1473; CHECK-FIX-NOSCHED-NEXT: vmov r3, s2 1474; CHECK-FIX-NOSCHED-NEXT: vmov.32 d17[0], r0 1475; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s2, s4 1476; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r1, r3, lsl #16 1477; CHECK-FIX-NOSCHED-NEXT: vmov r1, s0 1478; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s0, s1 1479; CHECK-FIX-NOSCHED-NEXT: vmov.32 d19[0], r0 1480; CHECK-FIX-NOSCHED-NEXT: vmov r0, s0 1481; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s0, s6 1482; CHECK-FIX-NOSCHED-NEXT: vmov r3, s0 1483; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r1, r0, lsl #16 1484; CHECK-FIX-NOSCHED-NEXT: vmov r1, s2 1485; CHECK-FIX-NOSCHED-NEXT: vmov.32 d19[1], r0 1486; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r1, r3, lsl #16 1487; CHECK-FIX-NOSCHED-NEXT: vmov.32 d17[1], r0 1488; CHECK-FIX-NOSCHED-NEXT: aese.8 q8, q9 1489; CHECK-FIX-NOSCHED-NEXT: aesmc.8 q8, q8 1490; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r2] 1491; CHECK-FIX-NOSCHED-NEXT: pop {r4, r5, r6, r7, r8, pc} 1492; 1493; CHECK-CORTEX-FIX-LABEL: aese_setf16_cond_via_ptr: 1494; CHECK-CORTEX-FIX: @ %bb.0: 1495; CHECK-CORTEX-FIX-NEXT: .save {r4, r5, r6, r7, r8, lr} 1496; CHECK-CORTEX-FIX-NEXT: push {r4, r5, r6, r7, r8, lr} 1497; CHECK-CORTEX-FIX-NEXT: .vsave {d8} 1498; CHECK-CORTEX-FIX-NEXT: vpush {d8} 1499; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 1500; CHECK-CORTEX-FIX-NEXT: beq .LBB36_2 1501; CHECK-CORTEX-FIX-NEXT: @ %bb.1: 1502; CHECK-CORTEX-FIX-NEXT: vld1.64 {d16, d17}, [r2] 1503; CHECK-CORTEX-FIX-NEXT: vld1.16 {d16[0]}, [r1:16] 1504; CHECK-CORTEX-FIX-NEXT: vmov r5, r6, d17 1505; CHECK-CORTEX-FIX-NEXT: lsr r7, r5, #16 1506; CHECK-CORTEX-FIX-NEXT: lsr r4, r6, #16 1507; CHECK-CORTEX-FIX-NEXT: vmov s4, r6 1508; CHECK-CORTEX-FIX-NEXT: vmov s6, r5 1509; CHECK-CORTEX-FIX-NEXT: vmov s14, r4 1510; CHECK-CORTEX-FIX-NEXT: vmov s7, r7 1511; CHECK-CORTEX-FIX-NEXT: vmov r12, r3, d16 1512; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s12, s4 1513; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s4, s6 1514; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s14, s14 1515; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s6, s7 1516; CHECK-CORTEX-FIX-NEXT: lsr lr, r12, #16 1517; CHECK-CORTEX-FIX-NEXT: lsr r8, r3, #16 1518; CHECK-CORTEX-FIX-NEXT: vmov s8, r3 1519; CHECK-CORTEX-FIX-NEXT: vmov s10, r12 1520; CHECK-CORTEX-FIX-NEXT: vmov s9, r8 1521; CHECK-CORTEX-FIX-NEXT: vmov s11, lr 1522; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s5, s8 1523; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s8, s10 1524; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s7, s9 1525; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s10, s11 1526; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 1527; CHECK-CORTEX-FIX-NEXT: bne .LBB36_3 1528; CHECK-CORTEX-FIX-NEXT: b .LBB36_4 1529; CHECK-CORTEX-FIX-NEXT: .LBB36_2: 1530; CHECK-CORTEX-FIX-NEXT: ldrh r12, [r2] 1531; CHECK-CORTEX-FIX-NEXT: ldrh lr, [r2, #2] 1532; CHECK-CORTEX-FIX-NEXT: ldrh r8, [r2, #4] 1533; CHECK-CORTEX-FIX-NEXT: ldrh r5, [r2, #6] 1534; CHECK-CORTEX-FIX-NEXT: ldrh r4, [r2, #8] 1535; CHECK-CORTEX-FIX-NEXT: ldrh r3, [r2, #10] 1536; CHECK-CORTEX-FIX-NEXT: ldrh r7, [r2, #12] 1537; CHECK-CORTEX-FIX-NEXT: ldrh r6, [r2, #14] 1538; CHECK-CORTEX-FIX-NEXT: vmov s4, r6 1539; CHECK-CORTEX-FIX-NEXT: vmov s6, r7 1540; CHECK-CORTEX-FIX-NEXT: vmov s5, r5 1541; CHECK-CORTEX-FIX-NEXT: vmov s8, r3 1542; CHECK-CORTEX-FIX-NEXT: vmov s10, r4 1543; CHECK-CORTEX-FIX-NEXT: vmov s9, r8 1544; CHECK-CORTEX-FIX-NEXT: vmov s11, lr 1545; CHECK-CORTEX-FIX-NEXT: vmov s13, r12 1546; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s14, s4 1547; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s12, s6 1548; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s6, s8 1549; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s4, s10 1550; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s7, s5 1551; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s5, s9 1552; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s10, s11 1553; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s8, s13 1554; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 1555; CHECK-CORTEX-FIX-NEXT: beq .LBB36_4 1556; CHECK-CORTEX-FIX-NEXT: .LBB36_3: 1557; CHECK-CORTEX-FIX-NEXT: vld1.16 {d0[0]}, [r1:16] 1558; CHECK-CORTEX-FIX-NEXT: .LBB36_4: 1559; CHECK-CORTEX-FIX-NEXT: vmov r6, r5, d1 1560; CHECK-CORTEX-FIX-NEXT: vmov r0, r1, d0 1561; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s12, s12 1562; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s14, s14 1563; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s5, s5 1564; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s4, s4 1565; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s6, s6 1566; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s8, s8 1567; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s10, s10 1568; CHECK-CORTEX-FIX-NEXT: lsr r3, r5, #16 1569; CHECK-CORTEX-FIX-NEXT: vmov s0, r5 1570; CHECK-CORTEX-FIX-NEXT: lsr r7, r1, #16 1571; CHECK-CORTEX-FIX-NEXT: lsr r4, r6, #16 1572; CHECK-CORTEX-FIX-NEXT: vmov s1, r1 1573; CHECK-CORTEX-FIX-NEXT: lsr r12, r0, #16 1574; CHECK-CORTEX-FIX-NEXT: vmov s9, r0 1575; CHECK-CORTEX-FIX-NEXT: vmov r0, s12 1576; CHECK-CORTEX-FIX-NEXT: vmov r1, s14 1577; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s12, s7 1578; CHECK-CORTEX-FIX-NEXT: vmov s2, r6 1579; CHECK-CORTEX-FIX-NEXT: vmov r5, s6 1580; CHECK-CORTEX-FIX-NEXT: vmov s13, r3 1581; CHECK-CORTEX-FIX-NEXT: vmov s15, r4 1582; CHECK-CORTEX-FIX-NEXT: vmov s16, r7 1583; CHECK-CORTEX-FIX-NEXT: vmov r4, s10 1584; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s3, s0 1585; CHECK-CORTEX-FIX-NEXT: vmov s0, r12 1586; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s11, s1 1587; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s1, s9 1588; CHECK-CORTEX-FIX-NEXT: pkhbt r12, r0, r1, lsl #16 1589; CHECK-CORTEX-FIX-NEXT: vmov r1, s5 1590; CHECK-CORTEX-FIX-NEXT: vmov r3, s12 1591; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s2, s2 1592; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s13, s13 1593; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s9, s15 1594; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s15, s16 1595; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s14, s3 1596; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s7, s11 1597; CHECK-CORTEX-FIX-NEXT: pkhbt lr, r1, r3, lsl #16 1598; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s0, s0 1599; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s2, s2 1600; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s1, s1 1601; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s3, s13 1602; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s11, s15 1603; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s9, s9 1604; CHECK-CORTEX-FIX-NEXT: vmov r3, s14 1605; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s0, s0 1606; CHECK-CORTEX-FIX-NEXT: vmov r7, s3 1607; CHECK-CORTEX-FIX-NEXT: vmov r6, s11 1608; CHECK-CORTEX-FIX-NEXT: vmov r0, s9 1609; CHECK-CORTEX-FIX-NEXT: vmov r1, s0 1610; CHECK-CORTEX-FIX-NEXT: pkhbt r3, r3, r7, lsl #16 1611; CHECK-CORTEX-FIX-NEXT: vmov r7, s7 1612; CHECK-CORTEX-FIX-NEXT: pkhbt r7, r7, r6, lsl #16 1613; CHECK-CORTEX-FIX-NEXT: vmov r6, s4 1614; CHECK-CORTEX-FIX-NEXT: pkhbt r6, r6, r5, lsl #16 1615; CHECK-CORTEX-FIX-NEXT: vmov r5, s8 1616; CHECK-CORTEX-FIX-NEXT: pkhbt r5, r5, r4, lsl #16 1617; CHECK-CORTEX-FIX-NEXT: vmov r4, s2 1618; CHECK-CORTEX-FIX-NEXT: vmov.32 d18[0], r5 1619; CHECK-CORTEX-FIX-NEXT: vmov.32 d19[0], r6 1620; CHECK-CORTEX-FIX-NEXT: vmov.32 d18[1], lr 1621; CHECK-CORTEX-FIX-NEXT: vmov.32 d19[1], r12 1622; CHECK-CORTEX-FIX-NEXT: pkhbt r0, r4, r0, lsl #16 1623; CHECK-CORTEX-FIX-NEXT: vmov r4, s1 1624; CHECK-CORTEX-FIX-NEXT: pkhbt r1, r4, r1, lsl #16 1625; CHECK-CORTEX-FIX-NEXT: vmov.32 d16[0], r1 1626; CHECK-CORTEX-FIX-NEXT: vmov.32 d17[0], r0 1627; CHECK-CORTEX-FIX-NEXT: vmov.32 d16[1], r7 1628; CHECK-CORTEX-FIX-NEXT: vmov.32 d17[1], r3 1629; CHECK-CORTEX-FIX-NEXT: aese.8 q9, q8 1630; CHECK-CORTEX-FIX-NEXT: aesmc.8 q8, q9 1631; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r2] 1632; CHECK-CORTEX-FIX-NEXT: vpop {d8} 1633; CHECK-CORTEX-FIX-NEXT: pop {r4, r5, r6, r7, r8, pc} 1634 br i1 %0, label %5, label %12 1635 16365: 1637 %6 = bitcast half* %1 to i16* 1638 %7 = load i16, i16* %6, align 2 1639 %8 = bitcast <16 x i8>* %3 to <8 x i16>* 1640 %9 = load <8 x i16>, <8 x i16>* %8, align 8 1641 %10 = insertelement <8 x i16> %9, i16 %7, i64 0 1642 %11 = bitcast <8 x i16> %10 to <8 x half> 1643 br label %15 1644 164512: 1646 %13 = bitcast <16 x i8>* %3 to <8 x half>* 1647 %14 = load <8 x half>, <8 x half>* %13, align 8 1648 br label %15 1649 165015: 1651 %16 = phi <8 x half> [ %11, %5 ], [ %14, %12 ] 1652 br i1 %0, label %17, label %23 1653 165417: 1655 %18 = bitcast half* %1 to i16* 1656 %19 = load i16, i16* %18, align 2 1657 %20 = bitcast <16 x i8> %2 to <8 x i16> 1658 %21 = insertelement <8 x i16> %20, i16 %19, i64 0 1659 %22 = bitcast <8 x i16> %21 to <8 x half> 1660 br label %25 1661 166223: 1663 %24 = bitcast <16 x i8> %2 to <8 x half> 1664 br label %25 1665 166625: 1667 %26 = phi <8 x half> [ %22, %17 ], [ %24, %23 ] 1668 %27 = bitcast <8 x half> %16 to <16 x i8> 1669 %28 = bitcast <8 x half> %26 to <16 x i8> 1670 %29 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %27, <16 x i8> %28) 1671 %30 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %29) 1672 store <16 x i8> %30, <16 x i8>* %3, align 8 1673 ret void 1674} 1675 1676define arm_aapcs_vfpcc void @aese_setf16_cond_via_val(i1 zeroext %0, half %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 1677; CHECK-FIX-NOSCHED-LABEL: aese_setf16_cond_via_val: 1678; CHECK-FIX-NOSCHED: @ %bb.0: 1679; CHECK-FIX-NOSCHED-NEXT: .save {r4, r5, r6, r7, r11, lr} 1680; CHECK-FIX-NOSCHED-NEXT: push {r4, r5, r6, r7, r11, lr} 1681; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s9, s0 1682; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 1683; CHECK-FIX-NOSCHED-NEXT: beq .LBB37_2 1684; CHECK-FIX-NOSCHED-NEXT: @ %bb.1: 1685; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s0, s9 1686; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r1] 1687; CHECK-FIX-NOSCHED-NEXT: vmov r2, s0 1688; CHECK-FIX-NOSCHED-NEXT: vmov.16 d16[0], r2 1689; CHECK-FIX-NOSCHED-NEXT: vmov r3, lr, d17 1690; CHECK-FIX-NOSCHED-NEXT: vmov r2, r12, d16 1691; CHECK-FIX-NOSCHED-NEXT: vmov s2, r3 1692; CHECK-FIX-NOSCHED-NEXT: lsr r3, r3, #16 1693; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s8, s2 1694; CHECK-FIX-NOSCHED-NEXT: lsr r4, lr, #16 1695; CHECK-FIX-NOSCHED-NEXT: vmov s0, lr 1696; CHECK-FIX-NOSCHED-NEXT: vmov s2, r12 1697; CHECK-FIX-NOSCHED-NEXT: lsr r5, r2, #16 1698; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s12, s2 1699; CHECK-FIX-NOSCHED-NEXT: vmov s2, r2 1700; CHECK-FIX-NOSCHED-NEXT: lsr r2, r12, #16 1701; CHECK-FIX-NOSCHED-NEXT: vmov s10, r3 1702; CHECK-FIX-NOSCHED-NEXT: vmov s14, r2 1703; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s1, s2 1704; CHECK-FIX-NOSCHED-NEXT: vmov s2, r4 1705; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s0, s0 1706; CHECK-FIX-NOSCHED-NEXT: vmov s3, r5 1707; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s2, s2 1708; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s10, s10 1709; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s14, s14 1710; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s3, s3 1711; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 1712; CHECK-FIX-NOSCHED-NEXT: bne .LBB37_3 1713; CHECK-FIX-NOSCHED-NEXT: b .LBB37_4 1714; CHECK-FIX-NOSCHED-NEXT: .LBB37_2: 1715; CHECK-FIX-NOSCHED-NEXT: ldrh r3, [r1, #10] 1716; CHECK-FIX-NOSCHED-NEXT: ldrh r4, [r1, #6] 1717; CHECK-FIX-NOSCHED-NEXT: ldrh lr, [r1, #2] 1718; CHECK-FIX-NOSCHED-NEXT: ldrh r7, [r1, #14] 1719; CHECK-FIX-NOSCHED-NEXT: vmov s8, r3 1720; CHECK-FIX-NOSCHED-NEXT: ldrh r2, [r1, #12] 1721; CHECK-FIX-NOSCHED-NEXT: vmov s12, r4 1722; CHECK-FIX-NOSCHED-NEXT: ldrh r5, [r1, #8] 1723; CHECK-FIX-NOSCHED-NEXT: vmov s1, lr 1724; CHECK-FIX-NOSCHED-NEXT: ldrh r12, [r1, #4] 1725; CHECK-FIX-NOSCHED-NEXT: vmov s0, r7 1726; CHECK-FIX-NOSCHED-NEXT: ldrh r6, [r1] 1727; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s2, s0 1728; CHECK-FIX-NOSCHED-NEXT: vmov s0, r2 1729; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s10, s8 1730; CHECK-FIX-NOSCHED-NEXT: vmov s8, r5 1731; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s14, s12 1732; CHECK-FIX-NOSCHED-NEXT: vmov s12, r12 1733; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s3, s1 1734; CHECK-FIX-NOSCHED-NEXT: vmov s1, r6 1735; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s0, s0 1736; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s8, s8 1737; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s12, s12 1738; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s1, s1 1739; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 1740; CHECK-FIX-NOSCHED-NEXT: beq .LBB37_4 1741; CHECK-FIX-NOSCHED-NEXT: .LBB37_3: 1742; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s9, s9 1743; CHECK-FIX-NOSCHED-NEXT: vmov r0, s9 1744; CHECK-FIX-NOSCHED-NEXT: vmov.16 d2[0], r0 1745; CHECK-FIX-NOSCHED-NEXT: .LBB37_4: 1746; CHECK-FIX-NOSCHED-NEXT: vmov r0, r2, d2 1747; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s1, s1 1748; CHECK-FIX-NOSCHED-NEXT: vmov r3, r7, d3 1749; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s12, s12 1750; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s8, s8 1751; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s0, s0 1752; CHECK-FIX-NOSCHED-NEXT: vmov s5, r2 1753; CHECK-FIX-NOSCHED-NEXT: lsr r2, r2, #16 1754; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s9, s5 1755; CHECK-FIX-NOSCHED-NEXT: vmov s5, r0 1756; CHECK-FIX-NOSCHED-NEXT: lsr r0, r0, #16 1757; CHECK-FIX-NOSCHED-NEXT: vmov s13, r2 1758; CHECK-FIX-NOSCHED-NEXT: vmov s15, r0 1759; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s11, s5 1760; CHECK-FIX-NOSCHED-NEXT: vmov r0, s1 1761; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s1, s3 1762; CHECK-FIX-NOSCHED-NEXT: vmov r2, s1 1763; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s15, s15 1764; CHECK-FIX-NOSCHED-NEXT: vmov s6, r3 1765; CHECK-FIX-NOSCHED-NEXT: lsr r3, r3, #16 1766; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s1, s15 1767; CHECK-FIX-NOSCHED-NEXT: vmov s7, r3 1768; CHECK-FIX-NOSCHED-NEXT: vmov r3, s1 1769; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s11, s11 1770; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s13, s13 1771; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s1, s9 1772; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s6, s6 1773; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s7, s7 1774; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s6, s6 1775; CHECK-FIX-NOSCHED-NEXT: vmov s4, r7 1776; CHECK-FIX-NOSCHED-NEXT: lsr r7, r7, #16 1777; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s4, s4 1778; CHECK-FIX-NOSCHED-NEXT: vmov s5, r7 1779; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s4, s4 1780; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s5, s5 1781; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r0, r2, lsl #16 1782; CHECK-FIX-NOSCHED-NEXT: vmov r2, s11 1783; CHECK-FIX-NOSCHED-NEXT: vmov.32 d16[0], r0 1784; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r2, r3, lsl #16 1785; CHECK-FIX-NOSCHED-NEXT: vmov r2, s12 1786; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s12, s14 1787; CHECK-FIX-NOSCHED-NEXT: vmov.32 d18[0], r0 1788; CHECK-FIX-NOSCHED-NEXT: vmov r0, s12 1789; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s12, s13 1790; CHECK-FIX-NOSCHED-NEXT: vmov r3, s12 1791; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r2, r0, lsl #16 1792; CHECK-FIX-NOSCHED-NEXT: vmov r2, s1 1793; CHECK-FIX-NOSCHED-NEXT: vmov.32 d16[1], r0 1794; CHECK-FIX-NOSCHED-NEXT: pkhbt r2, r2, r3, lsl #16 1795; CHECK-FIX-NOSCHED-NEXT: vmov.32 d18[1], r2 1796; CHECK-FIX-NOSCHED-NEXT: vmov r2, s8 1797; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s8, s10 1798; CHECK-FIX-NOSCHED-NEXT: vmov r3, s8 1799; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r2, r3, lsl #16 1800; CHECK-FIX-NOSCHED-NEXT: vmov r2, s6 1801; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s6, s7 1802; CHECK-FIX-NOSCHED-NEXT: vmov r3, s6 1803; CHECK-FIX-NOSCHED-NEXT: vmov.32 d17[0], r0 1804; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r2, r3, lsl #16 1805; CHECK-FIX-NOSCHED-NEXT: vmov r2, s4 1806; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s4, s5 1807; CHECK-FIX-NOSCHED-NEXT: vmov.32 d19[0], r0 1808; CHECK-FIX-NOSCHED-NEXT: vmov r0, s4 1809; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r2, r0, lsl #16 1810; CHECK-FIX-NOSCHED-NEXT: vmov r2, s0 1811; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s0, s2 1812; CHECK-FIX-NOSCHED-NEXT: vmov r3, s0 1813; CHECK-FIX-NOSCHED-NEXT: vmov.32 d19[1], r0 1814; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r2, r3, lsl #16 1815; CHECK-FIX-NOSCHED-NEXT: vmov.32 d17[1], r0 1816; CHECK-FIX-NOSCHED-NEXT: aese.8 q8, q9 1817; CHECK-FIX-NOSCHED-NEXT: aesmc.8 q8, q8 1818; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r1] 1819; CHECK-FIX-NOSCHED-NEXT: pop {r4, r5, r6, r7, r11, pc} 1820; 1821; CHECK-CORTEX-FIX-LABEL: aese_setf16_cond_via_val: 1822; CHECK-CORTEX-FIX: @ %bb.0: 1823; CHECK-CORTEX-FIX-NEXT: .save {r4, r5, r6, r7, r11, lr} 1824; CHECK-CORTEX-FIX-NEXT: push {r4, r5, r6, r7, r11, lr} 1825; CHECK-CORTEX-FIX-NEXT: .vsave {d8} 1826; CHECK-CORTEX-FIX-NEXT: vpush {d8} 1827; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s9, s0 1828; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 1829; CHECK-CORTEX-FIX-NEXT: beq .LBB37_2 1830; CHECK-CORTEX-FIX-NEXT: @ %bb.1: 1831; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s0, s9 1832; CHECK-CORTEX-FIX-NEXT: vld1.64 {d16, d17}, [r1] 1833; CHECK-CORTEX-FIX-NEXT: vmov r2, s0 1834; CHECK-CORTEX-FIX-NEXT: vmov.16 d16[0], r2 1835; CHECK-CORTEX-FIX-NEXT: vmov r4, r5, d17 1836; CHECK-CORTEX-FIX-NEXT: lsr r6, r4, #16 1837; CHECK-CORTEX-FIX-NEXT: lsr r7, r5, #16 1838; CHECK-CORTEX-FIX-NEXT: vmov s0, r5 1839; CHECK-CORTEX-FIX-NEXT: vmov s2, r4 1840; CHECK-CORTEX-FIX-NEXT: vmov s14, r7 1841; CHECK-CORTEX-FIX-NEXT: vmov s3, r6 1842; CHECK-CORTEX-FIX-NEXT: vmov r2, r3, d16 1843; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s12, s0 1844; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s0, s2 1845; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s14, s14 1846; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s2, s3 1847; CHECK-CORTEX-FIX-NEXT: lsr r12, r2, #16 1848; CHECK-CORTEX-FIX-NEXT: lsr lr, r3, #16 1849; CHECK-CORTEX-FIX-NEXT: vmov s8, r3 1850; CHECK-CORTEX-FIX-NEXT: vmov s10, r2 1851; CHECK-CORTEX-FIX-NEXT: vmov s11, lr 1852; CHECK-CORTEX-FIX-NEXT: vmov s13, r12 1853; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s1, s8 1854; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s8, s10 1855; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s3, s11 1856; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s10, s13 1857; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 1858; CHECK-CORTEX-FIX-NEXT: bne .LBB37_3 1859; CHECK-CORTEX-FIX-NEXT: b .LBB37_4 1860; CHECK-CORTEX-FIX-NEXT: .LBB37_2: 1861; CHECK-CORTEX-FIX-NEXT: ldrh r12, [r1] 1862; CHECK-CORTEX-FIX-NEXT: ldrh lr, [r1, #2] 1863; CHECK-CORTEX-FIX-NEXT: ldrh r7, [r1, #4] 1864; CHECK-CORTEX-FIX-NEXT: ldrh r6, [r1, #6] 1865; CHECK-CORTEX-FIX-NEXT: ldrh r5, [r1, #8] 1866; CHECK-CORTEX-FIX-NEXT: ldrh r4, [r1, #10] 1867; CHECK-CORTEX-FIX-NEXT: ldrh r2, [r1, #12] 1868; CHECK-CORTEX-FIX-NEXT: ldrh r3, [r1, #14] 1869; CHECK-CORTEX-FIX-NEXT: vmov s0, r3 1870; CHECK-CORTEX-FIX-NEXT: vmov s2, r2 1871; CHECK-CORTEX-FIX-NEXT: vmov s1, r6 1872; CHECK-CORTEX-FIX-NEXT: vmov s8, r4 1873; CHECK-CORTEX-FIX-NEXT: vmov s10, r5 1874; CHECK-CORTEX-FIX-NEXT: vmov s11, r7 1875; CHECK-CORTEX-FIX-NEXT: vmov s13, lr 1876; CHECK-CORTEX-FIX-NEXT: vmov s15, r12 1877; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s14, s0 1878; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s12, s2 1879; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s2, s8 1880; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s0, s10 1881; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s3, s1 1882; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s1, s11 1883; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s10, s13 1884; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s8, s15 1885; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 1886; CHECK-CORTEX-FIX-NEXT: beq .LBB37_4 1887; CHECK-CORTEX-FIX-NEXT: .LBB37_3: 1888; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s9, s9 1889; CHECK-CORTEX-FIX-NEXT: vmov r0, s9 1890; CHECK-CORTEX-FIX-NEXT: vmov.16 d2[0], r0 1891; CHECK-CORTEX-FIX-NEXT: .LBB37_4: 1892; CHECK-CORTEX-FIX-NEXT: vmov r6, r5, d3 1893; CHECK-CORTEX-FIX-NEXT: vmov r0, r2, d2 1894; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s12, s12 1895; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s14, s14 1896; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s1, s1 1897; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s0, s0 1898; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s2, s2 1899; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s8, s8 1900; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s10, s10 1901; CHECK-CORTEX-FIX-NEXT: lsr r3, r5, #16 1902; CHECK-CORTEX-FIX-NEXT: vmov s4, r5 1903; CHECK-CORTEX-FIX-NEXT: lsr r7, r2, #16 1904; CHECK-CORTEX-FIX-NEXT: lsr r4, r6, #16 1905; CHECK-CORTEX-FIX-NEXT: vmov s5, r2 1906; CHECK-CORTEX-FIX-NEXT: lsr r12, r0, #16 1907; CHECK-CORTEX-FIX-NEXT: vmov s9, r0 1908; CHECK-CORTEX-FIX-NEXT: vmov r0, s12 1909; CHECK-CORTEX-FIX-NEXT: vmov r2, s14 1910; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s12, s3 1911; CHECK-CORTEX-FIX-NEXT: vmov s6, r6 1912; CHECK-CORTEX-FIX-NEXT: vmov r5, s2 1913; CHECK-CORTEX-FIX-NEXT: vmov s13, r3 1914; CHECK-CORTEX-FIX-NEXT: vmov s15, r4 1915; CHECK-CORTEX-FIX-NEXT: vmov s16, r7 1916; CHECK-CORTEX-FIX-NEXT: vmov r4, s10 1917; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s7, s4 1918; CHECK-CORTEX-FIX-NEXT: vmov s4, r12 1919; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s11, s5 1920; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s5, s9 1921; CHECK-CORTEX-FIX-NEXT: pkhbt r12, r0, r2, lsl #16 1922; CHECK-CORTEX-FIX-NEXT: vmov r2, s1 1923; CHECK-CORTEX-FIX-NEXT: vmov r3, s12 1924; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s6, s6 1925; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s13, s13 1926; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s9, s15 1927; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s15, s16 1928; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s14, s7 1929; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s7, s11 1930; CHECK-CORTEX-FIX-NEXT: pkhbt lr, r2, r3, lsl #16 1931; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s4, s4 1932; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s6, s6 1933; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s5, s5 1934; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s3, s13 1935; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s11, s15 1936; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s9, s9 1937; CHECK-CORTEX-FIX-NEXT: vmov r3, s14 1938; CHECK-CORTEX-FIX-NEXT: vmov r7, s3 1939; CHECK-CORTEX-FIX-NEXT: vmov r6, s11 1940; CHECK-CORTEX-FIX-NEXT: vmov r0, s9 1941; CHECK-CORTEX-FIX-NEXT: pkhbt r3, r3, r7, lsl #16 1942; CHECK-CORTEX-FIX-NEXT: vmov r7, s7 1943; CHECK-CORTEX-FIX-NEXT: pkhbt r7, r7, r6, lsl #16 1944; CHECK-CORTEX-FIX-NEXT: vmov r6, s0 1945; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s0, s4 1946; CHECK-CORTEX-FIX-NEXT: pkhbt r6, r6, r5, lsl #16 1947; CHECK-CORTEX-FIX-NEXT: vmov r5, s8 1948; CHECK-CORTEX-FIX-NEXT: vmov r2, s0 1949; CHECK-CORTEX-FIX-NEXT: pkhbt r5, r5, r4, lsl #16 1950; CHECK-CORTEX-FIX-NEXT: vmov r4, s6 1951; CHECK-CORTEX-FIX-NEXT: vmov.32 d18[0], r5 1952; CHECK-CORTEX-FIX-NEXT: vmov.32 d19[0], r6 1953; CHECK-CORTEX-FIX-NEXT: vmov.32 d18[1], lr 1954; CHECK-CORTEX-FIX-NEXT: vmov.32 d19[1], r12 1955; CHECK-CORTEX-FIX-NEXT: pkhbt r0, r4, r0, lsl #16 1956; CHECK-CORTEX-FIX-NEXT: vmov r4, s5 1957; CHECK-CORTEX-FIX-NEXT: pkhbt r2, r4, r2, lsl #16 1958; CHECK-CORTEX-FIX-NEXT: vmov.32 d16[0], r2 1959; CHECK-CORTEX-FIX-NEXT: vmov.32 d17[0], r0 1960; CHECK-CORTEX-FIX-NEXT: vmov.32 d16[1], r7 1961; CHECK-CORTEX-FIX-NEXT: vmov.32 d17[1], r3 1962; CHECK-CORTEX-FIX-NEXT: aese.8 q9, q8 1963; CHECK-CORTEX-FIX-NEXT: aesmc.8 q8, q9 1964; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r1] 1965; CHECK-CORTEX-FIX-NEXT: vpop {d8} 1966; CHECK-CORTEX-FIX-NEXT: pop {r4, r5, r6, r7, r11, pc} 1967 br i1 %0, label %5, label %11 1968 19695: 1970 %6 = bitcast <16 x i8>* %3 to <8 x i16>* 1971 %7 = load <8 x i16>, <8 x i16>* %6, align 8 1972 %8 = bitcast half %1 to i16 1973 %9 = insertelement <8 x i16> %7, i16 %8, i64 0 1974 %10 = bitcast <8 x i16> %9 to <8 x half> 1975 br label %14 1976 197711: 1978 %12 = bitcast <16 x i8>* %3 to <8 x half>* 1979 %13 = load <8 x half>, <8 x half>* %12, align 8 1980 br label %14 1981 198214: 1983 %15 = phi <8 x half> [ %10, %5 ], [ %13, %11 ] 1984 br i1 %0, label %16, label %21 1985 198616: 1987 %17 = bitcast <16 x i8> %2 to <8 x i16> 1988 %18 = bitcast half %1 to i16 1989 %19 = insertelement <8 x i16> %17, i16 %18, i64 0 1990 %20 = bitcast <8 x i16> %19 to <8 x half> 1991 br label %23 1992 199321: 1994 %22 = bitcast <16 x i8> %2 to <8 x half> 1995 br label %23 1996 199723: 1998 %24 = phi <8 x half> [ %20, %16 ], [ %22, %21 ] 1999 %25 = bitcast <8 x half> %15 to <16 x i8> 2000 %26 = bitcast <8 x half> %24 to <16 x i8> 2001 %27 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %25, <16 x i8> %26) 2002 %28 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %27) 2003 store <16 x i8> %28, <16 x i8>* %3, align 8 2004 ret void 2005} 2006 2007define arm_aapcs_vfpcc void @aese_setf16_loop_via_ptr(i32 %0, half* %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 2008; CHECK-FIX-LABEL: aese_setf16_loop_via_ptr: 2009; CHECK-FIX: @ %bb.0: 2010; CHECK-FIX-NEXT: vorr q0, q0, q0 2011; CHECK-FIX-NEXT: ldrh r1, [r1] 2012; CHECK-FIX-NEXT: cmp r0, #0 2013; CHECK-FIX-NEXT: strh r1, [r2] 2014; CHECK-FIX-NEXT: bxeq lr 2015; CHECK-FIX-NEXT: .LBB38_1: 2016; CHECK-FIX-NEXT: vmov.16 d0[0], r1 2017; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 2018; CHECK-FIX-NEXT: .LBB38_2: @ =>This Inner Loop Header: Depth=1 2019; CHECK-FIX-NEXT: aese.8 q8, q0 2020; CHECK-FIX-NEXT: subs r0, r0, #1 2021; CHECK-FIX-NEXT: aesmc.8 q8, q8 2022; CHECK-FIX-NEXT: bne .LBB38_2 2023; CHECK-FIX-NEXT: @ %bb.3: 2024; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 2025; CHECK-FIX-NEXT: bx lr 2026 %5 = bitcast half* %1 to i16* 2027 %6 = load i16, i16* %5, align 2 2028 %7 = bitcast <16 x i8> %2 to <8 x i16> 2029 %8 = insertelement <8 x i16> %7, i16 %6, i64 0 2030 %9 = bitcast <8 x i16> %8 to <16 x i8> 2031 %10 = bitcast <16 x i8>* %3 to i16* 2032 store i16 %6, i16* %10, align 8 2033 %11 = icmp eq i32 %0, 0 2034 br i1 %11, label %15, label %12 2035 203612: 2037 %13 = load <16 x i8>, <16 x i8>* %3, align 8 2038 br label %16 2039 204014: 2041 store <16 x i8> %20, <16 x i8>* %3, align 8 2042 br label %15 2043 204415: 2045 ret void 2046 204716: 2048 %17 = phi <16 x i8> [ %13, %12 ], [ %20, %16 ] 2049 %18 = phi i32 [ 0, %12 ], [ %21, %16 ] 2050 %19 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %17, <16 x i8> %9) 2051 %20 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %19) 2052 %21 = add nuw i32 %18, 1 2053 %22 = icmp eq i32 %21, %0 2054 br i1 %22, label %14, label %16 2055} 2056 2057define arm_aapcs_vfpcc void @aese_setf16_loop_via_val(i32 %0, half %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 2058; CHECK-FIX-LABEL: aese_setf16_loop_via_val: 2059; CHECK-FIX: @ %bb.0: 2060; CHECK-FIX-NEXT: vorr q1, q1, q1 2061; CHECK-FIX-NEXT: cmp r0, #0 2062; CHECK-FIX-NEXT: bxeq lr 2063; CHECK-FIX-NEXT: .LBB39_1: 2064; CHECK-FIX-NEXT: vcvtb.f32.f16 s0, s0 2065; CHECK-FIX-NEXT: vcvtb.f16.f32 s0, s0 2066; CHECK-FIX-NEXT: vmov r2, s0 2067; CHECK-FIX-NEXT: uxth r2, r2 2068; CHECK-FIX-NEXT: vmov.16 d2[0], r2 2069; CHECK-FIX-NEXT: .LBB39_2: @ =>This Inner Loop Header: Depth=1 2070; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r1] 2071; CHECK-FIX-NEXT: subs r0, r0, #1 2072; CHECK-FIX-NEXT: vmov.16 d16[0], r2 2073; CHECK-FIX-NEXT: aese.8 q8, q1 2074; CHECK-FIX-NEXT: aesmc.8 q8, q8 2075; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r1] 2076; CHECK-FIX-NEXT: bne .LBB39_2 2077; CHECK-FIX-NEXT: @ %bb.3: 2078; CHECK-FIX-NEXT: bx lr 2079 %5 = icmp eq i32 %0, 0 2080 br i1 %5, label %13, label %6 2081 20826: 2083 %7 = bitcast <16 x i8> %2 to <8 x i16> 2084 %8 = bitcast half %1 to i16 2085 %9 = insertelement <8 x i16> %7, i16 %8, i64 0 2086 %10 = bitcast <8 x i16> %9 to <16 x i8> 2087 %11 = bitcast <16 x i8>* %3 to <8 x i16>* 2088 %12 = bitcast <16 x i8>* %3 to half* 2089 br label %14 2090 209113: 2092 ret void 2093 209414: 2095 %15 = phi i32 [ 0, %6 ], [ %21, %14 ] 2096 %16 = load <8 x i16>, <8 x i16>* %11, align 8 2097 %17 = insertelement <8 x i16> %16, i16 %8, i64 0 2098 %18 = bitcast <8 x i16> %17 to <16 x i8> 2099 store half %1, half* %12, align 8 2100 %19 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %18, <16 x i8> %10) 2101 %20 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %19) 2102 store <16 x i8> %20, <16 x i8>* %3, align 8 2103 %21 = add nuw i32 %15, 1 2104 %22 = icmp eq i32 %21, %0 2105 br i1 %22, label %13, label %14 2106} 2107 2108define arm_aapcs_vfpcc void @aese_setf32_via_ptr(float* %0, <16 x i8> %1, <16 x i8>* %2) nounwind { 2109; CHECK-FIX-LABEL: aese_setf32_via_ptr: 2110; CHECK-FIX: @ %bb.0: 2111; CHECK-FIX-NEXT: vldr s0, [r0] 2112; CHECK-FIX-NEXT: vld1.64 {d2, d3}, [r1] 2113; CHECK-FIX-NEXT: vmov.f32 s4, s0 2114; CHECK-FIX-NEXT: vorr q1, q1, q1 2115; CHECK-FIX-NEXT: vorr q0, q0, q0 2116; CHECK-FIX-NEXT: aese.8 q1, q0 2117; CHECK-FIX-NEXT: aesmc.8 q8, q1 2118; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r1] 2119; CHECK-FIX-NEXT: bx lr 2120 %4 = load float, float* %0, align 4 2121 %5 = bitcast <16 x i8>* %2 to <4 x float>* 2122 %6 = load <4 x float>, <4 x float>* %5, align 8 2123 %7 = insertelement <4 x float> %6, float %4, i64 0 2124 %8 = bitcast <4 x float> %7 to <16 x i8> 2125 %9 = bitcast <16 x i8> %1 to <4 x float> 2126 %10 = insertelement <4 x float> %9, float %4, i64 0 2127 %11 = bitcast <4 x float> %10 to <16 x i8> 2128 %12 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %8, <16 x i8> %11) 2129 %13 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %12) 2130 store <16 x i8> %13, <16 x i8>* %2, align 8 2131 ret void 2132} 2133 2134define arm_aapcs_vfpcc void @aese_setf32_via_val(float %0, <16 x i8> %1, <16 x i8>* %2) nounwind { 2135; CHECK-FIX-LABEL: aese_setf32_via_val: 2136; CHECK-FIX: @ %bb.0: 2137; CHECK-FIX-NEXT: vmov.f32 s4, s0 2138; CHECK-FIX-NEXT: vld1.64 {d0, d1}, [r0] 2139; CHECK-FIX-NEXT: vmov.f32 s0, s4 2140; CHECK-FIX-NEXT: vorr q0, q0, q0 2141; CHECK-FIX-NEXT: vorr q1, q1, q1 2142; CHECK-FIX-NEXT: aese.8 q0, q1 2143; CHECK-FIX-NEXT: aesmc.8 q8, q0 2144; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r0] 2145; CHECK-FIX-NEXT: bx lr 2146 %4 = bitcast <16 x i8>* %2 to <4 x float>* 2147 %5 = load <4 x float>, <4 x float>* %4, align 8 2148 %6 = insertelement <4 x float> %5, float %0, i64 0 2149 %7 = bitcast <4 x float> %6 to <16 x i8> 2150 %8 = bitcast <16 x i8> %1 to <4 x float> 2151 %9 = insertelement <4 x float> %8, float %0, i64 0 2152 %10 = bitcast <4 x float> %9 to <16 x i8> 2153 %11 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %7, <16 x i8> %10) 2154 %12 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %11) 2155 store <16 x i8> %12, <16 x i8>* %2, align 8 2156 ret void 2157} 2158 2159define arm_aapcs_vfpcc void @aese_setf32_cond_via_ptr(i1 zeroext %0, float* %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 2160; CHECK-FIX-LABEL: aese_setf32_cond_via_ptr: 2161; CHECK-FIX: @ %bb.0: 2162; CHECK-FIX-NEXT: vorr q0, q0, q0 2163; CHECK-FIX-NEXT: cmp r0, #0 2164; CHECK-FIX-NEXT: beq .LBB42_2 2165; CHECK-FIX-NEXT: @ %bb.1: 2166; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 2167; CHECK-FIX-NEXT: vld1.32 {d16[0]}, [r1:32] 2168; CHECK-FIX-NEXT: cmp r0, #0 2169; CHECK-FIX-NEXT: bne .LBB42_3 2170; CHECK-FIX-NEXT: b .LBB42_4 2171; CHECK-FIX-NEXT: .LBB42_2: 2172; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 2173; CHECK-FIX-NEXT: cmp r0, #0 2174; CHECK-FIX-NEXT: beq .LBB42_4 2175; CHECK-FIX-NEXT: .LBB42_3: 2176; CHECK-FIX-NEXT: vld1.32 {d0[0]}, [r1:32] 2177; CHECK-FIX-NEXT: .LBB42_4: 2178; CHECK-FIX-NEXT: aese.8 q8, q0 2179; CHECK-FIX-NEXT: aesmc.8 q8, q8 2180; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 2181; CHECK-FIX-NEXT: bx lr 2182 br i1 %0, label %5, label %10 2183 21845: 2185 %6 = load float, float* %1, align 4 2186 %7 = bitcast <16 x i8>* %3 to <4 x float>* 2187 %8 = load <4 x float>, <4 x float>* %7, align 8 2188 %9 = insertelement <4 x float> %8, float %6, i64 0 2189 br label %13 2190 219110: 2192 %11 = bitcast <16 x i8>* %3 to <4 x float>* 2193 %12 = load <4 x float>, <4 x float>* %11, align 8 2194 br label %13 2195 219613: 2197 %14 = phi <4 x float> [ %9, %5 ], [ %12, %10 ] 2198 br i1 %0, label %15, label %19 2199 220015: 2201 %16 = load float, float* %1, align 4 2202 %17 = bitcast <16 x i8> %2 to <4 x float> 2203 %18 = insertelement <4 x float> %17, float %16, i64 0 2204 br label %21 2205 220619: 2207 %20 = bitcast <16 x i8> %2 to <4 x float> 2208 br label %21 2209 221021: 2211 %22 = phi <4 x float> [ %18, %15 ], [ %20, %19 ] 2212 %23 = bitcast <4 x float> %14 to <16 x i8> 2213 %24 = bitcast <4 x float> %22 to <16 x i8> 2214 %25 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %23, <16 x i8> %24) 2215 %26 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %25) 2216 store <16 x i8> %26, <16 x i8>* %3, align 8 2217 ret void 2218} 2219 2220define arm_aapcs_vfpcc void @aese_setf32_cond_via_val(i1 zeroext %0, float %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 2221; CHECK-FIX-NOSCHED-LABEL: aese_setf32_cond_via_val: 2222; CHECK-FIX-NOSCHED: @ %bb.0: 2223; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d4, d5}, [r1] 2224; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 2225; CHECK-FIX-NOSCHED-NEXT: vmovne.f32 s8, s0 2226; CHECK-FIX-NOSCHED-NEXT: vorr q2, q2, q2 2227; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 2228; CHECK-FIX-NOSCHED-NEXT: vmovne.f32 s4, s0 2229; CHECK-FIX-NOSCHED-NEXT: vorr q1, q1, q1 2230; CHECK-FIX-NOSCHED-NEXT: aese.8 q2, q1 2231; CHECK-FIX-NOSCHED-NEXT: aesmc.8 q8, q2 2232; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r1] 2233; CHECK-FIX-NOSCHED-NEXT: bx lr 2234; 2235; CHECK-CORTEX-FIX-LABEL: aese_setf32_cond_via_val: 2236; CHECK-CORTEX-FIX: @ %bb.0: 2237; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 2238; CHECK-CORTEX-FIX-NEXT: vld1.64 {d4, d5}, [r1] 2239; CHECK-CORTEX-FIX-NEXT: vmovne.f32 s8, s0 2240; CHECK-CORTEX-FIX-NEXT: vorr q2, q2, q2 2241; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 2242; CHECK-CORTEX-FIX-NEXT: vmovne.f32 s4, s0 2243; CHECK-CORTEX-FIX-NEXT: vorr q1, q1, q1 2244; CHECK-CORTEX-FIX-NEXT: aese.8 q2, q1 2245; CHECK-CORTEX-FIX-NEXT: aesmc.8 q8, q2 2246; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r1] 2247; CHECK-CORTEX-FIX-NEXT: bx lr 2248 %5 = bitcast <16 x i8>* %3 to <4 x float>* 2249 %6 = load <4 x float>, <4 x float>* %5, align 8 2250 %7 = insertelement <4 x float> %6, float %1, i64 0 2251 %8 = select i1 %0, <4 x float> %7, <4 x float> %6 2252 %9 = bitcast <16 x i8> %2 to <4 x float> 2253 %10 = insertelement <4 x float> %9, float %1, i64 0 2254 %11 = select i1 %0, <4 x float> %10, <4 x float> %9 2255 %12 = bitcast <4 x float> %8 to <16 x i8> 2256 %13 = bitcast <4 x float> %11 to <16 x i8> 2257 %14 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %12, <16 x i8> %13) 2258 %15 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %14) 2259 store <16 x i8> %15, <16 x i8>* %3, align 8 2260 ret void 2261} 2262 2263define arm_aapcs_vfpcc void @aese_setf32_loop_via_ptr(i32 %0, float* %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 2264; CHECK-FIX-NOSCHED-LABEL: aese_setf32_loop_via_ptr: 2265; CHECK-FIX-NOSCHED: @ %bb.0: 2266; CHECK-FIX-NOSCHED-NEXT: vldr s4, [r1] 2267; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 2268; CHECK-FIX-NOSCHED-NEXT: vstr s4, [r2] 2269; CHECK-FIX-NOSCHED-NEXT: bxeq lr 2270; CHECK-FIX-NOSCHED-NEXT: .LBB44_1: 2271; CHECK-FIX-NOSCHED-NEXT: vmov.f32 s0, s4 2272; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r2] 2273; CHECK-FIX-NOSCHED-NEXT: .LBB44_2: @ =>This Inner Loop Header: Depth=1 2274; CHECK-FIX-NOSCHED-NEXT: vorr q0, q0, q0 2275; CHECK-FIX-NOSCHED-NEXT: aese.8 q8, q0 2276; CHECK-FIX-NOSCHED-NEXT: subs r0, r0, #1 2277; CHECK-FIX-NOSCHED-NEXT: aesmc.8 q8, q8 2278; CHECK-FIX-NOSCHED-NEXT: bne .LBB44_2 2279; CHECK-FIX-NOSCHED-NEXT: @ %bb.3: 2280; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r2] 2281; CHECK-FIX-NOSCHED-NEXT: bx lr 2282; 2283; CHECK-CORTEX-FIX-LABEL: aese_setf32_loop_via_ptr: 2284; CHECK-CORTEX-FIX: @ %bb.0: 2285; CHECK-CORTEX-FIX-NEXT: vldr s4, [r1] 2286; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 2287; CHECK-CORTEX-FIX-NEXT: vstr s4, [r2] 2288; CHECK-CORTEX-FIX-NEXT: bxeq lr 2289; CHECK-CORTEX-FIX-NEXT: .LBB44_1: 2290; CHECK-CORTEX-FIX-NEXT: vld1.64 {d16, d17}, [r2] 2291; CHECK-CORTEX-FIX-NEXT: vmov.f32 s0, s4 2292; CHECK-CORTEX-FIX-NEXT: .LBB44_2: @ =>This Inner Loop Header: Depth=1 2293; CHECK-CORTEX-FIX-NEXT: vorr q0, q0, q0 2294; CHECK-CORTEX-FIX-NEXT: aese.8 q8, q0 2295; CHECK-CORTEX-FIX-NEXT: subs r0, r0, #1 2296; CHECK-CORTEX-FIX-NEXT: aesmc.8 q8, q8 2297; CHECK-CORTEX-FIX-NEXT: bne .LBB44_2 2298; CHECK-CORTEX-FIX-NEXT: @ %bb.3: 2299; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r2] 2300; CHECK-CORTEX-FIX-NEXT: bx lr 2301 %5 = load float, float* %1, align 4 2302 %6 = bitcast <16 x i8> %2 to <4 x float> 2303 %7 = insertelement <4 x float> %6, float %5, i64 0 2304 %8 = bitcast <4 x float> %7 to <16 x i8> 2305 %9 = bitcast <16 x i8>* %3 to float* 2306 store float %5, float* %9, align 8 2307 %10 = icmp eq i32 %0, 0 2308 br i1 %10, label %14, label %11 2309 231011: 2311 %12 = load <16 x i8>, <16 x i8>* %3, align 8 2312 br label %15 2313 231413: 2315 store <16 x i8> %19, <16 x i8>* %3, align 8 2316 br label %14 2317 231814: 2319 ret void 2320 232115: 2322 %16 = phi <16 x i8> [ %12, %11 ], [ %19, %15 ] 2323 %17 = phi i32 [ 0, %11 ], [ %20, %15 ] 2324 %18 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %16, <16 x i8> %8) 2325 %19 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %18) 2326 %20 = add nuw i32 %17, 1 2327 %21 = icmp eq i32 %20, %0 2328 br i1 %21, label %13, label %15 2329} 2330 2331define arm_aapcs_vfpcc void @aese_setf32_loop_via_val(i32 %0, float %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 2332; CHECK-FIX-NOSCHED-LABEL: aese_setf32_loop_via_val: 2333; CHECK-FIX-NOSCHED: @ %bb.0: 2334; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 2335; CHECK-FIX-NOSCHED-NEXT: bxeq lr 2336; CHECK-FIX-NOSCHED-NEXT: .LBB45_1: 2337; CHECK-FIX-NOSCHED-NEXT: vmov.f32 s4, s0 2338; CHECK-FIX-NOSCHED-NEXT: .LBB45_2: @ =>This Inner Loop Header: Depth=1 2339; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d4, d5}, [r1] 2340; CHECK-FIX-NOSCHED-NEXT: subs r0, r0, #1 2341; CHECK-FIX-NOSCHED-NEXT: vmov.f32 s8, s0 2342; CHECK-FIX-NOSCHED-NEXT: vorr q2, q2, q2 2343; CHECK-FIX-NOSCHED-NEXT: vorr q1, q1, q1 2344; CHECK-FIX-NOSCHED-NEXT: aese.8 q2, q1 2345; CHECK-FIX-NOSCHED-NEXT: aesmc.8 q8, q2 2346; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r1] 2347; CHECK-FIX-NOSCHED-NEXT: bne .LBB45_2 2348; CHECK-FIX-NOSCHED-NEXT: @ %bb.3: 2349; CHECK-FIX-NOSCHED-NEXT: bx lr 2350; 2351; CHECK-CORTEX-FIX-LABEL: aese_setf32_loop_via_val: 2352; CHECK-CORTEX-FIX: @ %bb.0: 2353; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 2354; CHECK-CORTEX-FIX-NEXT: bxeq lr 2355; CHECK-CORTEX-FIX-NEXT: .LBB45_1: 2356; CHECK-CORTEX-FIX-NEXT: vmov.f32 s4, s0 2357; CHECK-CORTEX-FIX-NEXT: .LBB45_2: @ =>This Inner Loop Header: Depth=1 2358; CHECK-CORTEX-FIX-NEXT: vld1.64 {d4, d5}, [r1] 2359; CHECK-CORTEX-FIX-NEXT: vmov.f32 s8, s0 2360; CHECK-CORTEX-FIX-NEXT: vorr q2, q2, q2 2361; CHECK-CORTEX-FIX-NEXT: subs r0, r0, #1 2362; CHECK-CORTEX-FIX-NEXT: vorr q1, q1, q1 2363; CHECK-CORTEX-FIX-NEXT: aese.8 q2, q1 2364; CHECK-CORTEX-FIX-NEXT: aesmc.8 q8, q2 2365; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r1] 2366; CHECK-CORTEX-FIX-NEXT: bne .LBB45_2 2367; CHECK-CORTEX-FIX-NEXT: @ %bb.3: 2368; CHECK-CORTEX-FIX-NEXT: bx lr 2369 %5 = icmp eq i32 %0, 0 2370 br i1 %5, label %12, label %6 2371 23726: 2373 %7 = bitcast <16 x i8> %2 to <4 x float> 2374 %8 = insertelement <4 x float> %7, float %1, i64 0 2375 %9 = bitcast <4 x float> %8 to <16 x i8> 2376 %10 = bitcast <16 x i8>* %3 to <4 x float>* 2377 %11 = bitcast <16 x i8>* %3 to float* 2378 br label %13 2379 238012: 2381 ret void 2382 238313: 2384 %14 = phi i32 [ 0, %6 ], [ %20, %13 ] 2385 %15 = load <4 x float>, <4 x float>* %10, align 8 2386 %16 = insertelement <4 x float> %15, float %1, i64 0 2387 %17 = bitcast <4 x float> %16 to <16 x i8> 2388 store float %1, float* %11, align 8 2389 %18 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %17, <16 x i8> %9) 2390 %19 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %18) 2391 store <16 x i8> %19, <16 x i8>* %3, align 8 2392 %20 = add nuw i32 %14, 1 2393 %21 = icmp eq i32 %20, %0 2394 br i1 %21, label %12, label %13 2395} 2396 2397define arm_aapcs_vfpcc void @aesd_zero(<16 x i8>* %0) nounwind { 2398; CHECK-FIX-LABEL: aesd_zero: 2399; CHECK-FIX: @ %bb.0: 2400; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r0] 2401; CHECK-FIX-NEXT: vmov.i32 q9, #0x0 2402; CHECK-FIX-NEXT: aesd.8 q9, q8 2403; CHECK-FIX-NEXT: aesimc.8 q8, q9 2404; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r0] 2405; CHECK-FIX-NEXT: bx lr 2406 %2 = load <16 x i8>, <16 x i8>* %0, align 8 2407 %3 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> zeroinitializer, <16 x i8> %2) 2408 %4 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %3) 2409 store <16 x i8> %4, <16 x i8>* %0, align 8 2410 ret void 2411} 2412 2413define arm_aapcs_vfpcc void @aesd_via_call1(<16 x i8>* %0) nounwind { 2414; CHECK-FIX-LABEL: aesd_via_call1: 2415; CHECK-FIX: @ %bb.0: 2416; CHECK-FIX-NEXT: .save {r4, lr} 2417; CHECK-FIX-NEXT: push {r4, lr} 2418; CHECK-FIX-NEXT: mov r4, r0 2419; CHECK-FIX-NEXT: bl get_input 2420; CHECK-FIX-NEXT: vorr q0, q0, q0 2421; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r4] 2422; CHECK-FIX-NEXT: aesd.8 q0, q8 2423; CHECK-FIX-NEXT: aesimc.8 q8, q0 2424; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r4] 2425; CHECK-FIX-NEXT: pop {r4, pc} 2426 %2 = call arm_aapcs_vfpcc <16 x i8> @get_input() 2427 %3 = load <16 x i8>, <16 x i8>* %0, align 8 2428 %4 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %2, <16 x i8> %3) 2429 %5 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %4) 2430 store <16 x i8> %5, <16 x i8>* %0, align 8 2431 ret void 2432} 2433 2434define arm_aapcs_vfpcc void @aesd_via_call2(half %0, <16 x i8>* %1) nounwind { 2435; CHECK-FIX-LABEL: aesd_via_call2: 2436; CHECK-FIX: @ %bb.0: 2437; CHECK-FIX-NEXT: .save {r4, lr} 2438; CHECK-FIX-NEXT: push {r4, lr} 2439; CHECK-FIX-NEXT: mov r4, r0 2440; CHECK-FIX-NEXT: bl get_inputf16 2441; CHECK-FIX-NEXT: vorr q0, q0, q0 2442; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r4] 2443; CHECK-FIX-NEXT: aesd.8 q0, q8 2444; CHECK-FIX-NEXT: aesimc.8 q8, q0 2445; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r4] 2446; CHECK-FIX-NEXT: pop {r4, pc} 2447 %3 = call arm_aapcs_vfpcc <16 x i8> @get_inputf16(half %0) 2448 %4 = load <16 x i8>, <16 x i8>* %1, align 8 2449 %5 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %3, <16 x i8> %4) 2450 %6 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %5) 2451 store <16 x i8> %6, <16 x i8>* %1, align 8 2452 ret void 2453} 2454 2455define arm_aapcs_vfpcc void @aesd_via_call3(float %0, <16 x i8>* %1) nounwind { 2456; CHECK-FIX-LABEL: aesd_via_call3: 2457; CHECK-FIX: @ %bb.0: 2458; CHECK-FIX-NEXT: .save {r4, lr} 2459; CHECK-FIX-NEXT: push {r4, lr} 2460; CHECK-FIX-NEXT: mov r4, r0 2461; CHECK-FIX-NEXT: bl get_inputf32 2462; CHECK-FIX-NEXT: vorr q0, q0, q0 2463; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r4] 2464; CHECK-FIX-NEXT: aesd.8 q0, q8 2465; CHECK-FIX-NEXT: aesimc.8 q8, q0 2466; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r4] 2467; CHECK-FIX-NEXT: pop {r4, pc} 2468 %3 = call arm_aapcs_vfpcc <16 x i8> @get_inputf32(float %0) 2469 %4 = load <16 x i8>, <16 x i8>* %1, align 8 2470 %5 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %3, <16 x i8> %4) 2471 %6 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %5) 2472 store <16 x i8> %6, <16 x i8>* %1, align 8 2473 ret void 2474} 2475 2476define arm_aapcs_vfpcc void @aesd_once_via_ptr(<16 x i8>* %0, <16 x i8>* %1) nounwind { 2477; CHECK-FIX-LABEL: aesd_once_via_ptr: 2478; CHECK-FIX: @ %bb.0: 2479; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r0] 2480; CHECK-FIX-NEXT: vld1.64 {d18, d19}, [r1] 2481; CHECK-FIX-NEXT: aesd.8 q9, q8 2482; CHECK-FIX-NEXT: aesimc.8 q8, q9 2483; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r1] 2484; CHECK-FIX-NEXT: bx lr 2485 %3 = load <16 x i8>, <16 x i8>* %1, align 8 2486 %4 = load <16 x i8>, <16 x i8>* %0, align 8 2487 %5 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %3, <16 x i8> %4) 2488 %6 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %5) 2489 store <16 x i8> %6, <16 x i8>* %1, align 8 2490 ret void 2491} 2492 2493define arm_aapcs_vfpcc <16 x i8> @aesd_once_via_val(<16 x i8> %0, <16 x i8> %1) nounwind { 2494; CHECK-FIX-LABEL: aesd_once_via_val: 2495; CHECK-FIX: @ %bb.0: 2496; CHECK-FIX-NEXT: vorr q1, q1, q1 2497; CHECK-FIX-NEXT: vorr q0, q0, q0 2498; CHECK-FIX-NEXT: aesd.8 q1, q0 2499; CHECK-FIX-NEXT: aesimc.8 q0, q1 2500; CHECK-FIX-NEXT: bx lr 2501 %3 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %1, <16 x i8> %0) 2502 %4 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %3) 2503 ret <16 x i8> %4 2504} 2505 2506define arm_aapcs_vfpcc void @aesd_twice_via_ptr(<16 x i8>* %0, <16 x i8>* %1) nounwind { 2507; CHECK-FIX-LABEL: aesd_twice_via_ptr: 2508; CHECK-FIX: @ %bb.0: 2509; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r0] 2510; CHECK-FIX-NEXT: vld1.64 {d18, d19}, [r1] 2511; CHECK-FIX-NEXT: aesd.8 q9, q8 2512; CHECK-FIX-NEXT: aesimc.8 q8, q9 2513; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r1] 2514; CHECK-FIX-NEXT: vld1.64 {d18, d19}, [r0] 2515; CHECK-FIX-NEXT: aesd.8 q8, q9 2516; CHECK-FIX-NEXT: aesimc.8 q8, q8 2517; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r1] 2518; CHECK-FIX-NEXT: bx lr 2519 %3 = load <16 x i8>, <16 x i8>* %1, align 8 2520 %4 = load <16 x i8>, <16 x i8>* %0, align 8 2521 %5 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %3, <16 x i8> %4) 2522 %6 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %5) 2523 store <16 x i8> %6, <16 x i8>* %1, align 8 2524 %7 = load <16 x i8>, <16 x i8>* %0, align 8 2525 %8 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %6, <16 x i8> %7) 2526 %9 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %8) 2527 store <16 x i8> %9, <16 x i8>* %1, align 8 2528 ret void 2529} 2530 2531define arm_aapcs_vfpcc <16 x i8> @aesd_twice_via_val(<16 x i8> %0, <16 x i8> %1) nounwind { 2532; CHECK-FIX-LABEL: aesd_twice_via_val: 2533; CHECK-FIX: @ %bb.0: 2534; CHECK-FIX-NEXT: vorr q1, q1, q1 2535; CHECK-FIX-NEXT: vorr q0, q0, q0 2536; CHECK-FIX-NEXT: vorr q0, q0, q0 2537; CHECK-FIX-NEXT: aesd.8 q1, q0 2538; CHECK-FIX-NEXT: aesimc.8 q8, q1 2539; CHECK-FIX-NEXT: aesd.8 q8, q0 2540; CHECK-FIX-NEXT: aesimc.8 q0, q8 2541; CHECK-FIX-NEXT: bx lr 2542 %3 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %1, <16 x i8> %0) 2543 %4 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %3) 2544 %5 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %4, <16 x i8> %0) 2545 %6 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %5) 2546 ret <16 x i8> %6 2547} 2548 2549define arm_aapcs_vfpcc void @aesd_loop_via_ptr(i32 %0, <16 x i8>* %1, <16 x i8>* %2) nounwind { 2550; CHECK-FIX-NOSCHED-LABEL: aesd_loop_via_ptr: 2551; CHECK-FIX-NOSCHED: @ %bb.0: 2552; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 2553; CHECK-FIX-NOSCHED-NEXT: bxeq lr 2554; CHECK-FIX-NOSCHED-NEXT: .LBB54_1: @ =>This Inner Loop Header: Depth=1 2555; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r1] 2556; CHECK-FIX-NOSCHED-NEXT: subs r0, r0, #1 2557; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d18, d19}, [r2] 2558; CHECK-FIX-NOSCHED-NEXT: aesd.8 q9, q8 2559; CHECK-FIX-NOSCHED-NEXT: aesimc.8 q8, q9 2560; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r2] 2561; CHECK-FIX-NOSCHED-NEXT: bne .LBB54_1 2562; CHECK-FIX-NOSCHED-NEXT: @ %bb.2: 2563; CHECK-FIX-NOSCHED-NEXT: bx lr 2564; 2565; CHECK-CORTEX-FIX-LABEL: aesd_loop_via_ptr: 2566; CHECK-CORTEX-FIX: @ %bb.0: 2567; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 2568; CHECK-CORTEX-FIX-NEXT: bxeq lr 2569; CHECK-CORTEX-FIX-NEXT: .LBB54_1: @ =>This Inner Loop Header: Depth=1 2570; CHECK-CORTEX-FIX-NEXT: vld1.64 {d16, d17}, [r1] 2571; CHECK-CORTEX-FIX-NEXT: vld1.64 {d18, d19}, [r2] 2572; CHECK-CORTEX-FIX-NEXT: subs r0, r0, #1 2573; CHECK-CORTEX-FIX-NEXT: aesd.8 q9, q8 2574; CHECK-CORTEX-FIX-NEXT: aesimc.8 q8, q9 2575; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r2] 2576; CHECK-CORTEX-FIX-NEXT: bne .LBB54_1 2577; CHECK-CORTEX-FIX-NEXT: @ %bb.2: 2578; CHECK-CORTEX-FIX-NEXT: bx lr 2579 %4 = icmp eq i32 %0, 0 2580 br i1 %4, label %5, label %6 2581 25825: 2583 ret void 2584 25856: 2586 %7 = phi i32 [ %12, %6 ], [ 0, %3 ] 2587 %8 = load <16 x i8>, <16 x i8>* %2, align 8 2588 %9 = load <16 x i8>, <16 x i8>* %1, align 8 2589 %10 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %8, <16 x i8> %9) 2590 %11 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %10) 2591 store <16 x i8> %11, <16 x i8>* %2, align 8 2592 %12 = add nuw i32 %7, 1 2593 %13 = icmp eq i32 %12, %0 2594 br i1 %13, label %5, label %6 2595} 2596 2597define arm_aapcs_vfpcc <16 x i8> @aesd_loop_via_val(i32 %0, <16 x i8> %1, <16 x i8> %2) nounwind { 2598; CHECK-FIX-LABEL: aesd_loop_via_val: 2599; CHECK-FIX: @ %bb.0: 2600; CHECK-FIX-NEXT: vorr q1, q1, q1 2601; CHECK-FIX-NEXT: vorr q0, q0, q0 2602; CHECK-FIX-NEXT: cmp r0, #0 2603; CHECK-FIX-NEXT: beq .LBB55_2 2604; CHECK-FIX-NEXT: .LBB55_1: @ =>This Inner Loop Header: Depth=1 2605; CHECK-FIX-NEXT: aesd.8 q1, q0 2606; CHECK-FIX-NEXT: subs r0, r0, #1 2607; CHECK-FIX-NEXT: aesimc.8 q1, q1 2608; CHECK-FIX-NEXT: bne .LBB55_1 2609; CHECK-FIX-NEXT: .LBB55_2: 2610; CHECK-FIX-NEXT: vorr q0, q1, q1 2611; CHECK-FIX-NEXT: bx lr 2612 %4 = icmp eq i32 %0, 0 2613 br i1 %4, label %5, label %7 2614 26155: 2616 %6 = phi <16 x i8> [ %2, %3 ], [ %11, %7 ] 2617 ret <16 x i8> %6 2618 26197: 2620 %8 = phi i32 [ %12, %7 ], [ 0, %3 ] 2621 %9 = phi <16 x i8> [ %11, %7 ], [ %2, %3 ] 2622 %10 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %9, <16 x i8> %1) 2623 %11 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %10) 2624 %12 = add nuw i32 %8, 1 2625 %13 = icmp eq i32 %12, %0 2626 br i1 %13, label %5, label %7 2627} 2628 2629define arm_aapcs_vfpcc void @aesd_set8_via_ptr(i8* %0, <16 x i8> %1, <16 x i8>* %2) nounwind { 2630; CHECK-FIX-NOSCHED-LABEL: aesd_set8_via_ptr: 2631; CHECK-FIX-NOSCHED: @ %bb.0: 2632; CHECK-FIX-NOSCHED-NEXT: vorr q0, q0, q0 2633; CHECK-FIX-NOSCHED-NEXT: ldrb r0, [r0] 2634; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r1] 2635; CHECK-FIX-NOSCHED-NEXT: vmov.8 d0[0], r0 2636; CHECK-FIX-NOSCHED-NEXT: vmov.8 d16[0], r0 2637; CHECK-FIX-NOSCHED-NEXT: aesd.8 q8, q0 2638; CHECK-FIX-NOSCHED-NEXT: aesimc.8 q8, q8 2639; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r1] 2640; CHECK-FIX-NOSCHED-NEXT: bx lr 2641; 2642; CHECK-CORTEX-FIX-LABEL: aesd_set8_via_ptr: 2643; CHECK-CORTEX-FIX: @ %bb.0: 2644; CHECK-CORTEX-FIX-NEXT: vorr q0, q0, q0 2645; CHECK-CORTEX-FIX-NEXT: vld1.64 {d16, d17}, [r1] 2646; CHECK-CORTEX-FIX-NEXT: ldrb r0, [r0] 2647; CHECK-CORTEX-FIX-NEXT: vmov.8 d0[0], r0 2648; CHECK-CORTEX-FIX-NEXT: vmov.8 d16[0], r0 2649; CHECK-CORTEX-FIX-NEXT: aesd.8 q8, q0 2650; CHECK-CORTEX-FIX-NEXT: aesimc.8 q8, q8 2651; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r1] 2652; CHECK-CORTEX-FIX-NEXT: bx lr 2653 %4 = load i8, i8* %0, align 1 2654 %5 = load <16 x i8>, <16 x i8>* %2, align 8 2655 %6 = insertelement <16 x i8> %5, i8 %4, i64 0 2656 %7 = insertelement <16 x i8> %1, i8 %4, i64 0 2657 %8 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %6, <16 x i8> %7) 2658 %9 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %8) 2659 store <16 x i8> %9, <16 x i8>* %2, align 8 2660 ret void 2661} 2662 2663define arm_aapcs_vfpcc void @aesd_set8_via_val(i8 zeroext %0, <16 x i8> %1, <16 x i8>* %2) nounwind { 2664; CHECK-FIX-LABEL: aesd_set8_via_val: 2665; CHECK-FIX: @ %bb.0: 2666; CHECK-FIX-NEXT: vorr q0, q0, q0 2667; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r1] 2668; CHECK-FIX-NEXT: vmov.8 d0[0], r0 2669; CHECK-FIX-NEXT: vmov.8 d16[0], r0 2670; CHECK-FIX-NEXT: aesd.8 q8, q0 2671; CHECK-FIX-NEXT: aesimc.8 q8, q8 2672; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r1] 2673; CHECK-FIX-NEXT: bx lr 2674 %4 = load <16 x i8>, <16 x i8>* %2, align 8 2675 %5 = insertelement <16 x i8> %4, i8 %0, i64 0 2676 %6 = insertelement <16 x i8> %1, i8 %0, i64 0 2677 %7 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %5, <16 x i8> %6) 2678 %8 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %7) 2679 store <16 x i8> %8, <16 x i8>* %2, align 8 2680 ret void 2681} 2682 2683define arm_aapcs_vfpcc void @aesd_set8_cond_via_ptr(i1 zeroext %0, i8* %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 2684; CHECK-FIX-LABEL: aesd_set8_cond_via_ptr: 2685; CHECK-FIX: @ %bb.0: 2686; CHECK-FIX-NEXT: vorr q0, q0, q0 2687; CHECK-FIX-NEXT: cmp r0, #0 2688; CHECK-FIX-NEXT: beq .LBB58_2 2689; CHECK-FIX-NEXT: @ %bb.1: 2690; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 2691; CHECK-FIX-NEXT: vld1.8 {d16[0]}, [r1] 2692; CHECK-FIX-NEXT: cmp r0, #0 2693; CHECK-FIX-NEXT: bne .LBB58_3 2694; CHECK-FIX-NEXT: b .LBB58_4 2695; CHECK-FIX-NEXT: .LBB58_2: 2696; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 2697; CHECK-FIX-NEXT: cmp r0, #0 2698; CHECK-FIX-NEXT: beq .LBB58_4 2699; CHECK-FIX-NEXT: .LBB58_3: 2700; CHECK-FIX-NEXT: vld1.8 {d0[0]}, [r1] 2701; CHECK-FIX-NEXT: .LBB58_4: 2702; CHECK-FIX-NEXT: aesd.8 q8, q0 2703; CHECK-FIX-NEXT: aesimc.8 q8, q8 2704; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 2705; CHECK-FIX-NEXT: bx lr 2706 br i1 %0, label %5, label %9 2707 27085: 2709 %6 = load i8, i8* %1, align 1 2710 %7 = load <16 x i8>, <16 x i8>* %3, align 8 2711 %8 = insertelement <16 x i8> %7, i8 %6, i64 0 2712 br label %11 2713 27149: 2715 %10 = load <16 x i8>, <16 x i8>* %3, align 8 2716 br label %11 2717 271811: 2719 %12 = phi <16 x i8> [ %8, %5 ], [ %10, %9 ] 2720 br i1 %0, label %13, label %16 2721 272213: 2723 %14 = load i8, i8* %1, align 1 2724 %15 = insertelement <16 x i8> %2, i8 %14, i64 0 2725 br label %16 2726 272716: 2728 %17 = phi <16 x i8> [ %15, %13 ], [ %2, %11 ] 2729 %18 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %12, <16 x i8> %17) 2730 %19 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %18) 2731 store <16 x i8> %19, <16 x i8>* %3, align 8 2732 ret void 2733} 2734 2735define arm_aapcs_vfpcc void @aesd_set8_cond_via_val(i1 zeroext %0, i8 zeroext %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 2736; CHECK-FIX-LABEL: aesd_set8_cond_via_val: 2737; CHECK-FIX: @ %bb.0: 2738; CHECK-FIX-NEXT: vorr q0, q0, q0 2739; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 2740; CHECK-FIX-NEXT: cmp r0, #0 2741; CHECK-FIX-NEXT: beq .LBB59_2 2742; CHECK-FIX-NEXT: @ %bb.1: 2743; CHECK-FIX-NEXT: vmov.8 d16[0], r1 2744; CHECK-FIX-NEXT: .LBB59_2: @ %select.end 2745; CHECK-FIX-NEXT: cmp r0, #0 2746; CHECK-FIX-NEXT: beq .LBB59_4 2747; CHECK-FIX-NEXT: @ %bb.3: 2748; CHECK-FIX-NEXT: vmov.8 d0[0], r1 2749; CHECK-FIX-NEXT: .LBB59_4: @ %select.end1 2750; CHECK-FIX-NEXT: aesd.8 q8, q0 2751; CHECK-FIX-NEXT: aesimc.8 q8, q8 2752; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 2753; CHECK-FIX-NEXT: bx lr 2754 %5 = load <16 x i8>, <16 x i8>* %3, align 8 2755 %6 = insertelement <16 x i8> %5, i8 %1, i64 0 2756 %7 = select i1 %0, <16 x i8> %6, <16 x i8> %5 2757 %8 = insertelement <16 x i8> %2, i8 %1, i64 0 2758 %9 = select i1 %0, <16 x i8> %8, <16 x i8> %2 2759 %10 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %7, <16 x i8> %9) 2760 %11 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %10) 2761 store <16 x i8> %11, <16 x i8>* %3, align 8 2762 ret void 2763} 2764 2765define arm_aapcs_vfpcc void @aesd_set8_loop_via_ptr(i32 %0, i8* %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 2766; CHECK-FIX-LABEL: aesd_set8_loop_via_ptr: 2767; CHECK-FIX: @ %bb.0: 2768; CHECK-FIX-NEXT: vorr q0, q0, q0 2769; CHECK-FIX-NEXT: ldrb r1, [r1] 2770; CHECK-FIX-NEXT: cmp r0, #0 2771; CHECK-FIX-NEXT: strb r1, [r2] 2772; CHECK-FIX-NEXT: bxeq lr 2773; CHECK-FIX-NEXT: .LBB60_1: 2774; CHECK-FIX-NEXT: vmov.8 d0[0], r1 2775; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 2776; CHECK-FIX-NEXT: .LBB60_2: @ =>This Inner Loop Header: Depth=1 2777; CHECK-FIX-NEXT: aesd.8 q8, q0 2778; CHECK-FIX-NEXT: subs r0, r0, #1 2779; CHECK-FIX-NEXT: aesimc.8 q8, q8 2780; CHECK-FIX-NEXT: bne .LBB60_2 2781; CHECK-FIX-NEXT: @ %bb.3: 2782; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 2783; CHECK-FIX-NEXT: bx lr 2784 %5 = load i8, i8* %1, align 1 2785 %6 = insertelement <16 x i8> %2, i8 %5, i64 0 2786 %7 = getelementptr inbounds <16 x i8>, <16 x i8>* %3, i32 0, i32 0 2787 store i8 %5, i8* %7, align 8 2788 %8 = icmp eq i32 %0, 0 2789 br i1 %8, label %12, label %9 2790 27919: 2792 %10 = load <16 x i8>, <16 x i8>* %3, align 8 2793 br label %13 2794 279511: 2796 store <16 x i8> %17, <16 x i8>* %3, align 8 2797 br label %12 2798 279912: 2800 ret void 2801 280213: 2803 %14 = phi <16 x i8> [ %10, %9 ], [ %17, %13 ] 2804 %15 = phi i32 [ 0, %9 ], [ %18, %13 ] 2805 %16 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %14, <16 x i8> %6) 2806 %17 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %16) 2807 %18 = add nuw i32 %15, 1 2808 %19 = icmp eq i32 %18, %0 2809 br i1 %19, label %11, label %13 2810} 2811 2812define arm_aapcs_vfpcc void @aesd_set8_loop_via_val(i32 %0, i8 zeroext %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 2813; CHECK-FIX-LABEL: aesd_set8_loop_via_val: 2814; CHECK-FIX: @ %bb.0: 2815; CHECK-FIX-NEXT: vorr q0, q0, q0 2816; CHECK-FIX-NEXT: cmp r0, #0 2817; CHECK-FIX-NEXT: bxeq lr 2818; CHECK-FIX-NEXT: .LBB61_1: 2819; CHECK-FIX-NEXT: vmov.8 d0[0], r1 2820; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 2821; CHECK-FIX-NEXT: .LBB61_2: @ =>This Inner Loop Header: Depth=1 2822; CHECK-FIX-NEXT: vmov.8 d16[0], r1 2823; CHECK-FIX-NEXT: subs r0, r0, #1 2824; CHECK-FIX-NEXT: aesd.8 q8, q0 2825; CHECK-FIX-NEXT: aesimc.8 q8, q8 2826; CHECK-FIX-NEXT: bne .LBB61_2 2827; CHECK-FIX-NEXT: @ %bb.3: 2828; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 2829; CHECK-FIX-NEXT: bx lr 2830 %5 = icmp eq i32 %0, 0 2831 br i1 %5, label %10, label %6 2832 28336: 2834 %7 = insertelement <16 x i8> %2, i8 %1, i64 0 2835 %8 = load <16 x i8>, <16 x i8>* %3, align 8 2836 br label %11 2837 28389: 2839 store <16 x i8> %16, <16 x i8>* %3, align 8 2840 br label %10 2841 284210: 2843 ret void 2844 284511: 2846 %12 = phi <16 x i8> [ %8, %6 ], [ %16, %11 ] 2847 %13 = phi i32 [ 0, %6 ], [ %17, %11 ] 2848 %14 = insertelement <16 x i8> %12, i8 %1, i64 0 2849 %15 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %14, <16 x i8> %7) 2850 %16 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %15) 2851 %17 = add nuw i32 %13, 1 2852 %18 = icmp eq i32 %17, %0 2853 br i1 %18, label %9, label %11 2854} 2855 2856define arm_aapcs_vfpcc void @aesd_set16_via_ptr(i16* %0, <16 x i8> %1, <16 x i8>* %2) nounwind { 2857; CHECK-FIX-NOSCHED-LABEL: aesd_set16_via_ptr: 2858; CHECK-FIX-NOSCHED: @ %bb.0: 2859; CHECK-FIX-NOSCHED-NEXT: vorr q0, q0, q0 2860; CHECK-FIX-NOSCHED-NEXT: ldrh r0, [r0] 2861; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r1] 2862; CHECK-FIX-NOSCHED-NEXT: vmov.16 d0[0], r0 2863; CHECK-FIX-NOSCHED-NEXT: vmov.16 d16[0], r0 2864; CHECK-FIX-NOSCHED-NEXT: aesd.8 q8, q0 2865; CHECK-FIX-NOSCHED-NEXT: aesimc.8 q8, q8 2866; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r1] 2867; CHECK-FIX-NOSCHED-NEXT: bx lr 2868; 2869; CHECK-CORTEX-FIX-LABEL: aesd_set16_via_ptr: 2870; CHECK-CORTEX-FIX: @ %bb.0: 2871; CHECK-CORTEX-FIX-NEXT: vorr q0, q0, q0 2872; CHECK-CORTEX-FIX-NEXT: vld1.64 {d16, d17}, [r1] 2873; CHECK-CORTEX-FIX-NEXT: ldrh r0, [r0] 2874; CHECK-CORTEX-FIX-NEXT: vmov.16 d0[0], r0 2875; CHECK-CORTEX-FIX-NEXT: vmov.16 d16[0], r0 2876; CHECK-CORTEX-FIX-NEXT: aesd.8 q8, q0 2877; CHECK-CORTEX-FIX-NEXT: aesimc.8 q8, q8 2878; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r1] 2879; CHECK-CORTEX-FIX-NEXT: bx lr 2880 %4 = load i16, i16* %0, align 2 2881 %5 = bitcast <16 x i8>* %2 to <8 x i16>* 2882 %6 = load <8 x i16>, <8 x i16>* %5, align 8 2883 %7 = insertelement <8 x i16> %6, i16 %4, i64 0 2884 %8 = bitcast <8 x i16> %7 to <16 x i8> 2885 %9 = bitcast <16 x i8> %1 to <8 x i16> 2886 %10 = insertelement <8 x i16> %9, i16 %4, i64 0 2887 %11 = bitcast <8 x i16> %10 to <16 x i8> 2888 %12 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %8, <16 x i8> %11) 2889 %13 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %12) 2890 store <16 x i8> %13, <16 x i8>* %2, align 8 2891 ret void 2892} 2893 2894define arm_aapcs_vfpcc void @aesd_set16_via_val(i16 zeroext %0, <16 x i8> %1, <16 x i8>* %2) nounwind { 2895; CHECK-FIX-LABEL: aesd_set16_via_val: 2896; CHECK-FIX: @ %bb.0: 2897; CHECK-FIX-NEXT: vorr q0, q0, q0 2898; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r1] 2899; CHECK-FIX-NEXT: vmov.16 d0[0], r0 2900; CHECK-FIX-NEXT: vmov.16 d16[0], r0 2901; CHECK-FIX-NEXT: aesd.8 q8, q0 2902; CHECK-FIX-NEXT: aesimc.8 q8, q8 2903; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r1] 2904; CHECK-FIX-NEXT: bx lr 2905 %4 = bitcast <16 x i8>* %2 to <8 x i16>* 2906 %5 = load <8 x i16>, <8 x i16>* %4, align 8 2907 %6 = insertelement <8 x i16> %5, i16 %0, i64 0 2908 %7 = bitcast <8 x i16> %6 to <16 x i8> 2909 %8 = bitcast <16 x i8> %1 to <8 x i16> 2910 %9 = insertelement <8 x i16> %8, i16 %0, i64 0 2911 %10 = bitcast <8 x i16> %9 to <16 x i8> 2912 %11 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %7, <16 x i8> %10) 2913 %12 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %11) 2914 store <16 x i8> %12, <16 x i8>* %2, align 8 2915 ret void 2916} 2917 2918define arm_aapcs_vfpcc void @aesd_set16_cond_via_ptr(i1 zeroext %0, i16* %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 2919; CHECK-FIX-LABEL: aesd_set16_cond_via_ptr: 2920; CHECK-FIX: @ %bb.0: 2921; CHECK-FIX-NEXT: vorr q0, q0, q0 2922; CHECK-FIX-NEXT: cmp r0, #0 2923; CHECK-FIX-NEXT: beq .LBB64_2 2924; CHECK-FIX-NEXT: @ %bb.1: 2925; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 2926; CHECK-FIX-NEXT: vld1.16 {d16[0]}, [r1:16] 2927; CHECK-FIX-NEXT: cmp r0, #0 2928; CHECK-FIX-NEXT: bne .LBB64_3 2929; CHECK-FIX-NEXT: b .LBB64_4 2930; CHECK-FIX-NEXT: .LBB64_2: 2931; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 2932; CHECK-FIX-NEXT: cmp r0, #0 2933; CHECK-FIX-NEXT: beq .LBB64_4 2934; CHECK-FIX-NEXT: .LBB64_3: 2935; CHECK-FIX-NEXT: vld1.16 {d0[0]}, [r1:16] 2936; CHECK-FIX-NEXT: .LBB64_4: 2937; CHECK-FIX-NEXT: aesd.8 q8, q0 2938; CHECK-FIX-NEXT: aesimc.8 q8, q8 2939; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 2940; CHECK-FIX-NEXT: bx lr 2941 br i1 %0, label %5, label %10 2942 29435: 2944 %6 = load i16, i16* %1, align 2 2945 %7 = bitcast <16 x i8>* %3 to <8 x i16>* 2946 %8 = load <8 x i16>, <8 x i16>* %7, align 8 2947 %9 = insertelement <8 x i16> %8, i16 %6, i64 0 2948 br label %13 2949 295010: 2951 %11 = bitcast <16 x i8>* %3 to <8 x i16>* 2952 %12 = load <8 x i16>, <8 x i16>* %11, align 8 2953 br label %13 2954 295513: 2956 %14 = phi <8 x i16> [ %9, %5 ], [ %12, %10 ] 2957 br i1 %0, label %15, label %19 2958 295915: 2960 %16 = load i16, i16* %1, align 2 2961 %17 = bitcast <16 x i8> %2 to <8 x i16> 2962 %18 = insertelement <8 x i16> %17, i16 %16, i64 0 2963 br label %21 2964 296519: 2966 %20 = bitcast <16 x i8> %2 to <8 x i16> 2967 br label %21 2968 296921: 2970 %22 = phi <8 x i16> [ %18, %15 ], [ %20, %19 ] 2971 %23 = bitcast <8 x i16> %14 to <16 x i8> 2972 %24 = bitcast <8 x i16> %22 to <16 x i8> 2973 %25 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %23, <16 x i8> %24) 2974 %26 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %25) 2975 store <16 x i8> %26, <16 x i8>* %3, align 8 2976 ret void 2977} 2978 2979define arm_aapcs_vfpcc void @aesd_set16_cond_via_val(i1 zeroext %0, i16 zeroext %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 2980; CHECK-FIX-LABEL: aesd_set16_cond_via_val: 2981; CHECK-FIX: @ %bb.0: 2982; CHECK-FIX-NEXT: vorr q0, q0, q0 2983; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 2984; CHECK-FIX-NEXT: cmp r0, #0 2985; CHECK-FIX-NEXT: beq .LBB65_2 2986; CHECK-FIX-NEXT: @ %bb.1: 2987; CHECK-FIX-NEXT: vmov.16 d16[0], r1 2988; CHECK-FIX-NEXT: .LBB65_2: @ %select.end 2989; CHECK-FIX-NEXT: cmp r0, #0 2990; CHECK-FIX-NEXT: beq .LBB65_4 2991; CHECK-FIX-NEXT: @ %bb.3: 2992; CHECK-FIX-NEXT: vmov.16 d0[0], r1 2993; CHECK-FIX-NEXT: .LBB65_4: @ %select.end1 2994; CHECK-FIX-NEXT: aesd.8 q8, q0 2995; CHECK-FIX-NEXT: aesimc.8 q8, q8 2996; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 2997; CHECK-FIX-NEXT: bx lr 2998 %5 = bitcast <16 x i8>* %3 to <8 x i16>* 2999 %6 = load <8 x i16>, <8 x i16>* %5, align 8 3000 %7 = insertelement <8 x i16> %6, i16 %1, i64 0 3001 %8 = select i1 %0, <8 x i16> %7, <8 x i16> %6 3002 %9 = bitcast <16 x i8> %2 to <8 x i16> 3003 %10 = insertelement <8 x i16> %9, i16 %1, i64 0 3004 %11 = select i1 %0, <8 x i16> %10, <8 x i16> %9 3005 %12 = bitcast <8 x i16> %8 to <16 x i8> 3006 %13 = bitcast <8 x i16> %11 to <16 x i8> 3007 %14 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %12, <16 x i8> %13) 3008 %15 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %14) 3009 store <16 x i8> %15, <16 x i8>* %3, align 8 3010 ret void 3011} 3012 3013define arm_aapcs_vfpcc void @aesd_set16_loop_via_ptr(i32 %0, i16* %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 3014; CHECK-FIX-LABEL: aesd_set16_loop_via_ptr: 3015; CHECK-FIX: @ %bb.0: 3016; CHECK-FIX-NEXT: vorr q0, q0, q0 3017; CHECK-FIX-NEXT: ldrh r1, [r1] 3018; CHECK-FIX-NEXT: cmp r0, #0 3019; CHECK-FIX-NEXT: strh r1, [r2] 3020; CHECK-FIX-NEXT: bxeq lr 3021; CHECK-FIX-NEXT: .LBB66_1: 3022; CHECK-FIX-NEXT: vmov.16 d0[0], r1 3023; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 3024; CHECK-FIX-NEXT: .LBB66_2: @ =>This Inner Loop Header: Depth=1 3025; CHECK-FIX-NEXT: aesd.8 q8, q0 3026; CHECK-FIX-NEXT: subs r0, r0, #1 3027; CHECK-FIX-NEXT: aesimc.8 q8, q8 3028; CHECK-FIX-NEXT: bne .LBB66_2 3029; CHECK-FIX-NEXT: @ %bb.3: 3030; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 3031; CHECK-FIX-NEXT: bx lr 3032 %5 = load i16, i16* %1, align 2 3033 %6 = bitcast <16 x i8> %2 to <8 x i16> 3034 %7 = insertelement <8 x i16> %6, i16 %5, i64 0 3035 %8 = bitcast <8 x i16> %7 to <16 x i8> 3036 %9 = bitcast <16 x i8>* %3 to i16* 3037 store i16 %5, i16* %9, align 8 3038 %10 = icmp eq i32 %0, 0 3039 br i1 %10, label %14, label %11 3040 304111: 3042 %12 = load <16 x i8>, <16 x i8>* %3, align 8 3043 br label %15 3044 304513: 3046 store <16 x i8> %19, <16 x i8>* %3, align 8 3047 br label %14 3048 304914: 3050 ret void 3051 305215: 3053 %16 = phi <16 x i8> [ %12, %11 ], [ %19, %15 ] 3054 %17 = phi i32 [ 0, %11 ], [ %20, %15 ] 3055 %18 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %16, <16 x i8> %8) 3056 %19 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %18) 3057 %20 = add nuw i32 %17, 1 3058 %21 = icmp eq i32 %20, %0 3059 br i1 %21, label %13, label %15 3060} 3061 3062define arm_aapcs_vfpcc void @aesd_set16_loop_via_val(i32 %0, i16 zeroext %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 3063; CHECK-FIX-LABEL: aesd_set16_loop_via_val: 3064; CHECK-FIX: @ %bb.0: 3065; CHECK-FIX-NEXT: vorr q0, q0, q0 3066; CHECK-FIX-NEXT: cmp r0, #0 3067; CHECK-FIX-NEXT: bxeq lr 3068; CHECK-FIX-NEXT: .LBB67_1: 3069; CHECK-FIX-NEXT: vmov.16 d0[0], r1 3070; CHECK-FIX-NEXT: .LBB67_2: @ =>This Inner Loop Header: Depth=1 3071; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 3072; CHECK-FIX-NEXT: subs r0, r0, #1 3073; CHECK-FIX-NEXT: vmov.16 d16[0], r1 3074; CHECK-FIX-NEXT: aesd.8 q8, q0 3075; CHECK-FIX-NEXT: aesimc.8 q8, q8 3076; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 3077; CHECK-FIX-NEXT: bne .LBB67_2 3078; CHECK-FIX-NEXT: @ %bb.3: 3079; CHECK-FIX-NEXT: bx lr 3080 %5 = icmp eq i32 %0, 0 3081 br i1 %5, label %12, label %6 3082 30836: 3084 %7 = bitcast <16 x i8> %2 to <8 x i16> 3085 %8 = insertelement <8 x i16> %7, i16 %1, i64 0 3086 %9 = bitcast <8 x i16> %8 to <16 x i8> 3087 %10 = bitcast <16 x i8>* %3 to <8 x i16>* 3088 %11 = bitcast <16 x i8>* %3 to i16* 3089 br label %13 3090 309112: 3092 ret void 3093 309413: 3095 %14 = phi i32 [ 0, %6 ], [ %20, %13 ] 3096 %15 = load <8 x i16>, <8 x i16>* %10, align 8 3097 %16 = insertelement <8 x i16> %15, i16 %1, i64 0 3098 %17 = bitcast <8 x i16> %16 to <16 x i8> 3099 store i16 %1, i16* %11, align 8 3100 %18 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %17, <16 x i8> %9) 3101 %19 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %18) 3102 store <16 x i8> %19, <16 x i8>* %3, align 8 3103 %20 = add nuw i32 %14, 1 3104 %21 = icmp eq i32 %20, %0 3105 br i1 %21, label %12, label %13 3106} 3107 3108define arm_aapcs_vfpcc void @aesd_set32_via_ptr(i32* %0, <16 x i8> %1, <16 x i8>* %2) nounwind { 3109; CHECK-FIX-NOSCHED-LABEL: aesd_set32_via_ptr: 3110; CHECK-FIX-NOSCHED: @ %bb.0: 3111; CHECK-FIX-NOSCHED-NEXT: vorr q0, q0, q0 3112; CHECK-FIX-NOSCHED-NEXT: ldr r0, [r0] 3113; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r1] 3114; CHECK-FIX-NOSCHED-NEXT: vmov.32 d0[0], r0 3115; CHECK-FIX-NOSCHED-NEXT: vmov.32 d16[0], r0 3116; CHECK-FIX-NOSCHED-NEXT: aesd.8 q8, q0 3117; CHECK-FIX-NOSCHED-NEXT: aesimc.8 q8, q8 3118; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r1] 3119; CHECK-FIX-NOSCHED-NEXT: bx lr 3120; 3121; CHECK-CORTEX-FIX-LABEL: aesd_set32_via_ptr: 3122; CHECK-CORTEX-FIX: @ %bb.0: 3123; CHECK-CORTEX-FIX-NEXT: vorr q0, q0, q0 3124; CHECK-CORTEX-FIX-NEXT: vld1.64 {d16, d17}, [r1] 3125; CHECK-CORTEX-FIX-NEXT: ldr r0, [r0] 3126; CHECK-CORTEX-FIX-NEXT: vmov.32 d0[0], r0 3127; CHECK-CORTEX-FIX-NEXT: vmov.32 d16[0], r0 3128; CHECK-CORTEX-FIX-NEXT: aesd.8 q8, q0 3129; CHECK-CORTEX-FIX-NEXT: aesimc.8 q8, q8 3130; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r1] 3131; CHECK-CORTEX-FIX-NEXT: bx lr 3132 %4 = load i32, i32* %0, align 4 3133 %5 = bitcast <16 x i8>* %2 to <4 x i32>* 3134 %6 = load <4 x i32>, <4 x i32>* %5, align 8 3135 %7 = insertelement <4 x i32> %6, i32 %4, i64 0 3136 %8 = bitcast <4 x i32> %7 to <16 x i8> 3137 %9 = bitcast <16 x i8> %1 to <4 x i32> 3138 %10 = insertelement <4 x i32> %9, i32 %4, i64 0 3139 %11 = bitcast <4 x i32> %10 to <16 x i8> 3140 %12 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %8, <16 x i8> %11) 3141 %13 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %12) 3142 store <16 x i8> %13, <16 x i8>* %2, align 8 3143 ret void 3144} 3145 3146define arm_aapcs_vfpcc void @aesd_set32_via_val(i32 %0, <16 x i8> %1, <16 x i8>* %2) nounwind { 3147; CHECK-FIX-LABEL: aesd_set32_via_val: 3148; CHECK-FIX: @ %bb.0: 3149; CHECK-FIX-NEXT: vorr q0, q0, q0 3150; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r1] 3151; CHECK-FIX-NEXT: vmov.32 d0[0], r0 3152; CHECK-FIX-NEXT: vmov.32 d16[0], r0 3153; CHECK-FIX-NEXT: aesd.8 q8, q0 3154; CHECK-FIX-NEXT: aesimc.8 q8, q8 3155; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r1] 3156; CHECK-FIX-NEXT: bx lr 3157 %4 = bitcast <16 x i8>* %2 to <4 x i32>* 3158 %5 = load <4 x i32>, <4 x i32>* %4, align 8 3159 %6 = insertelement <4 x i32> %5, i32 %0, i64 0 3160 %7 = bitcast <4 x i32> %6 to <16 x i8> 3161 %8 = bitcast <16 x i8> %1 to <4 x i32> 3162 %9 = insertelement <4 x i32> %8, i32 %0, i64 0 3163 %10 = bitcast <4 x i32> %9 to <16 x i8> 3164 %11 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %7, <16 x i8> %10) 3165 %12 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %11) 3166 store <16 x i8> %12, <16 x i8>* %2, align 8 3167 ret void 3168} 3169 3170define arm_aapcs_vfpcc void @aesd_set32_cond_via_ptr(i1 zeroext %0, i32* %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 3171; CHECK-FIX-LABEL: aesd_set32_cond_via_ptr: 3172; CHECK-FIX: @ %bb.0: 3173; CHECK-FIX-NEXT: vorr q0, q0, q0 3174; CHECK-FIX-NEXT: cmp r0, #0 3175; CHECK-FIX-NEXT: beq .LBB70_2 3176; CHECK-FIX-NEXT: @ %bb.1: 3177; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 3178; CHECK-FIX-NEXT: vld1.32 {d16[0]}, [r1:32] 3179; CHECK-FIX-NEXT: cmp r0, #0 3180; CHECK-FIX-NEXT: bne .LBB70_3 3181; CHECK-FIX-NEXT: b .LBB70_4 3182; CHECK-FIX-NEXT: .LBB70_2: 3183; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 3184; CHECK-FIX-NEXT: cmp r0, #0 3185; CHECK-FIX-NEXT: beq .LBB70_4 3186; CHECK-FIX-NEXT: .LBB70_3: 3187; CHECK-FIX-NEXT: vld1.32 {d0[0]}, [r1:32] 3188; CHECK-FIX-NEXT: .LBB70_4: 3189; CHECK-FIX-NEXT: aesd.8 q8, q0 3190; CHECK-FIX-NEXT: aesimc.8 q8, q8 3191; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 3192; CHECK-FIX-NEXT: bx lr 3193 br i1 %0, label %5, label %10 3194 31955: 3196 %6 = load i32, i32* %1, align 4 3197 %7 = bitcast <16 x i8>* %3 to <4 x i32>* 3198 %8 = load <4 x i32>, <4 x i32>* %7, align 8 3199 %9 = insertelement <4 x i32> %8, i32 %6, i64 0 3200 br label %13 3201 320210: 3203 %11 = bitcast <16 x i8>* %3 to <4 x i32>* 3204 %12 = load <4 x i32>, <4 x i32>* %11, align 8 3205 br label %13 3206 320713: 3208 %14 = phi <4 x i32> [ %9, %5 ], [ %12, %10 ] 3209 br i1 %0, label %15, label %19 3210 321115: 3212 %16 = load i32, i32* %1, align 4 3213 %17 = bitcast <16 x i8> %2 to <4 x i32> 3214 %18 = insertelement <4 x i32> %17, i32 %16, i64 0 3215 br label %21 3216 321719: 3218 %20 = bitcast <16 x i8> %2 to <4 x i32> 3219 br label %21 3220 322121: 3222 %22 = phi <4 x i32> [ %18, %15 ], [ %20, %19 ] 3223 %23 = bitcast <4 x i32> %14 to <16 x i8> 3224 %24 = bitcast <4 x i32> %22 to <16 x i8> 3225 %25 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %23, <16 x i8> %24) 3226 %26 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %25) 3227 store <16 x i8> %26, <16 x i8>* %3, align 8 3228 ret void 3229} 3230 3231define arm_aapcs_vfpcc void @aesd_set32_cond_via_val(i1 zeroext %0, i32 %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 3232; CHECK-FIX-LABEL: aesd_set32_cond_via_val: 3233; CHECK-FIX: @ %bb.0: 3234; CHECK-FIX-NEXT: vorr q0, q0, q0 3235; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 3236; CHECK-FIX-NEXT: cmp r0, #0 3237; CHECK-FIX-NEXT: beq .LBB71_2 3238; CHECK-FIX-NEXT: @ %bb.1: 3239; CHECK-FIX-NEXT: vmov.32 d16[0], r1 3240; CHECK-FIX-NEXT: .LBB71_2: @ %select.end 3241; CHECK-FIX-NEXT: cmp r0, #0 3242; CHECK-FIX-NEXT: beq .LBB71_4 3243; CHECK-FIX-NEXT: @ %bb.3: 3244; CHECK-FIX-NEXT: vmov.32 d0[0], r1 3245; CHECK-FIX-NEXT: .LBB71_4: @ %select.end1 3246; CHECK-FIX-NEXT: aesd.8 q8, q0 3247; CHECK-FIX-NEXT: aesimc.8 q8, q8 3248; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 3249; CHECK-FIX-NEXT: bx lr 3250 %5 = bitcast <16 x i8>* %3 to <4 x i32>* 3251 %6 = load <4 x i32>, <4 x i32>* %5, align 8 3252 %7 = insertelement <4 x i32> %6, i32 %1, i64 0 3253 %8 = select i1 %0, <4 x i32> %7, <4 x i32> %6 3254 %9 = bitcast <16 x i8> %2 to <4 x i32> 3255 %10 = insertelement <4 x i32> %9, i32 %1, i64 0 3256 %11 = select i1 %0, <4 x i32> %10, <4 x i32> %9 3257 %12 = bitcast <4 x i32> %8 to <16 x i8> 3258 %13 = bitcast <4 x i32> %11 to <16 x i8> 3259 %14 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %12, <16 x i8> %13) 3260 %15 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %14) 3261 store <16 x i8> %15, <16 x i8>* %3, align 8 3262 ret void 3263} 3264 3265define arm_aapcs_vfpcc void @aesd_set32_loop_via_ptr(i32 %0, i32* %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 3266; CHECK-FIX-LABEL: aesd_set32_loop_via_ptr: 3267; CHECK-FIX: @ %bb.0: 3268; CHECK-FIX-NEXT: vorr q0, q0, q0 3269; CHECK-FIX-NEXT: ldr r1, [r1] 3270; CHECK-FIX-NEXT: cmp r0, #0 3271; CHECK-FIX-NEXT: str r1, [r2] 3272; CHECK-FIX-NEXT: bxeq lr 3273; CHECK-FIX-NEXT: .LBB72_1: 3274; CHECK-FIX-NEXT: vmov.32 d0[0], r1 3275; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 3276; CHECK-FIX-NEXT: .LBB72_2: @ =>This Inner Loop Header: Depth=1 3277; CHECK-FIX-NEXT: aesd.8 q8, q0 3278; CHECK-FIX-NEXT: subs r0, r0, #1 3279; CHECK-FIX-NEXT: aesimc.8 q8, q8 3280; CHECK-FIX-NEXT: bne .LBB72_2 3281; CHECK-FIX-NEXT: @ %bb.3: 3282; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 3283; CHECK-FIX-NEXT: bx lr 3284 %5 = load i32, i32* %1, align 4 3285 %6 = bitcast <16 x i8> %2 to <4 x i32> 3286 %7 = insertelement <4 x i32> %6, i32 %5, i64 0 3287 %8 = bitcast <4 x i32> %7 to <16 x i8> 3288 %9 = bitcast <16 x i8>* %3 to i32* 3289 store i32 %5, i32* %9, align 8 3290 %10 = icmp eq i32 %0, 0 3291 br i1 %10, label %14, label %11 3292 329311: 3294 %12 = load <16 x i8>, <16 x i8>* %3, align 8 3295 br label %15 3296 329713: 3298 store <16 x i8> %19, <16 x i8>* %3, align 8 3299 br label %14 3300 330114: 3302 ret void 3303 330415: 3305 %16 = phi <16 x i8> [ %12, %11 ], [ %19, %15 ] 3306 %17 = phi i32 [ 0, %11 ], [ %20, %15 ] 3307 %18 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %16, <16 x i8> %8) 3308 %19 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %18) 3309 %20 = add nuw i32 %17, 1 3310 %21 = icmp eq i32 %20, %0 3311 br i1 %21, label %13, label %15 3312} 3313 3314define arm_aapcs_vfpcc void @aesd_set32_loop_via_val(i32 %0, i32 %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 3315; CHECK-FIX-LABEL: aesd_set32_loop_via_val: 3316; CHECK-FIX: @ %bb.0: 3317; CHECK-FIX-NEXT: vorr q0, q0, q0 3318; CHECK-FIX-NEXT: cmp r0, #0 3319; CHECK-FIX-NEXT: bxeq lr 3320; CHECK-FIX-NEXT: .LBB73_1: 3321; CHECK-FIX-NEXT: vmov.32 d0[0], r1 3322; CHECK-FIX-NEXT: .LBB73_2: @ =>This Inner Loop Header: Depth=1 3323; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 3324; CHECK-FIX-NEXT: subs r0, r0, #1 3325; CHECK-FIX-NEXT: vmov.32 d16[0], r1 3326; CHECK-FIX-NEXT: aesd.8 q8, q0 3327; CHECK-FIX-NEXT: aesimc.8 q8, q8 3328; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 3329; CHECK-FIX-NEXT: bne .LBB73_2 3330; CHECK-FIX-NEXT: @ %bb.3: 3331; CHECK-FIX-NEXT: bx lr 3332 %5 = icmp eq i32 %0, 0 3333 br i1 %5, label %12, label %6 3334 33356: 3336 %7 = bitcast <16 x i8> %2 to <4 x i32> 3337 %8 = insertelement <4 x i32> %7, i32 %1, i64 0 3338 %9 = bitcast <4 x i32> %8 to <16 x i8> 3339 %10 = bitcast <16 x i8>* %3 to <4 x i32>* 3340 %11 = bitcast <16 x i8>* %3 to i32* 3341 br label %13 3342 334312: 3344 ret void 3345 334613: 3347 %14 = phi i32 [ 0, %6 ], [ %20, %13 ] 3348 %15 = load <4 x i32>, <4 x i32>* %10, align 8 3349 %16 = insertelement <4 x i32> %15, i32 %1, i64 0 3350 %17 = bitcast <4 x i32> %16 to <16 x i8> 3351 store i32 %1, i32* %11, align 8 3352 %18 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %17, <16 x i8> %9) 3353 %19 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %18) 3354 store <16 x i8> %19, <16 x i8>* %3, align 8 3355 %20 = add nuw i32 %14, 1 3356 %21 = icmp eq i32 %20, %0 3357 br i1 %21, label %12, label %13 3358} 3359 3360define arm_aapcs_vfpcc void @aesd_set64_via_ptr(i64* %0, <16 x i8> %1, <16 x i8>* %2) nounwind { 3361; CHECK-FIX-NOSCHED-LABEL: aesd_set64_via_ptr: 3362; CHECK-FIX-NOSCHED: @ %bb.0: 3363; CHECK-FIX-NOSCHED-NEXT: vorr q0, q0, q0 3364; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r1] 3365; CHECK-FIX-NOSCHED-NEXT: vldr d0, [r0] 3366; CHECK-FIX-NOSCHED-NEXT: vorr d16, d0, d0 3367; CHECK-FIX-NOSCHED-NEXT: aesd.8 q8, q0 3368; CHECK-FIX-NOSCHED-NEXT: aesimc.8 q8, q8 3369; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r1] 3370; CHECK-FIX-NOSCHED-NEXT: bx lr 3371; 3372; CHECK-CORTEX-FIX-LABEL: aesd_set64_via_ptr: 3373; CHECK-CORTEX-FIX: @ %bb.0: 3374; CHECK-CORTEX-FIX-NEXT: vorr q0, q0, q0 3375; CHECK-CORTEX-FIX-NEXT: vldr d0, [r0] 3376; CHECK-CORTEX-FIX-NEXT: vld1.64 {d16, d17}, [r1] 3377; CHECK-CORTEX-FIX-NEXT: vorr d16, d0, d0 3378; CHECK-CORTEX-FIX-NEXT: aesd.8 q8, q0 3379; CHECK-CORTEX-FIX-NEXT: aesimc.8 q8, q8 3380; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r1] 3381; CHECK-CORTEX-FIX-NEXT: bx lr 3382 %4 = load i64, i64* %0, align 8 3383 %5 = bitcast <16 x i8>* %2 to <2 x i64>* 3384 %6 = load <2 x i64>, <2 x i64>* %5, align 8 3385 %7 = insertelement <2 x i64> %6, i64 %4, i64 0 3386 %8 = bitcast <2 x i64> %7 to <16 x i8> 3387 %9 = bitcast <16 x i8> %1 to <2 x i64> 3388 %10 = insertelement <2 x i64> %9, i64 %4, i64 0 3389 %11 = bitcast <2 x i64> %10 to <16 x i8> 3390 %12 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %8, <16 x i8> %11) 3391 %13 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %12) 3392 store <16 x i8> %13, <16 x i8>* %2, align 8 3393 ret void 3394} 3395 3396define arm_aapcs_vfpcc void @aesd_set64_via_val(i64 %0, <16 x i8> %1, <16 x i8>* %2) nounwind { 3397; CHECK-FIX-LABEL: aesd_set64_via_val: 3398; CHECK-FIX: @ %bb.0: 3399; CHECK-FIX-NEXT: vorr q0, q0, q0 3400; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 3401; CHECK-FIX-NEXT: vmov.32 d0[0], r0 3402; CHECK-FIX-NEXT: vmov.32 d16[0], r0 3403; CHECK-FIX-NEXT: vmov.32 d0[1], r1 3404; CHECK-FIX-NEXT: vmov.32 d16[1], r1 3405; CHECK-FIX-NEXT: aesd.8 q8, q0 3406; CHECK-FIX-NEXT: aesimc.8 q8, q8 3407; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 3408; CHECK-FIX-NEXT: bx lr 3409 %4 = bitcast <16 x i8>* %2 to <2 x i64>* 3410 %5 = load <2 x i64>, <2 x i64>* %4, align 8 3411 %6 = insertelement <2 x i64> %5, i64 %0, i64 0 3412 %7 = bitcast <2 x i64> %6 to <16 x i8> 3413 %8 = bitcast <16 x i8> %1 to <2 x i64> 3414 %9 = insertelement <2 x i64> %8, i64 %0, i64 0 3415 %10 = bitcast <2 x i64> %9 to <16 x i8> 3416 %11 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %7, <16 x i8> %10) 3417 %12 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %11) 3418 store <16 x i8> %12, <16 x i8>* %2, align 8 3419 ret void 3420} 3421 3422define arm_aapcs_vfpcc void @aesd_set64_cond_via_ptr(i1 zeroext %0, i64* %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 3423; CHECK-FIX-NOSCHED-LABEL: aesd_set64_cond_via_ptr: 3424; CHECK-FIX-NOSCHED: @ %bb.0: 3425; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 3426; CHECK-FIX-NOSCHED-NEXT: beq .LBB76_2 3427; CHECK-FIX-NOSCHED-NEXT: @ %bb.1: 3428; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r2] 3429; CHECK-FIX-NOSCHED-NEXT: vldr d16, [r1] 3430; CHECK-FIX-NOSCHED-NEXT: b .LBB76_3 3431; CHECK-FIX-NOSCHED-NEXT: .LBB76_2: 3432; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r2] 3433; CHECK-FIX-NOSCHED-NEXT: .LBB76_3: 3434; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 3435; CHECK-FIX-NOSCHED-NEXT: vldrne d0, [r1] 3436; CHECK-FIX-NOSCHED-NEXT: vorr q0, q0, q0 3437; CHECK-FIX-NOSCHED-NEXT: aesd.8 q8, q0 3438; CHECK-FIX-NOSCHED-NEXT: aesimc.8 q8, q8 3439; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r2] 3440; CHECK-FIX-NOSCHED-NEXT: bx lr 3441; 3442; CHECK-CORTEX-FIX-LABEL: aesd_set64_cond_via_ptr: 3443; CHECK-CORTEX-FIX: @ %bb.0: 3444; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 3445; CHECK-CORTEX-FIX-NEXT: beq .LBB76_2 3446; CHECK-CORTEX-FIX-NEXT: @ %bb.1: 3447; CHECK-CORTEX-FIX-NEXT: vldr d18, [r1] 3448; CHECK-CORTEX-FIX-NEXT: vld1.64 {d16, d17}, [r2] 3449; CHECK-CORTEX-FIX-NEXT: vorr d16, d18, d18 3450; CHECK-CORTEX-FIX-NEXT: b .LBB76_3 3451; CHECK-CORTEX-FIX-NEXT: .LBB76_2: 3452; CHECK-CORTEX-FIX-NEXT: vld1.64 {d16, d17}, [r2] 3453; CHECK-CORTEX-FIX-NEXT: .LBB76_3: 3454; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 3455; CHECK-CORTEX-FIX-NEXT: vldrne d0, [r1] 3456; CHECK-CORTEX-FIX-NEXT: vorr q0, q0, q0 3457; CHECK-CORTEX-FIX-NEXT: aesd.8 q8, q0 3458; CHECK-CORTEX-FIX-NEXT: aesimc.8 q8, q8 3459; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r2] 3460; CHECK-CORTEX-FIX-NEXT: bx lr 3461 br i1 %0, label %5, label %10 3462 34635: 3464 %6 = load i64, i64* %1, align 8 3465 %7 = bitcast <16 x i8>* %3 to <2 x i64>* 3466 %8 = load <2 x i64>, <2 x i64>* %7, align 8 3467 %9 = insertelement <2 x i64> %8, i64 %6, i64 0 3468 br label %13 3469 347010: 3471 %11 = bitcast <16 x i8>* %3 to <2 x i64>* 3472 %12 = load <2 x i64>, <2 x i64>* %11, align 8 3473 br label %13 3474 347513: 3476 %14 = phi <2 x i64> [ %9, %5 ], [ %12, %10 ] 3477 br i1 %0, label %15, label %19 3478 347915: 3480 %16 = load i64, i64* %1, align 8 3481 %17 = bitcast <16 x i8> %2 to <2 x i64> 3482 %18 = insertelement <2 x i64> %17, i64 %16, i64 0 3483 br label %21 3484 348519: 3486 %20 = bitcast <16 x i8> %2 to <2 x i64> 3487 br label %21 3488 348921: 3490 %22 = phi <2 x i64> [ %18, %15 ], [ %20, %19 ] 3491 %23 = bitcast <2 x i64> %14 to <16 x i8> 3492 %24 = bitcast <2 x i64> %22 to <16 x i8> 3493 %25 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %23, <16 x i8> %24) 3494 %26 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %25) 3495 store <16 x i8> %26, <16 x i8>* %3, align 8 3496 ret void 3497} 3498 3499define arm_aapcs_vfpcc void @aesd_set64_cond_via_val(i1 zeroext %0, i64 %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 3500; CHECK-FIX-LABEL: aesd_set64_cond_via_val: 3501; CHECK-FIX: @ %bb.0: 3502; CHECK-FIX-NEXT: vorr q0, q0, q0 3503; CHECK-FIX-NEXT: ldr r1, [sp] 3504; CHECK-FIX-NEXT: cmp r0, #0 3505; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r1] 3506; CHECK-FIX-NEXT: beq .LBB77_2 3507; CHECK-FIX-NEXT: @ %bb.1: 3508; CHECK-FIX-NEXT: vmov.32 d16[0], r2 3509; CHECK-FIX-NEXT: vmov.32 d16[1], r3 3510; CHECK-FIX-NEXT: .LBB77_2: @ %select.end 3511; CHECK-FIX-NEXT: cmp r0, #0 3512; CHECK-FIX-NEXT: beq .LBB77_4 3513; CHECK-FIX-NEXT: @ %bb.3: 3514; CHECK-FIX-NEXT: vmov.32 d0[0], r2 3515; CHECK-FIX-NEXT: vmov.32 d0[1], r3 3516; CHECK-FIX-NEXT: .LBB77_4: @ %select.end1 3517; CHECK-FIX-NEXT: aesd.8 q8, q0 3518; CHECK-FIX-NEXT: aesimc.8 q8, q8 3519; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r1] 3520; CHECK-FIX-NEXT: bx lr 3521 %5 = bitcast <16 x i8>* %3 to <2 x i64>* 3522 %6 = load <2 x i64>, <2 x i64>* %5, align 8 3523 %7 = insertelement <2 x i64> %6, i64 %1, i64 0 3524 %8 = select i1 %0, <2 x i64> %7, <2 x i64> %6 3525 %9 = bitcast <16 x i8> %2 to <2 x i64> 3526 %10 = insertelement <2 x i64> %9, i64 %1, i64 0 3527 %11 = select i1 %0, <2 x i64> %10, <2 x i64> %9 3528 %12 = bitcast <2 x i64> %8 to <16 x i8> 3529 %13 = bitcast <2 x i64> %11 to <16 x i8> 3530 %14 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %12, <16 x i8> %13) 3531 %15 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %14) 3532 store <16 x i8> %15, <16 x i8>* %3, align 8 3533 ret void 3534} 3535 3536define arm_aapcs_vfpcc void @aesd_set64_loop_via_ptr(i32 %0, i64* %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 3537; CHECK-FIX-NOSCHED-LABEL: aesd_set64_loop_via_ptr: 3538; CHECK-FIX-NOSCHED: @ %bb.0: 3539; CHECK-FIX-NOSCHED-NEXT: vorr q0, q0, q0 3540; CHECK-FIX-NOSCHED-NEXT: .save {r4, r5, r11, lr} 3541; CHECK-FIX-NOSCHED-NEXT: push {r4, r5, r11, lr} 3542; CHECK-FIX-NOSCHED-NEXT: ldrd r4, r5, [r1] 3543; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 3544; CHECK-FIX-NOSCHED-NEXT: strd r4, r5, [r2] 3545; CHECK-FIX-NOSCHED-NEXT: beq .LBB78_4 3546; CHECK-FIX-NOSCHED-NEXT: @ %bb.1: 3547; CHECK-FIX-NOSCHED-NEXT: vmov d0, r4, r5 3548; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r2] 3549; CHECK-FIX-NOSCHED-NEXT: .LBB78_2: @ =>This Inner Loop Header: Depth=1 3550; CHECK-FIX-NOSCHED-NEXT: aesd.8 q8, q0 3551; CHECK-FIX-NOSCHED-NEXT: subs r0, r0, #1 3552; CHECK-FIX-NOSCHED-NEXT: aesimc.8 q8, q8 3553; CHECK-FIX-NOSCHED-NEXT: bne .LBB78_2 3554; CHECK-FIX-NOSCHED-NEXT: @ %bb.3: 3555; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r2] 3556; CHECK-FIX-NOSCHED-NEXT: .LBB78_4: 3557; CHECK-FIX-NOSCHED-NEXT: pop {r4, r5, r11, pc} 3558; 3559; CHECK-CORTEX-FIX-LABEL: aesd_set64_loop_via_ptr: 3560; CHECK-CORTEX-FIX: @ %bb.0: 3561; CHECK-CORTEX-FIX-NEXT: vorr q0, q0, q0 3562; CHECK-CORTEX-FIX-NEXT: .save {r4, r5, r11, lr} 3563; CHECK-CORTEX-FIX-NEXT: push {r4, r5, r11, lr} 3564; CHECK-CORTEX-FIX-NEXT: ldrd r4, r5, [r1] 3565; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 3566; CHECK-CORTEX-FIX-NEXT: strd r4, r5, [r2] 3567; CHECK-CORTEX-FIX-NEXT: popeq {r4, r5, r11, pc} 3568; CHECK-CORTEX-FIX-NEXT: .LBB78_1: 3569; CHECK-CORTEX-FIX-NEXT: vmov d0, r4, r5 3570; CHECK-CORTEX-FIX-NEXT: vld1.64 {d16, d17}, [r2] 3571; CHECK-CORTEX-FIX-NEXT: .LBB78_2: @ =>This Inner Loop Header: Depth=1 3572; CHECK-CORTEX-FIX-NEXT: aesd.8 q8, q0 3573; CHECK-CORTEX-FIX-NEXT: subs r0, r0, #1 3574; CHECK-CORTEX-FIX-NEXT: aesimc.8 q8, q8 3575; CHECK-CORTEX-FIX-NEXT: bne .LBB78_2 3576; CHECK-CORTEX-FIX-NEXT: @ %bb.3: 3577; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r2] 3578; CHECK-CORTEX-FIX-NEXT: pop {r4, r5, r11, pc} 3579 %5 = load i64, i64* %1, align 8 3580 %6 = bitcast <16 x i8> %2 to <2 x i64> 3581 %7 = insertelement <2 x i64> %6, i64 %5, i64 0 3582 %8 = bitcast <2 x i64> %7 to <16 x i8> 3583 %9 = bitcast <16 x i8>* %3 to i64* 3584 store i64 %5, i64* %9, align 8 3585 %10 = icmp eq i32 %0, 0 3586 br i1 %10, label %14, label %11 3587 358811: 3589 %12 = load <16 x i8>, <16 x i8>* %3, align 8 3590 br label %15 3591 359213: 3593 store <16 x i8> %19, <16 x i8>* %3, align 8 3594 br label %14 3595 359614: 3597 ret void 3598 359915: 3600 %16 = phi <16 x i8> [ %12, %11 ], [ %19, %15 ] 3601 %17 = phi i32 [ 0, %11 ], [ %20, %15 ] 3602 %18 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %16, <16 x i8> %8) 3603 %19 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %18) 3604 %20 = add nuw i32 %17, 1 3605 %21 = icmp eq i32 %20, %0 3606 br i1 %21, label %13, label %15 3607} 3608 3609define arm_aapcs_vfpcc void @aesd_set64_loop_via_val(i32 %0, i64 %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 3610; CHECK-FIX-LABEL: aesd_set64_loop_via_val: 3611; CHECK-FIX: @ %bb.0: 3612; CHECK-FIX-NEXT: vorr q0, q0, q0 3613; CHECK-FIX-NEXT: cmp r0, #0 3614; CHECK-FIX-NEXT: bxeq lr 3615; CHECK-FIX-NEXT: .LBB79_1: 3616; CHECK-FIX-NEXT: vmov.32 d0[0], r2 3617; CHECK-FIX-NEXT: ldr r1, [sp] 3618; CHECK-FIX-NEXT: vmov.32 d0[1], r3 3619; CHECK-FIX-NEXT: .LBB79_2: @ =>This Inner Loop Header: Depth=1 3620; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r1] 3621; CHECK-FIX-NEXT: subs r0, r0, #1 3622; CHECK-FIX-NEXT: vmov.32 d16[0], r2 3623; CHECK-FIX-NEXT: vmov.32 d16[1], r3 3624; CHECK-FIX-NEXT: aesd.8 q8, q0 3625; CHECK-FIX-NEXT: aesimc.8 q8, q8 3626; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r1] 3627; CHECK-FIX-NEXT: bne .LBB79_2 3628; CHECK-FIX-NEXT: @ %bb.3: 3629; CHECK-FIX-NEXT: bx lr 3630 %5 = icmp eq i32 %0, 0 3631 br i1 %5, label %12, label %6 3632 36336: 3634 %7 = bitcast <16 x i8> %2 to <2 x i64> 3635 %8 = insertelement <2 x i64> %7, i64 %1, i64 0 3636 %9 = bitcast <2 x i64> %8 to <16 x i8> 3637 %10 = bitcast <16 x i8>* %3 to <2 x i64>* 3638 %11 = bitcast <16 x i8>* %3 to i64* 3639 br label %13 3640 364112: 3642 ret void 3643 364413: 3645 %14 = phi i32 [ 0, %6 ], [ %20, %13 ] 3646 %15 = load <2 x i64>, <2 x i64>* %10, align 8 3647 %16 = insertelement <2 x i64> %15, i64 %1, i64 0 3648 %17 = bitcast <2 x i64> %16 to <16 x i8> 3649 store i64 %1, i64* %11, align 8 3650 %18 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %17, <16 x i8> %9) 3651 %19 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %18) 3652 store <16 x i8> %19, <16 x i8>* %3, align 8 3653 %20 = add nuw i32 %14, 1 3654 %21 = icmp eq i32 %20, %0 3655 br i1 %21, label %12, label %13 3656} 3657 3658define arm_aapcs_vfpcc void @aesd_setf16_via_ptr(half* %0, <16 x i8> %1, <16 x i8>* %2) nounwind { 3659; CHECK-FIX-NOSCHED-LABEL: aesd_setf16_via_ptr: 3660; CHECK-FIX-NOSCHED: @ %bb.0: 3661; CHECK-FIX-NOSCHED-NEXT: vorr q0, q0, q0 3662; CHECK-FIX-NOSCHED-NEXT: ldrh r0, [r0] 3663; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r1] 3664; CHECK-FIX-NOSCHED-NEXT: vmov.16 d0[0], r0 3665; CHECK-FIX-NOSCHED-NEXT: vmov.16 d16[0], r0 3666; CHECK-FIX-NOSCHED-NEXT: aesd.8 q8, q0 3667; CHECK-FIX-NOSCHED-NEXT: aesimc.8 q8, q8 3668; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r1] 3669; CHECK-FIX-NOSCHED-NEXT: bx lr 3670; 3671; CHECK-CORTEX-FIX-LABEL: aesd_setf16_via_ptr: 3672; CHECK-CORTEX-FIX: @ %bb.0: 3673; CHECK-CORTEX-FIX-NEXT: vorr q0, q0, q0 3674; CHECK-CORTEX-FIX-NEXT: vld1.64 {d16, d17}, [r1] 3675; CHECK-CORTEX-FIX-NEXT: ldrh r0, [r0] 3676; CHECK-CORTEX-FIX-NEXT: vmov.16 d0[0], r0 3677; CHECK-CORTEX-FIX-NEXT: vmov.16 d16[0], r0 3678; CHECK-CORTEX-FIX-NEXT: aesd.8 q8, q0 3679; CHECK-CORTEX-FIX-NEXT: aesimc.8 q8, q8 3680; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r1] 3681; CHECK-CORTEX-FIX-NEXT: bx lr 3682 %4 = bitcast half* %0 to i16* 3683 %5 = load i16, i16* %4, align 2 3684 %6 = bitcast <16 x i8>* %2 to <8 x i16>* 3685 %7 = load <8 x i16>, <8 x i16>* %6, align 8 3686 %8 = insertelement <8 x i16> %7, i16 %5, i64 0 3687 %9 = bitcast <8 x i16> %8 to <16 x i8> 3688 %10 = bitcast <16 x i8> %1 to <8 x i16> 3689 %11 = insertelement <8 x i16> %10, i16 %5, i64 0 3690 %12 = bitcast <8 x i16> %11 to <16 x i8> 3691 %13 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %9, <16 x i8> %12) 3692 %14 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %13) 3693 store <16 x i8> %14, <16 x i8>* %2, align 8 3694 ret void 3695} 3696 3697define arm_aapcs_vfpcc void @aesd_setf16_via_val(half %0, <16 x i8> %1, <16 x i8>* %2) nounwind { 3698; CHECK-FIX-LABEL: aesd_setf16_via_val: 3699; CHECK-FIX: @ %bb.0: 3700; CHECK-FIX-NEXT: vorr q1, q1, q1 3701; CHECK-FIX-NEXT: vmov r1, s0 3702; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r0] 3703; CHECK-FIX-NEXT: vmov.16 d2[0], r1 3704; CHECK-FIX-NEXT: vmov.16 d16[0], r1 3705; CHECK-FIX-NEXT: aesd.8 q8, q1 3706; CHECK-FIX-NEXT: aesimc.8 q8, q8 3707; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r0] 3708; CHECK-FIX-NEXT: bx lr 3709 %4 = bitcast <16 x i8>* %2 to <8 x i16>* 3710 %5 = load <8 x i16>, <8 x i16>* %4, align 8 3711 %6 = bitcast half %0 to i16 3712 %7 = insertelement <8 x i16> %5, i16 %6, i64 0 3713 %8 = bitcast <8 x i16> %7 to <16 x i8> 3714 %9 = bitcast <16 x i8> %1 to <8 x i16> 3715 %10 = insertelement <8 x i16> %9, i16 %6, i64 0 3716 %11 = bitcast <8 x i16> %10 to <16 x i8> 3717 %12 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %8, <16 x i8> %11) 3718 %13 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %12) 3719 store <16 x i8> %13, <16 x i8>* %2, align 8 3720 ret void 3721} 3722 3723define arm_aapcs_vfpcc void @aesd_setf16_cond_via_ptr(i1 zeroext %0, half* %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 3724; CHECK-FIX-NOSCHED-LABEL: aesd_setf16_cond_via_ptr: 3725; CHECK-FIX-NOSCHED: @ %bb.0: 3726; CHECK-FIX-NOSCHED-NEXT: .save {r4, r5, r6, r7, r8, lr} 3727; CHECK-FIX-NOSCHED-NEXT: push {r4, r5, r6, r7, r8, lr} 3728; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 3729; CHECK-FIX-NOSCHED-NEXT: beq .LBB82_2 3730; CHECK-FIX-NOSCHED-NEXT: @ %bb.1: 3731; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r2] 3732; CHECK-FIX-NOSCHED-NEXT: vld1.16 {d16[0]}, [r1:16] 3733; CHECK-FIX-NOSCHED-NEXT: vmov r3, r4, d17 3734; CHECK-FIX-NOSCHED-NEXT: vmov lr, r12, d16 3735; CHECK-FIX-NOSCHED-NEXT: vmov s6, r3 3736; CHECK-FIX-NOSCHED-NEXT: lsr r3, r3, #16 3737; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s8, s6 3738; CHECK-FIX-NOSCHED-NEXT: vmov s4, r4 3739; CHECK-FIX-NOSCHED-NEXT: lsr r4, r4, #16 3740; CHECK-FIX-NOSCHED-NEXT: vmov s10, r3 3741; CHECK-FIX-NOSCHED-NEXT: vmov s6, r12 3742; CHECK-FIX-NOSCHED-NEXT: lsr r12, r12, #16 3743; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s12, s6 3744; CHECK-FIX-NOSCHED-NEXT: vmov s6, lr 3745; CHECK-FIX-NOSCHED-NEXT: lsr lr, lr, #16 3746; CHECK-FIX-NOSCHED-NEXT: vmov s14, r12 3747; CHECK-FIX-NOSCHED-NEXT: vmov s7, lr 3748; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s5, s6 3749; CHECK-FIX-NOSCHED-NEXT: vmov s6, r4 3750; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s4, s4 3751; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s6, s6 3752; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s10, s10 3753; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s14, s14 3754; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s7, s7 3755; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 3756; CHECK-FIX-NOSCHED-NEXT: bne .LBB82_3 3757; CHECK-FIX-NOSCHED-NEXT: b .LBB82_4 3758; CHECK-FIX-NOSCHED-NEXT: .LBB82_2: 3759; CHECK-FIX-NOSCHED-NEXT: ldrh r4, [r2, #10] 3760; CHECK-FIX-NOSCHED-NEXT: ldrh lr, [r2, #6] 3761; CHECK-FIX-NOSCHED-NEXT: ldrh r6, [r2, #2] 3762; CHECK-FIX-NOSCHED-NEXT: ldrh r7, [r2, #14] 3763; CHECK-FIX-NOSCHED-NEXT: vmov s8, r4 3764; CHECK-FIX-NOSCHED-NEXT: ldrh r3, [r2, #12] 3765; CHECK-FIX-NOSCHED-NEXT: vmov s12, lr 3766; CHECK-FIX-NOSCHED-NEXT: ldrh r12, [r2, #8] 3767; CHECK-FIX-NOSCHED-NEXT: vmov s5, r6 3768; CHECK-FIX-NOSCHED-NEXT: ldrh r5, [r2, #4] 3769; CHECK-FIX-NOSCHED-NEXT: vmov s4, r7 3770; CHECK-FIX-NOSCHED-NEXT: ldrh r8, [r2] 3771; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s6, s4 3772; CHECK-FIX-NOSCHED-NEXT: vmov s4, r3 3773; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s10, s8 3774; CHECK-FIX-NOSCHED-NEXT: vmov s8, r12 3775; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s14, s12 3776; CHECK-FIX-NOSCHED-NEXT: vmov s12, r5 3777; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s7, s5 3778; CHECK-FIX-NOSCHED-NEXT: vmov s5, r8 3779; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s4, s4 3780; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s8, s8 3781; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s12, s12 3782; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s5, s5 3783; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 3784; CHECK-FIX-NOSCHED-NEXT: beq .LBB82_4 3785; CHECK-FIX-NOSCHED-NEXT: .LBB82_3: 3786; CHECK-FIX-NOSCHED-NEXT: vld1.16 {d0[0]}, [r1:16] 3787; CHECK-FIX-NOSCHED-NEXT: .LBB82_4: 3788; CHECK-FIX-NOSCHED-NEXT: vmov r0, r1, d0 3789; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s5, s5 3790; CHECK-FIX-NOSCHED-NEXT: vmov r3, r7, d1 3791; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s12, s12 3792; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s8, s8 3793; CHECK-FIX-NOSCHED-NEXT: vmov s1, r1 3794; CHECK-FIX-NOSCHED-NEXT: lsr r1, r1, #16 3795; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s9, s1 3796; CHECK-FIX-NOSCHED-NEXT: vmov s1, r0 3797; CHECK-FIX-NOSCHED-NEXT: lsr r0, r0, #16 3798; CHECK-FIX-NOSCHED-NEXT: vmov s13, r1 3799; CHECK-FIX-NOSCHED-NEXT: vmov s15, r0 3800; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s11, s1 3801; CHECK-FIX-NOSCHED-NEXT: vmov r0, s5 3802; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s5, s7 3803; CHECK-FIX-NOSCHED-NEXT: vmov r1, s5 3804; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s15, s15 3805; CHECK-FIX-NOSCHED-NEXT: vmov s2, r3 3806; CHECK-FIX-NOSCHED-NEXT: lsr r3, r3, #16 3807; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s5, s15 3808; CHECK-FIX-NOSCHED-NEXT: vmov s3, r3 3809; CHECK-FIX-NOSCHED-NEXT: vmov r3, s5 3810; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s11, s11 3811; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s13, s13 3812; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s5, s9 3813; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s2, s2 3814; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s3, s3 3815; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s2, s2 3816; CHECK-FIX-NOSCHED-NEXT: vmov s0, r7 3817; CHECK-FIX-NOSCHED-NEXT: lsr r7, r7, #16 3818; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s0, s0 3819; CHECK-FIX-NOSCHED-NEXT: vmov s1, r7 3820; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s0, s0 3821; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s1, s1 3822; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r0, r1, lsl #16 3823; CHECK-FIX-NOSCHED-NEXT: vmov r1, s11 3824; CHECK-FIX-NOSCHED-NEXT: vmov.32 d16[0], r0 3825; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r1, r3, lsl #16 3826; CHECK-FIX-NOSCHED-NEXT: vmov r1, s12 3827; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s12, s14 3828; CHECK-FIX-NOSCHED-NEXT: vmov.32 d18[0], r0 3829; CHECK-FIX-NOSCHED-NEXT: vmov r0, s12 3830; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s12, s13 3831; CHECK-FIX-NOSCHED-NEXT: vmov r3, s12 3832; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r1, r0, lsl #16 3833; CHECK-FIX-NOSCHED-NEXT: vmov r1, s5 3834; CHECK-FIX-NOSCHED-NEXT: vmov.32 d16[1], r0 3835; CHECK-FIX-NOSCHED-NEXT: pkhbt r1, r1, r3, lsl #16 3836; CHECK-FIX-NOSCHED-NEXT: vmov.32 d18[1], r1 3837; CHECK-FIX-NOSCHED-NEXT: vmov r1, s8 3838; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s8, s10 3839; CHECK-FIX-NOSCHED-NEXT: vmov r3, s8 3840; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r1, r3, lsl #16 3841; CHECK-FIX-NOSCHED-NEXT: vmov r1, s2 3842; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s2, s3 3843; CHECK-FIX-NOSCHED-NEXT: vmov r3, s2 3844; CHECK-FIX-NOSCHED-NEXT: vmov.32 d17[0], r0 3845; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s2, s4 3846; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r1, r3, lsl #16 3847; CHECK-FIX-NOSCHED-NEXT: vmov r1, s0 3848; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s0, s1 3849; CHECK-FIX-NOSCHED-NEXT: vmov.32 d19[0], r0 3850; CHECK-FIX-NOSCHED-NEXT: vmov r0, s0 3851; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s0, s6 3852; CHECK-FIX-NOSCHED-NEXT: vmov r3, s0 3853; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r1, r0, lsl #16 3854; CHECK-FIX-NOSCHED-NEXT: vmov r1, s2 3855; CHECK-FIX-NOSCHED-NEXT: vmov.32 d19[1], r0 3856; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r1, r3, lsl #16 3857; CHECK-FIX-NOSCHED-NEXT: vmov.32 d17[1], r0 3858; CHECK-FIX-NOSCHED-NEXT: aesd.8 q8, q9 3859; CHECK-FIX-NOSCHED-NEXT: aesimc.8 q8, q8 3860; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r2] 3861; CHECK-FIX-NOSCHED-NEXT: pop {r4, r5, r6, r7, r8, pc} 3862; 3863; CHECK-CORTEX-FIX-LABEL: aesd_setf16_cond_via_ptr: 3864; CHECK-CORTEX-FIX: @ %bb.0: 3865; CHECK-CORTEX-FIX-NEXT: .save {r4, r5, r6, r7, r8, lr} 3866; CHECK-CORTEX-FIX-NEXT: push {r4, r5, r6, r7, r8, lr} 3867; CHECK-CORTEX-FIX-NEXT: .vsave {d8} 3868; CHECK-CORTEX-FIX-NEXT: vpush {d8} 3869; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 3870; CHECK-CORTEX-FIX-NEXT: beq .LBB82_2 3871; CHECK-CORTEX-FIX-NEXT: @ %bb.1: 3872; CHECK-CORTEX-FIX-NEXT: vld1.64 {d16, d17}, [r2] 3873; CHECK-CORTEX-FIX-NEXT: vld1.16 {d16[0]}, [r1:16] 3874; CHECK-CORTEX-FIX-NEXT: vmov r5, r6, d17 3875; CHECK-CORTEX-FIX-NEXT: lsr r7, r5, #16 3876; CHECK-CORTEX-FIX-NEXT: lsr r4, r6, #16 3877; CHECK-CORTEX-FIX-NEXT: vmov s4, r6 3878; CHECK-CORTEX-FIX-NEXT: vmov s6, r5 3879; CHECK-CORTEX-FIX-NEXT: vmov s14, r4 3880; CHECK-CORTEX-FIX-NEXT: vmov s7, r7 3881; CHECK-CORTEX-FIX-NEXT: vmov r12, r3, d16 3882; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s12, s4 3883; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s4, s6 3884; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s14, s14 3885; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s6, s7 3886; CHECK-CORTEX-FIX-NEXT: lsr lr, r12, #16 3887; CHECK-CORTEX-FIX-NEXT: lsr r8, r3, #16 3888; CHECK-CORTEX-FIX-NEXT: vmov s8, r3 3889; CHECK-CORTEX-FIX-NEXT: vmov s10, r12 3890; CHECK-CORTEX-FIX-NEXT: vmov s9, r8 3891; CHECK-CORTEX-FIX-NEXT: vmov s11, lr 3892; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s5, s8 3893; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s8, s10 3894; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s7, s9 3895; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s10, s11 3896; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 3897; CHECK-CORTEX-FIX-NEXT: bne .LBB82_3 3898; CHECK-CORTEX-FIX-NEXT: b .LBB82_4 3899; CHECK-CORTEX-FIX-NEXT: .LBB82_2: 3900; CHECK-CORTEX-FIX-NEXT: ldrh r12, [r2] 3901; CHECK-CORTEX-FIX-NEXT: ldrh lr, [r2, #2] 3902; CHECK-CORTEX-FIX-NEXT: ldrh r8, [r2, #4] 3903; CHECK-CORTEX-FIX-NEXT: ldrh r5, [r2, #6] 3904; CHECK-CORTEX-FIX-NEXT: ldrh r4, [r2, #8] 3905; CHECK-CORTEX-FIX-NEXT: ldrh r3, [r2, #10] 3906; CHECK-CORTEX-FIX-NEXT: ldrh r7, [r2, #12] 3907; CHECK-CORTEX-FIX-NEXT: ldrh r6, [r2, #14] 3908; CHECK-CORTEX-FIX-NEXT: vmov s4, r6 3909; CHECK-CORTEX-FIX-NEXT: vmov s6, r7 3910; CHECK-CORTEX-FIX-NEXT: vmov s5, r5 3911; CHECK-CORTEX-FIX-NEXT: vmov s8, r3 3912; CHECK-CORTEX-FIX-NEXT: vmov s10, r4 3913; CHECK-CORTEX-FIX-NEXT: vmov s9, r8 3914; CHECK-CORTEX-FIX-NEXT: vmov s11, lr 3915; CHECK-CORTEX-FIX-NEXT: vmov s13, r12 3916; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s14, s4 3917; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s12, s6 3918; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s6, s8 3919; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s4, s10 3920; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s7, s5 3921; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s5, s9 3922; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s10, s11 3923; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s8, s13 3924; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 3925; CHECK-CORTEX-FIX-NEXT: beq .LBB82_4 3926; CHECK-CORTEX-FIX-NEXT: .LBB82_3: 3927; CHECK-CORTEX-FIX-NEXT: vld1.16 {d0[0]}, [r1:16] 3928; CHECK-CORTEX-FIX-NEXT: .LBB82_4: 3929; CHECK-CORTEX-FIX-NEXT: vmov r6, r5, d1 3930; CHECK-CORTEX-FIX-NEXT: vmov r0, r1, d0 3931; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s12, s12 3932; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s14, s14 3933; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s5, s5 3934; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s4, s4 3935; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s6, s6 3936; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s8, s8 3937; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s10, s10 3938; CHECK-CORTEX-FIX-NEXT: lsr r3, r5, #16 3939; CHECK-CORTEX-FIX-NEXT: vmov s0, r5 3940; CHECK-CORTEX-FIX-NEXT: lsr r7, r1, #16 3941; CHECK-CORTEX-FIX-NEXT: lsr r4, r6, #16 3942; CHECK-CORTEX-FIX-NEXT: vmov s1, r1 3943; CHECK-CORTEX-FIX-NEXT: lsr r12, r0, #16 3944; CHECK-CORTEX-FIX-NEXT: vmov s9, r0 3945; CHECK-CORTEX-FIX-NEXT: vmov r0, s12 3946; CHECK-CORTEX-FIX-NEXT: vmov r1, s14 3947; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s12, s7 3948; CHECK-CORTEX-FIX-NEXT: vmov s2, r6 3949; CHECK-CORTEX-FIX-NEXT: vmov r5, s6 3950; CHECK-CORTEX-FIX-NEXT: vmov s13, r3 3951; CHECK-CORTEX-FIX-NEXT: vmov s15, r4 3952; CHECK-CORTEX-FIX-NEXT: vmov s16, r7 3953; CHECK-CORTEX-FIX-NEXT: vmov r4, s10 3954; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s3, s0 3955; CHECK-CORTEX-FIX-NEXT: vmov s0, r12 3956; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s11, s1 3957; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s1, s9 3958; CHECK-CORTEX-FIX-NEXT: pkhbt r12, r0, r1, lsl #16 3959; CHECK-CORTEX-FIX-NEXT: vmov r1, s5 3960; CHECK-CORTEX-FIX-NEXT: vmov r3, s12 3961; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s2, s2 3962; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s13, s13 3963; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s9, s15 3964; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s15, s16 3965; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s14, s3 3966; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s7, s11 3967; CHECK-CORTEX-FIX-NEXT: pkhbt lr, r1, r3, lsl #16 3968; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s0, s0 3969; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s2, s2 3970; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s1, s1 3971; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s3, s13 3972; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s11, s15 3973; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s9, s9 3974; CHECK-CORTEX-FIX-NEXT: vmov r3, s14 3975; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s0, s0 3976; CHECK-CORTEX-FIX-NEXT: vmov r7, s3 3977; CHECK-CORTEX-FIX-NEXT: vmov r6, s11 3978; CHECK-CORTEX-FIX-NEXT: vmov r0, s9 3979; CHECK-CORTEX-FIX-NEXT: vmov r1, s0 3980; CHECK-CORTEX-FIX-NEXT: pkhbt r3, r3, r7, lsl #16 3981; CHECK-CORTEX-FIX-NEXT: vmov r7, s7 3982; CHECK-CORTEX-FIX-NEXT: pkhbt r7, r7, r6, lsl #16 3983; CHECK-CORTEX-FIX-NEXT: vmov r6, s4 3984; CHECK-CORTEX-FIX-NEXT: pkhbt r6, r6, r5, lsl #16 3985; CHECK-CORTEX-FIX-NEXT: vmov r5, s8 3986; CHECK-CORTEX-FIX-NEXT: pkhbt r5, r5, r4, lsl #16 3987; CHECK-CORTEX-FIX-NEXT: vmov r4, s2 3988; CHECK-CORTEX-FIX-NEXT: vmov.32 d18[0], r5 3989; CHECK-CORTEX-FIX-NEXT: vmov.32 d19[0], r6 3990; CHECK-CORTEX-FIX-NEXT: vmov.32 d18[1], lr 3991; CHECK-CORTEX-FIX-NEXT: vmov.32 d19[1], r12 3992; CHECK-CORTEX-FIX-NEXT: pkhbt r0, r4, r0, lsl #16 3993; CHECK-CORTEX-FIX-NEXT: vmov r4, s1 3994; CHECK-CORTEX-FIX-NEXT: pkhbt r1, r4, r1, lsl #16 3995; CHECK-CORTEX-FIX-NEXT: vmov.32 d16[0], r1 3996; CHECK-CORTEX-FIX-NEXT: vmov.32 d17[0], r0 3997; CHECK-CORTEX-FIX-NEXT: vmov.32 d16[1], r7 3998; CHECK-CORTEX-FIX-NEXT: vmov.32 d17[1], r3 3999; CHECK-CORTEX-FIX-NEXT: aesd.8 q9, q8 4000; CHECK-CORTEX-FIX-NEXT: aesimc.8 q8, q9 4001; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r2] 4002; CHECK-CORTEX-FIX-NEXT: vpop {d8} 4003; CHECK-CORTEX-FIX-NEXT: pop {r4, r5, r6, r7, r8, pc} 4004 br i1 %0, label %5, label %12 4005 40065: 4007 %6 = bitcast half* %1 to i16* 4008 %7 = load i16, i16* %6, align 2 4009 %8 = bitcast <16 x i8>* %3 to <8 x i16>* 4010 %9 = load <8 x i16>, <8 x i16>* %8, align 8 4011 %10 = insertelement <8 x i16> %9, i16 %7, i64 0 4012 %11 = bitcast <8 x i16> %10 to <8 x half> 4013 br label %15 4014 401512: 4016 %13 = bitcast <16 x i8>* %3 to <8 x half>* 4017 %14 = load <8 x half>, <8 x half>* %13, align 8 4018 br label %15 4019 402015: 4021 %16 = phi <8 x half> [ %11, %5 ], [ %14, %12 ] 4022 br i1 %0, label %17, label %23 4023 402417: 4025 %18 = bitcast half* %1 to i16* 4026 %19 = load i16, i16* %18, align 2 4027 %20 = bitcast <16 x i8> %2 to <8 x i16> 4028 %21 = insertelement <8 x i16> %20, i16 %19, i64 0 4029 %22 = bitcast <8 x i16> %21 to <8 x half> 4030 br label %25 4031 403223: 4033 %24 = bitcast <16 x i8> %2 to <8 x half> 4034 br label %25 4035 403625: 4037 %26 = phi <8 x half> [ %22, %17 ], [ %24, %23 ] 4038 %27 = bitcast <8 x half> %16 to <16 x i8> 4039 %28 = bitcast <8 x half> %26 to <16 x i8> 4040 %29 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %27, <16 x i8> %28) 4041 %30 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %29) 4042 store <16 x i8> %30, <16 x i8>* %3, align 8 4043 ret void 4044} 4045 4046define arm_aapcs_vfpcc void @aesd_setf16_cond_via_val(i1 zeroext %0, half %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 4047; CHECK-FIX-NOSCHED-LABEL: aesd_setf16_cond_via_val: 4048; CHECK-FIX-NOSCHED: @ %bb.0: 4049; CHECK-FIX-NOSCHED-NEXT: .save {r4, r5, r6, r7, r11, lr} 4050; CHECK-FIX-NOSCHED-NEXT: push {r4, r5, r6, r7, r11, lr} 4051; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s9, s0 4052; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 4053; CHECK-FIX-NOSCHED-NEXT: beq .LBB83_2 4054; CHECK-FIX-NOSCHED-NEXT: @ %bb.1: 4055; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s0, s9 4056; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r1] 4057; CHECK-FIX-NOSCHED-NEXT: vmov r2, s0 4058; CHECK-FIX-NOSCHED-NEXT: vmov.16 d16[0], r2 4059; CHECK-FIX-NOSCHED-NEXT: vmov r3, lr, d17 4060; CHECK-FIX-NOSCHED-NEXT: vmov r2, r12, d16 4061; CHECK-FIX-NOSCHED-NEXT: vmov s2, r3 4062; CHECK-FIX-NOSCHED-NEXT: lsr r3, r3, #16 4063; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s8, s2 4064; CHECK-FIX-NOSCHED-NEXT: lsr r4, lr, #16 4065; CHECK-FIX-NOSCHED-NEXT: vmov s0, lr 4066; CHECK-FIX-NOSCHED-NEXT: vmov s2, r12 4067; CHECK-FIX-NOSCHED-NEXT: lsr r5, r2, #16 4068; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s12, s2 4069; CHECK-FIX-NOSCHED-NEXT: vmov s2, r2 4070; CHECK-FIX-NOSCHED-NEXT: lsr r2, r12, #16 4071; CHECK-FIX-NOSCHED-NEXT: vmov s10, r3 4072; CHECK-FIX-NOSCHED-NEXT: vmov s14, r2 4073; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s1, s2 4074; CHECK-FIX-NOSCHED-NEXT: vmov s2, r4 4075; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s0, s0 4076; CHECK-FIX-NOSCHED-NEXT: vmov s3, r5 4077; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s2, s2 4078; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s10, s10 4079; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s14, s14 4080; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s3, s3 4081; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 4082; CHECK-FIX-NOSCHED-NEXT: bne .LBB83_3 4083; CHECK-FIX-NOSCHED-NEXT: b .LBB83_4 4084; CHECK-FIX-NOSCHED-NEXT: .LBB83_2: 4085; CHECK-FIX-NOSCHED-NEXT: ldrh r3, [r1, #10] 4086; CHECK-FIX-NOSCHED-NEXT: ldrh r4, [r1, #6] 4087; CHECK-FIX-NOSCHED-NEXT: ldrh lr, [r1, #2] 4088; CHECK-FIX-NOSCHED-NEXT: ldrh r7, [r1, #14] 4089; CHECK-FIX-NOSCHED-NEXT: vmov s8, r3 4090; CHECK-FIX-NOSCHED-NEXT: ldrh r2, [r1, #12] 4091; CHECK-FIX-NOSCHED-NEXT: vmov s12, r4 4092; CHECK-FIX-NOSCHED-NEXT: ldrh r5, [r1, #8] 4093; CHECK-FIX-NOSCHED-NEXT: vmov s1, lr 4094; CHECK-FIX-NOSCHED-NEXT: ldrh r12, [r1, #4] 4095; CHECK-FIX-NOSCHED-NEXT: vmov s0, r7 4096; CHECK-FIX-NOSCHED-NEXT: ldrh r6, [r1] 4097; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s2, s0 4098; CHECK-FIX-NOSCHED-NEXT: vmov s0, r2 4099; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s10, s8 4100; CHECK-FIX-NOSCHED-NEXT: vmov s8, r5 4101; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s14, s12 4102; CHECK-FIX-NOSCHED-NEXT: vmov s12, r12 4103; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s3, s1 4104; CHECK-FIX-NOSCHED-NEXT: vmov s1, r6 4105; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s0, s0 4106; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s8, s8 4107; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s12, s12 4108; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s1, s1 4109; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 4110; CHECK-FIX-NOSCHED-NEXT: beq .LBB83_4 4111; CHECK-FIX-NOSCHED-NEXT: .LBB83_3: 4112; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s9, s9 4113; CHECK-FIX-NOSCHED-NEXT: vmov r0, s9 4114; CHECK-FIX-NOSCHED-NEXT: vmov.16 d2[0], r0 4115; CHECK-FIX-NOSCHED-NEXT: .LBB83_4: 4116; CHECK-FIX-NOSCHED-NEXT: vmov r0, r2, d2 4117; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s1, s1 4118; CHECK-FIX-NOSCHED-NEXT: vmov r3, r7, d3 4119; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s12, s12 4120; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s8, s8 4121; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s0, s0 4122; CHECK-FIX-NOSCHED-NEXT: vmov s5, r2 4123; CHECK-FIX-NOSCHED-NEXT: lsr r2, r2, #16 4124; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s9, s5 4125; CHECK-FIX-NOSCHED-NEXT: vmov s5, r0 4126; CHECK-FIX-NOSCHED-NEXT: lsr r0, r0, #16 4127; CHECK-FIX-NOSCHED-NEXT: vmov s13, r2 4128; CHECK-FIX-NOSCHED-NEXT: vmov s15, r0 4129; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s11, s5 4130; CHECK-FIX-NOSCHED-NEXT: vmov r0, s1 4131; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s1, s3 4132; CHECK-FIX-NOSCHED-NEXT: vmov r2, s1 4133; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s15, s15 4134; CHECK-FIX-NOSCHED-NEXT: vmov s6, r3 4135; CHECK-FIX-NOSCHED-NEXT: lsr r3, r3, #16 4136; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s1, s15 4137; CHECK-FIX-NOSCHED-NEXT: vmov s7, r3 4138; CHECK-FIX-NOSCHED-NEXT: vmov r3, s1 4139; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s11, s11 4140; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s13, s13 4141; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s1, s9 4142; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s6, s6 4143; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s7, s7 4144; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s6, s6 4145; CHECK-FIX-NOSCHED-NEXT: vmov s4, r7 4146; CHECK-FIX-NOSCHED-NEXT: lsr r7, r7, #16 4147; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s4, s4 4148; CHECK-FIX-NOSCHED-NEXT: vmov s5, r7 4149; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s4, s4 4150; CHECK-FIX-NOSCHED-NEXT: vcvtb.f32.f16 s5, s5 4151; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r0, r2, lsl #16 4152; CHECK-FIX-NOSCHED-NEXT: vmov r2, s11 4153; CHECK-FIX-NOSCHED-NEXT: vmov.32 d16[0], r0 4154; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r2, r3, lsl #16 4155; CHECK-FIX-NOSCHED-NEXT: vmov r2, s12 4156; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s12, s14 4157; CHECK-FIX-NOSCHED-NEXT: vmov.32 d18[0], r0 4158; CHECK-FIX-NOSCHED-NEXT: vmov r0, s12 4159; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s12, s13 4160; CHECK-FIX-NOSCHED-NEXT: vmov r3, s12 4161; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r2, r0, lsl #16 4162; CHECK-FIX-NOSCHED-NEXT: vmov r2, s1 4163; CHECK-FIX-NOSCHED-NEXT: vmov.32 d16[1], r0 4164; CHECK-FIX-NOSCHED-NEXT: pkhbt r2, r2, r3, lsl #16 4165; CHECK-FIX-NOSCHED-NEXT: vmov.32 d18[1], r2 4166; CHECK-FIX-NOSCHED-NEXT: vmov r2, s8 4167; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s8, s10 4168; CHECK-FIX-NOSCHED-NEXT: vmov r3, s8 4169; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r2, r3, lsl #16 4170; CHECK-FIX-NOSCHED-NEXT: vmov r2, s6 4171; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s6, s7 4172; CHECK-FIX-NOSCHED-NEXT: vmov r3, s6 4173; CHECK-FIX-NOSCHED-NEXT: vmov.32 d17[0], r0 4174; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r2, r3, lsl #16 4175; CHECK-FIX-NOSCHED-NEXT: vmov r2, s4 4176; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s4, s5 4177; CHECK-FIX-NOSCHED-NEXT: vmov.32 d19[0], r0 4178; CHECK-FIX-NOSCHED-NEXT: vmov r0, s4 4179; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r2, r0, lsl #16 4180; CHECK-FIX-NOSCHED-NEXT: vmov r2, s0 4181; CHECK-FIX-NOSCHED-NEXT: vcvtb.f16.f32 s0, s2 4182; CHECK-FIX-NOSCHED-NEXT: vmov r3, s0 4183; CHECK-FIX-NOSCHED-NEXT: vmov.32 d19[1], r0 4184; CHECK-FIX-NOSCHED-NEXT: pkhbt r0, r2, r3, lsl #16 4185; CHECK-FIX-NOSCHED-NEXT: vmov.32 d17[1], r0 4186; CHECK-FIX-NOSCHED-NEXT: aesd.8 q8, q9 4187; CHECK-FIX-NOSCHED-NEXT: aesimc.8 q8, q8 4188; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r1] 4189; CHECK-FIX-NOSCHED-NEXT: pop {r4, r5, r6, r7, r11, pc} 4190; 4191; CHECK-CORTEX-FIX-LABEL: aesd_setf16_cond_via_val: 4192; CHECK-CORTEX-FIX: @ %bb.0: 4193; CHECK-CORTEX-FIX-NEXT: .save {r4, r5, r6, r7, r11, lr} 4194; CHECK-CORTEX-FIX-NEXT: push {r4, r5, r6, r7, r11, lr} 4195; CHECK-CORTEX-FIX-NEXT: .vsave {d8} 4196; CHECK-CORTEX-FIX-NEXT: vpush {d8} 4197; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s9, s0 4198; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 4199; CHECK-CORTEX-FIX-NEXT: beq .LBB83_2 4200; CHECK-CORTEX-FIX-NEXT: @ %bb.1: 4201; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s0, s9 4202; CHECK-CORTEX-FIX-NEXT: vld1.64 {d16, d17}, [r1] 4203; CHECK-CORTEX-FIX-NEXT: vmov r2, s0 4204; CHECK-CORTEX-FIX-NEXT: vmov.16 d16[0], r2 4205; CHECK-CORTEX-FIX-NEXT: vmov r4, r5, d17 4206; CHECK-CORTEX-FIX-NEXT: lsr r6, r4, #16 4207; CHECK-CORTEX-FIX-NEXT: lsr r7, r5, #16 4208; CHECK-CORTEX-FIX-NEXT: vmov s0, r5 4209; CHECK-CORTEX-FIX-NEXT: vmov s2, r4 4210; CHECK-CORTEX-FIX-NEXT: vmov s14, r7 4211; CHECK-CORTEX-FIX-NEXT: vmov s3, r6 4212; CHECK-CORTEX-FIX-NEXT: vmov r2, r3, d16 4213; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s12, s0 4214; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s0, s2 4215; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s14, s14 4216; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s2, s3 4217; CHECK-CORTEX-FIX-NEXT: lsr r12, r2, #16 4218; CHECK-CORTEX-FIX-NEXT: lsr lr, r3, #16 4219; CHECK-CORTEX-FIX-NEXT: vmov s8, r3 4220; CHECK-CORTEX-FIX-NEXT: vmov s10, r2 4221; CHECK-CORTEX-FIX-NEXT: vmov s11, lr 4222; CHECK-CORTEX-FIX-NEXT: vmov s13, r12 4223; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s1, s8 4224; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s8, s10 4225; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s3, s11 4226; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s10, s13 4227; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 4228; CHECK-CORTEX-FIX-NEXT: bne .LBB83_3 4229; CHECK-CORTEX-FIX-NEXT: b .LBB83_4 4230; CHECK-CORTEX-FIX-NEXT: .LBB83_2: 4231; CHECK-CORTEX-FIX-NEXT: ldrh r12, [r1] 4232; CHECK-CORTEX-FIX-NEXT: ldrh lr, [r1, #2] 4233; CHECK-CORTEX-FIX-NEXT: ldrh r7, [r1, #4] 4234; CHECK-CORTEX-FIX-NEXT: ldrh r6, [r1, #6] 4235; CHECK-CORTEX-FIX-NEXT: ldrh r5, [r1, #8] 4236; CHECK-CORTEX-FIX-NEXT: ldrh r4, [r1, #10] 4237; CHECK-CORTEX-FIX-NEXT: ldrh r2, [r1, #12] 4238; CHECK-CORTEX-FIX-NEXT: ldrh r3, [r1, #14] 4239; CHECK-CORTEX-FIX-NEXT: vmov s0, r3 4240; CHECK-CORTEX-FIX-NEXT: vmov s2, r2 4241; CHECK-CORTEX-FIX-NEXT: vmov s1, r6 4242; CHECK-CORTEX-FIX-NEXT: vmov s8, r4 4243; CHECK-CORTEX-FIX-NEXT: vmov s10, r5 4244; CHECK-CORTEX-FIX-NEXT: vmov s11, r7 4245; CHECK-CORTEX-FIX-NEXT: vmov s13, lr 4246; CHECK-CORTEX-FIX-NEXT: vmov s15, r12 4247; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s14, s0 4248; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s12, s2 4249; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s2, s8 4250; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s0, s10 4251; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s3, s1 4252; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s1, s11 4253; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s10, s13 4254; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s8, s15 4255; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 4256; CHECK-CORTEX-FIX-NEXT: beq .LBB83_4 4257; CHECK-CORTEX-FIX-NEXT: .LBB83_3: 4258; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s9, s9 4259; CHECK-CORTEX-FIX-NEXT: vmov r0, s9 4260; CHECK-CORTEX-FIX-NEXT: vmov.16 d2[0], r0 4261; CHECK-CORTEX-FIX-NEXT: .LBB83_4: 4262; CHECK-CORTEX-FIX-NEXT: vmov r6, r5, d3 4263; CHECK-CORTEX-FIX-NEXT: vmov r0, r2, d2 4264; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s12, s12 4265; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s14, s14 4266; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s1, s1 4267; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s0, s0 4268; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s2, s2 4269; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s8, s8 4270; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s10, s10 4271; CHECK-CORTEX-FIX-NEXT: lsr r3, r5, #16 4272; CHECK-CORTEX-FIX-NEXT: vmov s4, r5 4273; CHECK-CORTEX-FIX-NEXT: lsr r7, r2, #16 4274; CHECK-CORTEX-FIX-NEXT: lsr r4, r6, #16 4275; CHECK-CORTEX-FIX-NEXT: vmov s5, r2 4276; CHECK-CORTEX-FIX-NEXT: lsr r12, r0, #16 4277; CHECK-CORTEX-FIX-NEXT: vmov s9, r0 4278; CHECK-CORTEX-FIX-NEXT: vmov r0, s12 4279; CHECK-CORTEX-FIX-NEXT: vmov r2, s14 4280; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s12, s3 4281; CHECK-CORTEX-FIX-NEXT: vmov s6, r6 4282; CHECK-CORTEX-FIX-NEXT: vmov r5, s2 4283; CHECK-CORTEX-FIX-NEXT: vmov s13, r3 4284; CHECK-CORTEX-FIX-NEXT: vmov s15, r4 4285; CHECK-CORTEX-FIX-NEXT: vmov s16, r7 4286; CHECK-CORTEX-FIX-NEXT: vmov r4, s10 4287; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s7, s4 4288; CHECK-CORTEX-FIX-NEXT: vmov s4, r12 4289; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s11, s5 4290; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s5, s9 4291; CHECK-CORTEX-FIX-NEXT: pkhbt r12, r0, r2, lsl #16 4292; CHECK-CORTEX-FIX-NEXT: vmov r2, s1 4293; CHECK-CORTEX-FIX-NEXT: vmov r3, s12 4294; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s6, s6 4295; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s13, s13 4296; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s9, s15 4297; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s15, s16 4298; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s14, s7 4299; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s7, s11 4300; CHECK-CORTEX-FIX-NEXT: pkhbt lr, r2, r3, lsl #16 4301; CHECK-CORTEX-FIX-NEXT: vcvtb.f32.f16 s4, s4 4302; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s6, s6 4303; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s5, s5 4304; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s3, s13 4305; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s11, s15 4306; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s9, s9 4307; CHECK-CORTEX-FIX-NEXT: vmov r3, s14 4308; CHECK-CORTEX-FIX-NEXT: vmov r7, s3 4309; CHECK-CORTEX-FIX-NEXT: vmov r6, s11 4310; CHECK-CORTEX-FIX-NEXT: vmov r0, s9 4311; CHECK-CORTEX-FIX-NEXT: pkhbt r3, r3, r7, lsl #16 4312; CHECK-CORTEX-FIX-NEXT: vmov r7, s7 4313; CHECK-CORTEX-FIX-NEXT: pkhbt r7, r7, r6, lsl #16 4314; CHECK-CORTEX-FIX-NEXT: vmov r6, s0 4315; CHECK-CORTEX-FIX-NEXT: vcvtb.f16.f32 s0, s4 4316; CHECK-CORTEX-FIX-NEXT: pkhbt r6, r6, r5, lsl #16 4317; CHECK-CORTEX-FIX-NEXT: vmov r5, s8 4318; CHECK-CORTEX-FIX-NEXT: vmov r2, s0 4319; CHECK-CORTEX-FIX-NEXT: pkhbt r5, r5, r4, lsl #16 4320; CHECK-CORTEX-FIX-NEXT: vmov r4, s6 4321; CHECK-CORTEX-FIX-NEXT: vmov.32 d18[0], r5 4322; CHECK-CORTEX-FIX-NEXT: vmov.32 d19[0], r6 4323; CHECK-CORTEX-FIX-NEXT: vmov.32 d18[1], lr 4324; CHECK-CORTEX-FIX-NEXT: vmov.32 d19[1], r12 4325; CHECK-CORTEX-FIX-NEXT: pkhbt r0, r4, r0, lsl #16 4326; CHECK-CORTEX-FIX-NEXT: vmov r4, s5 4327; CHECK-CORTEX-FIX-NEXT: pkhbt r2, r4, r2, lsl #16 4328; CHECK-CORTEX-FIX-NEXT: vmov.32 d16[0], r2 4329; CHECK-CORTEX-FIX-NEXT: vmov.32 d17[0], r0 4330; CHECK-CORTEX-FIX-NEXT: vmov.32 d16[1], r7 4331; CHECK-CORTEX-FIX-NEXT: vmov.32 d17[1], r3 4332; CHECK-CORTEX-FIX-NEXT: aesd.8 q9, q8 4333; CHECK-CORTEX-FIX-NEXT: aesimc.8 q8, q9 4334; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r1] 4335; CHECK-CORTEX-FIX-NEXT: vpop {d8} 4336; CHECK-CORTEX-FIX-NEXT: pop {r4, r5, r6, r7, r11, pc} 4337 br i1 %0, label %5, label %11 4338 43395: 4340 %6 = bitcast <16 x i8>* %3 to <8 x i16>* 4341 %7 = load <8 x i16>, <8 x i16>* %6, align 8 4342 %8 = bitcast half %1 to i16 4343 %9 = insertelement <8 x i16> %7, i16 %8, i64 0 4344 %10 = bitcast <8 x i16> %9 to <8 x half> 4345 br label %14 4346 434711: 4348 %12 = bitcast <16 x i8>* %3 to <8 x half>* 4349 %13 = load <8 x half>, <8 x half>* %12, align 8 4350 br label %14 4351 435214: 4353 %15 = phi <8 x half> [ %10, %5 ], [ %13, %11 ] 4354 br i1 %0, label %16, label %21 4355 435616: 4357 %17 = bitcast <16 x i8> %2 to <8 x i16> 4358 %18 = bitcast half %1 to i16 4359 %19 = insertelement <8 x i16> %17, i16 %18, i64 0 4360 %20 = bitcast <8 x i16> %19 to <8 x half> 4361 br label %23 4362 436321: 4364 %22 = bitcast <16 x i8> %2 to <8 x half> 4365 br label %23 4366 436723: 4368 %24 = phi <8 x half> [ %20, %16 ], [ %22, %21 ] 4369 %25 = bitcast <8 x half> %15 to <16 x i8> 4370 %26 = bitcast <8 x half> %24 to <16 x i8> 4371 %27 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %25, <16 x i8> %26) 4372 %28 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %27) 4373 store <16 x i8> %28, <16 x i8>* %3, align 8 4374 ret void 4375} 4376 4377define arm_aapcs_vfpcc void @aesd_setf16_loop_via_ptr(i32 %0, half* %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 4378; CHECK-FIX-LABEL: aesd_setf16_loop_via_ptr: 4379; CHECK-FIX: @ %bb.0: 4380; CHECK-FIX-NEXT: vorr q0, q0, q0 4381; CHECK-FIX-NEXT: ldrh r1, [r1] 4382; CHECK-FIX-NEXT: cmp r0, #0 4383; CHECK-FIX-NEXT: strh r1, [r2] 4384; CHECK-FIX-NEXT: bxeq lr 4385; CHECK-FIX-NEXT: .LBB84_1: 4386; CHECK-FIX-NEXT: vmov.16 d0[0], r1 4387; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 4388; CHECK-FIX-NEXT: .LBB84_2: @ =>This Inner Loop Header: Depth=1 4389; CHECK-FIX-NEXT: aesd.8 q8, q0 4390; CHECK-FIX-NEXT: subs r0, r0, #1 4391; CHECK-FIX-NEXT: aesimc.8 q8, q8 4392; CHECK-FIX-NEXT: bne .LBB84_2 4393; CHECK-FIX-NEXT: @ %bb.3: 4394; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 4395; CHECK-FIX-NEXT: bx lr 4396 %5 = bitcast half* %1 to i16* 4397 %6 = load i16, i16* %5, align 2 4398 %7 = bitcast <16 x i8> %2 to <8 x i16> 4399 %8 = insertelement <8 x i16> %7, i16 %6, i64 0 4400 %9 = bitcast <8 x i16> %8 to <16 x i8> 4401 %10 = bitcast <16 x i8>* %3 to i16* 4402 store i16 %6, i16* %10, align 8 4403 %11 = icmp eq i32 %0, 0 4404 br i1 %11, label %15, label %12 4405 440612: 4407 %13 = load <16 x i8>, <16 x i8>* %3, align 8 4408 br label %16 4409 441014: 4411 store <16 x i8> %20, <16 x i8>* %3, align 8 4412 br label %15 4413 441415: 4415 ret void 4416 441716: 4418 %17 = phi <16 x i8> [ %13, %12 ], [ %20, %16 ] 4419 %18 = phi i32 [ 0, %12 ], [ %21, %16 ] 4420 %19 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %17, <16 x i8> %9) 4421 %20 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %19) 4422 %21 = add nuw i32 %18, 1 4423 %22 = icmp eq i32 %21, %0 4424 br i1 %22, label %14, label %16 4425} 4426 4427define arm_aapcs_vfpcc void @aesd_setf16_loop_via_val(i32 %0, half %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 4428; CHECK-FIX-LABEL: aesd_setf16_loop_via_val: 4429; CHECK-FIX: @ %bb.0: 4430; CHECK-FIX-NEXT: vorr q1, q1, q1 4431; CHECK-FIX-NEXT: cmp r0, #0 4432; CHECK-FIX-NEXT: bxeq lr 4433; CHECK-FIX-NEXT: .LBB85_1: 4434; CHECK-FIX-NEXT: vcvtb.f32.f16 s0, s0 4435; CHECK-FIX-NEXT: vcvtb.f16.f32 s0, s0 4436; CHECK-FIX-NEXT: vmov r2, s0 4437; CHECK-FIX-NEXT: uxth r2, r2 4438; CHECK-FIX-NEXT: vmov.16 d2[0], r2 4439; CHECK-FIX-NEXT: .LBB85_2: @ =>This Inner Loop Header: Depth=1 4440; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r1] 4441; CHECK-FIX-NEXT: subs r0, r0, #1 4442; CHECK-FIX-NEXT: vmov.16 d16[0], r2 4443; CHECK-FIX-NEXT: aesd.8 q8, q1 4444; CHECK-FIX-NEXT: aesimc.8 q8, q8 4445; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r1] 4446; CHECK-FIX-NEXT: bne .LBB85_2 4447; CHECK-FIX-NEXT: @ %bb.3: 4448; CHECK-FIX-NEXT: bx lr 4449 %5 = icmp eq i32 %0, 0 4450 br i1 %5, label %13, label %6 4451 44526: 4453 %7 = bitcast <16 x i8> %2 to <8 x i16> 4454 %8 = bitcast half %1 to i16 4455 %9 = insertelement <8 x i16> %7, i16 %8, i64 0 4456 %10 = bitcast <8 x i16> %9 to <16 x i8> 4457 %11 = bitcast <16 x i8>* %3 to <8 x i16>* 4458 %12 = bitcast <16 x i8>* %3 to half* 4459 br label %14 4460 446113: 4462 ret void 4463 446414: 4465 %15 = phi i32 [ 0, %6 ], [ %21, %14 ] 4466 %16 = load <8 x i16>, <8 x i16>* %11, align 8 4467 %17 = insertelement <8 x i16> %16, i16 %8, i64 0 4468 %18 = bitcast <8 x i16> %17 to <16 x i8> 4469 store half %1, half* %12, align 8 4470 %19 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %18, <16 x i8> %10) 4471 %20 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %19) 4472 store <16 x i8> %20, <16 x i8>* %3, align 8 4473 %21 = add nuw i32 %15, 1 4474 %22 = icmp eq i32 %21, %0 4475 br i1 %22, label %13, label %14 4476} 4477 4478define arm_aapcs_vfpcc void @aesd_setf32_via_ptr(float* %0, <16 x i8> %1, <16 x i8>* %2) nounwind { 4479; CHECK-FIX-LABEL: aesd_setf32_via_ptr: 4480; CHECK-FIX: @ %bb.0: 4481; CHECK-FIX-NEXT: vldr s0, [r0] 4482; CHECK-FIX-NEXT: vld1.64 {d2, d3}, [r1] 4483; CHECK-FIX-NEXT: vmov.f32 s4, s0 4484; CHECK-FIX-NEXT: vorr q1, q1, q1 4485; CHECK-FIX-NEXT: vorr q0, q0, q0 4486; CHECK-FIX-NEXT: aesd.8 q1, q0 4487; CHECK-FIX-NEXT: aesimc.8 q8, q1 4488; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r1] 4489; CHECK-FIX-NEXT: bx lr 4490 %4 = load float, float* %0, align 4 4491 %5 = bitcast <16 x i8>* %2 to <4 x float>* 4492 %6 = load <4 x float>, <4 x float>* %5, align 8 4493 %7 = insertelement <4 x float> %6, float %4, i64 0 4494 %8 = bitcast <4 x float> %7 to <16 x i8> 4495 %9 = bitcast <16 x i8> %1 to <4 x float> 4496 %10 = insertelement <4 x float> %9, float %4, i64 0 4497 %11 = bitcast <4 x float> %10 to <16 x i8> 4498 %12 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %8, <16 x i8> %11) 4499 %13 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %12) 4500 store <16 x i8> %13, <16 x i8>* %2, align 8 4501 ret void 4502} 4503 4504define arm_aapcs_vfpcc void @aesd_setf32_via_val(float %0, <16 x i8> %1, <16 x i8>* %2) nounwind { 4505; CHECK-FIX-LABEL: aesd_setf32_via_val: 4506; CHECK-FIX: @ %bb.0: 4507; CHECK-FIX-NEXT: vmov.f32 s4, s0 4508; CHECK-FIX-NEXT: vld1.64 {d0, d1}, [r0] 4509; CHECK-FIX-NEXT: vmov.f32 s0, s4 4510; CHECK-FIX-NEXT: vorr q0, q0, q0 4511; CHECK-FIX-NEXT: vorr q1, q1, q1 4512; CHECK-FIX-NEXT: aesd.8 q0, q1 4513; CHECK-FIX-NEXT: aesimc.8 q8, q0 4514; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r0] 4515; CHECK-FIX-NEXT: bx lr 4516 %4 = bitcast <16 x i8>* %2 to <4 x float>* 4517 %5 = load <4 x float>, <4 x float>* %4, align 8 4518 %6 = insertelement <4 x float> %5, float %0, i64 0 4519 %7 = bitcast <4 x float> %6 to <16 x i8> 4520 %8 = bitcast <16 x i8> %1 to <4 x float> 4521 %9 = insertelement <4 x float> %8, float %0, i64 0 4522 %10 = bitcast <4 x float> %9 to <16 x i8> 4523 %11 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %7, <16 x i8> %10) 4524 %12 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %11) 4525 store <16 x i8> %12, <16 x i8>* %2, align 8 4526 ret void 4527} 4528 4529define arm_aapcs_vfpcc void @aesd_setf32_cond_via_ptr(i1 zeroext %0, float* %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 4530; CHECK-FIX-LABEL: aesd_setf32_cond_via_ptr: 4531; CHECK-FIX: @ %bb.0: 4532; CHECK-FIX-NEXT: vorr q0, q0, q0 4533; CHECK-FIX-NEXT: cmp r0, #0 4534; CHECK-FIX-NEXT: beq .LBB88_2 4535; CHECK-FIX-NEXT: @ %bb.1: 4536; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 4537; CHECK-FIX-NEXT: vld1.32 {d16[0]}, [r1:32] 4538; CHECK-FIX-NEXT: cmp r0, #0 4539; CHECK-FIX-NEXT: bne .LBB88_3 4540; CHECK-FIX-NEXT: b .LBB88_4 4541; CHECK-FIX-NEXT: .LBB88_2: 4542; CHECK-FIX-NEXT: vld1.64 {d16, d17}, [r2] 4543; CHECK-FIX-NEXT: cmp r0, #0 4544; CHECK-FIX-NEXT: beq .LBB88_4 4545; CHECK-FIX-NEXT: .LBB88_3: 4546; CHECK-FIX-NEXT: vld1.32 {d0[0]}, [r1:32] 4547; CHECK-FIX-NEXT: .LBB88_4: 4548; CHECK-FIX-NEXT: aesd.8 q8, q0 4549; CHECK-FIX-NEXT: aesimc.8 q8, q8 4550; CHECK-FIX-NEXT: vst1.64 {d16, d17}, [r2] 4551; CHECK-FIX-NEXT: bx lr 4552 br i1 %0, label %5, label %10 4553 45545: 4555 %6 = load float, float* %1, align 4 4556 %7 = bitcast <16 x i8>* %3 to <4 x float>* 4557 %8 = load <4 x float>, <4 x float>* %7, align 8 4558 %9 = insertelement <4 x float> %8, float %6, i64 0 4559 br label %13 4560 456110: 4562 %11 = bitcast <16 x i8>* %3 to <4 x float>* 4563 %12 = load <4 x float>, <4 x float>* %11, align 8 4564 br label %13 4565 456613: 4567 %14 = phi <4 x float> [ %9, %5 ], [ %12, %10 ] 4568 br i1 %0, label %15, label %19 4569 457015: 4571 %16 = load float, float* %1, align 4 4572 %17 = bitcast <16 x i8> %2 to <4 x float> 4573 %18 = insertelement <4 x float> %17, float %16, i64 0 4574 br label %21 4575 457619: 4577 %20 = bitcast <16 x i8> %2 to <4 x float> 4578 br label %21 4579 458021: 4581 %22 = phi <4 x float> [ %18, %15 ], [ %20, %19 ] 4582 %23 = bitcast <4 x float> %14 to <16 x i8> 4583 %24 = bitcast <4 x float> %22 to <16 x i8> 4584 %25 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %23, <16 x i8> %24) 4585 %26 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %25) 4586 store <16 x i8> %26, <16 x i8>* %3, align 8 4587 ret void 4588} 4589 4590define arm_aapcs_vfpcc void @aesd_setf32_cond_via_val(i1 zeroext %0, float %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 4591; CHECK-FIX-NOSCHED-LABEL: aesd_setf32_cond_via_val: 4592; CHECK-FIX-NOSCHED: @ %bb.0: 4593; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d4, d5}, [r1] 4594; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 4595; CHECK-FIX-NOSCHED-NEXT: vmovne.f32 s8, s0 4596; CHECK-FIX-NOSCHED-NEXT: vorr q2, q2, q2 4597; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 4598; CHECK-FIX-NOSCHED-NEXT: vmovne.f32 s4, s0 4599; CHECK-FIX-NOSCHED-NEXT: vorr q1, q1, q1 4600; CHECK-FIX-NOSCHED-NEXT: aesd.8 q2, q1 4601; CHECK-FIX-NOSCHED-NEXT: aesimc.8 q8, q2 4602; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r1] 4603; CHECK-FIX-NOSCHED-NEXT: bx lr 4604; 4605; CHECK-CORTEX-FIX-LABEL: aesd_setf32_cond_via_val: 4606; CHECK-CORTEX-FIX: @ %bb.0: 4607; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 4608; CHECK-CORTEX-FIX-NEXT: vld1.64 {d4, d5}, [r1] 4609; CHECK-CORTEX-FIX-NEXT: vmovne.f32 s8, s0 4610; CHECK-CORTEX-FIX-NEXT: vorr q2, q2, q2 4611; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 4612; CHECK-CORTEX-FIX-NEXT: vmovne.f32 s4, s0 4613; CHECK-CORTEX-FIX-NEXT: vorr q1, q1, q1 4614; CHECK-CORTEX-FIX-NEXT: aesd.8 q2, q1 4615; CHECK-CORTEX-FIX-NEXT: aesimc.8 q8, q2 4616; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r1] 4617; CHECK-CORTEX-FIX-NEXT: bx lr 4618 %5 = bitcast <16 x i8>* %3 to <4 x float>* 4619 %6 = load <4 x float>, <4 x float>* %5, align 8 4620 %7 = insertelement <4 x float> %6, float %1, i64 0 4621 %8 = select i1 %0, <4 x float> %7, <4 x float> %6 4622 %9 = bitcast <16 x i8> %2 to <4 x float> 4623 %10 = insertelement <4 x float> %9, float %1, i64 0 4624 %11 = select i1 %0, <4 x float> %10, <4 x float> %9 4625 %12 = bitcast <4 x float> %8 to <16 x i8> 4626 %13 = bitcast <4 x float> %11 to <16 x i8> 4627 %14 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %12, <16 x i8> %13) 4628 %15 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %14) 4629 store <16 x i8> %15, <16 x i8>* %3, align 8 4630 ret void 4631} 4632 4633define arm_aapcs_vfpcc void @aesd_setf32_loop_via_ptr(i32 %0, float* %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 4634; CHECK-FIX-NOSCHED-LABEL: aesd_setf32_loop_via_ptr: 4635; CHECK-FIX-NOSCHED: @ %bb.0: 4636; CHECK-FIX-NOSCHED-NEXT: vldr s4, [r1] 4637; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 4638; CHECK-FIX-NOSCHED-NEXT: vstr s4, [r2] 4639; CHECK-FIX-NOSCHED-NEXT: bxeq lr 4640; CHECK-FIX-NOSCHED-NEXT: .LBB90_1: 4641; CHECK-FIX-NOSCHED-NEXT: vmov.f32 s0, s4 4642; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r2] 4643; CHECK-FIX-NOSCHED-NEXT: .LBB90_2: @ =>This Inner Loop Header: Depth=1 4644; CHECK-FIX-NOSCHED-NEXT: vorr q0, q0, q0 4645; CHECK-FIX-NOSCHED-NEXT: aesd.8 q8, q0 4646; CHECK-FIX-NOSCHED-NEXT: subs r0, r0, #1 4647; CHECK-FIX-NOSCHED-NEXT: aesimc.8 q8, q8 4648; CHECK-FIX-NOSCHED-NEXT: bne .LBB90_2 4649; CHECK-FIX-NOSCHED-NEXT: @ %bb.3: 4650; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r2] 4651; CHECK-FIX-NOSCHED-NEXT: bx lr 4652; 4653; CHECK-CORTEX-FIX-LABEL: aesd_setf32_loop_via_ptr: 4654; CHECK-CORTEX-FIX: @ %bb.0: 4655; CHECK-CORTEX-FIX-NEXT: vldr s4, [r1] 4656; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 4657; CHECK-CORTEX-FIX-NEXT: vstr s4, [r2] 4658; CHECK-CORTEX-FIX-NEXT: bxeq lr 4659; CHECK-CORTEX-FIX-NEXT: .LBB90_1: 4660; CHECK-CORTEX-FIX-NEXT: vld1.64 {d16, d17}, [r2] 4661; CHECK-CORTEX-FIX-NEXT: vmov.f32 s0, s4 4662; CHECK-CORTEX-FIX-NEXT: .LBB90_2: @ =>This Inner Loop Header: Depth=1 4663; CHECK-CORTEX-FIX-NEXT: vorr q0, q0, q0 4664; CHECK-CORTEX-FIX-NEXT: aesd.8 q8, q0 4665; CHECK-CORTEX-FIX-NEXT: subs r0, r0, #1 4666; CHECK-CORTEX-FIX-NEXT: aesimc.8 q8, q8 4667; CHECK-CORTEX-FIX-NEXT: bne .LBB90_2 4668; CHECK-CORTEX-FIX-NEXT: @ %bb.3: 4669; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r2] 4670; CHECK-CORTEX-FIX-NEXT: bx lr 4671 %5 = load float, float* %1, align 4 4672 %6 = bitcast <16 x i8> %2 to <4 x float> 4673 %7 = insertelement <4 x float> %6, float %5, i64 0 4674 %8 = bitcast <4 x float> %7 to <16 x i8> 4675 %9 = bitcast <16 x i8>* %3 to float* 4676 store float %5, float* %9, align 8 4677 %10 = icmp eq i32 %0, 0 4678 br i1 %10, label %14, label %11 4679 468011: 4681 %12 = load <16 x i8>, <16 x i8>* %3, align 8 4682 br label %15 4683 468413: 4685 store <16 x i8> %19, <16 x i8>* %3, align 8 4686 br label %14 4687 468814: 4689 ret void 4690 469115: 4692 %16 = phi <16 x i8> [ %12, %11 ], [ %19, %15 ] 4693 %17 = phi i32 [ 0, %11 ], [ %20, %15 ] 4694 %18 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %16, <16 x i8> %8) 4695 %19 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %18) 4696 %20 = add nuw i32 %17, 1 4697 %21 = icmp eq i32 %20, %0 4698 br i1 %21, label %13, label %15 4699} 4700 4701define arm_aapcs_vfpcc void @aesd_setf32_loop_via_val(i32 %0, float %1, <16 x i8> %2, <16 x i8>* %3) nounwind { 4702; CHECK-FIX-NOSCHED-LABEL: aesd_setf32_loop_via_val: 4703; CHECK-FIX-NOSCHED: @ %bb.0: 4704; CHECK-FIX-NOSCHED-NEXT: cmp r0, #0 4705; CHECK-FIX-NOSCHED-NEXT: bxeq lr 4706; CHECK-FIX-NOSCHED-NEXT: .LBB91_1: 4707; CHECK-FIX-NOSCHED-NEXT: vmov.f32 s4, s0 4708; CHECK-FIX-NOSCHED-NEXT: .LBB91_2: @ =>This Inner Loop Header: Depth=1 4709; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d4, d5}, [r1] 4710; CHECK-FIX-NOSCHED-NEXT: subs r0, r0, #1 4711; CHECK-FIX-NOSCHED-NEXT: vmov.f32 s8, s0 4712; CHECK-FIX-NOSCHED-NEXT: vorr q2, q2, q2 4713; CHECK-FIX-NOSCHED-NEXT: vorr q1, q1, q1 4714; CHECK-FIX-NOSCHED-NEXT: aesd.8 q2, q1 4715; CHECK-FIX-NOSCHED-NEXT: aesimc.8 q8, q2 4716; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r1] 4717; CHECK-FIX-NOSCHED-NEXT: bne .LBB91_2 4718; CHECK-FIX-NOSCHED-NEXT: @ %bb.3: 4719; CHECK-FIX-NOSCHED-NEXT: bx lr 4720; 4721; CHECK-CORTEX-FIX-LABEL: aesd_setf32_loop_via_val: 4722; CHECK-CORTEX-FIX: @ %bb.0: 4723; CHECK-CORTEX-FIX-NEXT: cmp r0, #0 4724; CHECK-CORTEX-FIX-NEXT: bxeq lr 4725; CHECK-CORTEX-FIX-NEXT: .LBB91_1: 4726; CHECK-CORTEX-FIX-NEXT: vmov.f32 s4, s0 4727; CHECK-CORTEX-FIX-NEXT: .LBB91_2: @ =>This Inner Loop Header: Depth=1 4728; CHECK-CORTEX-FIX-NEXT: vld1.64 {d4, d5}, [r1] 4729; CHECK-CORTEX-FIX-NEXT: vmov.f32 s8, s0 4730; CHECK-CORTEX-FIX-NEXT: vorr q2, q2, q2 4731; CHECK-CORTEX-FIX-NEXT: subs r0, r0, #1 4732; CHECK-CORTEX-FIX-NEXT: vorr q1, q1, q1 4733; CHECK-CORTEX-FIX-NEXT: aesd.8 q2, q1 4734; CHECK-CORTEX-FIX-NEXT: aesimc.8 q8, q2 4735; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r1] 4736; CHECK-CORTEX-FIX-NEXT: bne .LBB91_2 4737; CHECK-CORTEX-FIX-NEXT: @ %bb.3: 4738; CHECK-CORTEX-FIX-NEXT: bx lr 4739 %5 = icmp eq i32 %0, 0 4740 br i1 %5, label %12, label %6 4741 47426: 4743 %7 = bitcast <16 x i8> %2 to <4 x float> 4744 %8 = insertelement <4 x float> %7, float %1, i64 0 4745 %9 = bitcast <4 x float> %8 to <16 x i8> 4746 %10 = bitcast <16 x i8>* %3 to <4 x float>* 4747 %11 = bitcast <16 x i8>* %3 to float* 4748 br label %13 4749 475012: 4751 ret void 4752 475313: 4754 %14 = phi i32 [ 0, %6 ], [ %20, %13 ] 4755 %15 = load <4 x float>, <4 x float>* %10, align 8 4756 %16 = insertelement <4 x float> %15, float %1, i64 0 4757 %17 = bitcast <4 x float> %16 to <16 x i8> 4758 store float %1, float* %11, align 8 4759 %18 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %17, <16 x i8> %9) 4760 %19 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %18) 4761 store <16 x i8> %19, <16 x i8>* %3, align 8 4762 %20 = add nuw i32 %14, 1 4763 %21 = icmp eq i32 %20, %0 4764 br i1 %21, label %12, label %13 4765} 4766 4767define arm_aapcs_vfpcc void @aese_constantisland(<16 x i8>* %0) nounwind { 4768; CHECK-FIX-NOSCHED-LABEL: aese_constantisland: 4769; CHECK-FIX-NOSCHED: @ %bb.0: 4770; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d16, d17}, [r0] 4771; CHECK-FIX-NOSCHED-NEXT: adr r1, .LCPI92_0 4772; CHECK-FIX-NOSCHED-NEXT: vld1.64 {d18, d19}, [r1:128] 4773; CHECK-FIX-NOSCHED-NEXT: aese.8 q9, q8 4774; CHECK-FIX-NOSCHED-NEXT: aesmc.8 q8, q9 4775; CHECK-FIX-NOSCHED-NEXT: vst1.64 {d16, d17}, [r0] 4776; CHECK-FIX-NOSCHED-NEXT: bx lr 4777; CHECK-FIX-NOSCHED-NEXT: .p2align 4 4778; CHECK-FIX-NOSCHED-NEXT: @ %bb.1: 4779; CHECK-FIX-NOSCHED-NEXT: .LCPI92_0: 4780; CHECK-FIX-NOSCHED-NEXT: .byte 0 @ 0x0 4781; CHECK-FIX-NOSCHED-NEXT: .byte 1 @ 0x1 4782; CHECK-FIX-NOSCHED-NEXT: .byte 2 @ 0x2 4783; CHECK-FIX-NOSCHED-NEXT: .byte 3 @ 0x3 4784; CHECK-FIX-NOSCHED-NEXT: .byte 4 @ 0x4 4785; CHECK-FIX-NOSCHED-NEXT: .byte 5 @ 0x5 4786; CHECK-FIX-NOSCHED-NEXT: .byte 6 @ 0x6 4787; CHECK-FIX-NOSCHED-NEXT: .byte 7 @ 0x7 4788; CHECK-FIX-NOSCHED-NEXT: .byte 8 @ 0x8 4789; CHECK-FIX-NOSCHED-NEXT: .byte 9 @ 0x9 4790; CHECK-FIX-NOSCHED-NEXT: .byte 10 @ 0xa 4791; CHECK-FIX-NOSCHED-NEXT: .byte 11 @ 0xb 4792; CHECK-FIX-NOSCHED-NEXT: .byte 12 @ 0xc 4793; CHECK-FIX-NOSCHED-NEXT: .byte 13 @ 0xd 4794; CHECK-FIX-NOSCHED-NEXT: .byte 14 @ 0xe 4795; CHECK-FIX-NOSCHED-NEXT: .byte 15 @ 0xf 4796; 4797; CHECK-CORTEX-FIX-LABEL: aese_constantisland: 4798; CHECK-CORTEX-FIX: @ %bb.0: 4799; CHECK-CORTEX-FIX-NEXT: adr r1, .LCPI92_0 4800; CHECK-CORTEX-FIX-NEXT: vld1.64 {d16, d17}, [r0] 4801; CHECK-CORTEX-FIX-NEXT: vld1.64 {d18, d19}, [r1:128] 4802; CHECK-CORTEX-FIX-NEXT: aese.8 q9, q8 4803; CHECK-CORTEX-FIX-NEXT: aesmc.8 q8, q9 4804; CHECK-CORTEX-FIX-NEXT: vst1.64 {d16, d17}, [r0] 4805; CHECK-CORTEX-FIX-NEXT: bx lr 4806; CHECK-CORTEX-FIX-NEXT: .p2align 4 4807; CHECK-CORTEX-FIX-NEXT: @ %bb.1: 4808; CHECK-CORTEX-FIX-NEXT: .LCPI92_0: 4809; CHECK-CORTEX-FIX-NEXT: .byte 0 @ 0x0 4810; CHECK-CORTEX-FIX-NEXT: .byte 1 @ 0x1 4811; CHECK-CORTEX-FIX-NEXT: .byte 2 @ 0x2 4812; CHECK-CORTEX-FIX-NEXT: .byte 3 @ 0x3 4813; CHECK-CORTEX-FIX-NEXT: .byte 4 @ 0x4 4814; CHECK-CORTEX-FIX-NEXT: .byte 5 @ 0x5 4815; CHECK-CORTEX-FIX-NEXT: .byte 6 @ 0x6 4816; CHECK-CORTEX-FIX-NEXT: .byte 7 @ 0x7 4817; CHECK-CORTEX-FIX-NEXT: .byte 8 @ 0x8 4818; CHECK-CORTEX-FIX-NEXT: .byte 9 @ 0x9 4819; CHECK-CORTEX-FIX-NEXT: .byte 10 @ 0xa 4820; CHECK-CORTEX-FIX-NEXT: .byte 11 @ 0xb 4821; CHECK-CORTEX-FIX-NEXT: .byte 12 @ 0xc 4822; CHECK-CORTEX-FIX-NEXT: .byte 13 @ 0xd 4823; CHECK-CORTEX-FIX-NEXT: .byte 14 @ 0xe 4824; CHECK-CORTEX-FIX-NEXT: .byte 15 @ 0xf 4825 %2 = load <16 x i8>, <16 x i8>* %0, align 8 4826 %3 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, <16 x i8> %2) 4827 %4 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %3) 4828 store <16 x i8> %4, <16 x i8>* %0, align 8 4829 ret void 4830} 4831