1; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-DIV
2
3; int f(int n, int d) {
4;   if (n / d)
5;     return 1;
6;   return 0;
7; }
8
9define arm_aapcs_vfpcc i32 @f(i32 %n, i32 %d) {
10entry:
11  %retval = alloca i32, align 4
12  %n.addr = alloca i32, align 4
13  %d.addr = alloca i32, align 4
14  store i32 %n, i32* %n.addr, align 4
15  store i32 %d, i32* %d.addr, align 4
16  %0 = load i32, i32* %n.addr, align 4
17  %1 = load i32, i32* %d.addr, align 4
18  %div = sdiv i32 %0, %1
19  %tobool = icmp ne i32 %div, 0
20  br i1 %tobool, label %if.then, label %if.end
21
22if.then:
23  store i32 1, i32* %retval, align 4
24  br label %return
25
26if.end:
27  store i32 0, i32* %retval, align 4
28  br label %return
29
30return:
31  %2 = load i32, i32* %retval, align 4
32  ret i32 %2
33}
34
35; CHECK-DIV-DAG: BB#0
36; CHECK-DIV-DAG: Successors according to CFG: BB#1({{.*}}) BB#2
37; CHECK-DIV-DAG: BB#1
38; CHECK-DIV-DAG: Successors according to CFG: BB#3
39; CHECK-DIV-DAG: BB#2
40; CHECK-DIV-DAG: Successors according to CFG: BB#3
41; CHECK-DIV-DAG: BB#3
42
43; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-MOD
44
45; int r;
46; int g(int l, int m) {
47;   if (m <= 0)
48;     return 0;
49;   return (r = l % m);
50; }
51
52@r = common global i32 0, align 4
53
54define arm_aapcs_vfpcc i32 @g(i32 %l, i32 %m) {
55entry:
56  %cmp = icmp eq i32 %m, 0
57  br i1 %cmp, label %return, label %if.end
58
59if.end:
60  %rem = urem i32 %l, %m
61  store i32 %rem, i32* @r, align 4
62  br label %return
63
64return:
65  %retval.0 = phi i32 [ %rem, %if.end ], [ 0, %entry ]
66  ret i32 %retval.0
67}
68
69; CHECK-MOD-DAG: BB#0
70; CHECK-MOD-DAG: Successors according to CFG: BB#2({{.*}}) BB#1
71; CHECK-MOD-DAG: BB#1
72; CHECK-MOD-DAG: Successors according to CFG: BB#3
73; CHECK-MOD-DAG: BB#3
74; CHECK-MOD-DAG: Successors according to CFG: BB#2
75; CHECK-MOD-DAG: BB#2
76
77; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -filetype asm -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-CFG
78; RUN: llc -mtriple thumbv7--windows-itanium -verify-machineinstrs -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-CFG-ASM
79
80; unsigned c;
81; extern unsigned long g(void);
82; int f(unsigned u, signed char b) {
83;   if (b)
84;     c = g() % u;
85;   return c;
86; }
87
88@c = common global i32 0, align 4
89
90declare arm_aapcs_vfpcc i32 @i()
91
92define arm_aapcs_vfpcc i32 @h(i32 %u, i8 signext %b) #0 {
93entry:
94  %tobool = icmp eq i8 %b, 0
95  br i1 %tobool, label %entry.if.end_crit_edge, label %if.then
96
97entry.if.end_crit_edge:
98  %.pre = load i32, i32* @c, align 4
99  br label %if.end
100
101if.then:
102  %call = tail call arm_aapcs_vfpcc i32 @i()
103  %rem = urem i32 %call, %u
104  store i32 %rem, i32* @c, align 4
105  br label %if.end
106
107if.end:
108  %0 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %rem, %if.then ]
109  ret i32 %0
110}
111
112attributes #0 = { optsize }
113
114; CHECK-CFG-DAG: BB#0
115; CHECK-CFG-DAG: t2Bcc <BB#2>
116; CHECK-CFG-DAG: t2B <BB#1>
117
118; CHECK-CFG-DAG: BB#1
119; CHECK-CFG-DAG: t2B <BB#3>
120
121; CHECK-CFG-DAG: BB#2
122; CHECK-CFG-DAG: tCMPi8 %vreg{{[0-9]}}, 0
123; CHECK-CFG-DAG: t2Bcc <BB#5>
124
125; CHECK-CFG-DAG: BB#4
126
127; CHECK-CFG-DAG: BB#3
128; CHECK-CFG-DAG: tBX_RET
129
130; CHECK-CFG-DAG: BB#5
131; CHECK-CFG-DAG: t__brkdiv0
132
133; CHECK-CFG-ASM-LABEL: h:
134; CHECK-CFG-ASM: cbz r{{[0-9]}}, .LBB2_4
135; CHECK-CFG-ASM: bl __rt_udiv
136; CHECK-CFG-ASM-LABEL: .LBB2_4:
137; CHECK-CFG-ASM: __brkdiv0
138
139; RUN: llc -O1 -mtriple thumbv7--windows-itanium -verify-machineinstrs -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-WIN__DBZCHK
140
141; long k(void);
142; int l(void);
143; int j(int i) {
144;   if (l() == -1)
145;     return 0;
146;   return k() % i;
147; }
148
149declare arm_aapcs_vfpcc i32 @k()
150declare arm_aapcs_vfpcc i32 @l()
151
152define arm_aapcs_vfpcc i32 @j(i32 %i) {
153entry:
154  %retval = alloca i32, align 4
155  %i.addr = alloca i32, align 4
156  store i32 %i, i32* %i.addr, align 4
157  %call = call arm_aapcs_vfpcc i32 @l()
158  %cmp = icmp eq i32 %call, -1
159  br i1 %cmp, label %if.then, label %if.end
160
161if.then:
162  store i32 0, i32* %retval, align 4
163  br label %return
164
165if.end:
166  %call1 = call arm_aapcs_vfpcc i32 @k()
167  %0 = load i32, i32* %i.addr, align 4
168  %rem = srem i32 %call1, %0
169  store i32 %rem, i32* %retval, align 4
170  br label %return
171
172return:
173  %1 = load i32, i32* %retval, align 4
174  ret i32 %1
175}
176
177; CHECK-WIN__DBZCHK-LABEL: j:
178; CHECK-WIN__DBZCHK: cbz r{{[0-7]}}, .LBB
179; CHECK-WIN__DBZCHK-NOT: cbz r8, .LBB
180; CHECK-WIN__DBZCHK-NOT: cbz r9, .LBB
181; CHECK-WIN__DBZCHK-NOT: cbz r10, .LBB
182; CHECK-WIN__DBZCHK-NOT: cbz r11, .LBB
183; CHECK-WIN__DBZCHK-NOT: cbz ip, .LBB
184; CHECK-WIN__DBZCHK-NOT: cbz lr, .LBB
185
186