1; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefix=SI
2; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=SI
3; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600
4
5; R600: {{^}}s_mad_zext_i32_to_i64:
6; R600: MEM_RAT_CACHELESS STORE_RAW
7; R600: MEM_RAT_CACHELESS STORE_RAW
8
9; SI: {{^}}s_mad_zext_i32_to_i64:
10; SI: v_mov_b32_e32 v[[V_ZERO:[0-9]]], 0{{$}}
11; SI: buffer_store_dwordx2 v[0:[[V_ZERO]]{{\]}}
12define void @s_mad_zext_i32_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) #0 {
13entry:
14  %tmp0 = mul i32 %a, %b
15  %tmp1 = add i32 %tmp0, %c
16  %tmp2 = zext i32 %tmp1 to i64
17  store i64 %tmp2, i64 addrspace(1)* %out
18  ret void
19}
20
21; SI-LABEL: {{^}}s_cmp_zext_i1_to_i32
22; SI: v_cndmask_b32
23define void @s_cmp_zext_i1_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
24entry:
25  %tmp0 = icmp eq i32 %a, %b
26  %tmp1 = zext i1 %tmp0 to i32
27  store i32 %tmp1, i32 addrspace(1)* %out
28  ret void
29}
30
31; SI-LABEL: {{^}}s_arg_zext_i1_to_i64:
32define void @s_arg_zext_i1_to_i64(i64 addrspace(1)* %out, i1 zeroext %arg) #0 {
33  %ext = zext i1 %arg to i64
34  store i64 %ext, i64 addrspace(1)* %out, align 8
35  ret void
36}
37
38; SI-LABEL: {{^}}s_cmp_zext_i1_to_i64:
39; SI: s_mov_b32 s{{[0-9]+}}, 0
40; SI: v_cmp_eq_u32
41; SI: v_cndmask_b32
42define void @s_cmp_zext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) #0 {
43  %cmp = icmp eq i32 %a, %b
44  %ext = zext i1 %cmp to i64
45  store i64 %ext, i64 addrspace(1)* %out, align 8
46  ret void
47}
48
49; SI-LABEL: {{^}}s_cmp_zext_i1_to_i16
50; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
51; SI: buffer_store_short [[RESULT]]
52define void @s_cmp_zext_i1_to_i16(i16 addrspace(1)* %out, i16 zeroext %a, i16 zeroext %b) #0 {
53  %tmp0 = icmp eq i16 %a, %b
54  %tmp1 = zext i1 %tmp0 to i16
55  store i16 %tmp1, i16 addrspace(1)* %out
56  ret void
57}
58
59attributes #0 = { nounwind }
60