1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
3; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
4
5; ===================================================================================
6; V_XAD_U32
7; ===================================================================================
8
9define amdgpu_ps float @xor_add(i32 %a, i32 %b, i32 %c) {
10; VI-LABEL: xor_add:
11; VI:       ; %bb.0:
12; VI-NEXT:    v_xor_b32_e32 v0, v0, v1
13; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
14; VI-NEXT:    ; return to shader part epilog
15;
16; GFX9-LABEL: xor_add:
17; GFX9:       ; %bb.0:
18; GFX9-NEXT:    v_xad_u32 v0, v0, v1, v2
19; GFX9-NEXT:    ; return to shader part epilog
20  %x = xor i32 %a, %b
21  %result = add i32 %x, %c
22  %bc = bitcast i32 %result to float
23  ret float %bc
24}
25
26; ThreeOp instruction variant not used due to Constant Bus Limitations
27define amdgpu_ps float @xor_add_vgpr_a(i32 %a, i32 inreg %b, i32 inreg %c) {
28; VI-LABEL: xor_add_vgpr_a:
29; VI:       ; %bb.0:
30; VI-NEXT:    v_xor_b32_e32 v0, s2, v0
31; VI-NEXT:    v_add_u32_e32 v0, vcc, s3, v0
32; VI-NEXT:    ; return to shader part epilog
33;
34; GFX9-LABEL: xor_add_vgpr_a:
35; GFX9:       ; %bb.0:
36; GFX9-NEXT:    v_xor_b32_e32 v0, s2, v0
37; GFX9-NEXT:    v_add_u32_e32 v0, s3, v0
38; GFX9-NEXT:    ; return to shader part epilog
39  %x = xor i32 %a, %b
40  %result = add i32 %x, %c
41  %bc = bitcast i32 %result to float
42  ret float %bc
43}
44
45define amdgpu_ps float @xor_add_vgpr_all(i32 %a, i32 %b, i32 %c) {
46; VI-LABEL: xor_add_vgpr_all:
47; VI:       ; %bb.0:
48; VI-NEXT:    v_xor_b32_e32 v0, v0, v1
49; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
50; VI-NEXT:    ; return to shader part epilog
51;
52; GFX9-LABEL: xor_add_vgpr_all:
53; GFX9:       ; %bb.0:
54; GFX9-NEXT:    v_xad_u32 v0, v0, v1, v2
55; GFX9-NEXT:    ; return to shader part epilog
56  %x = xor i32 %a, %b
57  %result = add i32 %x, %c
58  %bc = bitcast i32 %result to float
59  ret float %bc
60}
61
62define amdgpu_ps float @xor_add_vgpr_ab(i32 %a, i32 %b, i32 inreg %c) {
63; VI-LABEL: xor_add_vgpr_ab:
64; VI:       ; %bb.0:
65; VI-NEXT:    v_xor_b32_e32 v0, v0, v1
66; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v0
67; VI-NEXT:    ; return to shader part epilog
68;
69; GFX9-LABEL: xor_add_vgpr_ab:
70; GFX9:       ; %bb.0:
71; GFX9-NEXT:    v_xad_u32 v0, v0, v1, s2
72; GFX9-NEXT:    ; return to shader part epilog
73  %x = xor i32 %a, %b
74  %result = add i32 %x, %c
75  %bc = bitcast i32 %result to float
76  ret float %bc
77}
78
79define amdgpu_ps float @xor_add_vgpr_const(i32 %a, i32 %b) {
80; VI-LABEL: xor_add_vgpr_const:
81; VI:       ; %bb.0:
82; VI-NEXT:    v_xor_b32_e32 v0, 3, v0
83; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
84; VI-NEXT:    ; return to shader part epilog
85;
86; GFX9-LABEL: xor_add_vgpr_const:
87; GFX9:       ; %bb.0:
88; GFX9-NEXT:    v_xad_u32 v0, v0, 3, v1
89; GFX9-NEXT:    ; return to shader part epilog
90  %x = xor i32 %a, 3
91  %result = add i32 %x, %b
92  %bc = bitcast i32 %result to float
93  ret float %bc
94}
95