1# RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass si-wqm -o -  %s | FileCheck %s
2
3---
4# Check for awareness that s_or_saveexec_b64 clobbers SCC
5#
6#CHECK: ENTER_STRICT_WWM
7#CHECK: S_CMP_LT_I32
8#CHECK: S_CSELECT_B32
9name:            test_strict_wwm_scc
10alignment:       1
11exposesReturnsTwice: false
12legalized:       false
13regBankSelected: false
14selected:        false
15tracksRegLiveness: true
16registers:
17  - { id: 0, class: sgpr_32, preferred-register: '' }
18  - { id: 1, class: sgpr_32, preferred-register: '' }
19  - { id: 2, class: sgpr_32, preferred-register: '' }
20  - { id: 3, class: vgpr_32, preferred-register: '' }
21  - { id: 4, class: vgpr_32, preferred-register: '' }
22  - { id: 5, class: sgpr_32, preferred-register: '' }
23  - { id: 6, class: vgpr_32, preferred-register: '' }
24  - { id: 7, class: vgpr_32, preferred-register: '' }
25  - { id: 8, class: sreg_32_xm0, preferred-register: '' }
26  - { id: 9, class: sreg_32, preferred-register: '' }
27  - { id: 10, class: sreg_32, preferred-register: '' }
28  - { id: 11, class: vgpr_32, preferred-register: '' }
29  - { id: 12, class: vgpr_32, preferred-register: '' }
30liveins:
31  - { reg: '$sgpr0', virtual-reg: '%0' }
32  - { reg: '$sgpr1', virtual-reg: '%1' }
33  - { reg: '$sgpr2', virtual-reg: '%2' }
34  - { reg: '$vgpr0', virtual-reg: '%3' }
35body:             |
36  bb.0:
37    liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0
38
39    %3 = COPY $vgpr0
40    %2 = COPY $sgpr2
41    %1 = COPY $sgpr1
42    %0 = COPY $sgpr0
43    S_CMP_LT_I32 0, %0, implicit-def $scc
44    %12 = V_ADD_CO_U32_e32 %3, %3, implicit-def $vcc, implicit $exec
45    %5 = S_CSELECT_B32 %2, %1, implicit $scc
46    %11 = V_ADD_CO_U32_e32 %5, %12, implicit-def $vcc, implicit $exec
47    $vgpr0 = STRICT_WWM %11, implicit $exec
48    SI_RETURN_TO_EPILOG $vgpr0
49
50...
51
52---
53# Second test for awareness that s_or_saveexec_b64 clobbers SCC
54# Because entry block is treated differently.
55#
56#CHECK: %bb.1
57#CHECK: S_CMP_LT_I32
58#CHECK: COPY $scc
59#CHECK: ENTER_STRICT_WWM
60#CHECK: $scc = COPY
61#CHECK: S_CSELECT_B32
62name:            test_strict_wwm_scc2
63tracksRegLiveness: true
64body:             |
65  bb.0:
66    liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0
67
68    %3:vgpr_32 = COPY $vgpr0
69    %2:sgpr_32 = COPY $sgpr2
70    %1:sgpr_32 = COPY $sgpr1
71    %0:sgpr_32 = COPY $sgpr0
72    %13:sgpr_128 = IMPLICIT_DEF
73
74  bb.1:
75    S_CMP_LT_I32 0, %0:sgpr_32, implicit-def $scc
76    %10:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %3:vgpr_32, %13:sgpr_128, 0, 0, 0, 0, 0, implicit $exec
77    %12:vgpr_32 = V_ADD_CO_U32_e32 %3:vgpr_32, %3:vgpr_32, implicit-def $vcc, implicit $exec
78    %5:sgpr_32 = S_CSELECT_B32 %2:sgpr_32, %1:sgpr_32, implicit $scc
79    %11:vgpr_32 = V_ADD_CO_U32_e32 %5:sgpr_32, %12:vgpr_32, implicit-def $vcc, implicit $exec
80    $vgpr0 = STRICT_WWM %11:vgpr_32, implicit $exec
81    $vgpr1 = COPY %10:vgpr_32
82    SI_RETURN_TO_EPILOG $vgpr0, $vgpr1
83
84...
85
86---
87# V_SET_INACTIVE, when its second operand is undef, is replaced by a
88# COPY by si-wqm. Ensure the instruction is removed.
89#CHECK-NOT: V_SET_INACTIVE
90name:            no_cfg
91alignment:       1
92exposesReturnsTwice: false
93legalized:       false
94regBankSelected: false
95selected:        false
96failedISel:      false
97tracksRegLiveness: true
98hasWinCFI:       false
99registers:
100  - { id: 0, class: sgpr_32, preferred-register: '' }
101  - { id: 1, class: sgpr_32, preferred-register: '' }
102  - { id: 2, class: sgpr_32, preferred-register: '' }
103  - { id: 3, class: sgpr_32, preferred-register: '' }
104  - { id: 4, class: sgpr_32, preferred-register: '' }
105  - { id: 5, class: sgpr_128, preferred-register: '' }
106  - { id: 6, class: sgpr_128, preferred-register: '' }
107  - { id: 7, class: sreg_32, preferred-register: '' }
108  - { id: 8, class: vreg_64, preferred-register: '' }
109  - { id: 9, class: sreg_32, preferred-register: '' }
110  - { id: 10, class: vgpr_32, preferred-register: '' }
111  - { id: 11, class: vgpr_32, preferred-register: '' }
112  - { id: 12, class: sreg_32, preferred-register: '' }
113  - { id: 13, class: vgpr_32, preferred-register: '' }
114  - { id: 14, class: vgpr_32, preferred-register: '' }
115  - { id: 15, class: vgpr_32, preferred-register: '' }
116  - { id: 16, class: vgpr_32, preferred-register: '' }
117liveins:
118  - { reg: '$sgpr0', virtual-reg: '%0' }
119  - { reg: '$sgpr1', virtual-reg: '%1' }
120  - { reg: '$sgpr2', virtual-reg: '%2' }
121  - { reg: '$sgpr3', virtual-reg: '%3' }
122body:             |
123  bb.0:
124    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
125
126    %3:sgpr_32 = COPY $sgpr3
127    %2:sgpr_32 = COPY $sgpr2
128    %1:sgpr_32 = COPY $sgpr1
129    %0:sgpr_32 = COPY $sgpr0
130    %6:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
131    %5:sgpr_128 = COPY %6
132    %7:sreg_32 = S_MOV_B32 0
133    %8:vreg_64 = BUFFER_LOAD_DWORDX2_OFFSET %6, %7, 0, 0, 0, 0, implicit $exec
134    %16:vgpr_32 = COPY %8.sub1
135    %11:vgpr_32 = COPY %16
136    %10:vgpr_32 = V_SET_INACTIVE_B32 %11, undef %12:sreg_32, implicit $exec, implicit-def $scc
137    %14:vgpr_32 = COPY %7
138    %13:vgpr_32 = V_MOV_B32_dpp %14, killed %10, 323, 12, 15, 0, implicit $exec
139    early-clobber %15:vgpr_32 = STRICT_WWM killed %13, implicit $exec
140    BUFFER_STORE_DWORD_OFFSET_exact killed %15, %6, %7, 4, 0, 0, 0, implicit $exec
141    S_ENDPGM 0
142
143...
144
145---
146# Ensure that strict_wwm is not put around an EXEC copy
147#CHECK-LABEL: name: copy_exec
148#CHECK: %7:sreg_64 = COPY $exec
149#CHECK-NEXT: %14:sreg_64 = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec
150#CHECK-NEXT: %8:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
151#CHECK-NEXT: $exec = EXIT_STRICT_WWM %14
152#CHECK-NEXT: %9:vgpr_32 = V_MBCNT_LO_U32_B32_e64 %7.sub0, 0, implicit $exec
153name:            copy_exec
154tracksRegLiveness: true
155body:             |
156  bb.0:
157    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
158
159    %3:sgpr_32 = COPY $sgpr3
160    %2:sgpr_32 = COPY $sgpr2
161    %1:sgpr_32 = COPY $sgpr1
162    %0:sgpr_32 = COPY $sgpr0
163    %4:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
164    %5:sreg_32 = S_MOV_B32 0
165    %6:vreg_64 = BUFFER_LOAD_DWORDX2_OFFSET %4, %5, 0, 0, 0, 0, implicit $exec
166
167    %8:sreg_64 = COPY $exec
168    %9:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
169    %10:vgpr_32 = V_MBCNT_LO_U32_B32_e64 %8.sub0:sreg_64, 0, implicit $exec
170    %11:vgpr_32 = V_MOV_B32_dpp %9:vgpr_32, %10:vgpr_32, 312, 15, 15, 0, implicit $exec
171    %12:sreg_32 = V_READLANE_B32 %11:vgpr_32, 63
172    early-clobber %13:sreg_32 = STRICT_WWM %9:vgpr_32, implicit $exec
173
174    %14:vgpr_32 = COPY %13
175    BUFFER_STORE_DWORD_OFFSET_exact killed %14, %4, %5, 4, 0, 0, 0, implicit $exec
176    S_ENDPGM 0
177
178...
179
180---
181# Check exit of WQM is still inserted correctly when SCC is live until block end.
182# Critially this tests that compilation does not fail.
183#CHECK-LABEL: name: scc_always_live
184#CHECK: %8:vreg_128 = IMAGE_SAMPLE_V4_V2 %7
185#CHECK-NEXT: S_CMP_EQ_U32 %2, 0, implicit-def $scc
186#CHECK-NEXT: undef %9.sub0:vreg_64 = nsz arcp nofpexcept V_ADD_F32_e64
187#CHECK-NEXT: %9.sub1:vreg_64 = nsz arcp nofpexcept V_MUL_F32_e32
188#CHECK-NEXT: %14:sreg_32_xm0 = COPY $scc
189#CHECK-NEXT: $exec = S_AND_B64 $exec, %13, implicit-def $scc
190#CHECK-NEXT: $scc = COPY %14
191#CHECK-NEXT: %10:vgpr_32 = nsz arcp nofpexcept V_ADD_F32_e64
192#CHECK-NEXT: %11:vreg_128 = IMAGE_SAMPLE_V4_V2
193#CHECK-NEXT: S_CBRANCH_SCC0 %bb.2
194name:            scc_always_live
195tracksRegLiveness: true
196body:             |
197  bb.0:
198    liveins: $sgpr1, $sgpr2, $vgpr1, $vgpr2
199
200    $m0 = COPY $sgpr1
201    %0:vgpr_32 = COPY $vgpr1
202    %1:vgpr_32 = COPY $vgpr2
203    %8:sgpr_32 = COPY $sgpr2
204    %100:sgpr_256 = IMPLICIT_DEF
205    %101:sgpr_128 = IMPLICIT_DEF
206
207    %2:vgpr_32 = V_INTERP_P1_F32 %0:vgpr_32, 3, 2, implicit $mode, implicit $m0, implicit $exec
208    %3:vgpr_32 = V_INTERP_P1_F32 %1:vgpr_32, 3, 2, implicit $mode, implicit $m0, implicit $exec
209
210    undef %7.sub0:vreg_64 = COPY %2:vgpr_32
211    %7.sub1:vreg_64 = COPY %3:vgpr_32
212
213    %4:vreg_128 = IMAGE_SAMPLE_V4_V2 %7:vreg_64, %100:sgpr_256, %101:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16, align 4, addrspace 4)
214    S_CMP_EQ_U32 %8:sgpr_32, 0, implicit-def $scc
215
216    undef %5.sub0:vreg_64 = nsz arcp nofpexcept V_ADD_F32_e64 0, %4.sub0:vreg_128, 0, %3:vgpr_32, 1, 0, implicit $mode, implicit $exec
217    %5.sub1:vreg_64 = nsz arcp nofpexcept V_MUL_F32_e32 %2, %3, implicit $mode, implicit $exec
218    %6:vgpr_32 = nsz arcp nofpexcept V_ADD_F32_e64 0, %2:vgpr_32, 0, %3:vgpr_32, 1, 0, implicit $mode, implicit $exec
219
220    %9:vreg_128 = IMAGE_SAMPLE_V4_V2 %5:vreg_64, %100:sgpr_256, %101:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16, align 4, addrspace 4)
221
222    S_CBRANCH_SCC0 %bb.2, implicit $scc
223
224  bb.1:
225    %10:sreg_32 = S_MOV_B32 0
226    BUFFER_STORE_DWORD_OFFSET_exact %6:vgpr_32, %101:sgpr_128, %10:sreg_32, 4, 0, 0, 0, implicit $exec
227    S_ENDPGM 0
228
229  bb.2:
230    $vgpr0 = COPY %4.sub0:vreg_128
231    $vgpr1 = COPY %4.sub1:vreg_128
232    $vgpr2 = COPY %9.sub0:vreg_128
233    $vgpr3 = COPY %9.sub1:vreg_128
234    SI_RETURN_TO_EPILOG $vgpr0, $vgpr1, $vgpr2, $vgpr3
235...
236
237---
238# Check that unnecessary instruction do not get marked for WWM
239#
240#CHECK-NOT: ENTER_STRICT_WWM
241#CHECK: BUFFER_LOAD_DWORDX2
242#CHECK-NOT: ENTER_STRICT_WWM
243#CHECK: V_SET_INACTIVE_B32
244#CHECK: V_SET_INACTIVE_B32
245#CHECK: ENTER_STRICT_WWM
246#CHECK: V_MAX
247name:            test_wwm_set_inactive_propagation
248tracksRegLiveness: true
249body:             |
250  bb.0:
251    liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $vgpr0
252    %0:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
253    %1:vgpr_32 = COPY $vgpr0
254    %2:vreg_64 = BUFFER_LOAD_DWORDX2_OFFEN %1:vgpr_32, %0:sgpr_128, 0, 0, 0, 0, 0, implicit $exec
255    %2.sub0:vreg_64 = V_SET_INACTIVE_B32 %2.sub0:vreg_64, 0, implicit $exec, implicit-def $scc
256    %2.sub1:vreg_64 = V_SET_INACTIVE_B32 %2.sub1:vreg_64, 0, implicit $exec, implicit-def $scc
257    %3:vreg_64 = nnan nsz arcp contract reassoc nofpexcept V_MAX_F64_e64 0, %2:vreg_64, 0, %2:vreg_64, 0, 0, implicit $mode, implicit $exec
258    $vgpr0 = STRICT_WWM %3.sub0:vreg_64, implicit $exec
259    $vgpr1 = STRICT_WWM %3.sub1:vreg_64, implicit $exec
260    SI_RETURN_TO_EPILOG $vgpr0, $vgpr1
261...
262
263---
264# Check that WQM marking occurs correctly through phi nodes in live range graph.
265# If not then initial V_MOV will not be in WQM.
266#
267#CHECK-LABEL: name: test_wqm_lr_phi
268#CHECK: COPY $exec
269#CHECK-NEXT: S_WQM
270#CHECK-NEXT: V_MOV_B32_e32 -10
271#CHECK-NEXT: V_MOV_B32_e32 0
272name:            test_wqm_lr_phi
273tracksRegLiveness: true
274body:             |
275  bb.0:
276    undef %0.sub0:vreg_64 = V_MOV_B32_e32 -10, implicit $exec
277    %0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
278    %1:sreg_64 = S_GETPC_B64
279    %2:sgpr_256 = S_LOAD_DWORDX8_IMM %1:sreg_64, 32, 0
280
281   bb.1:
282    $vcc = V_CMP_LT_U32_e64 4, 4, implicit $exec
283    S_CBRANCH_VCCNZ %bb.3, implicit $vcc
284    S_BRANCH %bb.2
285
286   bb.2:
287    %0.sub0:vreg_64 = V_ADD_U32_e32 1, %0.sub1, implicit $exec
288    S_BRANCH %bb.3
289
290   bb.3:
291    %0.sub1:vreg_64 = V_ADD_U32_e32 1, %0.sub1, implicit $exec
292    S_BRANCH %bb.4
293
294   bb.4:
295    %3:sgpr_128 = IMPLICIT_DEF
296    %4:vreg_128 = IMAGE_SAMPLE_V4_V2 %0:vreg_64, %2:sgpr_256, %3:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom "ImageResource")
297    $vgpr0 = COPY %4.sub0:vreg_128
298    $vgpr1 = COPY %4.sub1:vreg_128
299    SI_RETURN_TO_EPILOG $vgpr0, $vgpr1
300...
301