1; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK -check-prefix=SI %s 2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK -check-prefix=VI %s 3 4; Check that WQM isn't triggered by image load/store intrinsics. 5; 6;CHECK-LABEL: {{^}}test1: 7;CHECK-NOT: s_wqm 8define amdgpu_ps <4 x float> @test1(<8 x i32> inreg %rsrc, i32 %c) { 9main_body: 10 %tex = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %c, <8 x i32> %rsrc, i32 0, i32 0) 11 call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %tex, i32 15, i32 %c, <8 x i32> %rsrc, i32 0, i32 0) 12 ret <4 x float> %tex 13} 14 15; Check that WQM is triggered by code calculating inputs to image samples and is disabled as soon as possible 16; 17;CHECK-LABEL: {{^}}test2: 18;CHECK-NEXT: ; %main_body 19;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec 20;CHECK-NEXT: s_wqm_b64 exec, exec 21;CHECK: interp 22;CHECK: s_and_b64 exec, exec, [[ORIG]] 23;CHECK-NOT: interp 24;CHECK: image_sample 25;CHECK-NOT: exec 26;CHECK: .size test2 27define amdgpu_ps <4 x float> @test2(i32 inreg, i32 inreg, i32 inreg, i32 inreg %m0, <8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, <2 x float> %pos) #6 { 28main_body: 29 %inst23 = extractelement <2 x float> %pos, i32 0 30 %inst24 = extractelement <2 x float> %pos, i32 1 31 %inst25 = tail call float @llvm.amdgcn.interp.p1(float %inst23, i32 0, i32 0, i32 %m0) 32 %inst26 = tail call float @llvm.amdgcn.interp.p2(float %inst25, float %inst24, i32 0, i32 0, i32 %m0) 33 %inst28 = tail call float @llvm.amdgcn.interp.p1(float %inst23, i32 1, i32 0, i32 %m0) 34 %inst29 = tail call float @llvm.amdgcn.interp.p2(float %inst28, float %inst24, i32 1, i32 0, i32 %m0) 35 %tex = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %inst26, float %inst29, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 36 ret <4 x float> %tex 37} 38 39; ... but disabled for stores (and, in this simple case, not re-enabled) ... 40; 41;CHECK-LABEL: {{^}}test3: 42;CHECK-NEXT: ; %main_body 43;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec 44;CHECK-NEXT: s_wqm_b64 exec, exec 45;CHECK: s_and_b64 exec, exec, [[ORIG]] 46;CHECK: image_sample 47;CHECK: store 48;CHECK-NOT: exec 49;CHECK: .size test3 50define amdgpu_ps <4 x float> @test3(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float %c) { 51main_body: 52 %tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %c, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 53 %tex.1 = bitcast <4 x float> %tex to <4 x i32> 54 %tex.2 = extractelement <4 x i32> %tex.1, i32 0 55 56 call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %tex, <4 x i32> undef, i32 %tex.2, i32 0, i1 0, i1 0) 57 58 ret <4 x float> %tex 59} 60 61; ... and disabled for export. 62; 63;CHECK-LABEL: {{^}}test3x: 64;CHECK-NEXT: ; %main_body 65;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec 66;CHECK-NEXT: s_wqm_b64 exec, exec 67;CHECK: s_and_b64 exec, exec, [[ORIG]] 68;CHECK: image_sample 69;CHECK: exp 70;CHECK-NOT: exec 71;CHECK: .size test3x 72define amdgpu_ps void @test3x(i32 inreg, i32 inreg, i32 inreg, i32 inreg %m0, <8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, <2 x float> %pos) #6 { 73main_body: 74 %inst23 = extractelement <2 x float> %pos, i32 0 75 %inst24 = extractelement <2 x float> %pos, i32 1 76 %inst25 = tail call float @llvm.amdgcn.interp.p1(float %inst23, i32 0, i32 0, i32 %m0) 77 %inst26 = tail call float @llvm.amdgcn.interp.p2(float %inst25, float %inst24, i32 0, i32 0, i32 %m0) 78 %inst28 = tail call float @llvm.amdgcn.interp.p1(float %inst23, i32 1, i32 0, i32 %m0) 79 %inst29 = tail call float @llvm.amdgcn.interp.p2(float %inst28, float %inst24, i32 1, i32 0, i32 %m0) 80 %tex = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %inst26, float %inst29, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 81 %tex.0 = extractelement <4 x float> %tex, i32 0 82 %tex.1 = extractelement <4 x float> %tex, i32 1 83 %tex.2 = extractelement <4 x float> %tex, i32 2 84 %tex.3 = extractelement <4 x float> %tex, i32 3 85 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tex.0, float %tex.1, float %tex.2, float %tex.3, i1 true, i1 true) 86 ret void 87} 88 89; Check that WQM is re-enabled when required. 90; 91;CHECK-LABEL: {{^}}test4: 92;CHECK-NEXT: ; %main_body 93;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec 94;CHECK-NEXT: s_wqm_b64 exec, exec 95;CHECK: v_mul_lo_i32 [[MUL:v[0-9]+]], v0, v1 96;CHECK: s_and_b64 exec, exec, [[ORIG]] 97;CHECK: store 98;CHECK: s_wqm_b64 exec, exec 99;CHECK: image_sample 100;CHECK: image_sample 101define amdgpu_ps <4 x float> @test4(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, i32 %c, i32 %d, float %data) { 102main_body: 103 %c.1 = mul i32 %c, %d 104 105 call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> undef, <4 x i32> undef, i32 %c.1, i32 0, i1 0, i1 0) 106 %c.1.bc = bitcast i32 %c.1 to float 107 %tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %c.1.bc, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 108 %tex0 = extractelement <4 x float> %tex, i32 0 109 %dtex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %tex0, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 110 ret <4 x float> %dtex 111} 112 113; Check that WQM is triggered by the wqm intrinsic. 114; 115;CHECK-LABEL: {{^}}test5: 116;CHECK: s_wqm_b64 exec, exec 117;CHECK: buffer_load_dword 118;CHECK: buffer_load_dword 119;CHECK: v_add_f32_e32 120define amdgpu_ps float @test5(i32 inreg %idx0, i32 inreg %idx1) { 121main_body: 122 %src0 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i1 0, i1 0) 123 %src1 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i1 0, i1 0) 124 %out = fadd float %src0, %src1 125 %out.0 = call float @llvm.amdgcn.wqm.f32(float %out) 126 ret float %out.0 127} 128 129; Check that the wqm intrinsic works correctly for integers. 130; 131;CHECK-LABEL: {{^}}test6: 132;CHECK: s_wqm_b64 exec, exec 133;CHECK: buffer_load_dword 134;CHECK: buffer_load_dword 135;CHECK: v_add_f32_e32 136define amdgpu_ps float @test6(i32 inreg %idx0, i32 inreg %idx1) { 137main_body: 138 %src0 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i1 0, i1 0) 139 %src1 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i1 0, i1 0) 140 %out = fadd float %src0, %src1 141 %out.0 = bitcast float %out to i32 142 %out.1 = call i32 @llvm.amdgcn.wqm.i32(i32 %out.0) 143 %out.2 = bitcast i32 %out.1 to float 144 ret float %out.2 145} 146 147; Check that WWM is triggered by the wwm intrinsic. 148; 149;CHECK-LABEL: {{^}}test_wwm1: 150;CHECK: s_or_saveexec_b64 s{{\[[0-9]+:[0-9]+\]}}, -1 151;CHECK: buffer_load_dword 152;CHECK: buffer_load_dword 153;CHECK: v_add_f32_e32 154define amdgpu_ps float @test_wwm1(i32 inreg %idx0, i32 inreg %idx1) { 155main_body: 156 %src0 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i1 0, i1 0) 157 %src1 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i1 0, i1 0) 158 %out = fadd float %src0, %src1 159 %out.0 = call float @llvm.amdgcn.wwm.f32(float %out) 160 ret float %out.0 161} 162 163; Same as above, but with an integer type. 164; 165;CHECK-LABEL: {{^}}test_wwm2: 166;CHECK: s_or_saveexec_b64 s{{\[[0-9]+:[0-9]+\]}}, -1 167;CHECK: buffer_load_dword 168;CHECK: buffer_load_dword 169;CHECK: v_add_{{[iu]}}32_e32 170define amdgpu_ps float @test_wwm2(i32 inreg %idx0, i32 inreg %idx1) { 171main_body: 172 %src0 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i1 0, i1 0) 173 %src1 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i1 0, i1 0) 174 %src0.0 = bitcast float %src0 to i32 175 %src1.0 = bitcast float %src1 to i32 176 %out = add i32 %src0.0, %src1.0 177 %out.0 = call i32 @llvm.amdgcn.wwm.i32(i32 %out) 178 %out.1 = bitcast i32 %out.0 to float 179 ret float %out.1 180} 181 182; Check that we don't leave WWM on for computations that don't require WWM, 183; since that will lead clobbering things that aren't supposed to be clobbered 184; in cases like this. 185; 186;CHECK-LABEL: {{^}}test_wwm3: 187;CHECK: s_or_saveexec_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], -1 188;CHECK: buffer_load_dword 189;CHECK: v_add_f32_e32 190;CHECK: s_mov_b64 exec, [[ORIG]] 191;CHECK: v_add_f32_e32 192define amdgpu_ps float @test_wwm3(i32 inreg %idx) { 193main_body: 194 ; use mbcnt to make sure the branch is divergent 195 %lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) 196 %hi = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo) 197 %cc = icmp uge i32 %hi, 32 198 br i1 %cc, label %endif, label %if 199 200if: 201 %src = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx, i32 0, i1 0, i1 0) 202 %out = fadd float %src, %src 203 %out.0 = call float @llvm.amdgcn.wwm.f32(float %out) 204 %out.1 = fadd float %src, %out.0 205 br label %endif 206 207endif: 208 %out.2 = phi float [ %out.1, %if ], [ 0.0, %main_body ] 209 ret float %out.2 210} 211 212; Check that WWM writes aren't coalesced with non-WWM writes, since the WWM 213; write could clobber disabled channels in the non-WWM one. 214; 215;CHECK-LABEL: {{^}}test_wwm4: 216;CHECK: s_or_saveexec_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], -1 217;CHECK: buffer_load_dword 218;CHECK: v_add_f32_e32 219;CHECK: s_mov_b64 exec, [[ORIG]] 220;CHECK-NEXT: v_mov_b32_e32 221define amdgpu_ps float @test_wwm4(i32 inreg %idx) { 222main_body: 223 ; use mbcnt to make sure the branch is divergent 224 %lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) 225 %hi = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo) 226 %cc = icmp uge i32 %hi, 32 227 br i1 %cc, label %endif, label %if 228 229if: 230 %src = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx, i32 0, i1 0, i1 0) 231 %out = fadd float %src, %src 232 %out.0 = call float @llvm.amdgcn.wwm.f32(float %out) 233 br label %endif 234 235endif: 236 %out.1 = phi float [ %out.0, %if ], [ 0.0, %main_body ] 237 ret float %out.1 238} 239 240; Make sure the transition from Exact to WWM then WQM works properly. 241; 242;CHECK-LABEL: {{^}}test_wwm5: 243;CHECK: buffer_load_dword 244;CHECK: buffer_store_dword 245;CHECK: s_or_saveexec_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], -1 246;CHECK: buffer_load_dword 247;CHECK: v_add_f32_e32 248;CHECK: s_mov_b64 exec, [[ORIG]] 249;CHECK: s_wqm_b64 exec, exec 250define amdgpu_ps float @test_wwm5(i32 inreg %idx0, i32 inreg %idx1) { 251main_body: 252 %src0 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i1 0, i1 0) 253 call void @llvm.amdgcn.buffer.store.f32(float %src0, <4 x i32> undef, i32 %idx0, i32 0, i1 0, i1 0) 254 %src1 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i1 0, i1 0) 255 %temp = fadd float %src1, %src1 256 %temp.0 = call float @llvm.amdgcn.wwm.f32(float %temp) 257 %out = fadd float %temp.0, %temp.0 258 %out.0 = call float @llvm.amdgcn.wqm.f32(float %out) 259 ret float %out.0 260} 261 262; Check that WWM is turned on correctly across basic block boundaries. 263; if..then..endif version 264; 265;CHECK-LABEL: {{^}}test_wwm6_then: 266;CHECK: s_or_saveexec_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], -1 267;SI-CHECK: buffer_load_dword 268;VI-CHECK: flat_load_dword 269;CHECK: s_mov_b64 exec, [[ORIG]] 270;CHECK: %if 271;CHECK: s_or_saveexec_b64 [[ORIG2:s\[[0-9]+:[0-9]+\]]], -1 272;SI-CHECK: buffer_load_dword 273;VI-CHECK: flat_load_dword 274;CHECK: v_add_f32_e32 275;CHECK: s_mov_b64 exec, [[ORIG2]] 276define amdgpu_ps float @test_wwm6_then() { 277main_body: 278 %src0 = load volatile float, float addrspace(1)* undef 279 ; use mbcnt to make sure the branch is divergent 280 %lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) 281 %hi = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo) 282 %cc = icmp uge i32 %hi, 32 283 br i1 %cc, label %endif, label %if 284 285if: 286 %src1 = load volatile float, float addrspace(1)* undef 287 %out = fadd float %src0, %src1 288 %out.0 = call float @llvm.amdgcn.wwm.f32(float %out) 289 br label %endif 290 291endif: 292 %out.1 = phi float [ %out.0, %if ], [ 0.0, %main_body ] 293 ret float %out.1 294} 295 296; Check that WWM is turned on correctly across basic block boundaries. 297; loop version 298; 299;CHECK-LABEL: {{^}}test_wwm6_loop: 300;CHECK: s_or_saveexec_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], -1 301;SI-CHECK: buffer_load_dword 302;VI-CHECK: flat_load_dword 303;CHECK: s_mov_b64 exec, [[ORIG]] 304;CHECK: %loop 305;CHECK: s_or_saveexec_b64 [[ORIG2:s\[[0-9]+:[0-9]+\]]], -1 306;SI-CHECK: buffer_load_dword 307;VI-CHECK: flat_load_dword 308;CHECK: s_mov_b64 exec, [[ORIG2]] 309define amdgpu_ps float @test_wwm6_loop() { 310main_body: 311 %src0 = load volatile float, float addrspace(1)* undef 312 ; use mbcnt to make sure the branch is divergent 313 %lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) 314 %hi = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo) 315 br label %loop 316 317loop: 318 %counter = phi i32 [ %lo, %main_body ], [ %counter.1, %loop ] 319 %src1 = load volatile float, float addrspace(1)* undef 320 %out = fadd float %src0, %src1 321 %out.0 = call float @llvm.amdgcn.wwm.f32(float %out) 322 %counter.1 = sub i32 %counter, 1 323 %cc = icmp ne i32 %counter.1, 0 324 br i1 %cc, label %loop, label %endloop 325 326endloop: 327 ret float %out.0 328} 329 330; Check that @llvm.amdgcn.set.inactive disables WWM. 331; 332;CHECK-LABEL: {{^}}test_set_inactive1: 333;CHECK: buffer_load_dword 334;CHECK: s_not_b64 exec, exec 335;CHECK: v_mov_b32_e32 336;CHECK: s_not_b64 exec, exec 337;CHECK: s_or_saveexec_b64 s{{\[[0-9]+:[0-9]+\]}}, -1 338;CHECK: v_add_{{[iu]}}32_e32 339define amdgpu_ps void @test_set_inactive1(i32 inreg %idx) { 340main_body: 341 %src = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx, i32 0, i1 0, i1 0) 342 %src.0 = bitcast float %src to i32 343 %src.1 = call i32 @llvm.amdgcn.set.inactive.i32(i32 %src.0, i32 0) 344 %out = add i32 %src.1, %src.1 345 %out.0 = call i32 @llvm.amdgcn.wwm.i32(i32 %out) 346 %out.1 = bitcast i32 %out.0 to float 347 call void @llvm.amdgcn.buffer.store.f32(float %out.1, <4 x i32> undef, i32 %idx, i32 0, i1 0, i1 0) 348 ret void 349} 350 351; Check that enabling WQM anywhere enables WQM for the set.inactive source. 352; 353;CHECK-LABEL: {{^}}test_set_inactive2: 354;CHECK: s_wqm_b64 exec, exec 355;CHECK: buffer_load_dword 356;CHECK: buffer_load_dword 357define amdgpu_ps void @test_set_inactive2(i32 inreg %idx0, i32 inreg %idx1) { 358main_body: 359 %src1 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i1 0, i1 0) 360 %src1.0 = bitcast float %src1 to i32 361 %src1.1 = call i32 @llvm.amdgcn.set.inactive.i32(i32 %src1.0, i32 undef) 362 %src0 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i1 0, i1 0) 363 %src0.0 = bitcast float %src0 to i32 364 %src0.1 = call i32 @llvm.amdgcn.wqm.i32(i32 %src0.0) 365 %out = add i32 %src0.1, %src1.1 366 %out.0 = bitcast i32 %out to float 367 call void @llvm.amdgcn.buffer.store.f32(float %out.0, <4 x i32> undef, i32 %idx1, i32 0, i1 0, i1 0) 368 ret void 369} 370 371; Check a case of one branch of an if-else requiring WQM, the other requiring 372; exact. 373; 374; Note: In this particular case, the save-and-restore could be avoided if the 375; analysis understood that the two branches of the if-else are mutually 376; exclusive. 377; 378;CHECK-LABEL: {{^}}test_control_flow_0: 379;CHECK-NEXT: ; %main_body 380;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec 381;CHECK-NEXT: s_wqm_b64 exec, exec 382;CHECK: %ELSE 383;CHECK: s_and_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], [[ORIG]] 384;CHECK: store 385;CHECK: s_mov_b64 exec, [[SAVED]] 386;CHECK: %IF 387;CHECK: image_sample 388;CHECK: image_sample 389define amdgpu_ps float @test_control_flow_0(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, i32 %c, i32 %z, float %data) { 390main_body: 391 %cmp = icmp eq i32 %z, 0 392 br i1 %cmp, label %IF, label %ELSE 393 394IF: 395 %c.bc = bitcast i32 %c to float 396 %tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %c.bc, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 397 %tex0 = extractelement <4 x float> %tex, i32 0 398 %dtex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %tex0, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 399 %data.if = extractelement <4 x float> %dtex, i32 0 400 br label %END 401 402ELSE: 403 call void @llvm.amdgcn.buffer.store.f32(float %data, <4 x i32> undef, i32 %c, i32 0, i1 0, i1 0) 404 br label %END 405 406END: 407 %r = phi float [ %data.if, %IF ], [ %data, %ELSE ] 408 ret float %r 409} 410 411; Reverse branch order compared to the previous test. 412; 413;CHECK-LABEL: {{^}}test_control_flow_1: 414;CHECK-NEXT: ; %main_body 415;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec 416;CHECK-NEXT: s_wqm_b64 exec, exec 417;CHECK: %IF 418;CHECK: image_sample 419;CHECK: image_sample 420;CHECK: %Flow 421;CHECK-NEXT: s_or_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], 422;CHECK-NEXT: s_and_b64 exec, exec, [[ORIG]] 423;CHECK-NEXT: s_and_b64 [[SAVED]], exec, [[SAVED]] 424;CHECK-NEXT: s_xor_b64 exec, exec, [[SAVED]] 425;CHECK-NEXT: mask branch [[END_BB:BB[0-9]+_[0-9]+]] 426;CHECK-NEXT: BB{{[0-9]+_[0-9]+}}: ; %ELSE 427;CHECK: store_dword 428;CHECK: [[END_BB]]: ; %END 429;CHECK: s_or_b64 exec, exec, 430;CHECK: v_mov_b32_e32 v0 431;CHECK: ; return 432define amdgpu_ps float @test_control_flow_1(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, i32 %c, i32 %z, float %data) { 433main_body: 434 %cmp = icmp eq i32 %z, 0 435 br i1 %cmp, label %ELSE, label %IF 436 437IF: 438 %c.bc = bitcast i32 %c to float 439 %tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %c.bc, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 440 %tex0 = extractelement <4 x float> %tex, i32 0 441 %dtex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %tex0, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 442 %data.if = extractelement <4 x float> %dtex, i32 0 443 br label %END 444 445ELSE: 446 call void @llvm.amdgcn.buffer.store.f32(float %data, <4 x i32> undef, i32 %c, i32 0, i1 0, i1 0) 447 br label %END 448 449END: 450 %r = phi float [ %data.if, %IF ], [ %data, %ELSE ] 451 ret float %r 452} 453 454; Check that branch conditions are properly marked as needing WQM... 455; 456;CHECK-LABEL: {{^}}test_control_flow_2: 457;CHECK-NEXT: ; %main_body 458;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec 459;CHECK-NEXT: s_wqm_b64 exec, exec 460;CHECK: s_and_b64 exec, exec, [[ORIG]] 461;CHECK: store 462;CHECK: s_wqm_b64 exec, exec 463;CHECK: load 464;CHECK: s_and_b64 exec, exec, [[ORIG]] 465;CHECK: store 466;CHECK: s_wqm_b64 exec, exec 467;CHECK: v_cmp 468define amdgpu_ps <4 x float> @test_control_flow_2(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, <3 x i32> %idx, <2 x float> %data, i32 %coord) { 469main_body: 470 %idx.1 = extractelement <3 x i32> %idx, i32 0 471 %data.1 = extractelement <2 x float> %data, i32 0 472 call void @llvm.amdgcn.buffer.store.f32(float %data.1, <4 x i32> undef, i32 %idx.1, i32 0, i1 0, i1 0) 473 474 ; The load that determines the branch (and should therefore be WQM) is 475 ; surrounded by stores that require disabled WQM. 476 %idx.2 = extractelement <3 x i32> %idx, i32 1 477 %z = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 %idx.2, i32 0, i1 0, i1 0) 478 479 %idx.3 = extractelement <3 x i32> %idx, i32 2 480 %data.3 = extractelement <2 x float> %data, i32 1 481 call void @llvm.amdgcn.buffer.store.f32(float %data.3, <4 x i32> undef, i32 %idx.3, i32 0, i1 0, i1 0) 482 483 %cc = fcmp ogt float %z, 0.0 484 br i1 %cc, label %IF, label %ELSE 485 486IF: 487 %coord.IF = mul i32 %coord, 3 488 br label %END 489 490ELSE: 491 %coord.ELSE = mul i32 %coord, 4 492 br label %END 493 494END: 495 %coord.END = phi i32 [ %coord.IF, %IF ], [ %coord.ELSE, %ELSE ] 496 %coord.END.bc = bitcast i32 %coord.END to float 497 %tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %coord.END.bc, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 498 ret <4 x float> %tex 499} 500 501; ... but only if they really do need it. 502; 503;CHECK-LABEL: {{^}}test_control_flow_3: 504;CHECK-NEXT: ; %main_body 505;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec 506;CHECK-NEXT: s_wqm_b64 exec, exec 507;CHECK: image_sample 508;CHECK: s_and_b64 exec, exec, [[ORIG]] 509;CHECK: image_sample 510;CHECK-DAG: v_cmp 511;CHECK-DAG: store 512define amdgpu_ps float @test_control_flow_3(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, i32 %idx, float %coord) { 513main_body: 514 %tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 515 %tex0 = extractelement <4 x float> %tex, i32 0 516 %dtex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %tex0, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 517 %dtex.1 = extractelement <4 x float> %dtex, i32 0 518 call void @llvm.amdgcn.buffer.store.f32(float %dtex.1, <4 x i32> undef, i32 %idx, i32 0, i1 0, i1 0) 519 520 %cc = fcmp ogt float %dtex.1, 0.0 521 br i1 %cc, label %IF, label %ELSE 522 523IF: 524 %tex.IF = fmul float %dtex.1, 3.0 525 br label %END 526 527ELSE: 528 %tex.ELSE = fmul float %dtex.1, 4.0 529 br label %END 530 531END: 532 %tex.END = phi float [ %tex.IF, %IF ], [ %tex.ELSE, %ELSE ] 533 ret float %tex.END 534} 535 536; Another test that failed at some point because of terminator handling. 537; 538;CHECK-LABEL: {{^}}test_control_flow_4: 539;CHECK-NEXT: ; %main_body 540;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec 541;CHECK-NEXT: s_wqm_b64 exec, exec 542;CHECK: %IF 543;CHECK: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[ORIG]] 544;CHECK: load 545;CHECK: store 546;CHECK: s_mov_b64 exec, [[SAVE]] 547;CHECK: %END 548;CHECK: image_sample 549;CHECK: image_sample 550define amdgpu_ps <4 x float> @test_control_flow_4(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float %coord, i32 %y, float %z) { 551main_body: 552 %cond = icmp eq i32 %y, 0 553 br i1 %cond, label %IF, label %END 554 555IF: 556 %data = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> undef, i32 0, i32 0, i1 0, i1 0) 557 call void @llvm.amdgcn.buffer.store.f32(float %data, <4 x i32> undef, i32 1, i32 0, i1 0, i1 0) 558 br label %END 559 560END: 561 %tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 562 %tex0 = extractelement <4 x float> %tex, i32 0 563 %dtex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %tex0, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 564 ret <4 x float> %dtex 565} 566 567; Kill is performed in WQM mode so that uniform kill behaves correctly ... 568; 569;CHECK-LABEL: {{^}}test_kill_0: 570;CHECK-NEXT: ; %main_body 571;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec 572;CHECK-NEXT: s_wqm_b64 exec, exec 573;CHECK: s_and_b64 exec, exec, [[ORIG]] 574;CHECK: image_sample 575;CHECK: buffer_store_dword 576;CHECK: s_wqm_b64 exec, exec 577;CHECK: v_cmpx_ 578;CHECK: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[ORIG]] 579;CHECK: buffer_store_dword 580;CHECK: s_mov_b64 exec, [[SAVE]] 581;CHECK: image_sample 582define amdgpu_ps <4 x float> @test_kill_0(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <2 x i32> %idx, <2 x float> %data, float %coord, float %coord2, float %z) { 583main_body: 584 %tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 585 %idx.0 = extractelement <2 x i32> %idx, i32 0 586 %data.0 = extractelement <2 x float> %data, i32 0 587 call void @llvm.amdgcn.buffer.store.f32(float %data.0, <4 x i32> undef, i32 %idx.0, i32 0, i1 0, i1 0) 588 589 %z.cmp = fcmp olt float %z, 0.0 590 call void @llvm.amdgcn.kill(i1 %z.cmp) 591 592 %idx.1 = extractelement <2 x i32> %idx, i32 1 593 %data.1 = extractelement <2 x float> %data, i32 1 594 call void @llvm.amdgcn.buffer.store.f32(float %data.1, <4 x i32> undef, i32 %idx.1, i32 0, i1 0, i1 0) 595 %tex2 = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %coord2, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 596 %tex2.0 = extractelement <4 x float> %tex2, i32 0 597 %dtex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %tex2.0, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 598 %out = fadd <4 x float> %tex, %dtex 599 600 ret <4 x float> %out 601} 602 603; ... but only if WQM is necessary. 604; 605; CHECK-LABEL: {{^}}test_kill_1: 606; CHECK-NEXT: ; %main_body 607; CHECK: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec 608; CHECK: s_wqm_b64 exec, exec 609; CHECK: image_sample 610; CHECK: s_and_b64 exec, exec, [[ORIG]] 611; CHECK: image_sample 612; CHECK: buffer_store_dword 613; CHECK-NOT: wqm 614; CHECK: v_cmpx_ 615define amdgpu_ps <4 x float> @test_kill_1(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, i32 %idx, float %data, float %coord, float %coord2, float %z) { 616main_body: 617 %tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 618 %tex0 = extractelement <4 x float> %tex, i32 0 619 %dtex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %tex0, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 620 621 call void @llvm.amdgcn.buffer.store.f32(float %data, <4 x i32> undef, i32 0, i32 0, i1 0, i1 0) 622 623 %z.cmp = fcmp olt float %z, 0.0 624 call void @llvm.amdgcn.kill(i1 %z.cmp) 625 626 ret <4 x float> %dtex 627} 628 629; Check prolog shaders. 630; 631; CHECK-LABEL: {{^}}test_prolog_1: 632; CHECK: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec 633; CHECK: s_wqm_b64 exec, exec 634; CHECK: v_add_f32_e32 v0, 635; CHECK: s_and_b64 exec, exec, [[ORIG]] 636define amdgpu_ps float @test_prolog_1(float %a, float %b) #5 { 637main_body: 638 %s = fadd float %a, %b 639 ret float %s 640} 641 642; CHECK-LABEL: {{^}}test_loop_vcc: 643; CHECK-NEXT: ; %entry 644; CHECK-NEXT: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec 645; CHECK: s_wqm_b64 exec, exec 646; CHECK: s_and_b64 exec, exec, [[LIVE]] 647; CHECK: image_store 648; CHECK: s_wqm_b64 exec, exec 649; CHECK-DAG: v_mov_b32_e32 [[CTR:v[0-9]+]], 0 650; CHECK-DAG: s_mov_b32 [[SEVEN:s[0-9]+]], 0x40e00000 651 652; CHECK: [[LOOPHDR:BB[0-9]+_[0-9]+]]: ; %body 653; CHECK: v_add_f32_e32 [[CTR]], 2.0, [[CTR]] 654; CHECK: v_cmp_lt_f32_e32 vcc, [[SEVEN]], [[CTR]] 655; CHECK: s_cbranch_vccz [[LOOPHDR]] 656; CHECK: ; %break 657 658; CHECK: ; return 659define amdgpu_ps <4 x float> @test_loop_vcc(<4 x float> %in) nounwind { 660entry: 661 call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %in, i32 15, i32 undef, <8 x i32> undef, i32 0, i32 0) 662 br label %loop 663 664loop: 665 %ctr.iv = phi float [ 0.0, %entry ], [ %ctr.next, %body ] 666 %c.iv = phi <4 x float> [ %in, %entry ], [ %c.next, %body ] 667 %cc = fcmp ogt float %ctr.iv, 7.0 668 br i1 %cc, label %break, label %body 669 670body: 671 %c.iv0 = extractelement <4 x float> %c.iv, i32 0 672 %c.next = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %c.iv0, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0) #0 673 %ctr.next = fadd float %ctr.iv, 2.0 674 br label %loop 675 676break: 677 ret <4 x float> %c.iv 678} 679 680; Only intrinsic stores need exact execution -- other stores do not have 681; externally visible effects and may require WQM for correctness. 682; 683; CHECK-LABEL: {{^}}test_alloca: 684; CHECK: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec 685; CHECK: s_wqm_b64 exec, exec 686 687; CHECK: s_and_b64 exec, exec, [[LIVE]] 688; CHECK: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 689; CHECK: s_wqm_b64 exec, exec 690; CHECK: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:4{{$}} 691; CHECK: s_and_b64 exec, exec, [[LIVE]] 692; CHECK: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen 693; CHECK: s_wqm_b64 exec, exec 694; CHECK: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen 695 696; CHECK: s_and_b64 exec, exec, [[LIVE]] 697; CHECK: image_sample 698; CHECK: buffer_store_dwordx4 699define amdgpu_ps void @test_alloca(float %data, i32 %a, i32 %idx) nounwind { 700entry: 701 %array = alloca [32 x i32], align 4, addrspace(5) 702 703 call void @llvm.amdgcn.buffer.store.f32(float %data, <4 x i32> undef, i32 0, i32 0, i1 0, i1 0) 704 705 %s.gep = getelementptr [32 x i32], [32 x i32] addrspace(5)* %array, i32 0, i32 0 706 store volatile i32 %a, i32 addrspace(5)* %s.gep, align 4 707 708 call void @llvm.amdgcn.buffer.store.f32(float %data, <4 x i32> undef, i32 1, i32 0, i1 0, i1 0) 709 710 %c.gep = getelementptr [32 x i32], [32 x i32] addrspace(5)* %array, i32 0, i32 %idx 711 %c = load i32, i32 addrspace(5)* %c.gep, align 4 712 %c.bc = bitcast i32 %c to float 713 %t = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %c.bc, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0) #0 714 call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %t, <4 x i32> undef, i32 0, i32 0, i1 0, i1 0) 715 716 ret void 717} 718 719; Must return to exact at the end of a non-void returning shader, 720; otherwise the EXEC mask exported by the epilog will be wrong. This is true 721; even if the shader has no kills, because a kill could have happened in a 722; previous shader fragment. 723; 724; CHECK-LABEL: {{^}}test_nonvoid_return: 725; CHECK: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec 726; CHECK: s_wqm_b64 exec, exec 727; 728; CHECK: s_and_b64 exec, exec, [[LIVE]] 729; CHECK-NOT: exec 730define amdgpu_ps <4 x float> @test_nonvoid_return() nounwind { 731 %tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float undef, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0) #0 732 %tex0 = extractelement <4 x float> %tex, i32 0 733 %dtex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %tex0, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0) #0 734 ret <4 x float> %dtex 735} 736 737; CHECK-LABEL: {{^}}test_nonvoid_return_unreachable: 738; CHECK: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec 739; CHECK: s_wqm_b64 exec, exec 740; 741; CHECK: s_and_b64 exec, exec, [[LIVE]] 742; CHECK-NOT: exec 743define amdgpu_ps <4 x float> @test_nonvoid_return_unreachable(i32 inreg %c) nounwind { 744entry: 745 %tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float undef, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0) #0 746 %tex0 = extractelement <4 x float> %tex, i32 0 747 %dtex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %tex0, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0) #0 748 %cc = icmp sgt i32 %c, 0 749 br i1 %cc, label %if, label %else 750 751if: 752 store volatile <4 x float> %dtex, <4 x float> addrspace(1)* undef 753 unreachable 754 755else: 756 ret <4 x float> %dtex 757} 758 759; Test awareness that s_wqm_b64 clobbers SCC. 760; 761; CHECK-LABEL: {{^}}test_scc: 762; CHECK: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec 763; CHECK: s_wqm_b64 exec, exec 764; CHECK: s_cmp_ 765; CHECK-NEXT: s_cbranch_scc 766; CHECK: ; %if 767; CHECK: s_and_b64 exec, exec, [[ORIG]] 768; CHECK: image_sample 769; CHECK: ; %else 770; CHECK: s_and_b64 exec, exec, [[ORIG]] 771; CHECK: image_sample 772; CHECK: ; %end 773define amdgpu_ps <4 x float> @test_scc(i32 inreg %sel, i32 %idx) #1 { 774main_body: 775 %cc = icmp sgt i32 %sel, 0 776 br i1 %cc, label %if, label %else 777 778if: 779 %r.if = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float 0.0, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0) #0 780 br label %end 781 782else: 783 %r.else = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 0.0, float bitcast (i32 1 to float), <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0) #0 784 br label %end 785 786end: 787 %r = phi <4 x float> [ %r.if, %if ], [ %r.else, %else ] 788 call void @llvm.amdgcn.buffer.store.f32(float 1.0, <4 x i32> undef, i32 %idx, i32 0, i1 0, i1 0) 789 ret <4 x float> %r 790} 791 792; Check a case of a block being entirely WQM except for a bit of WWM. 793; There was a bug where it forgot to enter and leave WWM. 794; 795;CHECK-LABEL: {{^}}test_wwm_within_wqm: 796;CHECK: %IF 797;CHECK: s_or_saveexec_b64 {{.*}}, -1 798;CHECK: ds_swizzle 799; 800define amdgpu_ps float @test_wwm_within_wqm(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, i32 %c, i32 %z, float %data) { 801main_body: 802 %c.bc = bitcast i32 %c to float 803 %tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %c.bc, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 804 %tex0 = extractelement <4 x float> %tex, i32 0 805 %dtex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %tex0, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) #0 806 %cmp = icmp eq i32 %z, 0 807 br i1 %cmp, label %IF, label %ENDIF 808 809IF: 810 %dataf = extractelement <4 x float> %dtex, i32 0 811 %data1 = fptosi float %dataf to i32 812 %data2 = call i32 @llvm.amdgcn.set.inactive.i32(i32 %data1, i32 0) 813 %data3 = call i32 @llvm.amdgcn.ds.swizzle(i32 %data2, i32 2079) 814 %data4 = call i32 @llvm.amdgcn.wwm.i32(i32 %data3) 815 %data4f = sitofp i32 %data4 to float 816 br label %ENDIF 817 818ENDIF: 819 %r = phi float [ %data4f, %IF ], [ 0.0, %main_body ] 820 ret float %r 821} 822 823declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #1 824declare void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float>, i32, i32, <8 x i32>, i32, i32) #1 825declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) #2 826declare void @llvm.amdgcn.buffer.store.v4f32(<4 x float>, <4 x i32>, i32, i32, i1, i1) #2 827declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32, i32, <8 x i32>, i32, i32) #3 828declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #3 829declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #3 830declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #3 831declare void @llvm.amdgcn.kill(i1) #1 832declare float @llvm.amdgcn.wqm.f32(float) #3 833declare i32 @llvm.amdgcn.wqm.i32(i32) #3 834declare float @llvm.amdgcn.wwm.f32(float) #3 835declare i32 @llvm.amdgcn.wwm.i32(i32) #3 836declare i32 @llvm.amdgcn.set.inactive.i32(i32, i32) #4 837declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #3 838declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #3 839declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #3 840declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) #1 841declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #2 842declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #2 843declare i32 @llvm.amdgcn.ds.swizzle(i32, i32) 844 845attributes #1 = { nounwind } 846attributes #2 = { nounwind readonly } 847attributes #3 = { nounwind readnone } 848attributes #4 = { nounwind readnone convergent } 849attributes #5 = { "amdgpu-ps-wqm-outputs" } 850attributes #6 = { nounwind "InitialPSInputAddr"="2" } 851