1; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,GFX1032 %s 2; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,GFX1064 %s 3; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -amdgpu-early-ifcvt=1 -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,GFX1032 %s 4; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -amdgpu-early-ifcvt=1 -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,GFX1064 %s 5; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefixes=GCN,GFX1032,GFX10DEFWAVE %s 6 7; GCN-LABEL: {{^}}test_vopc_i32: 8; GFX1032: v_cmp_lt_i32_e32 vcc_lo, 0, v{{[0-9]+}} 9; GFX1032: v_cndmask_b32_e64 v{{[0-9]+}}, 2, 1, vcc_lo 10; GFX1064: v_cmp_lt_i32_e32 vcc, 0, v{{[0-9]+}} 11; GFX1064: v_cndmask_b32_e64 v{{[0-9]+}}, 2, 1, vcc{{$}} 12define amdgpu_kernel void @test_vopc_i32(i32 addrspace(1)* %arg) { 13 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 14 %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %lid 15 %load = load i32, i32 addrspace(1)* %gep, align 4 16 %cmp = icmp sgt i32 %load, 0 17 %sel = select i1 %cmp, i32 1, i32 2 18 store i32 %sel, i32 addrspace(1)* %gep, align 4 19 ret void 20} 21 22; GCN-LABEL: {{^}}test_vopc_f32: 23; GFX1032: v_cmp_nge_f32_e32 vcc_lo, 0, v{{[0-9]+}} 24; GFX1032: v_cndmask_b32_e64 v{{[0-9]+}}, 2.0, 1.0, vcc_lo 25; GFX1064: v_cmp_nge_f32_e32 vcc, 0, v{{[0-9]+}} 26; GFX1064: v_cndmask_b32_e64 v{{[0-9]+}}, 2.0, 1.0, vcc{{$}} 27define amdgpu_kernel void @test_vopc_f32(float addrspace(1)* %arg) { 28 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 29 %gep = getelementptr inbounds float, float addrspace(1)* %arg, i32 %lid 30 %load = load float, float addrspace(1)* %gep, align 4 31 %cmp = fcmp ugt float %load, 0.0 32 %sel = select i1 %cmp, float 1.0, float 2.0 33 store float %sel, float addrspace(1)* %gep, align 4 34 ret void 35} 36 37; GCN-LABEL: {{^}}test_vopc_vcmp: 38; GFX1032: v_cmp_nle_f32_e32 vcc_lo, 0, v{{[0-9]+}} 39; GFX1064: v_cmp_nle_f32_e32 vcc, 0, v{{[0-9]+}} 40define amdgpu_ps void @test_vopc_vcmp(float %x) { 41 %cmp = fcmp oge float %x, 0.0 42 call void @llvm.amdgcn.kill(i1 %cmp) 43 ret void 44} 45 46; GCN-LABEL: {{^}}test_vopc_2xf16: 47; GFX1032: v_cmp_le_f16_sdwa [[SC:vcc_lo|s[0-9]+]], {{[vs][0-9]+}}, v{{[0-9]+}} src0_sel:WORD_1 src1_sel:DWORD 48; GFX1032: v_cndmask_b32_e32 v{{[0-9]+}}, 0x3c003c00, v{{[0-9]+}}, [[SC]] 49; GFX1064: v_cmp_le_f16_sdwa [[SC:vcc|s\[[0-9:]+\]]], {{[vs][0-9]+}}, v{{[0-9]+}} src0_sel:WORD_1 src1_sel:DWORD 50; GFX1064: v_cndmask_b32_e32 v{{[0-9]+}}, 0x3c003c00, v{{[0-9]+}}, [[SC]] 51define amdgpu_kernel void @test_vopc_2xf16(<2 x half> addrspace(1)* %arg) { 52 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 53 %gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i32 %lid 54 %load = load <2 x half>, <2 x half> addrspace(1)* %gep, align 4 55 %elt = extractelement <2 x half> %load, i32 1 56 %cmp = fcmp ugt half %elt, 0.0 57 %sel = select i1 %cmp, <2 x half> <half 1.0, half 1.0>, <2 x half> %load 58 store <2 x half> %sel, <2 x half> addrspace(1)* %gep, align 4 59 ret void 60} 61 62; GCN-LABEL: {{^}}test_vopc_class: 63; GFX1032: v_cmp_class_f32_e64 [[C:vcc_lo|s[0-9:]+]], s{{[0-9]+}}, 0x204 64; GFX1032: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, [[C]] 65; GFX1064: v_cmp_class_f32_e64 [[C:vcc|s\[[0-9:]+\]]], s{{[0-9]+}}, 0x204 66; GFX1064: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, [[C]]{{$}} 67define amdgpu_kernel void @test_vopc_class(i32 addrspace(1)* %out, float %x) #0 { 68 %fabs = tail call float @llvm.fabs.f32(float %x) 69 %cmp = fcmp oeq float %fabs, 0x7FF0000000000000 70 %ext = zext i1 %cmp to i32 71 store i32 %ext, i32 addrspace(1)* %out, align 4 72 ret void 73} 74 75; GCN-LABEL: {{^}}test_vcmp_vcnd_f16: 76; GFX1032: v_cmp_neq_f16_e64 [[C:vcc_lo|s\[[0-9:]+\]]], 0x7c00, s{{[0-9]+}} 77; GFX1032: v_cndmask_b32_e32 v{{[0-9]+}}, 0x3c00, v{{[0-9]+}}, [[C]] 78 79; GFX1064: v_cmp_neq_f16_e64 [[C:vcc|s\[[0-9:]+\]]], 0x7c00, s{{[0-9]+}} 80; GFX1064: v_cndmask_b32_e32 v{{[0-9]+}}, 0x3c00, v{{[0-9]+}}, [[C]]{{$}} 81define amdgpu_kernel void @test_vcmp_vcnd_f16(half addrspace(1)* %out, half %x) #0 { 82 %cmp = fcmp oeq half %x, 0x7FF0000000000000 83 %sel = select i1 %cmp, half 1.0, half %x 84 store half %sel, half addrspace(1)* %out, align 2 85 ret void 86} 87 88; GCN-LABEL: {{^}}test_vop3_cmp_f32_sop_and: 89; GFX1032: v_cmp_nge_f32_e32 vcc_lo, 0, v{{[0-9]+}} 90; GFX1032: v_cmp_nle_f32_e64 [[C2:s[0-9]+]], 1.0, v{{[0-9]+}} 91; GFX1032: s_and_b32 [[AND:s[0-9]+]], vcc_lo, [[C2]] 92; GFX1032: v_cndmask_b32_e64 v{{[0-9]+}}, 2.0, 1.0, [[AND]] 93; GFX1064: v_cmp_nge_f32_e32 vcc, 0, v{{[0-9]+}} 94; GFX1064: v_cmp_nle_f32_e64 [[C2:s\[[0-9:]+\]]], 1.0, v{{[0-9]+}} 95; GFX1064: s_and_b64 [[AND:s\[[0-9:]+\]]], vcc, [[C2]] 96; GFX1064: v_cndmask_b32_e64 v{{[0-9]+}}, 2.0, 1.0, [[AND]] 97define amdgpu_kernel void @test_vop3_cmp_f32_sop_and(float addrspace(1)* %arg) { 98 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 99 %gep = getelementptr inbounds float, float addrspace(1)* %arg, i32 %lid 100 %load = load float, float addrspace(1)* %gep, align 4 101 %cmp = fcmp ugt float %load, 0.0 102 %cmp2 = fcmp ult float %load, 1.0 103 %and = and i1 %cmp, %cmp2 104 %sel = select i1 %and, float 1.0, float 2.0 105 store float %sel, float addrspace(1)* %gep, align 4 106 ret void 107} 108 109; GCN-LABEL: {{^}}test_vop3_cmp_i32_sop_xor: 110; GFX1032: v_cmp_lt_i32_e32 vcc_lo, 0, v{{[0-9]+}} 111; GFX1032: v_cmp_gt_i32_e64 [[C2:s[0-9]+]], 1, v{{[0-9]+}} 112; GFX1032: s_xor_b32 [[AND:s[0-9]+]], vcc_lo, [[C2]] 113; GFX1032: v_cndmask_b32_e64 v{{[0-9]+}}, 2, 1, [[AND]] 114; GFX1064: v_cmp_lt_i32_e32 vcc, 0, v{{[0-9]+}} 115; GFX1064: v_cmp_gt_i32_e64 [[C2:s\[[0-9:]+\]]], 1, v{{[0-9]+}} 116; GFX1064: s_xor_b64 [[AND:s\[[0-9:]+\]]], vcc, [[C2]] 117; GFX1064: v_cndmask_b32_e64 v{{[0-9]+}}, 2, 1, [[AND]] 118define amdgpu_kernel void @test_vop3_cmp_i32_sop_xor(i32 addrspace(1)* %arg) { 119 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 120 %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %lid 121 %load = load i32, i32 addrspace(1)* %gep, align 4 122 %cmp = icmp sgt i32 %load, 0 123 %cmp2 = icmp slt i32 %load, 1 124 %xor = xor i1 %cmp, %cmp2 125 %sel = select i1 %xor, i32 1, i32 2 126 store i32 %sel, i32 addrspace(1)* %gep, align 4 127 ret void 128} 129 130; GCN-LABEL: {{^}}test_vop3_cmp_u32_sop_or: 131; GFX1032: v_cmp_lt_u32_e32 vcc_lo, 3, v{{[0-9]+}} 132; GFX1032: v_cmp_gt_u32_e64 [[C2:s[0-9]+]], 2, v{{[0-9]+}} 133; GFX1032: s_or_b32 [[AND:s[0-9]+]], vcc_lo, [[C2]] 134; GFX1032: v_cndmask_b32_e64 v{{[0-9]+}}, 2, 1, [[AND]] 135; GFX1064: v_cmp_lt_u32_e32 vcc, 3, v{{[0-9]+}} 136; GFX1064: v_cmp_gt_u32_e64 [[C2:s\[[0-9:]+\]]], 2, v{{[0-9]+}} 137; GFX1064: s_or_b64 [[AND:s\[[0-9:]+\]]], vcc, [[C2]] 138; GFX1064: v_cndmask_b32_e64 v{{[0-9]+}}, 2, 1, [[AND]] 139define amdgpu_kernel void @test_vop3_cmp_u32_sop_or(i32 addrspace(1)* %arg) { 140 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 141 %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %lid 142 %load = load i32, i32 addrspace(1)* %gep, align 4 143 %cmp = icmp ugt i32 %load, 3 144 %cmp2 = icmp ult i32 %load, 2 145 %or = or i1 %cmp, %cmp2 146 %sel = select i1 %or, i32 1, i32 2 147 store i32 %sel, i32 addrspace(1)* %gep, align 4 148 ret void 149} 150 151; GCN-LABEL: {{^}}test_mask_if: 152; GFX1032: s_and_saveexec_b32 s{{[0-9]+}}, vcc_lo 153; GFX1064: s_and_saveexec_b64 s[{{[0-9:]+}}], vcc{{$}} 154; GCN: s_cbranch_execz 155define amdgpu_kernel void @test_mask_if(i32 addrspace(1)* %arg) #0 { 156 %lid = tail call i32 @llvm.amdgcn.workitem.id.x() 157 %cmp = icmp ugt i32 %lid, 10 158 br i1 %cmp, label %if, label %endif 159 160if: 161 store i32 0, i32 addrspace(1)* %arg, align 4 162 br label %endif 163 164endif: 165 ret void 166} 167 168; GCN-LABEL: {{^}}test_loop_with_if: 169; GFX1032: s_or_b32 s{{[0-9]+}}, vcc_lo, s{{[0-9]+}} 170; GFX1032: s_andn2_b32 exec_lo, exec_lo, s{{[0-9]+}} 171; GFX1064: s_or_b64 s[{{[0-9:]+}}], vcc, s[{{[0-9:]+}}] 172; GFX1064: s_andn2_b64 exec, exec, s[{{[0-9:]+}}] 173; GCN: s_cbranch_execz 174; GCN: BB{{.*}}: 175; GFX1032: s_and_saveexec_b32 s{{[0-9]+}}, vcc_lo 176; GFX1064: s_and_saveexec_b64 s[{{[0-9:]+}}], vcc{{$}} 177; GCN: s_cbranch_execz 178; GCN: ; %bb.{{[0-9]+}}: 179; GCN: BB{{.*}}: 180; GFX1032: s_xor_b32 s{{[0-9]+}}, exec_lo, s{{[0-9]+}} 181; GFX1064: s_xor_b64 s[{{[0-9:]+}}], exec, s[{{[0-9:]+}}] 182; GCN: ; %bb.{{[0-9]+}}: 183; GCN: ; %bb.{{[0-9]+}}: 184; GFX1032: s_or_b32 exec_lo, exec_lo, s{{[0-9]+}} 185; GFX1032: s_and_saveexec_b32 s{{[0-9]+}}, s{{[0-9]+}} 186; GFX1064: s_or_b64 exec, exec, s[{{[0-9:]+}}] 187; GFX1064: s_and_saveexec_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}]{{$}} 188; GCN: s_cbranch_execz BB 189; GCN: ; %bb.{{[0-9]+}}: 190; GCN: BB{{.*}}: 191; GCN: s_endpgm 192define amdgpu_kernel void @test_loop_with_if(i32 addrspace(1)* %arg) #0 { 193bb: 194 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() 195 br label %bb2 196 197bb1: 198 ret void 199 200bb2: 201 %tmp3 = phi i32 [ 0, %bb ], [ %tmp15, %bb13 ] 202 %tmp4 = icmp slt i32 %tmp3, %tmp 203 br i1 %tmp4, label %bb5, label %bb11 204 205bb5: 206 %tmp6 = sext i32 %tmp3 to i64 207 %tmp7 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp6 208 %tmp8 = load i32, i32 addrspace(1)* %tmp7, align 4 209 %tmp9 = icmp sgt i32 %tmp8, 10 210 br i1 %tmp9, label %bb10, label %bb11 211 212bb10: 213 store i32 %tmp, i32 addrspace(1)* %tmp7, align 4 214 br label %bb13 215 216bb11: 217 %tmp12 = sdiv i32 %tmp3, 2 218 br label %bb13 219 220bb13: 221 %tmp14 = phi i32 [ %tmp3, %bb10 ], [ %tmp12, %bb11 ] 222 %tmp15 = add nsw i32 %tmp14, 1 223 %tmp16 = icmp slt i32 %tmp14, 255 224 br i1 %tmp16, label %bb2, label %bb1 225} 226 227; GCN-LABEL: {{^}}test_loop_with_if_else_break: 228; GFX1032: s_and_saveexec_b32 s{{[0-9]+}}, vcc_lo 229; GFX1064: s_and_saveexec_b64 s[{{[0-9:]+}}], vcc{{$}} 230; GCN: s_cbranch_execz 231; GCN: ; %bb.{{[0-9]+}}: ; %.preheader 232; GCN: BB{{.*}}: 233 234; GCN: global_store_dword 235; GFX1032: s_or_b32 [[MASK0:s[0-9]+]], [[MASK0]], vcc_lo 236; GFX1064: s_or_b64 [[MASK0:s\[[0-9:]+\]]], [[MASK0]], vcc 237; GFX1032: s_andn2_b32 [[MASK1:s[0-9]+]], [[MASK1]], exec_lo 238; GFX1064: s_andn2_b64 [[MASK1:s\[[0-9:]+\]]], [[MASK1]], exec 239; GFX1032: s_and_b32 [[MASK0]], [[MASK0]], exec_lo 240; GFX1064: s_and_b64 [[MASK0]], [[MASK0]], exec 241; GFX1032: s_or_b32 [[MASK1]], [[MASK1]], [[MASK0]] 242; GFX1064: s_or_b64 [[MASK1]], [[MASK1]], [[MASK0]] 243; GCN: BB{{.*}}: ; %Flow 244; GFX1032: s_and_b32 [[TMP0:s[0-9]+]], exec_lo, [[MASK1]] 245; GFX1064: s_and_b64 [[TMP0:s\[[0-9:]+\]]], exec, [[MASK1]] 246; GFX1032: s_or_b32 [[ACC:s[0-9]+]], [[TMP0]], [[ACC]] 247; GFX1064: s_or_b64 [[ACC:s\[[0-9:]+\]]], [[TMP0]], [[ACC]] 248; GFX1032: s_andn2_b32 exec_lo, exec_lo, [[ACC]] 249; GFX1064: s_andn2_b64 exec, exec, [[ACC]] 250; GCN: s_cbranch_execz 251; GCN: BB{{.*}}: 252 253; GFX1032: s_or_b32 [[MASK1]], [[MASK1]], exec_lo 254; GFX1064: s_or_b64 [[MASK1]], [[MASK1]], exec 255; GCN: global_load_dword [[LOAD:v[0-9]+]] 256; GFX1032: v_cmp_gt_i32_e32 vcc_lo, 11, [[LOAD]] 257; GFX1064: v_cmp_gt_i32_e32 vcc, 11, [[LOAD]] 258define amdgpu_kernel void @test_loop_with_if_else_break(i32 addrspace(1)* %arg) #0 { 259bb: 260 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() 261 %tmp1 = icmp eq i32 %tmp, 0 262 br i1 %tmp1, label %.loopexit, label %.preheader 263 264.preheader: 265 br label %bb2 266 267bb2: 268 %tmp3 = phi i32 [ %tmp9, %bb8 ], [ 0, %.preheader ] 269 %tmp4 = zext i32 %tmp3 to i64 270 %tmp5 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp4 271 %tmp6 = load i32, i32 addrspace(1)* %tmp5, align 4 272 %tmp7 = icmp sgt i32 %tmp6, 10 273 br i1 %tmp7, label %bb8, label %.loopexit 274 275bb8: 276 store i32 %tmp, i32 addrspace(1)* %tmp5, align 4 277 %tmp9 = add nuw nsw i32 %tmp3, 1 278 %tmp10 = icmp ult i32 %tmp9, 256 279 %tmp11 = icmp ult i32 %tmp9, %tmp 280 %tmp12 = and i1 %tmp10, %tmp11 281 br i1 %tmp12, label %bb2, label %.loopexit 282 283.loopexit: 284 ret void 285} 286 287; GCN-LABEL: {{^}}test_addc_vop2b: 288; GFX1032: v_add_co_u32_e64 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, s{{[0-9]+}} 289; GFX1032: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, s{{[0-9]+}}, v{{[0-9]+}}, vcc_lo 290; GFX1064: v_add_co_u32_e64 v{{[0-9]+}}, vcc, v{{[0-9]+}}, s{{[0-9]+}} 291; GFX1064: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}, vcc{{$}} 292define amdgpu_kernel void @test_addc_vop2b(i64 addrspace(1)* %arg, i64 %arg1) #0 { 293bb: 294 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() 295 %tmp3 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %tmp 296 %tmp4 = load i64, i64 addrspace(1)* %tmp3, align 8 297 %tmp5 = add nsw i64 %tmp4, %arg1 298 store i64 %tmp5, i64 addrspace(1)* %tmp3, align 8 299 ret void 300} 301 302; GCN-LABEL: {{^}}test_subbrev_vop2b: 303; GFX1032: v_sub_co_u32_e64 v{{[0-9]+}}, [[A0:s[0-9]+|vcc_lo]], v{{[0-9]+}}, s{{[0-9]+}}{{$}} 304; GFX1032: v_subrev_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[A0]]{{$}} 305; GFX1064: v_sub_co_u32_e64 v{{[0-9]+}}, [[A0:s\[[0-9:]+\]|vcc]], v{{[0-9]+}}, s{{[0-9]+}}{{$}} 306; GFX1064: v_subrev_co_ci_u32_e32 v{{[0-9]+}}, vcc, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[A0]]{{$}} 307define amdgpu_kernel void @test_subbrev_vop2b(i64 addrspace(1)* %arg, i64 %arg1) #0 { 308bb: 309 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() 310 %tmp3 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %tmp 311 %tmp4 = load i64, i64 addrspace(1)* %tmp3, align 8 312 %tmp5 = sub nsw i64 %tmp4, %arg1 313 store i64 %tmp5, i64 addrspace(1)* %tmp3, align 8 314 ret void 315} 316 317; GCN-LABEL: {{^}}test_subb_vop2b: 318; GFX1032: v_sub_co_u32_e64 v{{[0-9]+}}, [[A0:s[0-9]+|vcc_lo]], s{{[0-9]+}}, v{{[0-9]+}}{{$}} 319; GFX1032: v_sub_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, {{[vs][0-9]+}}, v{{[0-9]+}}, [[A0]]{{$}} 320; GFX1064: v_sub_co_u32_e64 v{{[0-9]+}}, [[A0:s\[[0-9:]+\]|vcc]], s{{[0-9]+}}, v{{[0-9]+}}{{$}} 321; GFX1064: v_sub_co_ci_u32_e32 v{{[0-9]+}}, vcc, {{[vs][0-9]+}}, v{{[0-9]+}}, [[A0]]{{$}} 322define amdgpu_kernel void @test_subb_vop2b(i64 addrspace(1)* %arg, i64 %arg1) #0 { 323bb: 324 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() 325 %tmp3 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %tmp 326 %tmp4 = load i64, i64 addrspace(1)* %tmp3, align 8 327 %tmp5 = sub nsw i64 %arg1, %tmp4 328 store i64 %tmp5, i64 addrspace(1)* %tmp3, align 8 329 ret void 330} 331 332; GCN-LABEL: {{^}}test_udiv64: 333; GFX1032: v_add_co_u32_e64 v{{[0-9]+}}, [[SDST:s[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} 334; GFX1032: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, 0, v{{[0-9]+}}, vcc_lo 335; GFX1032: v_add_co_ci_u32_e64 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, v{{[0-9]+}}, [[SDST]] 336; GFX1032: v_add_co_u32_e64 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, v{{[0-9]+}} 337; GFX1032: v_add_co_u32_e64 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, v{{[0-9]+}} 338; GFX1032: v_add_co_u32_e64 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, v{{[0-9]+}} 339; GFX1032: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, 0, v{{[0-9]+}}, vcc_lo 340; GFX1032: v_sub_co_u32_e64 v{{[0-9]+}}, vcc_lo, s{{[0-9]+}}, v{{[0-9]+}} 341; GFX1032: v_subrev_co_ci_u32_e64 v{{[0-9]+}}, s{{[0-9]+}}, {{[vs][0-9]+}}, v{{[0-9]+}}, vcc_lo 342; GFX1032: v_sub_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, {{[vs][0-9]+}}, v{{[0-9]+}}, vcc_lo 343; GFX1064: v_add_co_u32_e64 v{{[0-9]+}}, [[SDST:s\[[0-9:]+\]]], v{{[0-9]+}}, v{{[0-9]+}} 344; GFX1064: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc{{$}} 345; GFX1064: v_add_co_ci_u32_e64 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}, [[SDST]] 346; GFX1064: v_add_co_u32_e64 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} 347; GFX1064: v_add_co_u32_e64 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} 348; GFX1064: v_add_co_u32_e64 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}} 349; GFX1064: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc{{$}} 350; GFX1064: v_sub_co_u32_e64 v{{[0-9]+}}, s[{{[0-9:]+}}], s{{[0-9]+}}, v{{[0-9]+}} 351; GFX1064: v_subrev_co_ci_u32_e64 v{{[0-9]+}}, vcc, {{[vs][0-9]+}}, v{{[0-9]+}}, s[{{[0-9:]+}}] 352; GFX1064: v_sub_co_ci_u32_e64 v{{[0-9]+}}, s[{{[0-9:]+}}], {{[vs][0-9]+}}, v{{[0-9]+}}, s[{{[0-9:]+}}] 353define amdgpu_kernel void @test_udiv64(i64 addrspace(1)* %arg) #0 { 354bb: 355 %tmp = getelementptr inbounds i64, i64 addrspace(1)* %arg, i64 1 356 %tmp1 = load i64, i64 addrspace(1)* %tmp, align 8 357 %tmp2 = load i64, i64 addrspace(1)* %arg, align 8 358 %tmp3 = udiv i64 %tmp1, %tmp2 359 %tmp4 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i64 2 360 store i64 %tmp3, i64 addrspace(1)* %tmp4, align 8 361 ret void 362} 363 364; GCN-LABEL: {{^}}test_div_scale_f32: 365; GFX1032: v_div_scale_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 366; GFX1064: v_div_scale_f32 v{{[0-9]+}}, s[{{[0-9:]+}}], v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 367define amdgpu_kernel void @test_div_scale_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 { 368 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 369 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid 370 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 371 372 %a = load volatile float, float addrspace(1)* %gep.0, align 4 373 %b = load volatile float, float addrspace(1)* %gep.1, align 4 374 375 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 false) nounwind readnone 376 %result0 = extractvalue { float, i1 } %result, 0 377 store float %result0, float addrspace(1)* %out, align 4 378 ret void 379} 380 381; GCN-LABEL: {{^}}test_div_scale_f64: 382; GFX1032: v_div_scale_f64 v[{{[0-9:]+}}], s{{[0-9]+}}, v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}] 383; GFX1064: v_div_scale_f64 v[{{[0-9:]+}}], s[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}] 384define amdgpu_kernel void @test_div_scale_f64(double addrspace(1)* %out, double addrspace(1)* %aptr, double addrspace(1)* %in) #0 { 385 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 386 %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid 387 %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 388 389 %a = load volatile double, double addrspace(1)* %gep.0, align 8 390 %b = load volatile double, double addrspace(1)* %gep.1, align 8 391 392 %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 true) nounwind readnone 393 %result0 = extractvalue { double, i1 } %result, 0 394 store double %result0, double addrspace(1)* %out, align 8 395 ret void 396} 397 398; GCN-LABEL: {{^}}test_mad_i64_i32: 399; GFX1032: v_mad_i64_i32 v[{{[0-9:]+}}], s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v[{{[0-9:]+}}] 400; GFX1064: v_mad_i64_i32 v[{{[0-9:]+}}], s[{{[0-9:]+}}], v{{[0-9]+}}, v{{[0-9]+}}, v[{{[0-9:]+}}] 401define i64 @test_mad_i64_i32(i32 %arg0, i32 %arg1, i64 %arg2) #0 { 402 %sext0 = sext i32 %arg0 to i64 403 %sext1 = sext i32 %arg1 to i64 404 %mul = mul i64 %sext0, %sext1 405 %mad = add i64 %mul, %arg2 406 ret i64 %mad 407} 408 409; GCN-LABEL: {{^}}test_mad_u64_u32: 410; GFX1032: v_mad_u64_u32 v[{{[0-9:]+}}], s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v[{{[0-9:]+}}] 411; GFX1064: v_mad_u64_u32 v[{{[0-9:]+}}], s[{{[0-9:]+}}], v{{[0-9]+}}, v{{[0-9]+}}, v[{{[0-9:]+}}] 412define i64 @test_mad_u64_u32(i32 %arg0, i32 %arg1, i64 %arg2) #0 { 413 %sext0 = zext i32 %arg0 to i64 414 %sext1 = zext i32 %arg1 to i64 415 %mul = mul i64 %sext0, %sext1 416 %mad = add i64 %mul, %arg2 417 ret i64 %mad 418} 419 420; GCN-LABEL: {{^}}test_div_fmas_f32: 421; GFX1032: v_cmp_eq_u32_e64 vcc_lo, 422; GFX1064: v_cmp_eq_u32_e64 vcc, 423; GCN: v_div_fmas_f32 v{{[0-9]+}}, {{[vs][0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 424define amdgpu_kernel void @test_div_fmas_f32(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind { 425 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %d) nounwind readnone 426 store float %result, float addrspace(1)* %out, align 4 427 ret void 428} 429 430; GCN-LABEL: {{^}}test_div_fmas_f64: 431; GFX1032: v_cmp_eq_u32_e64 vcc_lo, 432; GFX1064: v_cmp_eq_u32_e64 vcc, 433; GCN-DAG: v_div_fmas_f64 v[{{[0-9:]+}}], {{[vs]}}[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}] 434define amdgpu_kernel void @test_div_fmas_f64(double addrspace(1)* %out, double %a, double %b, double %c, i1 %d) nounwind { 435 %result = call double @llvm.amdgcn.div.fmas.f64(double %a, double %b, double %c, i1 %d) nounwind readnone 436 store double %result, double addrspace(1)* %out, align 8 437 ret void 438} 439 440; GCN-LABEL: {{^}}test_div_fmas_f32_i1_phi_vcc: 441; GFX1032: s_mov_b32 [[VCC:vcc_lo]], 0{{$}} 442; GFX1064: s_mov_b64 [[VCC:vcc]], 0{{$}} 443; GFX1032: s_and_saveexec_b32 [[SAVE:s[0-9]+]], s{{[0-9]+}}{{$}} 444; GFX1064: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], s[{{[0-9:]+}}]{{$}} 445 446; GCN: load_dword [[LOAD:v[0-9]+]] 447; GCN: v_cmp_ne_u32_e32 [[VCC]], 0, [[LOAD]] 448 449; GCN: BB{{[0-9_]+}}: 450; GFX1032: s_or_b32 exec_lo, exec_lo, [[SAVE]] 451; GFX1064: s_or_b64 exec, exec, [[SAVE]] 452; GCN: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} 453define amdgpu_kernel void @test_div_fmas_f32_i1_phi_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 addrspace(1)* %dummy) #0 { 454entry: 455 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 456 %gep.out = getelementptr float, float addrspace(1)* %out, i32 2 457 %gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid 458 %gep.b = getelementptr float, float addrspace(1)* %gep.a, i32 1 459 %gep.c = getelementptr float, float addrspace(1)* %gep.a, i32 2 460 461 %a = load float, float addrspace(1)* %gep.a 462 %b = load float, float addrspace(1)* %gep.b 463 %c = load float, float addrspace(1)* %gep.c 464 465 %cmp0 = icmp eq i32 %tid, 0 466 br i1 %cmp0, label %bb, label %exit 467 468bb: 469 %val = load volatile i32, i32 addrspace(1)* %dummy 470 %cmp1 = icmp ne i32 %val, 0 471 br label %exit 472 473exit: 474 %cond = phi i1 [false, %entry], [%cmp1, %bb] 475 %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %cond) nounwind readnone 476 store float %result, float addrspace(1)* %gep.out, align 4 477 ret void 478} 479 480; GCN-LABEL: {{^}}fdiv_f32: 481; GFX1032: v_div_scale_f32 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} 482; GFX1064: v_div_scale_f32 v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} 483; GCN: v_rcp_f32_e32 v{{[0-9]+}}, v{{[0-9]+}} 484; GFX1032: v_div_scale_f32 v{{[0-9]+}}, vcc_lo, s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} 485; GFX1064: v_div_scale_f32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} 486 487; GCN-NOT: vcc 488; GCN: v_div_fmas_f32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 489define amdgpu_kernel void @fdiv_f32(float addrspace(1)* %out, float %a, float %b) #0 { 490entry: 491 %fdiv = fdiv float %a, %b 492 store float %fdiv, float addrspace(1)* %out 493 ret void 494} 495 496; GCN-LABEL: {{^}}test_br_cc_f16: 497; GFX1032: v_cmp_nlt_f16_e32 vcc_lo, 498; GFX1032: s_and_b32 vcc_lo, exec_lo, vcc_lo 499; GFX1064: v_cmp_nlt_f16_e32 vcc, 500; GFX1064: s_and_b64 vcc, exec, vcc{{$}} 501; GCN-NEXT: s_cbranch_vccnz 502define amdgpu_kernel void @test_br_cc_f16( 503 half addrspace(1)* %r, 504 half addrspace(1)* %a, 505 half addrspace(1)* %b) { 506entry: 507 %a.val = load half, half addrspace(1)* %a 508 %b.val = load half, half addrspace(1)* %b 509 %fcmp = fcmp olt half %a.val, %b.val 510 br i1 %fcmp, label %one, label %two 511 512one: 513 store half %a.val, half addrspace(1)* %r 514 ret void 515 516two: 517 store half %b.val, half addrspace(1)* %r 518 ret void 519} 520 521; GCN-LABEL: {{^}}test_brcc_i1: 522; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 0 523; GCN-NEXT: s_cbranch_scc1 524define amdgpu_kernel void @test_brcc_i1(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i1 %val) #0 { 525 %cmp0 = icmp ne i1 %val, 0 526 br i1 %cmp0, label %store, label %end 527 528store: 529 store i32 222, i32 addrspace(1)* %out 530 ret void 531 532end: 533 ret void 534} 535 536; GCN-LABEL: {{^}}test_preserve_condition_undef_flag: 537; GFX1032-DAG: v_cmp_nlt_f32_e64 s{{[0-9]+}}, s{{[0-9]+}}, 1.0 538; GFX1032-DAG: v_cmp_ngt_f32_e64 s{{[0-9]+}}, s{{[0-9]+}}, 0 539; GFX1032: v_cmp_nlt_f32_e64 s{{[0-9]+}}, s{{[0-9]+}}, 1.0 540; GFX1032: s_or_b32 [[OR1:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}} 541; GFX1032: s_or_b32 [[OR2:s[0-9]+]], [[OR1]], s{{[0-9]+}} 542; GFX1032: s_and_b32 vcc_lo, exec_lo, [[OR2]] 543; GFX1064-DAG: v_cmp_nlt_f32_e64 s[{{[0-9:]+}}], s{{[0-9]+}}, 1.0 544; GFX1064-DAG: v_cmp_ngt_f32_e64 s[{{[0-9:]+}}], s{{[0-9]+}}, 0 545; GFX1064: v_cmp_nlt_f32_e64 s[{{[0-9:]+}}], s{{[0-9]+}}, 1.0 546; GFX1064: s_or_b64 [[OR1:s\[[0-9:]+\]]], s[{{[0-9:]+}}], s[{{[0-9:]+}}] 547; GFX1064: s_or_b64 [[OR2:s\[[0-9:]+\]]], [[OR1]], s[{{[0-9:]+}}] 548; GFX1064: s_and_b64 vcc, exec, [[OR2]] 549; GCN: s_cbranch_vccnz 550define amdgpu_kernel void @test_preserve_condition_undef_flag(float %arg, i32 %arg1, float %arg2) #0 { 551bb0: 552 %tmp = icmp sgt i32 %arg1, 4 553 %undef = call i1 @llvm.amdgcn.class.f32(float undef, i32 undef) 554 %tmp4 = select i1 %undef, float %arg, float 1.000000e+00 555 %tmp5 = fcmp ogt float %arg2, 0.000000e+00 556 %tmp6 = fcmp olt float %arg2, 1.000000e+00 557 %tmp7 = fcmp olt float %arg, %tmp4 558 %tmp8 = and i1 %tmp5, %tmp6 559 %tmp9 = and i1 %tmp8, %tmp7 560 br i1 %tmp9, label %bb1, label %bb2 561 562bb1: 563 store volatile i32 0, i32 addrspace(1)* undef 564 br label %bb2 565 566bb2: 567 ret void 568} 569 570; GCN-LABEL: {{^}}test_invert_true_phi_cond_break_loop: 571; GFX1032: s_xor_b32 s{{[0-9]+}}, s{{[0-9]+}}, -1 572; GFX1032: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} 573; GFX1064: s_xor_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}], -1 574; GFX1064: s_or_b64 s[{{[0-9:]+}}], s[{{[0-9:]+}}], s[{{[0-9:]+}}] 575define amdgpu_kernel void @test_invert_true_phi_cond_break_loop(i32 %arg) #0 { 576bb: 577 %id = call i32 @llvm.amdgcn.workitem.id.x() 578 %tmp = sub i32 %id, %arg 579 br label %bb1 580 581bb1: ; preds = %Flow, %bb 582 %lsr.iv = phi i32 [ undef, %bb ], [ %tmp2, %Flow ] 583 %lsr.iv.next = add i32 %lsr.iv, 1 584 %cmp0 = icmp slt i32 %lsr.iv.next, 0 585 br i1 %cmp0, label %bb4, label %Flow 586 587bb4: ; preds = %bb1 588 %load = load volatile i32, i32 addrspace(1)* undef, align 4 589 %cmp1 = icmp sge i32 %tmp, %load 590 br label %Flow 591 592Flow: ; preds = %bb4, %bb1 593 %tmp2 = phi i32 [ %lsr.iv.next, %bb4 ], [ undef, %bb1 ] 594 %tmp3 = phi i1 [ %cmp1, %bb4 ], [ true, %bb1 ] 595 br i1 %tmp3, label %bb1, label %bb9 596 597bb9: ; preds = %Flow 598 store volatile i32 7, i32 addrspace(3)* undef 599 ret void 600} 601 602; GCN-LABEL: {{^}}test_movrels_extract_neg_offset_vgpr: 603; GFX1032: v_cmp_eq_u32_e32 vcc_lo, 1, v{{[0-9]+}} 604; GFX1032: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc_lo 605; GFX1032: v_cmp_ne_u32_e32 vcc_lo, 2, v{{[0-9]+}} 606; GFX1032: v_cndmask_b32_e32 v{{[0-9]+}}, 2, v{{[0-9]+}}, vcc_lo 607; GFX1032: v_cmp_ne_u32_e32 vcc_lo, 3, v{{[0-9]+}} 608; GFX1032: v_cndmask_b32_e32 v{{[0-9]+}}, 3, v{{[0-9]+}}, vcc_lo 609; GFX1064: v_cmp_eq_u32_e32 vcc, 1, v{{[0-9]+}} 610; GFX1064: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc 611; GFX1064: v_cmp_ne_u32_e32 vcc, 2, v{{[0-9]+}} 612; GFX1064: v_cndmask_b32_e32 v{{[0-9]+}}, 2, v{{[0-9]+}}, vcc 613; GFX1064: v_cmp_ne_u32_e32 vcc, 3, v{{[0-9]+}} 614; GFX1064: v_cndmask_b32_e32 v{{[0-9]+}}, 3, v{{[0-9]+}}, vcc 615define amdgpu_kernel void @test_movrels_extract_neg_offset_vgpr(i32 addrspace(1)* %out) #0 { 616entry: 617 %id = call i32 @llvm.amdgcn.workitem.id.x() #1 618 %index = add i32 %id, -512 619 %value = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 %index 620 store i32 %value, i32 addrspace(1)* %out 621 ret void 622} 623 624; GCN-LABEL: {{^}}test_set_inactive: 625; GFX1032: s_not_b32 exec_lo, exec_lo 626; GFX1032: v_mov_b32_e32 {{v[0-9]+}}, 42 627; GFX1032: s_not_b32 exec_lo, exec_lo 628; GFX1064: s_not_b64 exec, exec{{$}} 629; GFX1064: v_mov_b32_e32 {{v[0-9]+}}, 42 630; GFX1064: s_not_b64 exec, exec{{$}} 631define amdgpu_kernel void @test_set_inactive(i32 addrspace(1)* %out, i32 %in) #0 { 632 %tmp = call i32 @llvm.amdgcn.set.inactive.i32(i32 %in, i32 42) 633 store i32 %tmp, i32 addrspace(1)* %out 634 ret void 635} 636 637; GCN-LABEL: {{^}}test_set_inactive_64: 638; GFX1032: s_not_b32 exec_lo, exec_lo 639; GFX1032: v_mov_b32_e32 {{v[0-9]+}}, 0 640; GFX1032: v_mov_b32_e32 {{v[0-9]+}}, 0 641; GFX1032: s_not_b32 exec_lo, exec_lo 642; GFX1064: s_not_b64 exec, exec{{$}} 643; GFX1064: v_mov_b32_e32 {{v[0-9]+}}, 0 644; GFX1064: v_mov_b32_e32 {{v[0-9]+}}, 0 645; GFX1064: s_not_b64 exec, exec{{$}} 646define amdgpu_kernel void @test_set_inactive_64(i64 addrspace(1)* %out, i64 %in) #0 { 647 %tmp = call i64 @llvm.amdgcn.set.inactive.i64(i64 %in, i64 0) 648 store i64 %tmp, i64 addrspace(1)* %out 649 ret void 650} 651 652; GCN-LABEL: {{^}}test_kill_i1_terminator_float: 653; GFX1032: s_mov_b32 exec_lo, 0 654; GFX1064: s_mov_b64 exec, 0 655define amdgpu_ps void @test_kill_i1_terminator_float() #0 { 656 call void @llvm.amdgcn.kill(i1 false) 657 ret void 658} 659 660; GCN-LABEL: {{^}}test_kill_i1_terminator_i1: 661; GFX1032: s_mov_b32 [[LIVE:s[0-9]+]], exec_lo 662; GFX1032: s_or_b32 [[OR:s[0-9]+]], 663; GFX1032: s_xor_b32 [[KILL:s[0-9]+]], [[OR]], exec_lo 664; GFX1032: s_andn2_b32 [[MASK:s[0-9]+]], [[LIVE]], [[KILL]] 665; GFX1032: s_and_b32 exec_lo, exec_lo, [[MASK]] 666; GFX1064: s_mov_b64 [[LIVE:s\[[0-9:]+\]]], exec 667; GFX1064: s_or_b64 [[OR:s\[[0-9:]+\]]], 668; GFX1064: s_xor_b64 [[KILL:s\[[0-9:]+\]]], [[OR]], exec 669; GFX1064: s_andn2_b64 [[MASK:s\[[0-9:]+\]]], [[LIVE]], [[KILL]] 670; GFX1064: s_and_b64 exec, exec, [[MASK]] 671define amdgpu_gs void @test_kill_i1_terminator_i1(i32 %a, i32 %b, i32 %c, i32 %d) #0 { 672 %c1 = icmp slt i32 %a, %b 673 %c2 = icmp slt i32 %c, %d 674 %x = or i1 %c1, %c2 675 call void @llvm.amdgcn.kill(i1 %x) 676 call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float 0.0, float 0.0, float 0.0, float 0.0, i1 false, i1 false) 677 ret void 678} 679 680; GCN-LABEL: {{^}}test_loop_vcc: 681; GFX1032: v_cmp_lt_f32_e32 vcc_lo, 682; GFX1064: v_cmp_lt_f32_e32 vcc, 683; GCN: s_cbranch_vccz 684define amdgpu_ps <4 x float> @test_loop_vcc(<4 x float> %in) #0 { 685entry: 686 br label %loop 687 688loop: 689 %ctr.iv = phi float [ 0.0, %entry ], [ %ctr.next, %body ] 690 %c.iv = phi <4 x float> [ %in, %entry ], [ %c.next, %body ] 691 %cc = fcmp ogt float %ctr.iv, 7.0 692 br i1 %cc, label %break, label %body 693 694body: 695 %c.iv0 = extractelement <4 x float> %c.iv, i32 0 696 %c.next = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %c.iv0, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0) 697 %ctr.next = fadd float %ctr.iv, 2.0 698 br label %loop 699 700break: 701 ret <4 x float> %c.iv 702} 703 704; GCN-LABEL: {{^}}test_wwm1: 705; GFX1032: s_or_saveexec_b32 [[SAVE:s[0-9]+]], -1 706; GFX1032: s_mov_b32 exec_lo, [[SAVE]] 707; GFX1064: s_or_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], -1 708; GFX1064: s_mov_b64 exec, [[SAVE]] 709define amdgpu_ps float @test_wwm1(i32 inreg %idx0, i32 inreg %idx1, float %src0, float %src1) { 710main_body: 711 %out = fadd float %src0, %src1 712 %out.0 = call float @llvm.amdgcn.wwm.f32(float %out) 713 ret float %out.0 714} 715 716; GCN-LABEL: {{^}}test_wwm2: 717; GFX1032: v_cmp_gt_u32_e32 vcc_lo, 32, v{{[0-9]+}} 718; GFX1032: s_and_saveexec_b32 [[SAVE1:s[0-9]+]], vcc_lo 719; GFX1032: s_or_saveexec_b32 [[SAVE2:s[0-9]+]], -1 720; GFX1032: s_mov_b32 exec_lo, [[SAVE2]] 721; GFX1032: s_or_b32 exec_lo, exec_lo, [[SAVE1]] 722; GFX1064: v_cmp_gt_u32_e32 vcc, 32, v{{[0-9]+}} 723; GFX1064: s_and_saveexec_b64 [[SAVE1:s\[[0-9:]+\]]], vcc{{$}} 724; GFX1064: s_or_saveexec_b64 [[SAVE2:s\[[0-9:]+\]]], -1 725; GFX1064: s_mov_b64 exec, [[SAVE2]] 726; GFX1064: s_or_b64 exec, exec, [[SAVE1]] 727define amdgpu_ps float @test_wwm2(i32 inreg %idx) { 728main_body: 729 ; use mbcnt to make sure the branch is divergent 730 %lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) 731 %hi = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo) 732 %cc = icmp uge i32 %hi, 32 733 br i1 %cc, label %endif, label %if 734 735if: 736 %src = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx, i32 0, i32 0, i32 0) 737 %out = fadd float %src, %src 738 %out.0 = call float @llvm.amdgcn.wwm.f32(float %out) 739 %out.1 = fadd float %src, %out.0 740 br label %endif 741 742endif: 743 %out.2 = phi float [ %out.1, %if ], [ 0.0, %main_body ] 744 ret float %out.2 745} 746 747; GCN-LABEL: {{^}}test_wqm1: 748; GFX1032: s_mov_b32 [[ORIG:s[0-9]+]], exec_lo 749; GFX1032: s_wqm_b32 exec_lo, exec_lo 750; GFX1032: s_and_b32 exec_lo, exec_lo, [[ORIG]] 751; GFX1064: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec{{$}} 752; GFX1064: s_wqm_b64 exec, exec{{$}} 753; GFX1064: s_and_b64 exec, exec, [[ORIG]] 754define amdgpu_ps <4 x float> @test_wqm1(i32 inreg, i32 inreg, i32 inreg, i32 inreg %m0, <8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, <2 x float> %pos) #0 { 755main_body: 756 %inst23 = extractelement <2 x float> %pos, i32 0 757 %inst24 = extractelement <2 x float> %pos, i32 1 758 %inst25 = tail call float @llvm.amdgcn.interp.p1(float %inst23, i32 0, i32 0, i32 %m0) 759 %inst26 = tail call float @llvm.amdgcn.interp.p2(float %inst25, float %inst24, i32 0, i32 0, i32 %m0) 760 %inst28 = tail call float @llvm.amdgcn.interp.p1(float %inst23, i32 1, i32 0, i32 %m0) 761 %inst29 = tail call float @llvm.amdgcn.interp.p2(float %inst28, float %inst24, i32 1, i32 0, i32 %m0) 762 %tex = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %inst26, float %inst29, <8 x i32> %rsrc, <4 x i32> %sampler, i1 0, i32 0, i32 0) 763 ret <4 x float> %tex 764} 765 766; GCN-LABEL: {{^}}test_wqm2: 767; GFX1032: s_wqm_b32 exec_lo, exec_lo 768; GFX1032: s_and_b32 exec_lo, exec_lo, s{{[0-9+]}} 769; GFX1064: s_wqm_b64 exec, exec{{$}} 770; GFX1064: s_and_b64 exec, exec, s[{{[0-9:]+}}] 771define amdgpu_ps float @test_wqm2(i32 inreg %idx0, i32 inreg %idx1) #0 { 772main_body: 773 %src0 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx0, i32 0, i32 0, i32 0) 774 %src1 = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> undef, i32 %idx1, i32 0, i32 0, i32 0) 775 %out = fadd float %src0, %src1 776 %out.0 = bitcast float %out to i32 777 %out.1 = call i32 @llvm.amdgcn.wqm.i32(i32 %out.0) 778 %out.2 = bitcast i32 %out.1 to float 779 ret float %out.2 780} 781 782; GCN-LABEL: {{^}}test_intr_fcmp_i64: 783; GFX1032-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], 0{{$}} 784; GFX1032-DAG: v_cmp_eq_f32_e64 s[[C_LO:[0-9]+]], {{s[0-9]+}}, |{{[vs][0-9]+}}| 785; GFX1032-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]] 786; GFX1064: v_cmp_eq_f32_e64 s{{\[}}[[C_LO:[0-9]+]]:[[C_HI:[0-9]+]]], {{s[0-9]+}}, |{{[vs][0-9]+}}| 787; GFX1064-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]] 788; GFX1064-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[C_HI]] 789; GCN: store_dwordx2 v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]], s 790define amdgpu_kernel void @test_intr_fcmp_i64(i64 addrspace(1)* %out, float %src, float %a) { 791 %temp = call float @llvm.fabs.f32(float %a) 792 %result = call i64 @llvm.amdgcn.fcmp.i64.f32(float %src, float %temp, i32 1) 793 store i64 %result, i64 addrspace(1)* %out 794 ret void 795} 796 797; GCN-LABEL: {{^}}test_intr_icmp_i64: 798; GFX1032-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], 0{{$}} 799; GFX1032-DAG: v_cmp_eq_u32_e64 [[C_LO:vcc_lo|s[0-9]+]], 0x64, {{s[0-9]+}} 800; GFX1032-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[C_LO]] 801; GFX1064: v_cmp_eq_u32_e64 s{{\[}}[[C_LO:[0-9]+]]:[[C_HI:[0-9]+]]], 0x64, {{s[0-9]+}} 802; GFX1064-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]] 803; GFX1064-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[C_HI]] 804; GCN: store_dwordx2 v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]], s 805define amdgpu_kernel void @test_intr_icmp_i64(i64 addrspace(1)* %out, i32 %src) { 806 %result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %src, i32 100, i32 32) 807 store i64 %result, i64 addrspace(1)* %out 808 ret void 809} 810 811; GCN-LABEL: {{^}}test_intr_fcmp_i32: 812; GFX1032-DAG: v_cmp_eq_f32_e64 s[[C_LO:[0-9]+]], {{s[0-9]+}}, |{{[vs][0-9]+}}| 813; GFX1032-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]] 814; GFX1064: v_cmp_eq_f32_e64 s{{\[}}[[C_LO:[0-9]+]]:[[C_HI:[0-9]+]]], {{s[0-9]+}}, |{{[vs][0-9]+}}| 815; GFX1064-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]] 816; GCN: store_dword v{{[0-9]+}}, v[[V_LO]], s 817define amdgpu_kernel void @test_intr_fcmp_i32(i32 addrspace(1)* %out, float %src, float %a) { 818 %temp = call float @llvm.fabs.f32(float %a) 819 %result = call i32 @llvm.amdgcn.fcmp.i32.f32(float %src, float %temp, i32 1) 820 store i32 %result, i32 addrspace(1)* %out 821 ret void 822} 823 824; GCN-LABEL: {{^}}test_intr_icmp_i32: 825; GFX1032-DAG: v_cmp_eq_u32_e64 s[[C_LO:[0-9]+]], 0x64, {{s[0-9]+}} 826; GFX1032-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]]{{$}} 827; GFX1064: v_cmp_eq_u32_e64 s{{\[}}[[C_LO:[0-9]+]]:{{[0-9]+}}], 0x64, {{s[0-9]+}} 828; GFX1064-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[C_LO]]{{$}} 829; GCN: store_dword v{{[0-9]+}}, v[[V_LO]], s 830define amdgpu_kernel void @test_intr_icmp_i32(i32 addrspace(1)* %out, i32 %src) { 831 %result = call i32 @llvm.amdgcn.icmp.i32.i32(i32 %src, i32 100, i32 32) 832 store i32 %result, i32 addrspace(1)* %out 833 ret void 834} 835 836; GCN-LABEL: {{^}}test_wqm_vote: 837; GFX1032: v_cmp_neq_f32_e32 vcc_lo, 0 838; GFX1032: s_mov_b32 [[LIVE:s[0-9]+]], exec_lo 839; GFX1032: s_wqm_b32 [[WQM:s[0-9]+]], vcc_lo 840; GFX1032: s_xor_b32 [[KILL:s[0-9]+]], [[WQM]], exec_lo 841; GFX1032: s_andn2_b32 [[MASK:s[0-9]+]], [[LIVE]], [[KILL]] 842; GFX1032: s_and_b32 exec_lo, exec_lo, [[MASK]] 843; GFX1064: v_cmp_neq_f32_e32 vcc, 0 844; GFX1064: s_mov_b64 [[LIVE:s\[[0-9:]+\]]], exec 845; GFX1064: s_wqm_b64 [[WQM:s\[[0-9:]+\]]], vcc 846; GFX1064: s_xor_b64 [[KILL:s\[[0-9:]+\]]], [[WQM]], exec 847; GFX1064: s_andn2_b64 [[MASK:s\[[0-9:]+\]]], [[LIVE]], [[KILL]] 848; GFX1064: s_and_b64 exec, exec, [[MASK]] 849define amdgpu_ps void @test_wqm_vote(float %a) { 850 %c1 = fcmp une float %a, 0.0 851 %c2 = call i1 @llvm.amdgcn.wqm.vote(i1 %c1) 852 call void @llvm.amdgcn.kill(i1 %c2) 853 call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float 0.0, float 0.0, float 0.0, float 0.0, i1 false, i1 false) 854 ret void 855} 856 857; GCN-LABEL: {{^}}test_branch_true: 858; GFX1032: s_mov_b32 vcc_lo, exec_lo 859; GFX1064: s_mov_b64 vcc, exec 860define amdgpu_kernel void @test_branch_true() #2 { 861entry: 862 br i1 true, label %for.end, label %for.body.lr.ph 863 864for.body.lr.ph: ; preds = %entry 865 br label %for.body 866 867for.body: ; preds = %for.body, %for.body.lr.ph 868 br i1 undef, label %for.end, label %for.body 869 870for.end: ; preds = %for.body, %entry 871 ret void 872} 873 874; GCN-LABEL: {{^}}test_ps_live: 875; GFX1032: s_mov_b32 [[C:s[0-9]+]], exec_lo 876; GFX1064: s_mov_b64 [[C:s\[[0-9:]+\]]], exec{{$}} 877; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, [[C]] 878define amdgpu_ps float @test_ps_live() #0 { 879 %live = call i1 @llvm.amdgcn.ps.live() 880 %live.32 = zext i1 %live to i32 881 %r = bitcast i32 %live.32 to float 882 ret float %r 883} 884 885; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle64: 886; GFX1032: v_cmp_neq_f64_e64 [[C:s[0-9]+]], s[{{[0-9:]+}}], 1.0 887; GFX1032: s_and_b32 vcc_lo, exec_lo, [[C]] 888; GFX1064: v_cmp_neq_f64_e64 [[C:s\[[0-9:]+\]]], s[{{[0-9:]+}}], 1.0 889; GFX1064: s_and_b64 vcc, exec, [[C]] 890define amdgpu_kernel void @test_vccnz_ifcvt_triangle64(double addrspace(1)* %out, double addrspace(1)* %in) #0 { 891entry: 892 %v = load double, double addrspace(1)* %in 893 %cc = fcmp oeq double %v, 1.000000e+00 894 br i1 %cc, label %if, label %endif 895 896if: 897 %u = fadd double %v, %v 898 br label %endif 899 900endif: 901 %r = phi double [ %v, %entry ], [ %u, %if ] 902 store double %r, double addrspace(1)* %out 903 ret void 904} 905 906; GCN-LABEL: {{^}}test_vgprblocks_w32_attr: 907; Test that the wave size can be overridden in function attributes and that the block size is correct as a result 908; GFX10DEFWAVE: ; VGPRBlocks: 1 909define amdgpu_gs float @test_vgprblocks_w32_attr(float %a, float %b, float %c, float %d, float %e, 910 float %f, float %g, float %h, float %i, float %j, float %k, float %l) #3 { 911main_body: 912 %s = fadd float %a, %b 913 %s.1 = fadd float %s, %c 914 %s.2 = fadd float %s.1, %d 915 %s.3 = fadd float %s.2, %e 916 %s.4 = fadd float %s.3, %f 917 %s.5 = fadd float %s.4, %g 918 %s.6 = fadd float %s.5, %h 919 %s.7 = fadd float %s.6, %i 920 %s.8 = fadd float %s.7, %j 921 %s.9 = fadd float %s.8, %k 922 %s.10 = fadd float %s.9, %l 923 ret float %s.10 924} 925 926; GCN-LABEL: {{^}}test_vgprblocks_w64_attr: 927; Test that the wave size can be overridden in function attributes and that the block size is correct as a result 928; GFX10DEFWAVE: ; VGPRBlocks: 2 929define amdgpu_gs float @test_vgprblocks_w64_attr(float %a, float %b, float %c, float %d, float %e, 930 float %f, float %g, float %h, float %i, float %j, float %k, float %l) #4 { 931main_body: 932 %s = fadd float %a, %b 933 %s.1 = fadd float %s, %c 934 %s.2 = fadd float %s.1, %d 935 %s.3 = fadd float %s.2, %e 936 %s.4 = fadd float %s.3, %f 937 %s.5 = fadd float %s.4, %g 938 %s.6 = fadd float %s.5, %h 939 %s.7 = fadd float %s.6, %i 940 %s.8 = fadd float %s.7, %j 941 %s.9 = fadd float %s.8, %k 942 %s.10 = fadd float %s.9, %l 943 ret float %s.10 944} 945 946; GCN-LABEL: {{^}}icmp64: 947; GFX1032: v_cmp_eq_u32_e32 vcc_lo, 0, v 948; GFX1064: v_cmp_eq_u32_e32 vcc, 0, v 949define amdgpu_kernel void @icmp64(i32 %n, i32 %s) { 950entry: 951 %id = tail call i32 @llvm.amdgcn.workitem.id.x() 952 %mul4 = mul nsw i32 %s, %n 953 %cmp = icmp slt i32 0, %mul4 954 br label %if.end 955 956if.end: ; preds = %entry 957 %rem = urem i32 %id, %s 958 %icmp = tail call i64 @llvm.amdgcn.icmp.i64.i32(i32 %rem, i32 0, i32 32) 959 %shr = lshr i64 %icmp, 1 960 %notmask = shl nsw i64 -1, 0 961 %and = and i64 %notmask, %shr 962 %or = or i64 %and, -9223372036854775808 963 %cttz = tail call i64 @llvm.cttz.i64(i64 %or, i1 true) 964 %cast = trunc i64 %cttz to i32 965 %cmp3 = icmp ugt i32 10, %cast 966 %cmp6 = icmp ne i32 %rem, 0 967 %brmerge = or i1 %cmp6, %cmp3 968 br i1 %brmerge, label %if.end2, label %if.then 969 970if.then: ; preds = %if.end 971 unreachable 972 973if.end2: ; preds = %if.end 974 ret void 975} 976 977; GCN-LABEL: {{^}}fcmp64: 978; GFX1032: v_cmp_eq_f32_e32 vcc_lo, 0, v 979; GFX1064: v_cmp_eq_f32_e32 vcc, 0, v 980define amdgpu_kernel void @fcmp64(float %n, float %s) { 981entry: 982 %id = tail call i32 @llvm.amdgcn.workitem.id.x() 983 %id.f = uitofp i32 %id to float 984 %mul4 = fmul float %s, %n 985 %cmp = fcmp ult float 0.0, %mul4 986 br label %if.end 987 988if.end: ; preds = %entry 989 %rem.f = frem float %id.f, %s 990 %fcmp = tail call i64 @llvm.amdgcn.fcmp.i64.f32(float %rem.f, float 0.0, i32 1) 991 %shr = lshr i64 %fcmp, 1 992 %notmask = shl nsw i64 -1, 0 993 %and = and i64 %notmask, %shr 994 %or = or i64 %and, -9223372036854775808 995 %cttz = tail call i64 @llvm.cttz.i64(i64 %or, i1 true) 996 %cast = trunc i64 %cttz to i32 997 %cmp3 = icmp ugt i32 10, %cast 998 %cmp6 = fcmp one float %rem.f, 0.0 999 %brmerge = or i1 %cmp6, %cmp3 1000 br i1 %brmerge, label %if.end2, label %if.then 1001 1002if.then: ; preds = %if.end 1003 unreachable 1004 1005if.end2: ; preds = %if.end 1006 ret void 1007} 1008 1009; GCN-LABEL: {{^}}icmp32: 1010; GFX1032: v_cmp_eq_u32_e32 vcc_lo, 0, v 1011; GFX1064: v_cmp_eq_u32_e32 vcc, 0, v 1012define amdgpu_kernel void @icmp32(i32 %n, i32 %s) { 1013entry: 1014 %id = tail call i32 @llvm.amdgcn.workitem.id.x() 1015 %mul4 = mul nsw i32 %s, %n 1016 %cmp = icmp slt i32 0, %mul4 1017 br label %if.end 1018 1019if.end: ; preds = %entry 1020 %rem = urem i32 %id, %s 1021 %icmp = tail call i32 @llvm.amdgcn.icmp.i32.i32(i32 %rem, i32 0, i32 32) 1022 %shr = lshr i32 %icmp, 1 1023 %notmask = shl nsw i32 -1, 0 1024 %and = and i32 %notmask, %shr 1025 %or = or i32 %and, 2147483648 1026 %cttz = tail call i32 @llvm.cttz.i32(i32 %or, i1 true) 1027 %cmp3 = icmp ugt i32 10, %cttz 1028 %cmp6 = icmp ne i32 %rem, 0 1029 %brmerge = or i1 %cmp6, %cmp3 1030 br i1 %brmerge, label %if.end2, label %if.then 1031 1032if.then: ; preds = %if.end 1033 unreachable 1034 1035if.end2: ; preds = %if.end 1036 ret void 1037} 1038 1039; GCN-LABEL: {{^}}fcmp32: 1040; GFX1032: v_cmp_eq_f32_e32 vcc_lo, 0, v 1041; GFX1064: v_cmp_eq_f32_e32 vcc, 0, v 1042define amdgpu_kernel void @fcmp32(float %n, float %s) { 1043entry: 1044 %id = tail call i32 @llvm.amdgcn.workitem.id.x() 1045 %id.f = uitofp i32 %id to float 1046 %mul4 = fmul float %s, %n 1047 %cmp = fcmp ult float 0.0, %mul4 1048 br label %if.end 1049 1050if.end: ; preds = %entry 1051 %rem.f = frem float %id.f, %s 1052 %fcmp = tail call i32 @llvm.amdgcn.fcmp.i32.f32(float %rem.f, float 0.0, i32 1) 1053 %shr = lshr i32 %fcmp, 1 1054 %notmask = shl nsw i32 -1, 0 1055 %and = and i32 %notmask, %shr 1056 %or = or i32 %and, 2147483648 1057 %cttz = tail call i32 @llvm.cttz.i32(i32 %or, i1 true) 1058 %cmp3 = icmp ugt i32 10, %cttz 1059 %cmp6 = fcmp one float %rem.f, 0.0 1060 %brmerge = or i1 %cmp6, %cmp3 1061 br i1 %brmerge, label %if.end2, label %if.then 1062 1063if.then: ; preds = %if.end 1064 unreachable 1065 1066if.end2: ; preds = %if.end 1067 ret void 1068} 1069 1070declare void @external_void_func_void() #1 1071 1072; Test save/restore of VGPR needed for SGPR spilling. 1073 1074; GCN-LABEL: {{^}}callee_no_stack_with_call: 1075; GCN: s_waitcnt 1076; GCN-NEXT: s_waitcnt_vscnt 1077 1078; GFX1064-NEXT: s_or_saveexec_b64 [[COPY_EXEC0:s\[[0-9]+:[0-9]+\]]], -1{{$}} 1079; GFX1032-NEXT: s_or_saveexec_b32 [[COPY_EXEC0:s[0-9]+]], -1{{$}} 1080; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill 1081; GCN-NEXT: s_waitcnt_depctr 0xffe3 1082; GFX1064-NEXT: s_mov_b64 exec, [[COPY_EXEC0]] 1083; GFX1032-NEXT: s_mov_b32 exec_lo, [[COPY_EXEC0]] 1084 1085; GCN-NEXT: v_writelane_b32 v40, s33, 2 1086; GCN: s_mov_b32 s33, s32 1087; GFX1064: s_add_u32 s32, s32, 0x400 1088; GFX1032: s_add_u32 s32, s32, 0x200 1089 1090 1091; GCN-DAG: v_writelane_b32 v40, s30, 0 1092; GCN-DAG: v_writelane_b32 v40, s31, 1 1093; GCN: s_swappc_b64 1094; GCN-DAG: v_readlane_b32 s4, v40, 0 1095; GCN-DAG: v_readlane_b32 s5, v40, 1 1096 1097 1098; GFX1064: s_sub_u32 s32, s32, 0x400 1099; GFX1032: s_sub_u32 s32, s32, 0x200 1100; GCN: v_readlane_b32 s33, v40, 2 1101; GFX1064: s_or_saveexec_b64 [[COPY_EXEC1:s\[[0-9]+:[0-9]+\]]], -1{{$}} 1102; GFX1032: s_or_saveexec_b32 [[COPY_EXEC1:s[0-9]]], -1{{$}} 1103; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload 1104; GCN-NEXT: s_waitcnt_depctr 0xffe3 1105; GFX1064-NEXT: s_mov_b64 exec, [[COPY_EXEC1]] 1106; GFX1032-NEXT: s_mov_b32 exec_lo, [[COPY_EXEC1]] 1107; GCN-NEXT: s_waitcnt vmcnt(0) 1108; GCN-NEXT: s_setpc_b64 1109define void @callee_no_stack_with_call() #1 { 1110 call void @external_void_func_void() 1111 ret void 1112} 1113 1114 1115declare i32 @llvm.amdgcn.workitem.id.x() 1116declare float @llvm.fabs.f32(float) 1117declare { float, i1 } @llvm.amdgcn.div.scale.f32(float, float, i1) 1118declare { double, i1 } @llvm.amdgcn.div.scale.f64(double, double, i1) 1119declare float @llvm.amdgcn.div.fmas.f32(float, float, float, i1) 1120declare double @llvm.amdgcn.div.fmas.f64(double, double, double, i1) 1121declare i1 @llvm.amdgcn.class.f32(float, i32) 1122declare i32 @llvm.amdgcn.set.inactive.i32(i32, i32) 1123declare i64 @llvm.amdgcn.set.inactive.i64(i64, i64) 1124declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) 1125declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) 1126declare float @llvm.amdgcn.wwm.f32(float) 1127declare i32 @llvm.amdgcn.wqm.i32(i32) 1128declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) 1129declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) 1130declare float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32>, i32, i32, i32, i32 immarg) 1131declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) 1132declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) 1133declare i64 @llvm.amdgcn.fcmp.i64.f32(float, float, i32) 1134declare i64 @llvm.amdgcn.icmp.i64.i32(i32, i32, i32) 1135declare i32 @llvm.amdgcn.fcmp.i32.f32(float, float, i32) 1136declare i32 @llvm.amdgcn.icmp.i32.i32(i32, i32, i32) 1137declare void @llvm.amdgcn.kill(i1) 1138declare i1 @llvm.amdgcn.wqm.vote(i1) 1139declare i1 @llvm.amdgcn.ps.live() 1140declare i64 @llvm.cttz.i64(i64, i1) 1141declare i32 @llvm.cttz.i32(i32, i1) 1142declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #5 1143 1144attributes #0 = { nounwind readnone speculatable } 1145attributes #1 = { nounwind } 1146attributes #2 = { nounwind readnone optnone noinline } 1147attributes #3 = { "target-features"="+wavefrontsize32" } 1148attributes #4 = { "target-features"="+wavefrontsize64" } 1149attributes #5 = { inaccessiblememonly nounwind } 1150