1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 | FileCheck %s --check-prefix=GCN
3; RUN: llc < %s -march=amdgcn -mcpu=gfx1100 | FileCheck %s --check-prefix=GFX11
4
5define void @vgpr_descriptor_waterfall_loop_idom_update(<4 x i32>* %arg) #0 {
6; GCN-LABEL: vgpr_descriptor_waterfall_loop_idom_update:
7; GCN:       ; %bb.0: ; %entry
8; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
9; GCN-NEXT:    s_waitcnt_vscnt null, 0x0
10; GCN-NEXT:    v_add_co_u32 v6, vcc_lo, v0, 8
11; GCN-NEXT:    v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
12; GCN-NEXT:  .LBB0_1: ; %bb0
13; GCN-NEXT:    ; =>This Loop Header: Depth=1
14; GCN-NEXT:    ; Child Loop BB0_2 Depth 2
15; GCN-NEXT:    s_clause 0x1
16; GCN-NEXT:    flat_load_dwordx2 v[4:5], v[6:7]
17; GCN-NEXT:    flat_load_dwordx2 v[2:3], v[0:1]
18; GCN-NEXT:    s_mov_b32 s5, exec_lo
19; GCN-NEXT:  .LBB0_2: ; Parent Loop BB0_1 Depth=1
20; GCN-NEXT:    ; => This Inner Loop Header: Depth=2
21; GCN-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
22; GCN-NEXT:    v_readfirstlane_b32 s8, v2
23; GCN-NEXT:    v_readfirstlane_b32 s9, v3
24; GCN-NEXT:    v_readfirstlane_b32 s10, v4
25; GCN-NEXT:    v_readfirstlane_b32 s11, v5
26; GCN-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[8:9], v[2:3]
27; GCN-NEXT:    v_cmp_eq_u64_e64 s4, s[10:11], v[4:5]
28; GCN-NEXT:    s_and_b32 s4, vcc_lo, s4
29; GCN-NEXT:    s_and_saveexec_b32 s4, s4
30; GCN-NEXT:    buffer_store_dword v0, v0, s[8:11], 0 offen
31; GCN-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5
32; GCN-NEXT:    s_waitcnt_depctr 0xffe3
33; GCN-NEXT:    s_xor_b32 exec_lo, exec_lo, s4
34; GCN-NEXT:    s_cbranch_execnz .LBB0_2
35; GCN-NEXT:  ; %bb.3: ; in Loop: Header=BB0_1 Depth=1
36; GCN-NEXT:    s_mov_b32 exec_lo, s5
37; GCN-NEXT:    s_branch .LBB0_1
38;
39; GFX11-LABEL: vgpr_descriptor_waterfall_loop_idom_update:
40; GFX11:       ; %bb.0: ; %entry
41; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
42; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
43; GFX11-NEXT:    .p2align 6
44; GFX11-NEXT:  .LBB0_1: ; %bb0
45; GFX11-NEXT:    ; =>This Loop Header: Depth=1
46; GFX11-NEXT:    ; Child Loop BB0_2 Depth 2
47; GFX11-NEXT:    flat_load_b128 v[2:5], v[0:1]
48; GFX11-NEXT:    s_mov_b32 s1, exec_lo
49; GFX11-NEXT:  .LBB0_2: ; Parent Loop BB0_1 Depth=1
50; GFX11-NEXT:    ; => This Inner Loop Header: Depth=2
51; GFX11-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
52; GFX11-NEXT:    v_readfirstlane_b32 s4, v2
53; GFX11-NEXT:    v_readfirstlane_b32 s5, v3
54; GFX11-NEXT:    v_readfirstlane_b32 s6, v4
55; GFX11-NEXT:    v_readfirstlane_b32 s7, v5
56; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
57; GFX11-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[2:3]
58; GFX11-NEXT:    v_cmp_eq_u64_e64 s0, s[6:7], v[4:5]
59; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
60; GFX11-NEXT:    s_and_b32 s0, vcc_lo, s0
61; GFX11-NEXT:    s_and_saveexec_b32 s0, s0
62; GFX11-NEXT:    buffer_store_b32 v0, v0, s[4:7], 0 offen
63; GFX11-NEXT:    ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5
64; GFX11-NEXT:    s_xor_b32 exec_lo, exec_lo, s0
65; GFX11-NEXT:    s_cbranch_execnz .LBB0_2
66; GFX11-NEXT:  ; %bb.3: ; in Loop: Header=BB0_1 Depth=1
67; GFX11-NEXT:    s_mov_b32 exec_lo, s1
68; GFX11-NEXT:    s_branch .LBB0_1
69entry:
70  br label %bb0
71
72bb0:
73  %desc = load <4 x i32>, <4 x i32>* %arg, align 8
74  tail call void @llvm.amdgcn.raw.buffer.store.f32(float undef, <4 x i32> %desc, i32 undef, i32 0, i32 0)
75  br label %bb0
76}
77
78declare void @llvm.amdgcn.raw.buffer.store.f32(float, <4 x i32>, i32, i32, i32 immarg) #0
79
80attributes #0 = { nounwind writeonly }
81