1; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-ALLOCA %s 2; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-PROMOTE %s 3; RUN: opt -S -mtriple=amdgcn-- -amdgpu-promote-alloca -sroa -instcombine < %s | FileCheck -check-prefix=OPT %s 4 5target datalayout = "A5" 6 7; OPT-LABEL: @vector_read_alloca_bitcast( 8; OPT-NOT: alloca 9; OPT: %0 = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 %index 10; OPT-NEXT: store i32 %0, i32 addrspace(1)* %out, align 4 11 12; GCN-LABEL: {{^}}vector_read_alloca_bitcast: 13; GCN-ALLOCA-COUNT-4: buffer_store_dword 14; GCN-ALLOCA: buffer_load_dword 15 16; GCN-PROMOTE: v_cmp_eq_u32_e64 [[CC1:[^,]+]], s{{[0-9]+}}, 1 17; GCN-PROMOTE: v_cndmask_b32_e{{32|64}} [[IND1:v[0-9]+]], 0, 1, [[CC1]] 18; GCN-PROMOTE: v_cmp_ne_u32_e64 [[CC2:[^,]+]], s{{[0-9]+}}, 2 19; GCN-PROMOTE: v_cndmask_b32_e{{32|64}} [[IND2:v[0-9]+]], 2, [[IND1]], [[CC2]] 20; GCN-PROMOTE: v_cmp_ne_u32_e64 [[CC3:[^,]+]], s{{[0-9]+}}, 3 21; GCN-PROMOTE: v_cndmask_b32_e{{32|64}} [[IND3:v[0-9]+]], 3, [[IND2]], [[CC3]] 22 23; GCN-PROMOTE: ScratchSize: 0 24 25define amdgpu_kernel void @vector_read_alloca_bitcast(i32 addrspace(1)* %out, i32 %index) { 26entry: 27 %tmp = alloca [4 x i32], addrspace(5) 28 %x = bitcast [4 x i32] addrspace(5)* %tmp to i32 addrspace(5)* 29 %y = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 1 30 %z = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 2 31 %w = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 3 32 store i32 0, i32 addrspace(5)* %x 33 store i32 1, i32 addrspace(5)* %y 34 store i32 2, i32 addrspace(5)* %z 35 store i32 3, i32 addrspace(5)* %w 36 %tmp1 = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 %index 37 %tmp2 = load i32, i32 addrspace(5)* %tmp1 38 store i32 %tmp2, i32 addrspace(1)* %out 39 ret void 40} 41 42; OPT-LABEL: @vector_write_alloca_bitcast( 43; OPT-NOT: alloca 44; OPT: %0 = insertelement <4 x i32> zeroinitializer, i32 1, i32 %w_index 45; OPT-NEXT: %1 = extractelement <4 x i32> %0, i32 %r_index 46; OPT-NEXT: store i32 %1, i32 addrspace(1)* %out, align 47 48; GCN-LABEL: {{^}}vector_write_alloca_bitcast: 49; GCN-ALLOCA-COUNT-5: buffer_store_dword 50; GCN-ALLOCA: buffer_load_dword 51 52; GCN-PROMOTE-COUNT-7: v_cndmask 53 54; GCN-PROMOTE: ScratchSize: 0 55 56define amdgpu_kernel void @vector_write_alloca_bitcast(i32 addrspace(1)* %out, i32 %w_index, i32 %r_index) { 57entry: 58 %tmp = alloca [4 x i32], addrspace(5) 59 %x = bitcast [4 x i32] addrspace(5)* %tmp to i32 addrspace(5)* 60 %y = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 1 61 %z = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 2 62 %w = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 3 63 store i32 0, i32 addrspace(5)* %x 64 store i32 0, i32 addrspace(5)* %y 65 store i32 0, i32 addrspace(5)* %z 66 store i32 0, i32 addrspace(5)* %w 67 %tmp1 = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 %w_index 68 store i32 1, i32 addrspace(5)* %tmp1 69 %tmp2 = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 %r_index 70 %tmp3 = load i32, i32 addrspace(5)* %tmp2 71 store i32 %tmp3, i32 addrspace(1)* %out 72 ret void 73} 74 75; OPT-LABEL: @vector_write_read_bitcast_to_float( 76; OPT-NOT: alloca 77; OPT: bb2: 78; OPT: %tmp.sroa.0.0 = phi <6 x float> [ undef, %bb ], [ %0, %bb2 ] 79; OPT: %0 = insertelement <6 x float> %tmp.sroa.0.0, float %tmp73, i32 %tmp10 80; OPT: .preheader: 81; OPT: %bc = bitcast <6 x float> %0 to <6 x i32> 82; OPT: %1 = extractelement <6 x i32> %bc, i32 %tmp20 83 84; GCN-LABEL: {{^}}vector_write_read_bitcast_to_float: 85; GCN-ALLOCA: buffer_store_dword 86 87; GCN-PROMOTE-COUNT-6: v_cmp_eq_u16 88; GCN-PROMOTE-COUNT-6: v_cndmask 89 90; GCN: s_cbranch 91 92; GCN-ALLOCA: buffer_load_dword 93 94; GCN-PROMOTE: v_cmp_eq_u16 95; GCN-PROMOTE: v_cndmask 96; GCN-PROMOTE: v_cmp_eq_u16 97; GCN-PROMOTE: v_cndmask 98; GCN-PROMOTE: v_cmp_eq_u16 99; GCN-PROMOTE: v_cndmask 100; GCN-PROMOTE: v_cmp_eq_u16 101; GCN-PROMOTE: v_cndmask 102; GCN-PROMOTE: v_cmp_eq_u16 103; GCN-PROMOTE: v_cndmask 104 105; GCN-PROMOTE: ScratchSize: 0 106 107define amdgpu_kernel void @vector_write_read_bitcast_to_float(float addrspace(1)* %arg) { 108bb: 109 %tmp = alloca [6 x float], align 4, addrspace(5) 110 %tmp1 = bitcast [6 x float] addrspace(5)* %tmp to i8 addrspace(5)* 111 call void @llvm.lifetime.start.p5i8(i64 24, i8 addrspace(5)* %tmp1) #2 112 br label %bb2 113 114bb2: ; preds = %bb2, %bb 115 %tmp3 = phi i32 [ 0, %bb ], [ %tmp13, %bb2 ] 116 %tmp4 = zext i32 %tmp3 to i64 117 %tmp5 = getelementptr inbounds float, float addrspace(1)* %arg, i64 %tmp4 118 %tmp6 = bitcast float addrspace(1)* %tmp5 to i32 addrspace(1)* 119 %tmp7 = load i32, i32 addrspace(1)* %tmp6, align 4 120 %tmp8 = trunc i32 %tmp3 to i16 121 %tmp9 = urem i16 %tmp8, 6 122 %tmp10 = zext i16 %tmp9 to i32 123 %tmp11 = getelementptr inbounds [6 x float], [6 x float] addrspace(5)* %tmp, i32 0, i32 %tmp10 124 %tmp12 = bitcast float addrspace(5)* %tmp11 to i32 addrspace(5)* 125 store i32 %tmp7, i32 addrspace(5)* %tmp12, align 4 126 %tmp13 = add nuw nsw i32 %tmp3, 1 127 %tmp14 = icmp eq i32 %tmp13, 1000 128 br i1 %tmp14, label %.preheader, label %bb2 129 130bb15: ; preds = %.preheader 131 call void @llvm.lifetime.end.p5i8(i64 24, i8 addrspace(5)* %tmp1) #2 132 ret void 133 134.preheader: ; preds = %.preheader, %bb2 135 %tmp16 = phi i32 [ %tmp27, %.preheader ], [ 0, %bb2 ] 136 %tmp17 = trunc i32 %tmp16 to i16 137 %tmp18 = urem i16 %tmp17, 6 138 %tmp19 = sub nuw nsw i16 5, %tmp18 139 %tmp20 = zext i16 %tmp19 to i32 140 %tmp21 = getelementptr inbounds [6 x float], [6 x float] addrspace(5)* %tmp, i32 0, i32 %tmp20 141 %tmp22 = bitcast float addrspace(5)* %tmp21 to i32 addrspace(5)* 142 %tmp23 = load i32, i32 addrspace(5)* %tmp22, align 4 143 %tmp24 = zext i32 %tmp16 to i64 144 %tmp25 = getelementptr inbounds float, float addrspace(1)* %arg, i64 %tmp24 145 %tmp26 = bitcast float addrspace(1)* %tmp25 to i32 addrspace(1)* 146 store i32 %tmp23, i32 addrspace(1)* %tmp26, align 4 147 %tmp27 = add nuw nsw i32 %tmp16, 1 148 %tmp28 = icmp eq i32 %tmp27, 1000 149 br i1 %tmp28, label %bb15, label %.preheader 150} 151 152; OPT-LABEL: @vector_write_read_bitcast_to_double( 153; OPT-NOT: alloca 154; OPT: bb2: 155; OPT: %tmp.sroa.0.0 = phi <6 x double> [ undef, %bb ], [ %0, %bb2 ] 156; OPT: %0 = insertelement <6 x double> %tmp.sroa.0.0, double %tmp73, i32 %tmp10 157; OPT: .preheader: 158; OPT: %bc = bitcast <6 x double> %0 to <6 x i64> 159; OPT: %1 = extractelement <6 x i64> %bc, i32 %tmp20 160 161; GCN-LABEL: {{^}}vector_write_read_bitcast_to_double: 162 163; GCN-ALLOCA-COUNT-2: buffer_store_dword 164; GCN-PROMOTE-COUNT-2: v_movreld_b32_e32 165 166; GCN: s_cbranch 167 168; GCN-ALLOCA-COUNT-2: buffer_load_dword 169; GCN-PROMOTE-COUNT-2: v_movrels_b32_e32 170 171; GCN-PROMOTE: ScratchSize: 0 172 173define amdgpu_kernel void @vector_write_read_bitcast_to_double(double addrspace(1)* %arg) { 174bb: 175 %tmp = alloca [6 x double], align 8, addrspace(5) 176 %tmp1 = bitcast [6 x double] addrspace(5)* %tmp to i8 addrspace(5)* 177 call void @llvm.lifetime.start.p5i8(i64 48, i8 addrspace(5)* %tmp1) #2 178 br label %bb2 179 180bb2: ; preds = %bb2, %bb 181 %tmp3 = phi i32 [ 0, %bb ], [ %tmp13, %bb2 ] 182 %tmp4 = zext i32 %tmp3 to i64 183 %tmp5 = getelementptr inbounds double, double addrspace(1)* %arg, i64 %tmp4 184 %tmp6 = bitcast double addrspace(1)* %tmp5 to i64 addrspace(1)* 185 %tmp7 = load i64, i64 addrspace(1)* %tmp6, align 8 186 %tmp8 = trunc i32 %tmp3 to i16 187 %tmp9 = urem i16 %tmp8, 6 188 %tmp10 = zext i16 %tmp9 to i32 189 %tmp11 = getelementptr inbounds [6 x double], [6 x double] addrspace(5)* %tmp, i32 0, i32 %tmp10 190 %tmp12 = bitcast double addrspace(5)* %tmp11 to i64 addrspace(5)* 191 store i64 %tmp7, i64 addrspace(5)* %tmp12, align 8 192 %tmp13 = add nuw nsw i32 %tmp3, 1 193 %tmp14 = icmp eq i32 %tmp13, 1000 194 br i1 %tmp14, label %.preheader, label %bb2 195 196bb15: ; preds = %.preheader 197 call void @llvm.lifetime.end.p5i8(i64 48, i8 addrspace(5)* %tmp1) #2 198 ret void 199 200.preheader: ; preds = %.preheader, %bb2 201 %tmp16 = phi i32 [ %tmp27, %.preheader ], [ 0, %bb2 ] 202 %tmp17 = trunc i32 %tmp16 to i16 203 %tmp18 = urem i16 %tmp17, 6 204 %tmp19 = sub nuw nsw i16 5, %tmp18 205 %tmp20 = zext i16 %tmp19 to i32 206 %tmp21 = getelementptr inbounds [6 x double], [6 x double] addrspace(5)* %tmp, i32 0, i32 %tmp20 207 %tmp22 = bitcast double addrspace(5)* %tmp21 to i64 addrspace(5)* 208 %tmp23 = load i64, i64 addrspace(5)* %tmp22, align 8 209 %tmp24 = zext i32 %tmp16 to i64 210 %tmp25 = getelementptr inbounds double, double addrspace(1)* %arg, i64 %tmp24 211 %tmp26 = bitcast double addrspace(1)* %tmp25 to i64 addrspace(1)* 212 store i64 %tmp23, i64 addrspace(1)* %tmp26, align 8 213 %tmp27 = add nuw nsw i32 %tmp16, 1 214 %tmp28 = icmp eq i32 %tmp27, 1000 215 br i1 %tmp28, label %bb15, label %.preheader 216} 217 218; OPT-LABEL: @vector_write_read_bitcast_to_i64( 219; OPT-NOT: alloca 220; OPT: bb2: 221; OPT: %tmp.sroa.0.0 = phi <6 x i64> [ undef, %bb ], [ %0, %bb2 ] 222; OPT: %0 = insertelement <6 x i64> %tmp.sroa.0.0, i64 %tmp6, i32 %tmp9 223; OPT: .preheader: 224; OPT: %1 = extractelement <6 x i64> %0, i32 %tmp18 225 226; GCN-LABEL: {{^}}vector_write_read_bitcast_to_i64: 227 228; GCN-ALLOCA-COUNT-2: buffer_store_dword 229; GCN-PROMOTE-COUNT-2: v_movreld_b32_e32 230 231; GCN: s_cbranch 232 233; GCN-ALLOCA-COUNT-2: buffer_load_dword 234; GCN-PROMOTE-COUNT-2: v_movrels_b32_e32 235 236; GCN-PROMOTE: ScratchSize: 0 237 238define amdgpu_kernel void @vector_write_read_bitcast_to_i64(i64 addrspace(1)* %arg) { 239bb: 240 %tmp = alloca [6 x i64], align 8, addrspace(5) 241 %tmp1 = bitcast [6 x i64] addrspace(5)* %tmp to i8 addrspace(5)* 242 call void @llvm.lifetime.start.p5i8(i64 48, i8 addrspace(5)* %tmp1) #2 243 br label %bb2 244 245bb2: ; preds = %bb2, %bb 246 %tmp3 = phi i32 [ 0, %bb ], [ %tmp11, %bb2 ] 247 %tmp4 = zext i32 %tmp3 to i64 248 %tmp5 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i64 %tmp4 249 %tmp6 = load i64, i64 addrspace(1)* %tmp5, align 8 250 %tmp7 = trunc i32 %tmp3 to i16 251 %tmp8 = urem i16 %tmp7, 6 252 %tmp9 = zext i16 %tmp8 to i32 253 %tmp10 = getelementptr inbounds [6 x i64], [6 x i64] addrspace(5)* %tmp, i32 0, i32 %tmp9 254 store i64 %tmp6, i64 addrspace(5)* %tmp10, align 8 255 %tmp11 = add nuw nsw i32 %tmp3, 1 256 %tmp12 = icmp eq i32 %tmp11, 1000 257 br i1 %tmp12, label %.preheader, label %bb2 258 259bb13: ; preds = %.preheader 260 call void @llvm.lifetime.end.p5i8(i64 48, i8 addrspace(5)* %tmp1) #2 261 ret void 262 263.preheader: ; preds = %.preheader, %bb2 264 %tmp14 = phi i32 [ %tmp23, %.preheader ], [ 0, %bb2 ] 265 %tmp15 = trunc i32 %tmp14 to i16 266 %tmp16 = urem i16 %tmp15, 6 267 %tmp17 = sub nuw nsw i16 5, %tmp16 268 %tmp18 = zext i16 %tmp17 to i32 269 %tmp19 = getelementptr inbounds [6 x i64], [6 x i64] addrspace(5)* %tmp, i32 0, i32 %tmp18 270 %tmp20 = load i64, i64 addrspace(5)* %tmp19, align 8 271 %tmp21 = zext i32 %tmp14 to i64 272 %tmp22 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i64 %tmp21 273 store i64 %tmp20, i64 addrspace(1)* %tmp22, align 8 274 %tmp23 = add nuw nsw i32 %tmp14, 1 275 %tmp24 = icmp eq i32 %tmp23, 1000 276 br i1 %tmp24, label %bb13, label %.preheader 277} 278 279; TODO: llvm.assume can be ingored 280 281; OPT-LABEL: @vector_read_alloca_bitcast_assume( 282; OPT: %tmp = alloca <4 x i32>, align 16, addrspace(5) 283; OPT-NEXT: %x = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %tmp, i64 0, i64 0 284; OPT-NEXT: store i32 0, i32 addrspace(5)* %x, align 16 285; OPT-NEXT: %0 = load <4 x i32>, <4 x i32> addrspace(5)* %tmp, align 16 286; OPT-NEXT: %1 = shufflevector <4 x i32> %0, <4 x i32> <i32 undef, i32 1, i32 2, i32 3>, <4 x i32> <i32 0, i32 5, i32 6, i32 7> 287; OPT-NEXT: store <4 x i32> %1, <4 x i32> addrspace(5)* %tmp, align 16 288; OPT-NEXT: %2 = extractelement <4 x i32> %1, i32 %index 289; OPT-NEXT: store i32 %2, i32 addrspace(1)* %out, align 4 290 291; GCN-LABEL: {{^}}vector_read_alloca_bitcast_assume: 292; GCN-COUNT-4: buffer_store_dword 293 294define amdgpu_kernel void @vector_read_alloca_bitcast_assume(i32 addrspace(1)* %out, i32 %index) { 295entry: 296 %tmp = alloca [4 x i32], addrspace(5) 297 %x = bitcast [4 x i32] addrspace(5)* %tmp to i32 addrspace(5)* 298 %cmp = icmp ne i32 addrspace(5)* %x, null 299 call void @llvm.assume(i1 %cmp) 300 %y = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 1 301 %z = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 2 302 %w = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 3 303 store i32 0, i32 addrspace(5)* %x 304 store i32 1, i32 addrspace(5)* %y 305 store i32 2, i32 addrspace(5)* %z 306 store i32 3, i32 addrspace(5)* %w 307 %tmp1 = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 %index 308 %tmp2 = load i32, i32 addrspace(5)* %tmp1 309 store i32 %tmp2, i32 addrspace(1)* %out 310 ret void 311} 312 313; OPT-LABEL: @vector_read_alloca_multiuse( 314; OPT-NOT: alloca 315; OPT: %0 = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 %index 316; OPT-NEXT: %add2 = add nuw nsw i32 %0, 1 317; OPT-NEXT: store i32 %add2, i32 addrspace(1)* %out, align 4 318 319; GCN-LABEL: {{^}}vector_read_alloca_multiuse: 320; GCN-ALLOCA-COUNT-4: buffer_store_dword 321; GCN-ALLOCA: buffer_load_dword 322 323; GCN-PROMOTE: v_cmp_eq_u32_e64 [[CC1:[^,]+]], s{{[0-9]+}}, 1 324; GCN-PROMOTE: v_cndmask_b32_e{{32|64}} [[IND1:v[0-9]+]], 0, 1, [[CC1]] 325; GCN-PROMOTE: v_cmp_ne_u32_e64 [[CC2:[^,]+]], s{{[0-9]+}}, 2 326; GCN-PROMOTE: v_cndmask_b32_e{{32|64}} [[IND2:v[0-9]+]], 2, [[IND1]], [[CC2]] 327; GCN-PROMOTE: v_cmp_ne_u32_e64 [[CC3:[^,]+]], s{{[0-9]+}}, 3 328; GCN-PROMOTE: v_cndmask_b32_e{{32|64}} [[IND3:v[0-9]+]], 3, [[IND2]], [[CC3]] 329 330; GCN-PROMOTE: ScratchSize: 0 331 332define amdgpu_kernel void @vector_read_alloca_multiuse(i32 addrspace(1)* %out, i32 %index) { 333entry: 334 %tmp = alloca [4 x i32], addrspace(5) 335 %b = bitcast [4 x i32] addrspace(5)* %tmp to float addrspace(5)* 336 %x = bitcast float addrspace(5)* %b to i32 addrspace(5)* 337 %y = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 1 338 %z = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 2 339 %w = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 3 340 store i32 0, i32 addrspace(5)* %x 341 store i32 1, i32 addrspace(5)* %y 342 store i32 2, i32 addrspace(5)* %z 343 store i32 3, i32 addrspace(5)* %w 344 %tmp1 = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 %index 345 %tmp2 = load i32, i32 addrspace(5)* %tmp1 346 %tmp3 = load i32, i32 addrspace(5)* %x 347 %tmp4 = load i32, i32 addrspace(5)* %y 348 %add1 = add i32 %tmp2, %tmp3 349 %add2 = add i32 %add1, %tmp4 350 store i32 %add2, i32 addrspace(1)* %out 351 ret void 352} 353 354; OPT-LABEL: @bitcast_vector_to_vector( 355; OPT-NOT: alloca 356; OPT: store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> addrspace(1)* %out, align 16 357 358; GCN-LABEL: {{^}}bitcast_vector_to_vector: 359; GCN: v_mov_b32_e32 v0, 1 360; GCN: v_mov_b32_e32 v1, 2 361; GCN: v_mov_b32_e32 v2, 3 362; GCN: v_mov_b32_e32 v3, 4 363 364; GCN: ScratchSize: 0 365 366define amdgpu_kernel void @bitcast_vector_to_vector(<4 x i32> addrspace(1)* %out) { 367.entry: 368 %alloca = alloca <4 x float>, align 16, addrspace(5) 369 %cast = bitcast <4 x float> addrspace(5)* %alloca to <4 x i32> addrspace(5)* 370 store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> addrspace(5)* %cast 371 %load = load <4 x i32>, <4 x i32> addrspace(5)* %cast, align 16 372 store <4 x i32> %load, <4 x i32> addrspace(1)* %out 373 ret void 374} 375 376; OPT-LABEL: @vector_bitcast_from_alloca_array( 377; OPT-NOT: alloca 378; OPT: store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> addrspace(1)* %out, align 16 379 380; GCN-LABEL: {{^}}vector_bitcast_from_alloca_array: 381; GCN: v_mov_b32_e32 v0, 1 382; GCN: v_mov_b32_e32 v1, 2 383; GCN: v_mov_b32_e32 v2, 3 384; GCN: v_mov_b32_e32 v3, 4 385 386; GCN: ScratchSize: 0 387 388define amdgpu_kernel void @vector_bitcast_from_alloca_array(<4 x i32> addrspace(1)* %out) { 389.entry: 390 %alloca = alloca [4 x float], align 16, addrspace(5) 391 %cast = bitcast [4 x float] addrspace(5)* %alloca to <4 x i32> addrspace(5)* 392 store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> addrspace(5)* %cast 393 %load = load <4 x i32>, <4 x i32> addrspace(5)* %cast, align 16 394 store <4 x i32> %load, <4 x i32> addrspace(1)* %out 395 ret void 396} 397 398; OPT-LABEL: @vector_bitcast_to_array_from_alloca_array( 399; OPT-NOT: alloca 400; OPT: %out.repack = getelementptr inbounds [4 x i32], [4 x i32] addrspace(1)* %out, i64 0, i64 0 401; OPT-NEXT: store i32 1, i32 addrspace(1)* %out.repack, align 4 402; OPT-NEXT: %out.repack1 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(1)* %out, i64 0, i64 1 403; OPT-NEXT: store i32 2, i32 addrspace(1)* %out.repack1, align 4 404; OPT-NEXT: %out.repack2 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(1)* %out, i64 0, i64 2 405; OPT-NEXT: store i32 3, i32 addrspace(1)* %out.repack2, align 4 406; OPT-NEXT: %out.repack3 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(1)* %out, i64 0, i64 3 407; OPT-NEXT: store i32 4, i32 addrspace(1)* %out.repack3, align 4 408 409; GCN-LABEL: {{^}}vector_bitcast_to_array_from_alloca_array: 410; GCN: v_mov_b32_e32 v0, 1 411; GCN: v_mov_b32_e32 v1, 2 412; GCN: v_mov_b32_e32 v2, 3 413; GCN: v_mov_b32_e32 v3, 4 414 415; GCN: ScratchSize: 0 416 417define amdgpu_kernel void @vector_bitcast_to_array_from_alloca_array([4 x i32] addrspace(1)* %out) { 418.entry: 419 %alloca = alloca [4 x float], align 16, addrspace(5) 420 %cast = bitcast [4 x float] addrspace(5)* %alloca to [4 x i32] addrspace(5)* 421 store [4 x i32] [i32 1, i32 2, i32 3, i32 4], [4 x i32] addrspace(5)* %cast 422 %load = load [4 x i32], [4 x i32] addrspace(5)* %cast, align 16 423 store [4 x i32] %load, [4 x i32] addrspace(1)* %out 424 ret void 425} 426 427; OPT-LABEL: @vector_bitcast_to_struct_from_alloca_array( 428; OPT-NOT: alloca 429; OPT: %out.repack = getelementptr inbounds %struct.v4, %struct.v4 addrspace(1)* %out, i64 0, i32 0 430; OPT-NEXT: store i32 1, i32 addrspace(1)* %out.repack, align 4 431; OPT-NEXT: %out.repack1 = getelementptr inbounds %struct.v4, %struct.v4 addrspace(1)* %out, i64 0, i32 1 432; OPT-NEXT: store i32 2, i32 addrspace(1)* %out.repack1, align 4 433; OPT-NEXT: %out.repack2 = getelementptr inbounds %struct.v4, %struct.v4 addrspace(1)* %out, i64 0, i32 2 434; OPT-NEXT: store i32 3, i32 addrspace(1)* %out.repack2, align 4 435; OPT-NEXT: %out.repack3 = getelementptr inbounds %struct.v4, %struct.v4 addrspace(1)* %out, i64 0, i32 3 436; OPT-NEXT: store i32 4, i32 addrspace(1)* %out.repack3, align 4 437 438; GCN-LABEL: {{^}}vector_bitcast_to_struct_from_alloca_array: 439; GCN: v_mov_b32_e32 v0, 1 440; GCN: v_mov_b32_e32 v1, 2 441; GCN: v_mov_b32_e32 v2, 3 442; GCN: v_mov_b32_e32 v3, 4 443 444; GCN: ScratchSize: 0 445 446%struct.v4 = type { i32, i32, i32, i32 } 447 448define amdgpu_kernel void @vector_bitcast_to_struct_from_alloca_array(%struct.v4 addrspace(1)* %out) { 449.entry: 450 %alloca = alloca [4 x float], align 16, addrspace(5) 451 %cast = bitcast [4 x float] addrspace(5)* %alloca to %struct.v4 addrspace(5)* 452 store %struct.v4 { i32 1, i32 2, i32 3, i32 4 }, %struct.v4 addrspace(5)* %cast 453 %load = load %struct.v4, %struct.v4 addrspace(5)* %cast, align 16 454 store %struct.v4 %load, %struct.v4 addrspace(1)* %out 455 ret void 456} 457 458declare void @llvm.lifetime.start.p5i8(i64 immarg, i8 addrspace(5)* nocapture) 459 460declare void @llvm.lifetime.end.p5i8(i64 immarg, i8 addrspace(5)* nocapture) 461 462declare void @llvm.assume(i1) 463